Living in a 3D World: Why not
Make 3D Integrated Circuits?
Yang (Cindy) Yi
Electrical Engineering and Computer Science
University of Kansas
Outline
•
•
•
•
Introduction
Advantages of 3D IC
3D IC Development and Challenges
Through Silicon Via (TSV) Modeling and
Design
• 3D Stacking for Neuromorphic Computing
• Summary
DASS 2016
2
Living in a 3D World
DASS 2016
3
Why not Make 3D Circuit?
DASS 2016
4
What is 3D Integrated Circuit
• A chip with active
electronic components
stacked on one or more
layers.
• Each block placed on a
separate layer of Si.
• Each die is stacked on top
of another and
communicated by ThroughSilicon Vias (TSVs).
Source: ITRI
DASS 2016
5
3D IC is like a 3D Hamburger
Source: Terahertz Interconnection and Package Lab at KAIST
DASS 2016
6
3D IC is also like a 3D Skyscrapers
3D space with skyscrapers
New York City in 1800
New York City in 2000
DASS 2016
7
Package Function
Provides mechanical, electrical, and thermal
connections necessary for system functionality.
DASS 2016
8
Traditional Technologies
Wire bonding
Flip Chip
DASS 2016
9
Device Packaging – Changing Landscape
Critical performance metrics are shifting
from CMOS Scaling and Package Form
Factor to SYSTEM LEVEL Power
Consumption and Bandwidth.
DASS 2016
10
Communication Bottleneck
• Architectural issues
– Traditional shared buses do
not scale well – bandwidth
saturation
– Chip IO is pad limited
• Physical issues
– On-chip Interconnects become
increasingly slower w.r.t. logic
– IOs are increasingly expensive
• Consequences
– Performance losses
– Power/Energy cost
– Design closure issues or
infeasibility
DASS 2016
11
Vertical Integration
One solution: Go vertical!
• Dies with different functions fabricated with
different technologies are integrated.
Schematic of a System-on-a-Chip design using a planar
(2-D) IC
DASS 2016
Schematic of a 3-D chip showing
integrated heterogeneous technologies
12
Example
• Apple A4 Chip (for 1st Gen iPad and iPhone 4)
Off-chip vertical connections
DASS 2016
Source: Apple Inc.
13
3D IC Market Drivers
“More than Moore”
Heterogeneous integration
 Co-integration of RF + logic +
memory + sensors in a reduced
space
Electrical performance
 Interconnect speed
and reduced parasitic
power consumption
Performance
driven
CPU
GPU
3D vs. “More
Moore”  Can 3D
be cheaper than
going to the next
lithography node?
DRAM
MEMS
RF
3D IC
Optimum Market
Access Conditions
Cost
driven
Flash
CIS
 “Long term”
driver: > 2012
Form factor
driven
 “Short term”
driver: > 2008
Density
 Achieving the
highest capacity /
volume ratio
Source: Yole Development
DASS 2016
14
System in Package (SiP)
Wire Bonding Stacked Chip Package
Long Interconnection
 Long RC Delays
 High Impedance for Power Distribution
Network
 High Power Consumption
 Poor Heat Dissipation (Thick Substrate)
Bonding Wire located in Chip Perimeter
 Low Density Chip Wiring
 Limited Number of I/O
 Limited I/O Pitch
 Large Area Package
DASS 2016
15
3D IC with TSVs
TSV
First Chip
Bump to TSV
Short Interconnection
 Reduced RC Delays
 Low Impedance for Power
Distribution Network
 Low Power Consumption
 Heat Dissipation Through Via
Second Chip
Bottom Chip
No Space Limitation for Interconnection
 High Density Chip Wiring
 No Limitation of I/O Number
 No Limitation of I/O Pitch
 Small Area Package
DASS 2016
16
Benefit of 3D IC with TSVs
3D IC is considered one of the most promising alternatives at
the limit of device scaling:
• Reduced interconnect length
Through-silicon
• Reduced delay
vias (TSVs) for
vertical signal link
• Comparable with current technology
• Heterogeneous integration
DASS 2016
17
Example
Source: Samsung Inc.
DASS 2016
18
Source: Samsung
Manufacturing Cost Reduction
Source: Market trends & Cost analysis for 3D ICs, JC Eloy
DASS 2016
19
3D IC Applications
Source: QUALCOMM Inc.
DASS 2016
20
Market Evolution
DASS 2016
21
Challenges & Opportunities in EDA
Challenges
Design
3D IC EDA Tool Environment
3D IC Design Flow from IC to System
Electrical
TSV Modeling and Characterization
System-level Signal Integrity/Power Integrity
Thermal
3D IC Thermal Models
Thermally Aware Design & Management
DASS 2016
22
3D IC Modeling and Design
DASS 2016
23
TSV Structures
• TSVs are fabricated by high aspect ratio deep silicon etching, lining
with dielectric layer, and super conformal filling with copper.
• A metal insulator semiconductor (MIS) device in which a dielectric
layer SiO2 is deposited to isolate the metals from the substrate.
DASS 2016
24
TSV MIS Interface
• TSV MIS interface can be in
accumulation, depletion,
inversion regions.
• Flat Band Voltage VFB
QS
VFB =ϕ m −ϕ si −
Cox
• if V < VFB, the positively
charged holes in silicon are
dragged to Si-SiO2 interface,
and an accumulation layer is
formed.
• if V > VFB, holes are pushed
away and a depletion region
is formed.
TSV Capacitance Table
DASS 2016
25
High Frequency Effect
• Skin/Proximity effects
Simple Example
Proximity effect:
opposite currents in nearby
conductors attract each other
Skin effect:
high frequency currents crowd
toward the surface of conductors
Resistance increases
26
DASS 2016
6/4/2016
26
Skin Effect
 The field amplitude decreases exponentially into the
Penetration into conductor
10
Skin Depth In Copper
Electromagnetic
Wave
X
Skin Depth, microns
9
Amplitude

thickness of the conductor – skin depth
Defined as the penetration depth at a given frequency
where the amplitude is attenuated 63% (e-1) of initial value
8
7
6
5
4
3
2
ρ
δ=
πfµ
1
0
0.E+00
1.E+09
2.E+09
3.E+09
4.E+09
5.E+09
6.E+09
Frequency, Hz
DASS 2016
27
TSV Rough Surface
•
Mainly occurred due to the etching of TSV and the poor
polymer deposition during passivation.
•
At ultra high frequency, TSV skin depth and root-meansquare (rms) height of the rough surface are comparable.
•
Badly impact on current flowing through TSV in high
frequency range.
DASS 2016
28
Figure courtesy: Tomoji Nakamura et al
Small Perturbation Method
• Analyze the effect of surface roughness at millimeter wave
frequencies by using analytic small perturbation method.
• Analytical expression of modeling and associated
equivalent circuit are based on these structures.
Signal TSV
Signal TSV
Ground TSV
TSV pair without surface roughness
DASS 2016
Ground TSV
TSV pair with surface roughness
29
Skin Effect and Surface Roughness Modeling
 Considering
the skin effect in high frequency TSV, additional
resistance and inductance occurs.
ℎ
𝑅𝑅0 =
𝜎𝜎𝜎𝜎 𝑟𝑟 2 − 𝑟𝑟 − 𝜎𝜎𝐶𝐶𝐶𝐶
ℎ𝑓𝑓𝜎𝜎𝐶𝐶𝐶𝐶
=
𝑑𝑑 𝜋𝜋𝜋𝜋𝜇𝜇0 𝜎𝜎𝐶𝐶𝐶𝐶 − 1
𝐿𝐿0 =
 Using
2
𝜇𝜇𝜇
2.84ℎ
𝑅𝑅0
𝑙𝑙𝑙𝑙 1 +
+
2𝜋𝜋
𝜋𝜋𝜋𝜋
2𝜋𝜋𝜋𝜋
Gaussian distribution function, an increased in conductor
resistance due to the roughness of TSV.
𝑅𝑅𝑆𝑆 =
𝑎𝑎 ℎ − 𝑎𝑎
𝜎𝜎𝑔𝑔3
2𝜋𝜋
𝑒𝑒
− ℎ−𝑎𝑎 2
2𝜎𝜎𝑔𝑔2
DASS 2016
𝑘𝑘𝑐𝑐
𝜎𝜎𝑐𝑐𝑐𝑐 𝜋𝜋 𝑟𝑟 + ∆𝑥𝑥
2
− 𝑟𝑟 2
30
Eye Diagram of TSVs
Pseudo-random data transmitted over wafer level, chip level, and interposer TSV.
DASS 2016
31
TSV Design Optimization
• Smaller TSV capacitance ->
faster signal response and
lower signal distortion.
• Nature of TSV C-V
characteristics depends on
TSV process and architecture.
• Achieve minimum TSV
capacitance in the desired
operating voltage region by
tuning TSV process and
geometry parameters.
DASS 2016
Static C-V Curve of MIS
32
Eye Diagram of Interposer TSV
•
•
Optimize TSV depletion capacitance at 25 Gbps.
Achieved by biasing the TSV into the deep depletion
region with low work function metal for p-type Si.
DASS 2016
33
Outline
•
•
•
•
Introduction
Advantages of 3D IC
3D IC Development and Challenges
Through Silicon Via (TSV) Modeling and
Design
• 3D Stacking for Neuromorphic Computing
• Summary
DASS 2016
34
Neuromorphic Computing
• Inspired by the working mechanism of human brain
• Use analog, digital, mixed-mode very-large-scale integration
(VLSI) circuits to implement the neural systems
Computers will help
people to understand
brains better;
understanding brains
will help people to
build better
computers.
http://www.economist.com/news/science-and-technology//better-and-understanding-brains
DASS 2016
35
Who is this Guy?
Albert Einstein
DASS 2016
36
Brain Inspired vs. Traditional Computing
Human Brain
Traditional Computers
(example taken Tianhe-2)
Speed: 10 PFLOPS (Floating-point Speed: 33.86 PFLOPS
Operations Per Second)
Storage: 3.5 PB (1000 terabytes)
Storage: 12.4 PB
Weight: 1350 g
Weight: 10 Tons (9.07e7 g)
Power: 20 W
Power:17.6 MegaWatt
Cost: $390 million
Size: 1195 cm3
Size: 7,750 sq. ft.
(1 http://www.thehindu.com/sci-tech/health/medicine-andresearch/brain-circuits-behind-hearing-develop-without-sensoryexperience/article477048.ece)
(2 http://spectrum.ieee.org/tech
talk/computing/hardware/chinese-supercomputer-tianhe2continues-reign-as-worlds-best-super-computer)
DASS 2016
37
Biological vs. Hardware
“Neuromorphic Architectures” James Kempsell
DASS 2016
38
3D Stacking is Essential for Neuromorphic IC
IBM TrueNorth Chip:
• Neurosynaptic core contains 256
neurons, and a 64k synaptic crossbar.
• 4096 neurosynaptic cores in a 2-D array
occupies 4.3 cm.
2
• Consumes 65 mW of power while
running a typical computer vision
application.
Source: IBM Inc.
DARPA SyNAPSE 16 chip
board with IBM TrueNorth
DASS 2016
Source: IBM
39Inc.
Neuromorphic 3D Stacking
• Provide massive parallelism among neurons that is required for highly
demanding computational task.
• Offer high device integration density using fast and energy efficient link.
• Provide higher bandwidth and lower routing cost between the layers by
minimizing the obstacles introduced by 2D circuits.
DASS 2016
40
2D vs. 3D
Characteristics and breakdown of (two-layer) 3D circuit.
2D over 3D ratios for main characteristics: time
to process an image, energy per image,
energy per spike, power, area.
Characteristics and breakdown of (two-layer) 2D circuit.
The Improbable But Highly Appropriate Marriage of 3D Stacking and Neuromorphic Accelerators
DASS 2016
41
Step Response
DASS 2016
42
Summary
• 3D IC is considered one of the most emerging technologies
at the limit of device scaling.
• Needs strong EDA tools for automated design.
• Our study helps in developing design guidelines for TSVs in
3D IC.
– Proposed an accurate broadband circuit model.
– Optimized the parameters of TSVs architecture and manufacturing
process to obtain the minimum depletion.
• 3D stacking is essential for neuromorphic IC design.
IC
DASS 2016
43
Thank you very much!