End-to-End Design and Simulation of
Handset Modules
Pete Zampardi and Hongxiao Shao
Skyworks Solutions, Inc.
Skyworks Solutions, Inc. Proprietary Information
1
Research vs. Production Design Flows
Research Design Flow
Production Design Flow
Simulate
Simulate
Fabricate
Fabricate
Test
Test
Yes
Work?
No
Ask for
More
Funding
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Apply for
Follow-on
Repeat
50 Million
Times
Work?
Yes
No
Re-Tune
2
Outline
• Simulation Philosophy
• What Does a Handset Amplifier Design Look Like?
• Example Design Flows
– GSM (Controller + PA)
– WCDMA (Bias/Logic Integrated with PA)
• Design Automation and Modeling Requirements/Strategy to Support This
Flow
• Modeling Approach
–
–
–
–
–
Device Models
Inductor Tool
Thermal Considerations
Circuit Level “Modeling”
Laminates – Man Does Not Live by GaAs Die Alone…
• Conclusions
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Modeling/Design Philosophy
What are the Expectations?
• Goal of Modeling (for PA) is to Get Designer on the Green
– Compact Models are the Drivers, Irons, and Wedges
– Correlation of Lab and Simulation Benches is like “reading the green”
– Behavioral Models could be the Putter
• Modeling VARIATION of the Process is More Important than Modeling a
“Hero Device”
– Variation is Important for Yield and System Performance
• Use Best Available Software for Each Piece,
Glue Together with Custom Solutions
The time needed for measuring a PAM with Pout sweeping
from -5 to + 28 dBm (1dBm/step) and three frequencies, plus changing
one
SMT component was about 1500 sec.
(V. Ho)
Goal of Simulation is to Get Close as
Fast as Possible, Predict Trends
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What Does a Handset Amplifier Design Look Like?
HINT: NOT MADE OF DISCRETES
Control/Logic IC
WCDMA Usually
Combine These
On-chip
Simulation: DC, Trans., S-par
and HB
Layout: GDSII
Power Amp IC
Simulation: DC, Trans., S-par
and HB
Layout: GDSII
Glasbrener
Breaking EDA Barriers
RFIC Panel 2002
Power Amp Product
Components
SMT, Filter, etc
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EM Simulation
Layout: Gerber
Simulation: DC, Trans. S-par
and HB
Substrate and
Assembly
5
Simulation and Design Issues
• Components (Simple Small Signal Models Okay)
• Fit for Design Flow:
– Tunable for Optimization
– Sensitivity Analysis for Tolerance Selection
– Fixed Predefined Sizes
– NO Double-Counting
Components
• Substrate (Feature Size Determined by Customer/Product Needs)
• EM Simulate as Soon and Much as Possible
• Variation is Important (Weed Out Bad Layouts)
– Design Issue
• Need to Run DRC and LVS on Substrates
Substrate
• IC’s (Controller and PA)
• DC, Time Domain, Small Signal S-parameter and Possibly HB/Env sims
• Design Library Supported by Foundry/Fab
• EM Sim. for on Chip Passives (Inductors, MIM Caps, Bad wiring)
– Design Issue
• Need to Run DRC and LVS on ICs
– Challenges for Controller
• Predictable Interface with PA for Co-Simulation/Co-Development
– Challenges for PA
• Models Need to Work in DC, Small Signal, and Large Signal with Correct DC Predictions Under Large Signal
• Need to Simulate with Everything Else Substrate, Logic/Control and Components
Control/Logic IC
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Power Amp IC
6
PAM/FEM Design/Simulation Flow
Design Environment
Block Level System Performance Budget Analysis and Partition
Customized and Integrated Commercial and Home Grown EDA and other Application Software Tools
Product IP
Technology IP
Process Design Kit
Device Symbols
Device Models
Device Layout
DRC, LVS Rule Files
Hierarchical Schematic
Test Bench with Pkg/SMT
Full Chip(s)
Block in Design
IC-Package Link
Bonding Diagrams
Geom/S-Param
Etc.
Physical Design
Schematic Driven Layout
Layout Editor
IC/Block in Design
Package Libraries
Discrete Component
Vendor Models
Package Model
Physical Verification
Design Rule Check
IC/Reticle Level
IC/Block in Design
Standard root
Compatible with Tech
Parallel Dev Teams
Version Control
IP Share/Reuse
Post Layout Verification
Layout vs. Schematic
Parasitic Extraction
Re-Sim with LPE
IC Footprint
Netlist for Pkg/Brd
Physical Design
Package/Board/Module
Physical Design
Memory/Disk based
DRC
Bill of Materials
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Behavioral Models Could Be Effective Blocks Not
Being Implemented
Tools for root
/root/$projID gen
project Rev
project Lock
Release to Mask
OK to Mask
Man
Cntl
OK to
Tapeout
7
IC Centric Design Flow – Real Example
Chips
Control and Bias Chip
GaAs HBT PA Chip
Power Detector
Switch Chip
Diplexer
Packages
Embedded devices
Discrete
MCM
pHEMT Switch Chip
GaAs IC + Wire bond + Package (EM/Meas.)
CMOS Chip
CMOS IC + Wire bond + Discrete Components
GaAs HBT Power Amp Chip
Design
Electrical Design
Physical Constraints (IC/Package)
Thermal Management
Part Tuning
GaAs IC + CMOS IC (at circuit or behavior level) + Wire bond + SMT + Package (EM/Meas.)
Multiple Process Technologies (Multi-Chip)
ICs
– Active/Passive Device Models, Interconnect/Inductor Modeling
Package – Bond wire/Bump, SMT, Embedded Devices, Package Passive Modeling
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GaAs HBT PA / PHEMT Switch Design Flow
Models for
supplies, stimuli,
measurement, etc.
Package Models
SMT, BW,
Laminate
Si Models
HBT Models
Simulation
Bench
Hierarchical Schematic
Design, Analysis,
and Simulation
Test Bench
Schematic
Preliminary
MCM Schematic
EM Simulation
MMIC Schematic
MMIC Netlist
PA MMIC Layout
LVS
HBT Layout
Library, DRC
Rule Deck
HBT PA Design Flow
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HBT Mask
Generation
Die Symbol
for MCM
Layout
.die file
Die Symbol
for MCM
Schematic
9
Silicon PA Controller Design Flow
VerilogA Behavioral Model
HBT DC Model
Hierarchical Schematic
PA “Analog” Model
Models for
supplies, stimuli,
measurement, etc.
Package Models
Cadence Generic
Libraries
Design, Simulation, and Analysis
Top Level
Simulation Schematic
Si Die
Schematic
Si Mask
Generation (GDS)
Si Technology Models
Si Die Layout
LVS, DRC
Verification
Die Symbol
for MCM
Layout
.die file
Die Symbol
for MCM
Schematic
Si Layout Library,
Verification Rule Decks
Si Controller Design Flow
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MCM Design Flow
Hierarchical Schematic
From HBT / pHEMT Flow
Test Bench
Schematic
Design, Analysis,
and Simulation
DMS
Preliminary
MCM Schematic
MCM Package
Library
MMIC Schematic
EM Simulation
MCM Schematic pdf
Wirebond Diagram
DC/AC Simulations
to Verify Functionality
RFDE Dynamic Link
Required for Si
.die file
MCM
Package Level
Schematic
Die Symbol
for MCM
Schematic
Die Symbol
for MCM
Layout
MCM
MMIC Netlist
MCM Layout
PCB Fab Drawing
BOM
Generation
(1st time only)
Text File Manipulation
and Updates
MCM Design Flow
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Assembly Diagram
Prototype BOM
Tuning, Alternate
Component Eval, …
11
PA Module Design Optimization and
Verification RFDE ADS Dynamic Link
Package Models
SMT, BW,
Laminate
HBT Models
ADS
Hierarchical Schematic
ADS MCM
Level Schematic
ADS MMIC
Die Schematic
Cadence
Hierarchical Schematic
Si Models
ADS
Design, Analysis, and Simulation
ADS Top
Level Schematic
ADS DYNAMIC LINK
Models for
Supplies, Stimuli,
Measurement, etc.
Cadence Si Die
Schematic
Si PA Controller / HBT PA / MCM Co-Simulation
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WCDMA Considerations
• Control Circuitry is ON-CHIP!
– What the PA must do now is complicated
• Power Level Switching/Control
• No Vref Bias Circuits
Power
Power
Transistors Transistors
• Barrie Gilbert “RF design is 30% RF, 70% Bias Circuit”
– Analog-mixed Signal Modeling Methodology Must be Applied
• Fully Scalable Device Models (for Optimization)
• Statistical Simulations (Physically Based is Better)
• For High Volume Commercial Products, Yield Matters!
– Statistics for Laminate Variations are Important (Not Just the Die)
Most of the Chip is
NOT Power Transistors
PAs are More than “Just Two Transistors”
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(W)CDMA PA/FEM Product
Development Flow
Simulate Stuff
You Didn’t Know
Earlier (Passives)
Don’t Know Layout or off-chip stuff
Understand Critical Blocks
With Estimated Tolerance to Parasitics
Feasibility
Study
Scalable
Device
Models
Initial Simulation
Schematic
Connectivity/
DC/Functionality
Provide Tools
For 1st Order
Best Guess of
Things You’ll
Layout
(Inductors/Caps)
Know Variations
IC Design
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(Partial)
Building Block
IC Design
Extend
Simulation
MCM_RF
IC Layout Parasitic
Layout
Module Design
(Layout)
Layout
Best Guess
At Bond Wires
Co-Simulation
IC+Module
For Production,
Statistical
Simulation
Over Die Process
And
Package Variation
Design for
Manufacturing
EM Simulation
CoSimulation
14
Compact Models
• Compact Models Provided (at Schematic Phase) for:
– Transistors
• HBTs (for Logic and for Power Chain)
• MESFETs (for Logic and Switching Functions)
– Diodes (Used in Logic Circuits and ESD)
– Resistors (Precision Thin-film and Semiconductor)
– Inductors (Inductor Tool Provided to Help Selection, Assume EM Sim Later)
• Simulation Based on Method of Line, Momentum and S-parameters Pulled in
– Capacitors (Tool Provided for Selection, Assume EM Sim Later)
Compact Models are Required for Bias Circuit
Design and for Device Selection for Power
Devices
Provides an Easy Path for Statistical Simulation
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Evolution of Models at Skyworks
Zampardi, CMRF 2007
Increasing
Number of
Devices and
Materials to
Satisfy More
Diverse
Design
Demands
Tech
Devices Supported
Wafers
Meas.
Sites per
Wafer
Temperature
# of Epi
Statistics
GEN2
3 HBTs, 3 Diodes, Ls
1
1
HBT Only
1
No
GEN3
4 HBTs, 2 Diodes, Ls
1
1
HBT Only
1
No
GEN4
4 HBTs, 2 diodes, Ls,
C’s
1
1
HBT/Diode
2
No
Current
Scalable HBTs
Multiple
5
Yes
Curve Fit
(Fixed-cell Rings,
Many Geometries of
Straight Finger)
Ring
All
Horseshoe
CEBEC (QSF)
CEBEC (QSB_ALT)
QSB
QSM
CEB, BEC, 1, 2, 4 finger
5
Physics Based
Scalable Diodes
Rs, Ls, Cs
FETs for BiFET
Physics-Based Scalable Approach Makes This a Tractable Problem
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Inductor Tool Customized ADS
Specify
required L, Q,
layout area
Select inductor
type, frequency
Enter TW, S,
N, ID
Calculator
outputs L,
Q
Press ‘Select’ to
place instance in
schematic
Calculator Mode
Selector Mode
Kwok, Mantech 2008
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Thermal Approaches/Considerations
• Maximum Junction Temperature Simulations (Reliability)
• Thermal only Simulation (Okay if Properly Ballasted)
– Usually Compared/Validated Against IR Scans
Absolute
Temperature
• Thermal Coupling/Average Transistor Temperature (Electrical)
– Bias Circuit
– Array Design
– Array to Array Interactions
Coupling
• Complications
– Inter-transistor interaction through interconnect/semiconductor/etc.
– Thermal is Not Just Because of the Die: Laminate, Epoxy, Overmold, etc…
What Matters Thermally Depends on
What You are Designing
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The Simulation Problem
PA Module/Phoneboard Cross-Section
PAM
Thermal Simulations Require Inputs From
All of These
PHONEBOARD
Electro-thermal Couples the Temperature
Information Back into the Simulation
Circuit Simulation
Power Supply Voltages
Power Dissipation Per Transistor
Die Layout
Package Layout
Placement of Transistors
(Heat Sources)
Epoxy (Shape and Thickness)
Placement of PTH
Coupling Between Heat Sources
(Metal and Semiconductor)
Coupling Between Heat Sources
(Metal and Laminate)
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Compared to Digital/Analog Circuits, for a
PA this Will Need to be Done Several Times
at Any Given Power Since Electrical
Parameters and Thermal Conductivities
are Functions of Temperature
Much of the Packaging Information
(Epoxy Thickness, Shape,
Die Placement, Die Thickness) is Difficult
To collect Statistical Information on
19
Gaps in Circuit Level Thermal Simulation?
• User Friendly Interface/translator from Simulation to Thermal and
Back
– Scripts to Map Simulator Information (power) and Layout Information
(Position) Needed
– Scripts to Back-Annotate Temperature Information (From T simulator) into
Circuit Simulators
– Determination/Characterization of How Much of the Output Array Needs to be
“Lumped” Together
• First Order Estimate (During Simulation Pass) of Coupling and Array
Average Temperature (Analytical Equations Embedded in Simulator)
– Needs Some Background Work to Make it Generally Applicable Rather Than
for Each Array/Device/Technology
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Temperature Simulations on Array
Pout
Gain
30
20
gain
40
10
pout
RFpower=18.000
Pout=31.425
0
PAE
RFpower=18.000
PAE_C=58.930
0.9
Icc
-10
-5
0
5
10
15
20
20
0.5
0.4
0.3
0.1
-20
-15
-10
-5
RFpow er
RFpow er
-18.000
0.7
0.6
Icc
RFpower=18.000
real(Ic.i[::,0])=0.638
0
-15
0.8
0.2
-10
-20
1.0
0
5
10
15
20
RFpow er
gain
RFpow er
17.317
18.000
pout
31.425
PAE
Icc
58.930
0.638
Simulation No.
Description
Gain
Pout
PAE
1
No T Rise
17.317
31.425
58.93
2
T Rise = 10
17.938
31.48
58.893
3
Avg T Rise = 2.1
17.456
31.439
58.926
4
Avg T Rise = 4.54
17.61
31.455
58.917
5
Avg T Rise = 7.27
17.755
31.473
58.9
6
Avg T Rise = 20.9
18.324
31.565
58.745
7
Hotspot Avg T=6.8
17.607
31.479
58.856
Average Temperature is What Matters
For Electrical Simulation
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real(Ic.i[::,0])
22 Transistor Array
Optimal Load for All
Qs at same temp
Ballast and Pre-matched
pout
gain
RFpower=-18.000
Gain=17.317
PAE
60
PAE_C
40
CMRF 2007
21
Array Parasitic Approaches
(Teaching Designers to Fish)
Simple Multiplicity Factor
Pro: Fast/Simple
Con: Phase Error >8GHz
Lumped Element
Transmission Line:
Pro: Moderate Speed, Scalable, Easy
Con: Accurate Up to 12GHz
Pro: Fast
Con: Layout Specific, Hard to Scale
EM Simulation Reduced Number of HBTs or All HBTs
Pro: Easy to Do, No Modeler Required
Con: Simulation Speed Bogs Down with Increased Transistor Count
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22
Load-Pull Power Sweep with Different EM
Approaches
Gain Comparison
Pout Comparison
22
30
20
25
Pout, meas
Gain, meas
Gain, EM-1HBT
Gain, EM-2HBT
Gain, EM-3HBT
16
Gain,EM--12HBT
Gain, Simple_M
14
Gain, TLM
Pout, EM-1HBT
20
Pout (dBm)
Gain (dB)
18
Pout, EM-2HBT
Pout, EM-3HBT
15
Pout,EM-12HBT
Pout, Simple_M
10
Pout, TLM
Gain, Lumped
Pout, Lumped
5
12
0
10
-15
-10
-5
0
5
10
-15
15
-10
-5
0
5
10
15
Pin (dBm)
Pin (dBm)
• On-wafer LP measurement at freq=1.9GHz,
Vc=3.4V, Ic=14.6mA
Ic Comparison
200
180
Ic (mA)
160
Ic(mA), meas
140
Ic(mA), EM-1HBT
120
Ic(mA), EM-2HBT
Ic(mA), EM-3HBT
100
Ic(mA),EM-12HBT
80
Ic(mA),simple_M
60
Ic(mA), TLM
Ic(mA), Lumped
40
20
0
-15
-10
-5
0
Pin (dBm)
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5
10
15
No Huge Differences Based on
Approach!
EM Slightly Better
Simple Approach Off at High Power
23
Statistical Simulation:
All-In-One and Interactive
Yang, Microwave Journal, 2008
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Statistics – Understand Expected Variation
Compared with measurement, PA circuit simulation
shows good tracking of DOE variations.
Statistical Inputs:
PCM Parameters from
Measured
DOE Wafers
Power Sweep Performed
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25
Statistics: Identify Issues and Improve Design!
db(S 21) v s temp
33
db(S 21) v s temp
33
m1
indep(m1)=25.000
plot_vs(dB(S(2,1)), SP.temp)=29.12
freq=836.5000MHz, doeIter=0
32
31
31
30
30
m1
29
dB(S21)
dB(S21)
dB(S21)
m1
indep(m1)=25.000
plot_vs(dB(S(2,1)), SP.temp)=27.892
freq=836.5000MHz, doeIter=969
32
28
27
29
m1
28
27
26
26
25
25
24
-30
-20
-10
0
10
20
30
40
50
60
70
24
80 85
-30
-20
-10
0
10
20
Temperature (C)
30
40
50
60
70
80 85
Temperature (C)
0.035
0.035
0.030
0.025
Icq1 (A)
Icq1
Icq1 (A)
Variation Significantly
Reduced!
0.030
0.020
0.025
0.020
0.015
0.015
0.010
-30
-20
-10
0
10
20
30
40
50
60
70
80 85
0.010
Icq2 (A)
Icq2 (A)
85
80
70
60
50
Temperature (C)
0.07
0.06
0.05
0.05
0.04
0.04
0.03
0.03
Performance Ranges (at 25C):
dB(S21)(25.64 to 31.54)=5.9
Icq1(13 to 28)=15mA (79%)
Icq2(44 to 90)=46mA (72%)
BEFORE
85
80
Temperature (C)
80 85
70
70
60
60
50
50
40
40
30
30
20
20
10
10
0
0
-10
-10
-20
-20
-30
-30
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0.06
30
0.08
0.07
20
0.08
10
0.09
0.09
0
0.10
-10
Icq2
0.10
-20
-30
Temperature (C)
Temperature (C)
Performance Ranges (at 25C):
dB(S21)(25.88 to 29.42)=3.5
Icq1(19 to 30)=11mA (46%)
Icq2(35 to 53)=18mA (41%)
AFTER
26
Laminate DOE Simulation
• Batch Based Momentum Simulations on DOE states to
capture the laminate process variations:
–
–
–
–
Layer over Layer Misalignment
Geometry Size Variations
Dielectric and Layer Thickness Variations
Can Also Be Applied at Die Level
• After Completion of the Batch Based simulation, a
Symbol is Generated to Enable the Passive Block, with
DOE Analysis Results, to Simulator with Other Blocks
at the Circuit Level
• Pareto charts in ADS Data Display is created once the
circuit level DOE analysis is complete.
Assume SMT
cap variation as
follows:
C = +/- 0.1 pF
L = +/- 0.05 nH,
R = +/- 0.1
Ohm L1 trace width
Portion of Output
Match Symbol
in ADS schematic
7 laminate rerelated variables
are defined for
DOE analysis
Layer over layer offset in X-axis
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Issues for Behavioral Modeling
• We Use Multiple Materials to Address Diverse Product Needs = Nmaterial
• Allow Different Unit Cells for Application = Ncells
• Different Ballasting/Feedback For Different Designs = Nballast
• Different Array Layouts/Size Requirements for Applications = Narray
• Process Variation (Say a Few Parameters Will Multiply this by 2Nvariation)
N Models = N material N cells N ballast N array
For FETs, This is an Easier Problem – Single Gate Length, Gate Width Scaling (by Adding Cells), No
Ballasting. Process Variation is a Bigger Headache!
Using Behavioral Models For Simulating
Integrated PA Designs Creates an Intractable Problem!
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Where Does Behavioral
Modeling Fit In?
• Designs Using Discrete Transistor Blocks
• Not as Prevalent in Handset Designs Anymore but Used to be Common 10 year ago
• Simple Behavioral Models of PA for Bias Design, and of Bias for PA Design (Usually
Implemented in VerilogA)
• Package Centric Product Design (Re-use of Controller and/or PA Engines)
• System Level Simulations (Still Issues with Statistics, but More Manageable)
• If It Can Be Used to Improve Speed of Characterization
• When the Technology is Not Well Understood
• Could Be Used as “Putter” Once Compact Models get You Close
• Things That Still Need to Be Ironed Out
• Incorporation of Statistics
• Memory Effects (especially thermal)
• Validation that Insides of Black-Box are Independent of What Happens Outside
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29
Conclusions
• Compact Models Provide a Greatest Leverage in Simulating
Handset PAs, Especially Statistics
• The Real Issues Facing PA Designers are Often Misunderstood
• Layout Parasitics
• Thermal Impact on Electrical Performance
• Stuff Besides Die is also Critical
• Behavioral Models are Useful at System/FEM Design Level and for
Technologies that are not Well Understood.
• Statistics are Critical, Even for Package and Embedded Passives
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Acknowledgments
Mats Fredriksson
Mike Glasbrener
Kai Kwok
Yingying Yang
Juntao Hu
Shing Li
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References
M. Glasbrener, “Breaking EDA Barriers” 2002 IEEE MTT Panel Discussion
R. Jos, “Future developments and technology options in Cellular Phone Power
Amplifiers: from power amplifier to integrated RF front-end module”, BCTM Technical Digest, 2000, pp. 118-125
B. Gilbert, “Biasing techniques for RF/IF signal processing”, presented at the MEAD Lecture Series short-course
lecture, UC Berkeley, CA,1987
P. Zampardi, “III-V HBT Modeling Issues and Future Directions”, CMRF 2004 Workshop, Montreal, Quebec, Canada
K. Kwok, “Simple DOE-based inductor tool for design automation”, 2008 CS Mantech Conference, Paper 17.2
Y. Yang, “An Innovative and Integrated Approach to III-V Circuit Design”, Microwave Journal, September 2008, pp. 136-156
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