A Wideband Amplifier with 2.4 mm Connectors
Operating up to 48 GHz
M. Häfele∗‡ , C. Schick∗ , F. Hernandez-Guillen∗, A. Trasser∗ , P. Abele∗† , and H. Schumacher∗
∗ Dept.
of Electron Devices and Circuits, University of Ulm, D-89069 Ulm, Germany
with United Monolithic Semiconductors (UMS) GmbH, D-89081 Ulm, Germany
‡ Now with DaimlerChrysler AG, Research and Technology, D-89013 Ulm, Germany
Phone: +49 731 5052026, e-mail: Martin.Haefele@DaimlerChrysler.com
† Now
Abstract— In this paper, we report about an assembly technology for a wideband distributed amplifier (DA). The amplifier
MMIC is fabricated in a commercially available GaAs pHEMT
process with 150 nm gate length. The amplifier is connected to
a 50 Ω microstrip-line on an external rf-laminate with 2.4 mm
connectors attached to the input and output. A via-hole process
was developed for the Teflon based substrate material. All
elements are assembled on top of this substrate. To provide bias
decoupling down to the kHz-range, an external surface mount
device (SMD) resistor and capacitor are attached to the artificial
drain line termination of the DA. This enables the amplifier
to operate in non-return to zero (NRZ) optical communication
systems.
The packaged amplifier exhibits a gain of 11.2 dB near dc.
The midband gain equals to 8.9 dB±1.5 dB between 2 GHz and
48.5 GHz.
Index Terms— Distributed amplifiers, traveling wave amplifiers, optoelectronic devices, high-speed integrated circuits, packaging
For the assembly technology, an important technical
problem that must be overcome is how to cope with parasitic
effects [1]. As the bandwidth becomes wider and the
frequency becomes higher, the effects of circuit patterns
or structure increase significantly [1]. In particular, chip
mounting is most crucial, where the wavelength of the
electrical signal approaches the physical size of the mounting
elements such as the package cavity, input/output leads, and
bonding wires [1].
For achieving an excellent bandwidth performance [2] a
DA topology is utilized for the MMIC. The idea of a DA
is to use several small active devices in parallel instead of
one large transistor and to separate its parasitic capacitances
by high impedance transmission lines. The resulting small
signal structure at the input and output is designed to behave
like a 50 Ω artifical transmission line and therefore shows
both small input and output reflection as well as flat gain
over a large bandwidth. With this circuit topology, one can
simultaneously have the high frequency characteristics of one
unit-cell together with gain and output power performance of
all unit-cells in parallel. This concept is often used for high
speed broadband amplifiers with moderate gain.
OF THE
CD2
CD1
RD2
RD1
RD
ZD, lD
RExt
CExt
ZD, lD
ZD, lD
RS
VG2
RG2, Bias RG2, D
ZS, lS
RS
T2
ZS, lS
CG2
T1
Input
ZG , lG
Output
RG2, D
T2
CG2
ZD , lD
ZG, lG
T1
ZG , lG
ZG, lG
RG
RG, Bias
VG
I. I NTRODUCTION
II. C IRCUIT D ESIGN
process with 150 nm gate length from United Monolithic
Semiconductors (UMS). A circuit schematic is shown in Fig. 1.
MMIC
The circuit design of the MMIC is described in detail in [3].
The used topology is a distributed amplifier with four cascode
unit-cells based on a pseudomorphic GaAs pHEMT low noise
Fig. 1. Schematic of the MMIC. On the top left is the drain bias decoupling
shown.
Despite the gate line, also at the artifical drain line a 50 Ω
termination is needed for the reverse traveling wave. To have
no dc-current flowing through the resistor RD , serial blocking
capacitors are needed. High frequency components of the
wideband signal are already grounded on chip. To enable a flat
frequency response down to very low frequencies, additionally
an external SMD capacitor with a high capacitance of 100 nF
has to be attached to the chip.
The transmission lines at the input and output are kept
as short as possible. By this, the bond-wire inductance is
embedded into the circuit design and compensates for the
parasitic capacitance of the first and last transistor unit-cell.
The circuit design was optimized for a bond-wire inductance
of 0.1 nH.
The circuit performance up to 50 GHz is shown in detail
in [3]. Measurements up to 110 GHz were carried out at two
different bias points. For a bandwidth exceeding 60 GHz, a
drain biasing of 3.0 V is applied via the internal bias-Tee of
the measurement setup. Additionally a second gate voltage of
VG2 = 2.0 V is used. The small signal measurements for this
bias point are depicted in Fig. 2.
The measured gain close to dc equals 10.5 dB with a gain
ripple of ±1.0 dB between 10 MHz and 60 GHz. The -3 dB
bandwidth equals 62.2 GHz. Up to 50 GHz, input reflections
are smaller than -12 dB. Output reflections are lower than
Gain (S21) / Reflection [dB]
15
10
5
0
-5
-10
-15
-20
-25
±0.6 dB. For the bandwidth from 10 GHz up to the cut-off
frequency of 57.2 GHz, the gain variation is even smaller
and equals ±0.3 dB. Input reflections are better than -9.6 dB
up to 50 GHz. The output reflections are better than -10 dB
up to 74 GHz and less than -5 dB over the whole 110 GHz
measurement band.
For this amplifier, a demonstrator with 2.4 mm connectors
is assembled, which is described in the following.
Measured S21
Measured S11
Measured S22
III. A SSEMBLY T ECHNOLOGY
A. Substrate Material
0
20
40
60
80
100
Frequency f [GHz]
Gain (S21) / Reflection [dB]
Fig. 2. On-wafer small-signal parameters, measured up to 110 GHz. For a
drain biasing of 3 Vpp the amplifier is biased for maximum bandwidth. For
this bias point the gain close to dc equals 10.5 dB with a −3 dB bandwidth
of 62.2 GHz.
15
10
5
0
-5
-10
-15
-20
-25
Measured S21
Measured S11
Measured S22
0
20
40
60
80
100
Frequency f [GHz]
Fig. 3. On-wafer small-signal parameters, measured up to 110 GHz. A drain
biasing of 5.0 V is applied for a flat frequency response. Between 2 GHz and
57.2 GHz the gain variation is within ±0.6 dB. The gain at dc equals 11.8 dB.
-14 dB up to 50 GHz and less than -5 dB over the whole
measurement band.
Alternatively the amplifier can be biased for higher gain
with a very flat frequency response. In this case, the drain
biasing equals to 5.0 V with a second gate voltage of 3.7 V.
Small signal measurements at this bias-point are shown in
Fig. 3.
Close to dc the gain equals 11.8 dB. The gain variation
between 10 MHz and 57.8 GHz is ±1.4 dB. The increased
gain at low frequencies is due to the fact, that an additional
external resistor with 10 Ω is used in series to the external
SMD capacitor. This resistor is needed to prevent a resonance
between the on-chip capacitor-network and the parasitic inductance of the bond-wire which is needed to connect an external
SMD capacitor to the artificial drain line. The external SMD
capacitor is needed to have good bias decoupling down to
frequencies in the kHz-range, especially if the amplifier is
intended for applications in optical communication networks
with NRZ signal encoding.
Between 2 GHz and 57.2 GHz the gain ripple is within
At frequencies exceeding 20 GHz, the requirements for the
substrate material are critical. The generation of unwanted rfmodes has to be prevented and substrate losses have to be
small. Typically two types of substrates are used at the high
frequency end. One is an Al2 O3 based substrate. Losses for
this substrate material are very small (typically tanδ=0.0002
at 10 GHz). However, one disadvantage is that the material is
very hard. Therefore it is critical to apply a via-hole process
to it. In comparison, a Teflon based substrate is very soft and
is perfectly suited for test-structures, since it can be easily
cut and transmission lines can be trimmed to the desired
length even after fabrication. Additionally a via-hole process
is possible but critical, since processing is not easy. An other
advantage is the very low dielectric constant εr of the substrate.
Since the width of the microstrip line is wider for lower values
of εr , etching of 50 Ω microstrip lines can be done with a
standard printed-circuit-board process.
Due to the above described advantages, a Teflon based
rf-laminate was chosen as substrate material. Despite substrate
materials for low frequencies, Rogers Corp. provides a Teflon
based substrate (RT/Duroid 5880) which is typically intended
for military applications. For the substrate height, a thickness
of 127 µm was chosen to approximately fit the 100 µm height
of the fabricated GaAs MMIC. This gives the possibility
for short bond-wires if both, the amplifier and the substrate
are fixed next to each other on a metal block. The copper
cladding for this substrate equals to 17 µm and the dielectric
constant is εr = 2.20. The loss tangent tan δ is very low and
equals 0.0004 at 1 MHz and 0.0009 at 10 GHz. For this type
of substrate, a via-hole process is developed using reactive
ion etching and a gold galvanic process. The via-holes are
already drilled by the standard printed-circuit-board process.
To achieve stickiness of the gold vaporization at the via-hole
walls, a reactive ion etching process was used providing
some roughness to the substrate. The substrate is etched
three times with five seconds and additional three minutes
break to avoid too much heating of the substrate. Afterwards,
gold vaporization is used to achieve conductivity of the
via holes. This gold layer is very thin which results in a
low conductivity of the via-holes. Thus, an additional gold
galvanic process is applied to the substrate. The gold galvanic
process is uncritical and a thick (approximately 1 µm) gold
layer is deposited to achieve a good conductivity of the
via-holes.
B. Connector
As connector, an edge mount jack from the Rosenberger
RPC 2.4 mm series is used. The Rosenberger connector
09K243-40ME3 provides easy assembly to the metal brass and
p
a very low insertion loss of < 0.2 dB × f/GHz. The voltage
standing wave ratio (VSWR) is below 1.5 up to 40 GHz.
C. Assembly
Typically there exist three ways for assembling an amplifier
to an external rf-laminate. One possibility is to use flip-chip
technology, with the amplifier placed up-side-down on top
of an rf-substrate. In this case, grid ball bonds are used
to have a smaller and well controlled parasitic inductance
compared to bond-wires. This is especially useful in terms
of high frequency operation. However, arranging of the
amplifier to the pads on the substrate is critical. Especially,
the ground-signal-ground pad spacing is only 70 µm for the
already fabricated amplifier, which would additionally make
the fabrication of the transmission lines critical. Additionally,
there are other main road blocks for flip-chip technology. A
lack of experience and proven design data requires additional
efforts for production environment [4]. Furthermore, using
flip-chip technology implies a basic change in design strategy
and an additional bump fabrication step to the process flow
on the wafer level at the foundry side [4]. Due to the above
reasons, flip-chip technology is not utilized for this amplifier.
Fig. 5.
Picture of the fabricated low noise amplifier with Rosenberger
connectors attached. The picture on the left side shows a complete view of
the amplifier, on the right side a zoomed in view shows more details of the
assembled chip.
Another possibility is to mount both, the transmission line
and the amplifier to a metal block. The transmission lines and
the amplifier can thereby be fixed by a silver filled epoxy glue.
The amplifier’s input and output signal-lines are connected to
the microstrip line of the rf-laminate by bond-wires.
This is a very elegant way to connect the amplifier and
the substrate if both have approximately the same height.
By this, the bond-wire length can be kept relatively short,
reducing the parasitic inductance. This assembly technique is
especially useful if a rigid substrate material like AlO3 based
materials is taken. In this case, the amplifier and the substrate
can be fixed close to each other easily.
amplifier’s input and output to the 50 Ω transmission lines.
Underneath the amplifier are several via-holes to provide a
good ground and heat-sink to the amplifier.
Close to the on-chip drain line termination of the amplifier is
a pad provided for connecting bond-wires to a substrate with
external SMD components. From this pad, three bond-wires
are connected to a pad with a 10 Ω resistor. In series to the
resistor, two capacitors in parallel are mounted to a pad with
via holes to ground.
The size of the assembled amplifier is 1.2 × 1.5 × 1.1 cm3 for
the metal block or 3.1 × 1.5 × 2.7 cm3 for the metal block with
the 2.4 mm connectors.
If the substrate material is suited for a via-hole process,
then the amplifier can also be attached on top of the substrate.
The via-holes of the rf-laminate provide a good ground to the
backside of the MMIC. This makes the assembly-process easy,
because all passive structures can be easily glued on the same
piece of substrate. The above described assembly method is
utilized for the amplifier described here and is depicted in
Fig. 4.
IV. M EASUREMENT R ESULTS FOR THE A SSEMBLED
A MPLIFIER
50 Ω TL
GSG-pads
MMIC
Bondwires
50 Ω TL
RF laminate
Via holes
Fig. 4. MMIC mounted on top of an rf-laminate. Via-holes of the rf-laminate
provide a good ground to the backside-metalization of the MMIC.
A micrography of the assembled amplifier is shown in
Fig. 5.
On the top right, one can see a detailed view of the amplifier
MMIC. Two bond-wires in parallel are used for connecting the
Measurements of the small signal parameters of the amplifier are carried out with a single supply which provides a
drain voltage of 3.0 V and a current of 55 mA, resulting in
a total power consumption of 165 mW. The drain biasing is
applied via the internal bias-Tee of the used vector network
analyzer. Alternatively the drain biasing can be applied via
the reverse drain line termination, see [3]. This would provide
the advantage that no external bias-Tee is needed, but at the
expense of an increased power consumption. The gate of the
common source transistors is grounded via the 50 Ω resistor of
the artifical gate line termination. No additional gate biasing
is used for both, the common source and the common gate
transistor. Applying biasing to the gates could slightly improve
gain flatness and overall gain performance, but at the expense
of increased assembly effort and therefore cost. The small
signal measurements of the assembled amplifier are shown
in Fig. 6.
Near dc, the gain equals to 11.3 dB due to an external resistor of 10 Ω used for decoupling of the on-chip capacitances
and the bond-wire inductance. This resistor was not included
into original simulations and therefore results in a slightly
increased gain at low frequencies. However, this problem can
be easily overcome with a modified chip design as is shown
Gain (S21) / Reflection [dB]
[5] M. Häfele, A. Trasser, K. Beilenhoff, and H. Schumacher, “A GaAs
Distributed Amplifier with an Output Voltage of 8.5 Vpp for 40 Gb/s
Modulators,” in Proc. 13 th Gallium Arsenide and other Compound
Semiconductors Application Symposium, Paris, France, Oct. 2005, pp.
345–348.
10
Measured S21
Measured S11
Measured S22
0
-10
-20
-30
0
10
20
30
40
50
Frequency f [GHz]
Fig. 6.
Measured small-signal performance of the mounted low-noise
amplifier biased with a drain voltage of 3 V. At 2.0 GHz the gain equals
to 10.4 dB with a −3 dB bandwidth of 48.5 GHz. Due to the external bias
decoupling, the gain increases to 11.3 dB close to dc.
for example in [5]. Input and output reflections are better than
−12 dB up to 30 GHz. Over the whole measurement bandwidth
of 50 GHz reflections are still less than −5 dB.
V. S UMMARY
In this paper we presented new measurement results up to
110 GHz for an earlier published amplifier [3]. A drain biasing
of 3 V results in a gain of 10.5 dB ± 1.0 dB up to 60 GHz
and a -3dB bandwidth in excess of 62 GHz. This amplifier is
then mounted on top of a Teflon based rf-laminate (Ro5880)
with 50 Ω transmission lines at the input and output of the
amplifier. A via-hole process was developed for the rf-laminate
to enable easy attachment of the amplifier and SMD components needed for off-chip drain bias decoupling. Rosenberger
09K243-40ME3 connectors are used to enable attachment to
2.4 mm connectors. The assembled amplifier shows a gain of
10.4 dB at 2 GHz with a -3dB cut-off frequency of 48.5 GHz.
A bandwidth extension to lower frequencies is possible by a
redesign of the on-chip termination network of the MMIC.
Input and output reflections are better than −12 dB up to
30 GHz.
VI. ACKNOWLEDGMENTS
The authors would like to thank the "Fraunhofer Institute for
Reliability and Microintegration IZM" for performing smallsignal measurements of the amplifier MMIC up to 110 GHz.
R EFERENCES
[1] T. Shibata, S. Kimura, H. Kimura, Y. Imai, Y. Umeda, and Y. Akazawa,
“A Design Technique for a 60 GHz-Bandwidth Distributed Baseband
Amplifier IC Module,” IEEE Journal of Solid-State Circuits, vol. 29,
no. 12, pp. 1537–1544, Dec. 1994.
[2] K. Takahata, Y. Muramoto, H. Fukano, K. Kato, A. Kozen, S. Kimura,
Y. Imai, Y. Miyamoto, O. Nakajima, and Y. Matsuoka, “Ultrafast
Monolithic Receiver OEIC Composed of Multimode Waveguide p-i-n
Photodiode and HEMT Distributed Amplifier,” IEEE Journal of Selected
Topics in Quantum Electronics, vol. 6, no. 1, pp. 31–37, Feb. 2000.
[3] M. Häfele, K. Beilenhoff, and H. Schumacher, “A GaAs PHEMT Distributed Amplifier with Low Group Delay Time Variation for 40 GBit/s
Optical Systems,” in Proc. 33 th European Microwave Conf., Munich,
Germany, Oct. 2003, pp. 1091–1094.
[4] W. Heinrich, “The Flip-Chip Approach for Millimeter-Wave Packaging,”
IEEE Microwave Magazine, vol. 6, no. 3, pp. 36–45, Sep. 2005.