FABRICATION
3 EXAMPLES
Fabrication Example 1
• The example shows a 2‐D side view of the fabrication steps for the following
– A single NMOS transistor
– Metal1 contacts
– Metal1 layer
EEC 116, Winter 2010, B. Baas
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1
Fabrication – Patterning of SiO2
• Grow SiO2 on Si by exposing to O2
– high temperature accelerates this process
• Cover surface with photoresist (PR)
– Sensitive to UV light (wavelength determines feature size)
– Positive PR becomes soluble after exposure
– Negative PR becomes insoluble after exposure
EEC 116, Winter 2010, B. Baas
Source: CMOS Digital Integrated Circuits
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Fabrication – Patterning of SiO2
• Photoresist removed with a solvent
• SiO2 removed by etching (HF)
• Remaining photoresist removed with another solvent
EEC 116, Winter 2010, B. Baas
Source: CMOS Digital Integrated Circuits
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2
NMOS Transistor Fabrication
• Thick field oxide grown
• Field oxide etched to create area for transistor
• Gate oxide (high quality) grown
EEC 116, Winter 2010, B. Baas
Source: CMOS Digital Integrated Circuits
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NMOS Transistor Fabrication
• Polysilicon deposited (doped to reduce R)
• Polysilicon etched to form gate
• Gate oxide etched from source and drain
– Self‐aligned process because source/drain aligned by gate
• Si doped with donors to create n+ regions
EEC 116, Winter 2010, B. Baas
Source: CMOS Digital Integrated Circuits
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3
NMOS Transistor Fabrication
•
•
•
•
Insulating SiO2 grown to cover surface/gate
Source/Drain regions opened
Aluminum evaporated to cover surface
Aluminum etched to form metal1 interconnects
EEC 116, Winter 2010, B. Baas
Source: CMOS Digital Integrated Circuits
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Fabrication Example 2
• The example shows a 3‐D view of the fabrication steps for the following
– A CMOS inverter
• A single NMOS transistor
• A single PMOS transistor
– Metal1 contacts
– Metal1 layer
EEC 116, Winter 2010, B. Baas
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4
Inverter Fabrication
• Inverter
– Logic symbol
– CMOS inverter circuit
– CMOS inverter layout (top view of lithographic masks)
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EEC 116, Winter 2010, B. Baas
Inverter Fabrication
• N‐wells created
• Thick field oxide grown surrounding active regions
• Thin gate oxide grown over active regions
EEC 116, Winter 2010, B. Baas
Source: CMOS Digital Integrated Circuits
29
5
Inverter Fabrication
• Polysilicon deposited
– Chemical vapor deposition(Places the Poly)
– Dry plasma etch(Removes unwanted Poly)
EEC 116, Winter 2010, B. Baas
Source: CMOS Digital Integrated Circuits
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Inverter Fabrication
• N+ and P+ regions created using two masks
– Source/Drain regions
– Substrate contacts
EEC 116, Winter 2010, B. Baas
Source: CMOS Digital Integrated Circuits
31
6
Inverter Fabrication
• Insulating SiO2 deposited using CVD
• Source/Drain/Substrate contacts exposed
EEC 116, Winter 2010, B. Baas
Source: CMOS Digital Integrated Circuits
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Inverter Fabrication
• Metal (Al) deposited using evaporation
– Meta1 contacts made with Aluminum here
• Metal patterned by etching
EEC 116, Winter 2010, B. Baas
Source: CMOS Digital Integrated Circuits
33
7
Fabrication Example 3
• The example shows a 2‐D side view of the fabrication steps for the following
– A CMOS inverter
• A single NMOS transistor
• A single PMOS transistor
–
–
–
–
Metal1 contacts
Metal1 layer
Metal2 vias
Metal2
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EEC 116, Winter 2010, B. Baas
CMOS Process Walk-Through
p-epi
(a) Base material: p+ substrate
with p-epi layer
p+
SiN
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p-epi
p+
p+
EEC 116, Winter 2010, B. Baas
SiO
2
(b) After deposition of gate-oxide and
sacrificial nitride (acts as a
buffer layer)
(c) After plasma etch of insulating
trenches using the inverse of
the active area mask
Source: Digital Integrated Circuits, 2nd ©
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8
CMOS Process Walk-Through
SiO
2
(d) After trench filling, CMP
planarization, and removal of
sacrificial nitride
n
(e) After n-well and
V
adjust implants
Tp
p
(f) After p-well and
V
adjust implants
Tn
Source: Digital Integrated Circuits, 2nd ©
EEC 116, Winter 2010, B. Baas
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CMOS Process Walk-Through
poly(silicon)
(g) After polysilicon deposition
and etch
n+
p+
(h) After n+ source/drain and
p+source/drain implants. These
steps also dope the polysilicon.
SiO
2
(i) After deposition of SiO
insulator and contact hole2etch.
EEC 116, Winter 2010, B. Baas
Source: Digital Integrated Circuits, 2nd ©
37
9
CMOS Process Walk-Through
Al
(j) After deposition and
patterning of first Al layer.
Al
SiO
2
(k) After deposition of SiO
insulator, etching of via’s, 2
deposition and patterning of
second layer of Al.
EEC 116, Winter 2010, B. Baas
Source: Digital Integrated Circuits, 2nd ©
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ADVANCED METAL
INTERCONNECT EXAMPLES
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Four Levels of Metal Example
EEC 116, Winter 2010, B. Baas
Source: Digital Integrated Circuits, 2nd ©
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Advanced Metallization
EEC 116, Winter 2010, B. Baas
Source: Digital Integrated Circuits, 2nd ©
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Microprocessor
Interconnect
• Future microprocessor interconnect
• 8 levels of metal
• Steadily increasing pitch and thickness with higher levels for higher performance
m8
m7
m6
m5
m4
m3
m2
m1
Source: IBM
42
EEC 116, Winter 2010, B. Baas
Source: ITRS Interconnect, 2005
ASIC
Interconnect
m8
• Future Application Specific IC (ASIC) interconnect
• 8 levels of metal
• More regular structure
– Semi‐global is 2x Intermediate pitch
– Global is 4x Intermediate pitch
m7
m6
m5
m4
m3
m2
m1
Source: IBM
EEC 116, Winter 2010, B. Baas
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Source: ITRS Interconnect, 2005
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IBM
90 nm
• 64‐bit micro‐
processor
• (1) Al(Cu) [top]
• (2) 6x Cu
• (3) 2x Cu
• (5) 1x Cu
• (1) W local [bottom]
– 0.12 μm width & spacing
Source: IBM
EEC 116, Winter 2010, B. Baas
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