EEE 4310 DIGITAL INTEGRATED CIRCUIT DESIGN
EEE 5322 VLSI CIRCUITS AND TECHNOLOGY SYLLABUS
Instructor’s or Course Coordinator’s Name: Dr. William R. Eisenstadt
Course Outline: (See EDGE Produced Course Video Lectures Tab in Canvas for Streaming
Videos and Video Downloads)
Weekly Date(s), (No. of Classes) Class topics, Readings, In Class Notes in pdf form.
05/09 (3) Moore’s Law, History and Future of Computing, Chipworks tear down of a mobile
computer (iPhone and iPad), Design Rules Syllabus (this document),
Read Jaeger Chapter 1, Chap. 2 .1, 2.2 and 2.3 of Rabaey, 1.2, 1.3.1
Homework 1
In Class Notes Lecture 1, In Class Notes, Lecture 2, In Class Notes Lecture 3
05/16 (3) Design Rules, Contacts and Interconnects, MOS Process Integration and State of the
art CMOS planar and FinFET SOC process flow: 28nm, 20nm, 14nm, 10nm Logic
Technologies and advanced layout issues: Optical Proximity correction and Restrictive
Read Chap. 2 .1, 2.2 and 2.3 of Rabaey, 1.2, 1.3.1, 7. Chap. 7 Jaeger and handouts
In Class Notes Lecture 4, In Class Notes Lecture 5, In Class Notes Lecture
05/23 (3) and 6/01 (2) (Memorial Day Holiday May 30, 2016), What is VLSI, Cadence Design
Training, Statistics Review, and Introduction to micro fabrication with emphasis on process
variation.
Chapter 9 Jaeger, Chap. 5 .1, 5.2, 5.3, 5.4 of Jaeger, plus handouts and Chipworks reverse
engineering reports
In Class Notes Lecture 7, In Class Notes Lecture 8, In Class Notes Lecture 9,
In Class Notes Lecture 10, In Class Lecture 11, In Class Lecture 12,
06/06 (3) and 6/13 (3) Midterm 1 week of 6/06, CMOS Logic, DRAM, NAND, CMOS image
sensor chips fabrication, bit cell or pixel cell, and array architecture. Layout Layers and Xsections Design Rules.
Read Chap. 8.7 of Jaeger, Chapter 2.2 and Chap. 4.1 to 4.3 Rabaey plus handouts
In Class Lecture 13, In Class Lecture 14,
In Class Lecture 15, In Class Lecture 16, In Class Lecture 17,
06/20 (0) Summer Break, have a good vacation
06/27 (3) and 7/6 (2) (Independence Day Holiday, July 4, 2016) Layout Layers and X-sections
Design Rules, Resistance, Capacitance, MOSFET, MOS Transistors,
Read Chap. 4.1 to 4.3 and Chap. 3.3 of Rabaey and 9.2, 9.3 Jaeger
In Class Lecture 18, In Class Lecture 19, In Class Lecture 20
In Class Lecture 21, In Class Lecture 22,
07/11/ (3) and 7/18 (3) (Midterm 2 week of 7/11): CMOS Inverters, Combinational Logic
Read Chap. 5 of Rabaey
In Class Lecture 23, In Class Lecture 24,
In Class Lecture 25, In Class Lecture 26, In Class Lecture 27,
7/18 (3) Compound Gates, Transmission Gates, Memory
Read Chapter 6 and Chapter 12 of Rabaey
In Class Lecture 28, In Class Lecture 29, In Class Lecture 30,
7/25 (3) Memory, Pseudo NMOS, Pass Trans. Logic, Pre-charge Logic
Read Chapter 6 and Chapter 12 of Rabaey
In Class Lecture 31, In Class Lecture 32, In Class Lecture 33,
08/01 (3) (Final Exam week of 8/01) Dynamic Logic, Domino Logic, Logic Comparison, Noise
Read Chapter 6 of Rabaey
In Class Lecture 34, In Class Lecture 35,
Professor: William R. Eisenstadt,
Office: 529 NEB
Telephone: (352) 392-4946
Facsimile: (352) 392-8381
Email: wre@tec.ufl.edu
Web: http://www.tec.ufl.edu/~wre/
Admin. Assistant: Marcy Lee
Office: 440 NEB
Telephone: 352-846-0203
Email: marcy@ece.ufl.edu
Class Period and Location: 6th period, MWF, 3:30pm to 4:45pm, Room NEB 201.
Credits and Contact Hours: 3 credits; 3 classes per week of 65 minutes each
Catalog Description: Fabrication, Layout, Analysis and design of digital and circuits using
MOS Transistor.
Prerequisites or Co-requisites: EEL 3396, EEL 3308, or an Electrical Engineer Undergraduate
Degree
Office Hours: MWF 1:45 pm to 3:00 pm
TA: Anem Mouli, Office hours, TBA, Contact Info: mouli619@ufl.edu
Required Texts: Richard C. Jaeger, "Introduction to Microelectronic Fabrication," Second
Edition, Modular Series on Solid State Devices, Volume 5, Prentice Hall, ISDN 0-201-44494-7,
2002.
Jan. M. Rabaey, A. Chandrakasan, and B.Nikolic, "Digital Integrated Circuits, A Design
Perspective," 2nd Edition, Prentice Hall, ISDN 0-13-090996-3, 2003.
Course Goals: To develop proficiency in analyses, design and implementation of CMOS
circuits. To develop understanding of interdependence of CMOS circuit design with process
technology and IC manufacturing. To be a designer in modern CMOS processes with high level
of manufacturing variations.
EDGE Students: The EDGE studio will post recorded lectures in the Course Video Lectures
section of Canvas (see tabs on the left of the screen). I will give you up to 2 extra days (48 hours)
to complete and turn in class assignments and during the regular semester. Midterm exams will
have to be taken within a day of the in class exam. The EDGE final exam must be taken the same
day as the in class final and returned to the instructor that day.
Course Materials: I will be using the Syllabus to index of the daily class materials posted for
you to review and to learn from. So, you can find most learning materials by clicking on a link
from the Syllabus. I try to post all written materials and video materials used in the lectures to
assist in your learning. There will be folders that contain course materials (Course Notes, Old
Exams, Cadence notes, In Class Notes, etc) in the Resources section of Canvas (see tabs on the
left of this section).
Computer and Software Required:
Workstations with CADENCE Design system on campus, off-campus can use X-Windows or an
X-terminal on a high-speed internet link to UF Campus Computers, or can use equivalent IC
design software.
All students are required to have a Gator link account and use Canvas for course handouts, grade
information, course notices, etc., see e-learning support services
Course Study Requirements:
Students are responsible to study all in class materials including those written on the board and
presented orally, all Class Handouts all assigned readings, all projects and homework. Absence
from class can result in missing materials tested on exams.
Attendance and Expectations: Attendance is not required except for on-campus students during
the exams. This is an EDGE course so students are required to watch the class video for each
lecture. There is a no wireless device policy (no cell phones, smart phones, computers, tablets,
etc.) during exams.
Catalog Description: Introduction to VLSI circuit technology and manufacturing. Fabrication,
device models, layout, parasitics, and simple gate circuits.
Make Up Exam Policy: Students are expected to attend exams at the scheduled times. Exams
can be made up if there is a genuine medical emergency with a doctor's or clinic medical note or
a family emergency with some documentation. Students are NOT excused from exams for job
interviews and early holiday travel home. Students with other non-emergency exam scheduling
issues must obtain permission from the instructor prior to missing an exam.
Work Requirements:
Homework
Computer Laboratories and projects
Exams: Quizzes, Midterms and Final
Examinations: Quizzes as assigned
Midterm 1: Tentatively, 5th Week of the Summer semester
Midterm 2: Tentatively, 9th Week of the Summer Semester.
Final Exam: First week of August.
Grades will be on a curve and your relative statistical performance to the class average
grades counts, not your absolute numerical performance. For example, if you have a 91
average and the class median is 90 (not likely) you will get a B. You must be significantly
better than average to get an A.
Preliminary Grading Policy:
Homework - 10%
Projects - 15%
Midterms and Quizzes- 75%
Current UF Grading Policy for assigning grade points
https://catalog.ufl.edu/ugrad/current/regulations/info/grades.aspx.
Academic Honesty:
“UF students are bound by The Honor Pledge which states, “We, the members of the University
of Florida community, pledge to hold ourselves and our peers to the highest standards of honor
and integrity by abiding by the Honor Code. On all work submitted for credit by students at the
University of Florida, the following pledge is either required or implied: “On my honor, I have
neither given nor received unauthorized aid in doing this assignment.” The Honor Code
(http://www.dso.ufl.edu/sccr/process/student-conduct-honor-code/) specifies a number of
behaviors that are in violation of this code and the possible sanctions. Furthermore, you are
obligated to report any condition that facilitates academic misconduct to appropriate personnel.
If you have any questions or concerns, please consult with the instructor or TAs in this class.”
Software Use – All faculty, staff and student of the University are required and expected to obey
the laws and legal agreements governing software use. Failure to do so can lead to monetary
damages and/or criminal penalties for the individual violator. Because such violations are also
against University policies and rules, disciplinary action will be taken as appropriate. We, the
members of the University of Florida community, pledge to uphold ourselves and our peers to
the highest standards of honesty and integrity
Students with Disabilities
“Students with disabilities requesting accommodations should first register with the Disability
Resource Center (352-392-8565, www.dso.ufl.edu/drc/) by providing appropriate
documentation. Once registered, students will receive an accommodation letter which must be
presented to the instructor when requesting accommodation. Students with disabilities should
follow this procedure as early as possible in the semester.”
Course Evaluations
“Students are expected to provide feedback on the quality of instruction in this course by
completing online evaluations at https://evaluations.ufl.edu. Evaluations are typically open
during the last two or three weeks of the semester, but students will be given specific times when
they are open. Summary results of these assessments are available to students at
https://evaluations.ufl.edu/results/.”