2102-545 Digital Integrated Circuits

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2102-545 Digital Integrated Circuits
1st Semester, 2005
Course Syllabus
Instructor:
Boonchuay Supmonchai
Office: Rm. 105, Eng. Bldg. 1
Tel: 02-218-6541 Ext. 12
Email: [email protected]
Time: 15:30-17:00 Monday
12:30-14:00 Thursday
Room: Engineering Bldg. 4, 12th floor, Power System Laboratory
Office Hour: 9:00-11:00 Friday or By Appointment
Text:
•
Rabaey, Chandrakasan, and Nikolic, Digital Integrated Circuits: A Design
Perspective, 2nd ed., Prentice Hall, 2003.
Reference Texts:
1. Weste and Harris, CMOS VLSI Design: A Circuits and Systems Perspective, 3rd ed.,
Addison-Wesley, 2005.
2. Baker, CMOS: Circuit Design, Layout, and Simulation, 2nd ed.,Wiley Inter-Science,
2005.
3. Uyemura, Chip Design for Submicron VLSI: CMOS Layout and Simulation, ThomsonEngineering, 2005.
4. Hodges, Jackson, and Saleh, Analysis and Design of Digital Integrated Circuits: In
Deep Submicron Technology, 3rd ed., McGraw-Hill, 2004.
5. Kang and Leblebici, CMOS Digital Integrated Circuits: Analysis and Design, 3rd ed.,
McGraw-Hill, 2003.
6. Uyemura, Introduction to VLSI Circuits and Systems, John Wiley, 2001.
Grading Scheme:
Assignments
Midterm
Final
2 Mini Project
20%
20%
20%
40% (2 x 20%)
Tentative Program:
Lecture
No.
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
28
29
26
27
30
Topics
Course Overview and Organization
Introduction to Digital IC Design.
MOS Transistor Theory I
MOS Transistor Theory II
Interconnect I: Wire Models
Tutorial I: Circuit Simulation
MOS Processing Technology
Layout Design Rules
Tutorial II: Introduction to Design Tools
CMOS Inverter Circuits I
CMOS Inverter Circuits II
Mini Project I Assignment
CMOS Inverter Circuits III
Combinational Logic Circuits: Static I
Combinational Logic Circuits: Static II
Logical Efforts
Combinational Logic Circuits: Dynamic
Midterm
Sequential Logic Circuits: Static
Sequential Logic Circuits: Dynamic, Pipelining
Circuit Families: Bipolar, Differential Logics
Implementation Strategies for Digital ICs
Tutorial III: Design Synthesis Strategies
Interconnect II: Chip-Scale View
Timing Issues in Digital ICs I
Timing Issues in Digital ICs II
Mini Project II Assignment
Arithmetic Building Blocks: Adders, Multipliers
Arithmetic Building Blocks: Shifters, Decoders
Memory and Array Structures I
Memory and Array Structures II
Design for Low-Power
Design for Skew-Tolerant
Digital IC Testing I
Digital IC Testing II
Final
Tour: There will be one tour to the Fabrication Plant.
Chapter
Date
1
3.1-3.2
3.3-3.7
4
9 June
13 June
16 June
20 June
23 June
2
Note
27 June
30 June
5.1-5.3
4 July
7 July
5.4-5.5
Remark
Asgn. 1
Asgn. 1 Due
11 July
14 July
18 July
Asgn. 2
Asgn. 2 Due
7.1-7.3
7.5-7.6
Note
21 July
28 July
1 Aug
4 Aug
8 Aug
8
11 Aug
9
10.1-10.3
10.3
15 Aug
18 Aug
22 Aug
11.1-11.3
11.4-11.10
12.1-12.2
12.2
Note
Note
Note
Note
25 Aug
29 Aug
1 Sept.
5 Sept.
8 Sept.
12 Sept.
15 Sept.
19 Sept.
22 Sept.
5.6-5.8
6.1-6.2
6.2
6.3-6.6
Asgn. 3
Mini Proj. 1
Due
Asgn. 3 Due
Asgn. 4
Asgn. 4 Due
Mini Proj. 2
Due
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