Digital Integrated Circuit Design
Lecture 10 – Dynamic CMOS
CLK
inputs
PCLK
NMOS
Logic
Circuit
N CLK
Adib Abrishamifar
EE Department
IUST
Contents
}
}
}
}
}
}
}
Introduction
Dynamic CMOS Logic
CMOS Domino Logic
CD Domino Logic
Dynamic CVSL
Sample-Set Differential Logic (SSDL)
Summary
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LECTURE 10 : Dynamic CMOS
Adib Abrishamifar 2008
Introduction
} As mentioned before Digital MOS circuits can be classified
into two categories:
} Static Circuits: require no clock or other periodic signal for
operation (except sequential logic). In these circuits at every
point in time (except when switching) the output is connected
to either GND or Vdd via a low resistance path
} fan-in of N requires 2N devices (n N-type + n P-type)
} Dynamic Circuits: require periodic clock signals, synchronized
with data signals, for proper operation even in combinational
logic. These circuits rely on the temporary storage of signal
values on the (parasitic) capacitance of high impedance nodes
} requires only N + 2 transistors (n+1 N-type + 1 P-type)
} takes a sequence of precharge and conditional evaluation
phases to realize logic functions
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Adib Abrishamifar 2008
Introduction
} Why Dynamic Logic?
} In the area of high speed, higher Fan-in, extremely low
power dissipation, other digital logic circuit have been
considered. In this lecture, two of these alternatives to
CMOS are described. The circuits are basically NMOS or
CMOS Gates with slight improvements. These are:
} Dynamic CMOS Logic
} CMOS Domino Logic
} Each of them have specific operating advantages over
NMOS or CMOS, but exhibit disadvantages in other areas
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LECTURE 10 : Dynamic CMOS
Adib Abrishamifar 2008
Contents
}
}
}
}
}
}
}
Introduction
Dynamic CMOS Logic
CMOS Domino Logic
CD Domino Logic
Dynamic CVSL
Sample-Set Differential Logic (SSDL)
Summary
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Adib Abrishamifar 2008
Dynamic CMOS Logic
}
}
Dynamic Gates use a clocked PMOS pullup
Two modes: precharge and evaluate
2
A
Y
1
A
Static
f
2/3
1
Y
4/3
A
Pseudo-NMOS
Precharge
Evaluate
Y
1
Dynamic
Precharge
Y
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Adib Abrishamifar 2008
Dynamic CMOS Logic
} The Foot
} What if pulldown network is ON during precharge?
} Use series evaluation transistor to prevent fight
f
precharge transistor
Y
Y
inputs
A
Y
inputs
f
f
foot
footed
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unfooted
Adib Abrishamifar 2008
Dynamic CMOS Logic
} Dynamic CMOS Logic
} To make the gate dynamic, a
clock pulse is applied to the gate
of complementary P and N
channel
devices.
This
gate
consists of an NMOS Logic circuit
whose output node is precharged
to Vdd by the PMOS, when the
clock is zero. The output node is
discharged
by
the
NMOS
transistor connected to ground
when the clock is high
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CLK
inputs
LECTURE 10 : Dynamic CMOS
PCLK
NMOS
Logic
Circuit
N CLK
Adib Abrishamifar 2008
Dynamic CMOS Logic
} Dynamic CMOS Logic
Precharge (Clk = 0)
Evaluate (Clk = 1)
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Adib Abrishamifar 2008
Dynamic CMOS Logic
} Once the output of a dynamic gate is discharged, it cannot
be charged again until the next precharge operation
} Inputs to the gate can make at most one transition during
evaluation
} Output can be in the high impedance state during and after
evaluation (PDN off), state is stored on CL
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Dynamic CMOS Logic
} Canonical Forms
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Dynamic CMOS Logic
} Properties of Dynamic Gates
} Logic function is implemented by the PDN only
• should be smaller in area than static complementary CMOS
} Full swing outputs (VOL = GND and VOH = VDD)
} Nonratioed - sizing of the devices is not important for proper
functioning (only for performance)
} Faster switching speeds
• reduced load capacitance due to lower number of transistors per
gate (Cint) so a reduced logical effort
• reduced load capacitance due to smaller fan-out (Cext)
• no Isc, so all the current provided by PDN goes into discharging
CL
• Ignoring the influence of precharge time on the switching speed
of the gate, tpLH = 0 but the presence of the evaluation transistor
slows down the tpHL
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LECTURE 10 : Dynamic CMOS
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Dynamic CMOS Logic
} Properties of Dynamic Gates
} Power dissipation should be better
• consumes only dynamic power – no short circuit power
consumption since the pull-up path is not on when evaluating
• lower CL- both Cint (since there are fewer transistors connected
to the drain output) and Cext (since there the output load is one
per connected gate, not two)
} But power dissipation can be significantly higher due to
• higher transition probabilities
• extra load on CLK
} PDN starts to work as soon as the input signals exceed VTn,
so set VM, VIH and VIL all equal to VTn
• low noise margin (NML)
} Needs a precharge/evaluate clock
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LECTURE 10 : Dynamic CMOS
Adib Abrishamifar 2008
Dynamic CMOS Logic
} Leakage Sources
} Subthreshold conduction
} Transistors can’t abruptly turn
ON or OFF
} Reverse-biased
PN
junction
diode current
tox
VDD trend
106
0. 6 nm
0. 8 nm
103
1. 0 nm
1. 2 nm
100
1. 5 nm
)
JG A/cm 2 )
• Is depends on doping levels And area
and perimeter of diffusion regions,
typically < 1 fA/mm2
109
} Gate Leakage
• Carriers may tunnel thorough very thin
gate oxides
• Negligible for older processes
1. 9 nm
10-3
10-6
10-9
0
0.3
0.6
0.9
1.2
1.5
1.8
VDD
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LECTURE 10 : Dynamic CMOS
Adib Abrishamifar 2008
Dynamic CMOS Logic
} Leakage Sources
} Output settles to an intermediate voltage determined by a resistive
divider of the pull-up and pull-down networks
} Once the output drops below the switching threshold of the fan-out
logic gate, the output is interpreted as a low voltage
CLK
V o lta g e (V )
2.5
1.5
Out
0.5
-0.5
0
20
40
Time (ms)
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Dynamic CMOS Logic
} Leakage Sources
} Subthreshold leakage is dominant in modern transistors
CLK
Evaluate
VOut
Precharge
Leakage sources
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Adib Abrishamifar 2008
Dynamic CMOS Logic
} Solution to Charge Leakage
Keeper
Clk
Mp M kp
A
CL
Out
B
Clk
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Me
LECTURE 10 : Dynamic CMOS
Adib Abrishamifar 2008
Dynamic CMOS Logic
}
Charge Sharing
} Charge stored originally on CY is redistributed (shared) over CX
leading to static power consumption by downstream gates and
possible circuit malfunction
} When ΔVout = - Vdd (CX / (CX + CY )) the drop in Vout is large
enough to be below the switching threshold of the gate it drives
causing a malfunction
f
f
A
B=0
A
Y
CY
x
Cx
Y
Charge sharing noise
x
V x =V Y =
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LECTURE 10 : Dynamic CMOS
CY
V dd
C x + CY
Adib Abrishamifar 2008
Dynamic CMOS Logic
}
Solution to Charge Redistribution
} Add secondary precharge transistors (at the cost of
increased area and power)
• Typically need to precharge every other node
• Secondary precharge transistors should be small because their
diffusion capacitance slows the evaluation (increase delay)
• Big load capacitance CY helps as well
Y
A
secondary
precharge
transistor
x
B
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Dynamic CMOS Logic
}
Charge Sharing Example
} What is the worst case voltage drop on y? (Assume all
inputs are low during precharge and that all internal nodes
are initially at 0V)
CLK
a
Ca =15fF
B
c
Cc =15fF
y=A
A
A
B
B
C
C
B
C
Load
inverter
Cy =50fF
b
B
d
Cb =15fF
Cd =10fF
CLK
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LECTURE 10 : Dynamic CMOS
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Dynamic CMOS Logic
}
Charge Sharing Example
(
)
DVout = -Vdd é( Ca + Cc ) Ca + Cc + C y ù
ë
û
= -2.5V ( 30 ( 30 + 50 ) ) = -0.94V
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Dynamic CMOS Logic
} Backgate Coupling
} Susceptible to crosstalk due to
• High impedance of the output node
• Capacitive coupling
– Out2 capacitively couples with Out1 through the gate-source and gatedrain capacitances of M4
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Dynamic CMOS Logic
} Backgate Coupling
} Capacitive coupling means Out1 drops significantly so Out2
doesn’t go all the way to ground
Voltage
3
Due to clk feedthrough
2
1
Out1
Due to backgate
Clk
0
In
Out2
2
Time, ns
-1
0
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4
LECTURE 10 : Dynamic CMOS
6
Adib Abrishamifar 2008
Dynamic CMOS Logic
} Clock Feedthrough
} A special case of capacitive
coupling between the clock
input of the precharge transistor
and the dynamic output node
due to the gate to drain
capacitance
} So voltage of Out can rise above
Vdd. The fast rising (and falling
edges) of the clock couple to
Out
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Clk
Mp
Out
A
CL
B
Clk
LECTURE 10 : Dynamic CMOS
Me
Adib Abrishamifar 2008
Dynamic CMOS Logic
} Clock Feedthrough
Clock feedthrough
2.5
Voltage
1.5
In &
Clk
0.5
Out
-0.5
0
0.5
Time, ns
1
Clock feedthrough
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Dynamic CMOS Logic
} Other Effects
}
}
}
}
}
Capacitive coupling
Substrate coupling
Minority charge injection
Supply noise (Ground bounce)
Floating output nodes
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Dynamic CMOS Logic
} Floating output nodes
} Solutions:
• Only connect to gates
• Add staticizer to refresh the charge
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Dynamic CMOS Logic
} Advantages:
} For n inputs, dynamic logic requires
n+2 transistors
} have small area, high speed and
compact layouts
CLK
PCLK
} Disadvantages:
} Circuit operation is more complex
due to the required clock
} The inputs can only change during
the precharge phase and must be
stable during the evaluate portion of
the cycle
} Need Monotonicity
inputs
NMOS
Logic
Circuit
N CLK
• can not be cascaded
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Dynamic CMOS Logic
} Monotonicity
} Dynamic gates require monotonically rising inputs
during evaluation
violates monotonicity
during evaluation
A
f
Precharge
Evaluate
Precharge
f
A
Y
Output should rise but does not
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Dynamic CMOS Logic
}
Monotonicity Woes
} Dynamic gates produce monotonically falling outputs during
evaluation
} Illegal for one dynamic gate to drive another!
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Dynamic CMOS Logic
V
} Cascading
Clk
In
Out1
VTn
DV
Out2
t
Only 0 ® 1 transitions allowed at inputs!
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Dynamic CMOS Logic
} Cascading
} Input going from high to low during evaluation
• a is 5V when precharge b = 5V, c = 5V
• During evaluation:
– Wanted: b à 0V, c à 5V
– But, b takes some time to drop to 0V
– Consequently, c may fall to some unknown value
} Solution
} NP-CMOS
} NORA Logic
} Domino logic
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b
c
a
LECTURE 10 : Dynamic CMOS
Adib Abrishamifar 2008
Dynamic CMOS Logic
} NP-CMOS
} Only 0 ® 1 transitions allowed at inputs of PDN
} Only 1 ® 0 transitions allowed at inputs of PUN
Clk
Mp
1
1
In1
In2
PDN
1
0
Out1
Clk
Me
In4
PUN
In5
0
0
In3
Clk
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Clk
Mp
0
1
Out2
(to PDN)
LECTURE 10 : Dynamic CMOS
Adib Abrishamifar 2008
Dynamic CMOS Logic
} NORA Logic
} WARNING: Very sensitive to noise!
Clk
Mp
1
1
1
0
Out1
In1
In2
In3
Clk
PDN
Me
In4
In5
PUN
0
0
Clk
Me
to other
PDN’s
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0
1
Mp
Out2
(to PDN)
to other
PUN’s
LECTURE 10 : Dynamic CMOS
Adib Abrishamifar 2008
Dynamic CMOS Logic
} An example
Y=AB+C
A
B
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LECTURE 10 : Dynamic CMOS
C
Adib Abrishamifar 2008
Dynamic CMOS Logic
} Dynamic 4 Input NAND Gate
VDD
Out
In1
In2
In3
In4
f
GND
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Dynamic CMOS Logic
} Power Consumption
} Power only dissipated when previous Out = 0
CLK
Mp
Out
In1
In2
CL
PDN
In3
CLK
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Me
LECTURE 10 : Dynamic CMOS
Adib Abrishamifar 2008
Dynamic CMOS Logic
} Power Consumption
} Dynamic Power Consumption is Data Dependent
• Assume signal probabilities (Dynamic 2-input NOR Gate)
•
PA=1 = 1/2
•
PB=1 = 1/2
A
B
Out
• Then transition probability
0
0
1
•
P1→0 = Pout=0 = ¾
0
1
0
1
0
0
1
1
0
} Switching activity can be higher in dynamic gates!
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Dynamic CMOS Logic
} Rules of Thumb
}
}
Dynamic logic is best for wide OR/NOR structure (e.g. bitlines), providing 50% delay improvement over static CMOS
Dynamic logic consumes 2x power due to its phase activity
(unconditional pre-charging), not counting clock power
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Dynamic CMOS Logic
} Notes
} No need to implement the complement of the function,
leading to smaller area
} We can avoid the long PMOS chains
} Handle the charge sharing problem and floating output
nodes
} Input transistors should not change from on to off
during evaluation
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Contents
}
}
}
}
}
}
}
Introduction
Dynamic CMOS Logic
CMOS Domino Logic
CD Domino Logic
Dynamic CVSL
Sample-Set Differential Logic (SSDL)
Summary
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CMOS Domino Logic
} It is an extension of dynamic CMOS gates that allow
cascading of stages
} The simple modification entails incorporating a static
CMOS inverter at the output of each logic gate
domino AND
W
X
Y
Z
A
B
C
f
dynamic static
NAND inverter
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CMOS Domino Logic
} Stage A should be precharged in Φ1 and evaluate in Φ2
} Stage B should be precharged in Φ2 and evaluate in Φ1
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CMOS Domino Logic
} During precharge (clk=0), the output node of the dynamic
gate is precharged high and the output node of the CMOS
inverter is low. Then subsequent stages will be turned off
during the precharge phase
} When the clk=1, the output of the driving gate will
conditionally discharge, allowing the output of the inverter
to conditionally go high. Each connected gate output can
then make a transition from low-to-high, in sequence
} There is no restriction on the number of logic stages that
can be cascaded provided that all stages can evaluate
during one clock pulse
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CMOS Domino Logic
} pc = Φ1 and ev = Φ2
pc =
pc
W
V
X
Y
n- network
1
1
ev =
cycle
1
2
ev
2
precharge
evaluate
input latched
here
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output latched
here
Adib Abrishamifar 2008
CMOS Domino Logic
} Won’t work! If pc = Φ2 and ev = Φ1
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CMOS Domino Logic
} Why Domino?
} Like falling dominos!
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CMOS Domino Logic
} Produces monotonic outputs
f
domino AND
W
Precharge
Evaluate
Precharge
W
X
Y
Z
X
A
B
Y
C
f
Z
dynamic static
NAND inverter
f
A
B
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f
f
W
X
H
Y
C
LECTURE 10 : Dynamic CMOS
H
Z
=
A
B
f
X
C
Z
Adib Abrishamifar 2008
CMOS Domino Logic
}
Domino Optimizations
} Each domino gate triggers next one, like a string of dominos toppling
over
} Gates evaluate sequentially but precharge in parallel Thus evaluation
is more critical than precharge
} HI-skewed static stages can perform logic
} Static inverter can be optimized to match fan-out
f
S0
S1
S2
S3
D0
D1
D2
D3
H
Y
f
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S4
S5
S6
S7
D4
D5
D6
D7
LECTURE 10 : Dynamic CMOS
Adib Abrishamifar 2008
CMOS Domino Logic
} Leakage
} Dynamic node floats high during evaluation
• Transistors are leaky (IOFF ¹ 0)
• Dynamic value will leak away over time
• Formerly miliseconds, now nanoseconds!
} Use keeper to hold dynamic node
• Must be weak enough not to fight evaluation
weak keeper
f
A
1 k
X
H
Y
2
2
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CMOS Domino Logic
} Noise Sensitivity
} Dynamic gates are very sensitive to noise
• Inputs: VIH » Vtn
• Outputs: floating output susceptible noise
} Noise sources
•
•
•
•
•
Capacitive crosstalk
Charge sharing
Power supply noise
Feedthrough noise
And … !
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CMOS Domino Logic
} Designing with Domino Logic
}
}
If all the inputs come from other domino gates, then all the inputs will be low
during the precharge. You don’t need to explicit evaluate transistor
Need to be a little careful. When precharge begins, the first gate’s output must
precharge before the next gate can precharge. Both evaluate and precharge
ripple in this scheme. But, if there is already a tall stack, transistor ratioing will
let precharge win anyway. (but you waste power until the precharge ripples)
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CMOS Domino Logic
} Footless Domino
} The first gate in the chain needs a foot switch
Precharge is rippling – short – circuit current
} A solution is to delay the clock for each stage
VDD
Clk
VDD
Mp
Clk
Mp
Out1
0
0
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Clk
Mp
Out2
1
0
In1
1
VDD
Outn
1
0
In2
1
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0
In3
1
0
1
Inn
1
LECTURE 10 : Dynamic CMOS
0
Adib Abrishamifar 2008
CMOS Domino Logic
} Example
} During precharge, x, y, z = 1, x, y = 0
} During evaluation, x = 0 when a = b = 1
} Therefore, z = a b c d
x
a
b
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y
x
c
z
y
d
LECTURE 10 : Dynamic CMOS
Adib Abrishamifar 2008
CMOS Domino Logic
} Advantages:
} Large Fan-in, fewer transistors (n+4 transistors, whereas CMOS
requires 2n)
} Single clock can be used to precharge and evaluate all stages at the
same time
} It is attractive for high-speed circuits
} 1.5 – 2x faster than static CMOS
} Widely used in high-performance microprocessors
} Disadvantages:
}
}
}
}
}
}
Each logic block must incorporate a separate inverter
Each block performs only non-inverting logic
Monotonicity
Leakage
Charge sharing
Noise
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CMOS Domino Logic
}
Dual Rail Domino
} Domino only performs noninverting
functions
• AND, OR but not NAND, NOR, or XOR
Y_l
inputs
} Dual-rail domino solves this problem
f
sig_h
sig_l
Meaning
0
0
Precharged
0
1
‘0’
1
0
‘1’
1
1
invalid
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f
f
• Takes true and complementary inputs
• Produces true and complementary
outputs
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Y_h
f
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CMOS Domino Logic
}
Example AND/NAND
} Given A_h, A_l, B_h, B_l
} Compute Y_h = A * B, Y_l = ~(A * B)
}
Pulldown networks are conduction complements
Y_l
f
= A*B
A_l
B_l
A_h
Y_h
= A*B
B_h
f
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CMOS Domino Logic
} Example XOR/XNOR
} Sometimes possible to share transistors
Y_l
= A xnor B
A_h
f
A_l
B_l
Y_h
A_l
A_h
= A xor B
B_h
f
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CMOS Domino Logic
} Rules of Thumb
}
}
Typical domino keepers have W/L = 5-20% of effective width
of evaluate tree
Typical domino output buffers have a beta ratio of ~ 6:1 to
push the switch point higher for fast rise-time
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Contents
}
}
}
}
}
}
}
Introduction
Dynamic CMOS Logic
CMOS Domino Logic
CD Domino Logic
Dynamic CVSL
Sample-Set Differential Logic (SSDL)
Summary
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CD Domino Logic
} We noted that dynamic inputs never make 1 to 0
transitions while in evaluation
} Two solutions:
} Precharge outputs low using an inverting gate
(standard domino)
} Delay the evaluate clock until inputs settle (CD
domino)
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CD Domino Logic
} Self-timed dynamic logic family
} Consists of a dynamic gate, and an optional
delay element for the clock signal
OR2
Mpre
Out = a+b
a
clk(i)
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b
Meval delay clk(i+1)
LECTURE 10 : Dynamic CMOS
Adib Abrishamifar 2008
CD Domino Logic
} Advantages
} Uses single-rail circuits, rather than dual-rail for
standard domino
} Provides both inverting and non-inverting functions
} High-speed, large fan-in NOR and OR circuits
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CD Domino Logic
} Delay Matching
} CD domino requires delay matching between the
slowest dynamic gate at a level and a delay element
} A 20% margin is typically added to the delay of the
fixed delay element to account for PVT variations
} Thus, 20% of the speed gain possible with CD domino
is not realized
} Average speed gain of (60+20)% is theoretically
possible
} Use digitally programmable delay elements
(PDEs) to reduce the margin and attain a speed
improvement without affecting the reliability in
the presence of variations
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CD Domino Logic
} Clocking Scheme
} The circuits are fully levelized
} The delay element on each level is tuned to the
slowest gate at its level, plus a 20% margin
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LECTURE 10 : Dynamic CMOS
Adib Abrishamifar 2008
Contents
}
}
}
}
}
}
}
Introduction
Dynamic CMOS Logic
CMOS Domino Logic
CD Domino Logic
Dynamic CVSL
Sample-Set Differential Logic (SSDL)
Summary
IUST: Digital IC Design
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LECTURE 10 : Dynamic CMOS
Adib Abrishamifar 2008
Dynamic CVSL
} Positive feedback does not exist
F
F
C
IUST: Digital IC Design
In{
67/71
NMOS
Logic Array
LECTURE 10 : Dynamic CMOS
} In
C
Adib Abrishamifar 2008
Contents
}
}
}
}
}
}
}
Introduction
Dynamic CMOS Logic
CMOS Domino Logic
CD Domino Logic
Dynamic CVSL
Sample-Set Differential Logic (SSDL)
Summary
IUST: Digital IC Design
68/71
LECTURE 10 : Dynamic CMOS
Adib Abrishamifar 2008
Sample-Set Differential Logic (SSDL)
} It is one type of Dynamic CVSL with positive feedback
} By this logic the low level output is guaranteed to zero in
evaluation phase
F
F
C
In{
IUST: Digital IC Design
69/71
C
NMOS
Logic Array
} In
LECTURE 10 : Dynamic CMOS
Adib Abrishamifar 2008
Contents
}
}
}
}
}
}
}
Introduction
Dynamic CMOS Logic
CMOS Domino Logic
CD Domino Logic
Dynamic CVSL
Sample-Set Differential Logic (SSDL)
Summary
IUST: Digital IC Design
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LECTURE 10 : Dynamic CMOS
Adib Abrishamifar 2008
Summary
} This lecture describes many basics CMOS Logic
Gates which require clock or other periodic
signal for operation
} These circuits rely on the temporary storage of
signal values on the (parasitic) capacitance of
high impedance nodes
IUST: Digital IC Design
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LECTURE 10 : Dynamic CMOS
Adib Abrishamifar 2008