ESE570: Digital Integrated Circuits and VLSI Fundamentals

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ESE570: Digital Integrated Circuits and VLSI
Fundamentals
University of Pennsylvania
Course Overview
The course explores the design aspects involved in the realization of CMOS integrated
circuits/systems from device up to the register/subsystem level. It addresses major design
methodologies with emphasis placed on structured full custom design. The course includes
the study of the MOS device, critical interconnect and gate characteristics that determine the
performance of VLSI circuits. It also includes CMOS logic design from transistor level
schematic to layout for fabrication. Students will use state-of-the art CAD tools to verify
designs and develop efficient circuit layouts.
Course Objectives
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Students learn the fundamentals of digital CMOS VLSI design from the transistor up to the
system level.
Students learn the models for state-of-the-art VLSI components, fabrication steps, hierarchical
design flow and semiconductor business economics.
Students apply this knowledge in design examples through homework problems.
Students learn the Cadence VLSI CAD environment and do three lab assignments that span
the Cadence tool set, including schematic capture, Verilog and SPICE simulations. parasitic
extraction, layout, design rule check.
Students apply their course knowledge and the Cadence VLSI CAD tools in a team based
capstone design project that involves much the same design flow they would encounter in a
semiconductor design industrial setting. All ESE570 projects involve the development of
detailed behavioral description, a verified transistor level design and a verified silicon layout.
Capstone project is presented in a formal report due at the end of the semester
Instructor
Prof. John Carelli
Room 276 Towne Bldg
[email protected]
Time and Location
Wednesday, 4:30-7:30 pm, Room 315 Towne
Prerequisite
ESE319 or equivalent. Undergraduate students need permission of instructor
Syllabus
1
2
Introduction
Fabrication of MOS Circuits
1
2
No.
CLASS
PERIODS
2
2
3
3
3
4
1
5
3
6
3
7
2
10
MOS Transistor Theory
Modeling of MOS Transistors using
SPICE
MOS Inverters: Static Characteristics
MOS Inverters: SwitchingCharacteristics
& Interconnect Effects
Combinational MOS Logic Circuits
MID-TERM EXAM - Weds, 14 March
2007
Sequential MOS Logic Circuits
Library Based Circuit Design & Design
Automation
Dynamic MOS Logic Circuit
11
12
Semiconductor Memories
Chip Input and Output (I/O) Circuits
13
Design for Manufacturability
FINAL PROJECT DUE - Friday, 4 May
2007 by 4:30 PM
No.
4
5
6
7
8
9
TOPIC(s)
TEXT CHAPTERS
1
8
3
NA
1
9
3
10
13
2
2
14(select topics)
1
Note: One Wednesday session equals 2 class periods
Main Texts
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CMOS DIGITAL INTEGRATED CIRCUITS ANALYSIS AND DESIGN, Third Edition, By S. M.
Kang and Y. Leblebici, McGraw Hill, 2002.
o Please click the above text title to check out the website developed to support the
text.
ON-LINE CADENCE TUTORIAL, updated by Alper Meric Feb, 2007 prepared by Viktor Gruev
and Sameer Sonkusale
Grading Policies
Homework: 20 %
Midterm: 40 %
Project: 40 %
Homework: Homework assignments will be a combination of textbook problems and
CADENCE exercises. Homework is assigned each week by Wednesday and is due on
Wednesday the week after it is assigned. All homework assignments and due dates will be
posted on the ESE 570 blackboard website https://courseweb.library.upenn.edu/. Students
are permitted up to THREE one-week latenesses without penalty. That is on three occasions
homework may be turned in one week after the official due date. No other late turn-in of
homework will be accepted for any reason. Homework not turned in accordance with this
policy will receive zero grade. Students are expected to manage their three allowed
latenesses to allow for unforeseen situations that will result in homework to be turned in late.
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