Michael David Bryant
ME 348C/392Q Mechatronics 1
1
11/1/07
University of Texas at Austin
Basic electronics
Operational Amplifiers (Op-Amps)
Op-Amp Features
Other Op-Amp Specifications & Issues
Amplifier Configurations
Inverting amplifier
Multiple Inputs: Sum Over Inverting Point
Three Resistor Equivalent Feedback Network
Non-inverting Amplifier
Differential Amplifier
Instrumentation Amplifier
Design Guidelines
Passive Element Filters
Basic Op-Amp Active Filters
Digital to Analog Converters (D/A)
D/A: Weighted Current Sources
D/A: R - 2R Ladder Network
Sample and Hold Circuits
Analog to Digital Converters (A/D)
A/D Successive Approximation
A/D Parallel (flash) converters
Hybrid Digital/Analog Systems
Michael David Bryant
ME 348C/392Q Mechatronics 1
2
11/1/07
University of Texas at Austin
Purpose
Amplify (boost) weak signal
Remove noise or other unwanted signal components
filtering
common mode rejection
Preprocess signal for later operations
Attenuate high frequencies: anti-aliasing before
A/D conversion
Michael David Bryant
ME 348C/392Q Mechatronics 1
3
11/1/07
University of Texas at Austin
Basic electronics
Operational Amplifiers (Op-Amps)
| V+ | , | V- | usually between 0 and 25 volts
Michael David Bryant
ME 348C/392Q Mechatronics 1
4
11/1/07
University of Texas at Austin
Op-Amp Features
1.
Very high gain | eo / ei | = A ≈ 106 to 108
2.
Large bandwidth (MHz or more)
3.
High input impedance Ri ≈ 100 kΩ to 100 MΩ
(⇒ small input load currents)
4.
Low output impedance Ro ≈ 101 to 102 Ω
5.
Differential inputs ei = ea - eb
6.
High Common Mode Rejection Ratio (CMRR) ≈ 50
to 100 dB. (dB = 20 log10 )
CMRR: same common mode signal eCM into ea &
eb ⇒ tiny eo
If channel a & b input impedances same, minimizes
effect of signals induced on both channels (e.g. 60
Hz from building supply).
Common Mode Gain: CMG = A/CMRR ( e.g., =
106 /105 ≈ 10).
7.
Temperature dependent parameters: design to
minimize effects.
8.
Voltage Supply Rejection Ratio (VSRR) gauges
effect of power supply drift & variations V+ and
V- as equivalent input ei .
9.
Input Offset voltage Voffset : Manufacturing
imperfections & temperature variations ⇒ eo ≠ 0
when ei = 0 (violating desired eo = - A ei ). To
correct, adjust Voffset :
Michael David Bryant
ME 348C/392Q Mechatronics 1
5
11/1/07
University of Texas at Austin
V+
eo
+
Voffset
V- (or V+ )
Voffset allows low cost Op-Amp. Imperfections
corrected (cheaply) at installation, not (expensively)
during chip manufacture.
10.
Op-Amp acts as controllable valve.
VV+
Output V- ≤ eo ≤ V+
⇒
≤
e
≤
i
A
A .
11.
Input bias currents I+ and I- (10 nA to µA) flow
through + (b) and - (a) input terminals to bias input
transistors (FET gate or BJT base). Voltage drop
developed across input elements must be balanced
(same at both terminals) so that eo = 0. ⇒ Balanced
input resistances to + and - .
12.
Input offset currents I+ and I- ⇒ residual eo ≠ 0
unless minimized with potentiometer on one input
to fine tune. Can also adjust Voffset . Puts upper
limit on values of input resistors (minimize voltage
drops due to I+ and I- ).
Michael David Bryant
ME 348C/392Q Mechatronics 1
13.
6
11/1/07
University of Texas at Austin
Class B operation often used in output stage:
complementary npn & pnp in push/pull (Nearly
identical amplifier circuits--stage 1 & stage 2-arranged in parallel. Stage 1 amplifies only positive
voltages, and switches off for negative. Stage 2
amplifies only negative, and switches off for
positive.) Crossover distortions possible (small
signals) in dead space as transistors in stages switch
on/off.
eo
stage 1:
positive
response
stage 2:
negative
response
ei
dead space:
transistors on/off
Michael David Bryant
ME 348C/392Q Mechatronics 1
7
11/1/07
University of Texas at Austin
Other Op-Amp Specifications & Issues
deo
A. Slew rate SR ≡ dt max important to avoid large signal
distortions.
ei = E sin ωt ;
SR = E ω cos ωt
=Eω
max
Require SR ≥ 2π f E for amp to follow largest voltage swing.
B. Compensation: Lead/lag network to control phase margin
when negative feedback. For stable amplifier design gain ( R2
R2
for
inverting
amplifier,
1
+
R1
R1 for noninverting
amplifier), require closed loop response curve to meet open
loop curve where slope of closed loop curve is -20 dB/dec.
- 20dB/dec ⇒ 1st order term ⇒ - 90° phase ⇒ limited signal
growth (phase margin = 180° - 90° = 90°⇒ stable closed loop
system)
Internally compensated: manufacturer provides network for 20 dB/decade; limits bandwidth but unconditionally stable.
Externally compensated: Install capacitance (≈ pF) across
indicated frequency compensation terminals to control
bandwidth and closed loop gain (-40 dB ⇒ -20dB).
Manufacturer specifies needed capacitance. Conditionally
stable (for given closed loop gain).
M
dB
open loop: gain A
externally compensated:
stable design (crosses -20 dB/dec)
-20 dB/dec
120
-20 dB/dec
uncompensated: unstable design
(closed loop design crosses -60 dB/dec)
-40 dB/dec
80
design gain:
closed loop
-20 dB/dec
40
0
open loop at -20 dB/dec
meets closed loop gain
1k
-60 dB/dec
1M
f (Hz)
internally compensated:
unconditionally stable
(-20 dB/dec up to 100kHz)
Michael David Bryant
ME 348C/392Q Mechatronics 1
8
11/1/07
University of Texas at Austin
Unstable Feedback Oscillation: Sinusoid grows
output sine: G
causes phase lag
+
G
input sine
H
additional phase lag
of H inverts sine
First cycle: No feedback, but GH inverts. First cycle: Negative feedback
& GH inversion (- 360° phase) add constructively with input.
+
G
H
After second pass, feedback promotes signal growth. Further
passes ⇒ unstable!
Michael David Bryant
ME 348C/392Q Mechatronics 1
C.
9
11/1/07
University of Texas at Austin
Power Supply Filter Capacitors (10-1 to 1 µF) to
minimize power supply fluctuations
V+
0.1 µF
V-
0.1 µF
Michael David Bryant
ME 348C/392Q Mechatronics 1
10
11/1/07
University of Texas at Austin
Amplifier Configurations
Inverting amplifier
R
i2
R
1
i1
2
ea -
es
eb
+
eo
i3
R
a.
3
DC analysis
DC
DC
DC
DC biases: Very large Ri ⇒ eab ≈ 0 ⇒ ea ≈ eb
DC
Small bias current i3
DC
DC
≈ 0 ⇒ eb
DC
= - i3 R 3 ≈ 0
⇒ ea ≈ 0 : node a at virtual ground!
Negative feedback (via R2 ) enhances.
Michael David Bryant
ME 348C/392Q Mechatronics 1
11
11/1/07
University of Texas at Austin
R1 R2
R3 = R1  R2 = R + R
to balance input bias
1
2
current voltage drop:
b.
DC
DC
DC
DC
If R3 = 0, ea ≈ eb = 0 ⇒ i1
DC
DC
eo - ea
= 0 & i2 =
R2
DC
DC
⇒ e o = i2 R 2 ≠ 0
DC
AC
Required: zero input es = 0 ⇒ eo = eo + eo = 0.
Achieved via R3 = R1  R2
(balanced bias currents i3DC = i1DC + i2DC ) .
AC signal analysis
c.
Currents into – inverting terminal negligible (very
large Ri ) ⇒ i1 ≈ - i2
es - ea
eo - ea
=
R1
R2 ,
with eo = - A ei = - A ( ea - eb )= - A ea
⇒
eo
A
es = - 1 + R1/R2 (1 + A) ≈ -R2 /R1 at low freq, A >> 1
breaks down at high freq, A = A(f) & Ri = Ri(f)
d.
es
es R1
Input resistance Rin = i = e - e ≈ R1
1
s
a
at low
frequency
e.
Output resistance Rout ≈ (10-1 to 100 )
Ro ( 1 + R1/R2 )
small
A
Michael David Bryant
ME 348C/392Q Mechatronics 1
12
11/1/07
University of Texas at Austin
Multiple Inputs: Sum Over Inverting Point
R
e1
e2
e3
R
R
11
i1
R
12
i2
ea
13
i3
eb
2
+
R
3
e1
e2
e3
eo ≈ -R2 { R
+R
+R
}
11
12
13
R3 =(R11 R12 R13 ) R2
eo
Michael David Bryant
ME 348C/392Q Mechatronics 1
13
11/1/07
University of Texas at Austin
Three Resistor Equivalent Feedback Network
R 2a
R 2b
R 2c
R1
es
i
ea eb
R
+
eo
3
Equivalent feedback resistor R2 = R2a + R2b + R2a R2b /R2c
Small R2c ⇒ large equivalent R2 without big (noisy) resistors
For higher gain Op-amp designs
Michael David Bryant
ME 348C/392Q Mechatronics 1
14
11/1/07
University of Texas at Austin
Non-inverting Amplifier
R2
R1
R3
+
eo
es
R3 = R1  R2
a.
b.
Input on non-inverting + terminal, feedback to
inverting - terminal for stability
eo
A
=
es
1 + A R1/(R1 + R2 )
≈1 + R2 /R1 @ low freq, A >> 1
c.
Ri A
Input resistance Rin ≈ 1 + R /R >> Ri
2 1
extremely large
d.
Output resistance Rout same as inverting amp.
Michael David Bryant
ME 348C/392Q Mechatronics 1
15
11/1/07
University of Texas at Austin
Differential Amplifier
R2
R1
e s1
R3
e s2
a.
+
eo
R4
Common mode rejected (e.g., drift) via high CMRR
R3 = R1
b.
R4
R2
R2
R2
eo ≈ R + R ( 1 + R ) es2 - R es1 = R ( es2 - es1 )
3
4
1
1
1
R4 = R2
c.
Rin = R1 (small)
+
Rin ≈ R3 + R4 (small)
Michael David Bryant
ME 348C/392Q Mechatronics 1
16
11/1/07
University of Texas at Austin
Instrumentation Amplifier
R
2
-
R
3
R
+
e s1
R
4
R2
1
-
+
R3
R
4
+
e s2
Combine advantages:
High input impedance / non-inverting terminals
Differential stage (CMRR)
eo
Michael David Bryant
ME 348C/392Q Mechatronics 1
17
11/1/07
University of Texas at Austin
Design Guidelines
A.
Op-Amp selection
Gain & bandwidth within scope of amp design
Peak to Peak output voltage swing within range
of supply rails (V+ , V- )
dv
Slew rate SR ≥ dt 
max
Acceptable noise figure (NF) over operating range
B.
Stability
frequency compensation (internal or external) for
- 20 dB/dec
external: resisitors and capacitors specified by
manufacturer
- 20 dB/dec. at desired gain ⇒ stable amplifier
C.
Power supply
Supply rails V+ , V- sufficient for swings
minimize power supply fluctuations with
filter capacitors
avoid draining: power peaks sufficient
V+ , V- not too high: excessive shot noise
Michael David Bryant
ME 348C/392Q Mechatronics 1
18
11/1/07
University of Texas at Austin
D.
Resistor selection
Rin = R1
Rmin < R1 < Rmax
Rmin lower bound from signal source (i, v)
impedance: want high Rmax limited by
offset current (⇒ DC drop at output) &
thermal noise
oc
Va = [{R1 ||R2 } ioc ]max < 10% max allowed
distort; oc: offset current
R2 /R1 gain for inverting amp, 1 + R2 /R1
for non-inverting amp
R3 = R1 || R2
Networks (manufacturer)
voltage offset
compensation
E.
Offset ( defined by ei = 0 ⇒ eo ≠ 0 )
oc
Va << Voffset
Voffset reduced via voltage offset
temperature dependence within operating range
zero at Toperating
δVout for δT < allowable distortion
F.
Distortion components (total < allowable)
common mode / bias current (CMRR)
Voc
δVout
power supply fluctuations (VSRR)
insufficient bandwidth, slew rate, supply rails
Michael David Bryant
ME 348C/392Q Mechatronics 1
19
11/1/07
University of Texas at Austin
Passive Element Filters
T network
π network
Z1/2
Z1/2
Z2
Z1
Zload
2 Z2
2 Z2
Zload
.
Goal: overall impedance = Zload
Capacitor: C , Inductor: L , low cutoff frequency: fl ,
high cutoff frequency: fh
Designs:
1
fl = 0, fh =
! LC
1
High pass: Z1 = C, Z2 = L, fl =
,f =∞
4! LC h
Bandpass: Z1 = L1 series C1 , Z2 = L2 || C2 ,
fl , fh depend on Zload
Bandreject: Z1 = L1 || C1 , Z2 = L2 series C2 ,
fl , fh depend on Zload
Low pass: Z1 = L, Z2 = C,
.
Michael David Bryant
ME 348C/392Q Mechatronics 1
20
11/1/07
University of Texas at Austin
Basic Op-Amp Active Filters
1st order active filter
C
R
R
1
2
+
es
eo
R
3
Inverting amp with feedback C & R2 :
eo(s)
R2 || 1/sC
R2/R1
H(s) = e (s) ≈ =
R1
R2 C s + 1
s
R2
low frequency gain:
R1
1
3 dB cutoff frequency: fc = 2π R C
2
Michael David Bryant
ME 348C/392Q Mechatronics 1
21
11/1/07
University of Texas at Austin
2nd order active filter, Low gain type
C
R
R
1
1
2
+
-
es
C
2
R
R
eo
b
a
Non-inverting amp with coupling capacitors. Low
Rb
frequency gain: K = 1 + R
a
eo(s)
K
H(s)= e (s) = 2
s
s R1R2C1C2 + s [R2 C1 + R1C1 + (1 - K) R1C2] + 1
cutoff (natural) frequency:
1
fc =
2π R1R2 C1 C2
Michael David Bryant
ME 348C/392Q Mechatronics 1
22
11/1/07
University of Texas at Austin
2nd order active filter, High gain type
R
R
C
4
R
1
2
2
+
es
C
eo
1
R
3
Inverting amp with feedback C2 ||(R4 + R2 ), input R1 + R2 ,
coupling capacitor C1
eo(s)
H(s) = e (s)
s
1/R1R2C1C2
= - 2
s + s [1/R1 + 1/R4+ 1/R2](1/C1) + 1/R4R2C1C2
cutoff (natural) frequency:
1
fc =
2π R4R2 C1 C2
Higher order filters usually cascade 1st & 2nd order filters
Michael David Bryant
ME 348C/392Q Mechatronics 1
23
Analog Integrator
Inverting amp with feedback C & input R
Replace feedback R with impedance 1/sC:
H(s) =
eo (s)
1/sC
1
="
="
eI (s)
R
sRC
Integrator: eo (t) = "
!
!
1
RC
# e (t)dt
o
11/1/07
University of Texas at Austin
Michael David Bryant
ME 348C/392Q Mechatronics 1
24
11/1/07
University of Texas at Austin
R2R Resistance Ladder
Enables digital (software) control of resistance
Input resistance can be changed in-situ
Vi
2R
R
R
2R
2R
2R
Z
Vo
operation
switches control currents to terminals:
non-inverting (ground)
inverting terminals (virtual ground)
total ladder current constant
currents half (left to right), each ladder step
resistance into op-amp looking into any node: R
2R || 2R
currents split in half
Michael David Bryant
ME 348C/392Q Mechatronics 1
25
11/1/07
University of Texas at Austin
Digital to Analog Converters (D/A or DAC)
Converts digital (binary number) to analog voltage
Settling time ts :
time required for analog input (voltage or current)
to settle within ± LSB/2 following input code
change
typical: nsec to 100 µsec
circuits downstream add dynamics ⇒ increases ts
Michael David Bryant
ME 348C/392Q Mechatronics 1
26
11/1/07
University of Texas at Austin
D/A: Weighted Current Sources
1, Sk closed
Switch function ak =
{
controlled by bit settings
0, Sk open
"Bit" currents ik sum, give output:
3
Vo = - Vs R2 ∑ ak/R1k
k=0
Problems:
Many bits ⇒ many resistors
Usually R1k = 2k R for binary powers
requires accurate resistors: each resistor must be
precisely 1/2 its neighbor
Michael David Bryant
ME 348C/392Q Mechatronics 1
27
11/1/07
University of Texas at Austin
DAC: R2R Ladder Network
R2R Ladder Network DACs in 8, 10, 12, 14, 16, or 18 bits
Output Vo more accurate: only 2 resistor values needed
similar to weighted current source: currents in powers of 2
noninverting terminal at ground, inverting terminal at virtual
ground ⇒ ladder currents constant, independent of switches
Example: 4 bit D/A (Bits 3 ,2, 1, 0)
2 R i0 =V0 =2 R it
⇒
2 R i1 =V1 =R( i0 + it )+V0
⇒
2 R i2 =V2 =R( i1 + i0 + it )+V1 ⇒
i=
3
∑ak ik
k=0
;
3
i0 = it
i1 = 2 i0
i2 = 2 i1
3
R2
Vo = - ∑ ak 2 R Vk = -R2 ∑ak ik = -R2 i
k=0
k=0
Michael David Bryant
ME 348C/392Q Mechatronics 1
28
11/1/07
University of Texas at Austin
Sample and Hold Circuits
voltage follower (R = 0)
2
MOS
Analog
input
voltage
enhancement
FET
S
buffered output
(same V but
larger i)
iD
+
Vo
D
G
+5V
C
V+
from CPU via
control register
control
signal
+
comparator
high: sample
low: hold
V-
In higher performance A/D converters
Operation (Sample & Hold Input during A/D conversion)
switch (FET) closes & analog voltage charges capacitor
capacitor voltage to Op-Amp constant (held) after switch opens
MOSFET:
Positive gate voltage attracts electrons (charge carriers)
into channel, increasing conductance
FET "switch" characteristics
VGS low ⇒ 10 MΩ (open switch)
VGS high ⇒ 200 Ω (closed switch)
200 ! = 2V/10 mA
i D(mA)
20
7V
5V
VGS = 4V
10
VGS = 0V
5
10
10 M!
VDS (V)
Michael David Bryant
ME 348C/392Q Mechatronics 1
29
11/1/07
University of Texas at Austin
Comparator: Special Op-Amp circuit prone to saturation,
but optimized for fast recovery from saturation
Vout =
V1 > V2
V-
(low),
V1 < V2
output
voltage
-
V2
(high),
+
V1
{
V+
comparator
.
Michael David Bryant
ME 348C/392Q Mechatronics 1
30
11/1/07
University of Texas at Austin
Analog to Digital Converters (A/D or ADC)
Convert analog voltage to digital (binary)
1) A/D Successive Approximation
Vin
analog input
from sample
& hold
Vin /R
I test
comparator
b
-
B3 B2 B1 B0
R
a
+
4 bit D/A
I
I
MSB
a
voltage limiting
diode pair
b
Vd
LSB
a
b
clock
D
start
control logic
Input frozen by sample & hold
Vin
Diodes limit Vd swing due to I = R - I test
series of n (# bits) bit tests places input in bin (voltage range)
D/A converter generates test currents I test (or voltages) , to be
compared to input
final D/A number = A/D result
I test reflects current D/A setting
Vin
I = R - I test ⇒ Vd ⇒ high or low logic
Michael David Bryant
ME 348C/392Q Mechatronics 1
31
11/1/07
University of Texas at Austin
Test sequence, 4 bit A/D ⇒ 4 tests
test
1
2
3
4
bit tested
3 (MSB)
2
1
0 (LSB)
ak =
D/A test setting
0111
a3 011
a3 a2 01
a3 a2 a1 0
bit test result
a3
a2
a1
a0
1,
Vd > 0 ⇒ I test < Vin /R
0,
Vd < 0 ⇒ I test > Vin /R
{
Bit test result ak causes D/A to output current I test that
CANCELS a component of input current Vin /R, thereby fine
tuning D/A register. Final result a3 a2 a1 a0 .
Problem: accurate but moderate speed.
Conversion times 1 µs to 100 µs.
Michael David Bryant
ME 348C/392Q Mechatronics 1
32
11/1/07
University of Texas at Austin
Capacitor Based Successive Approximation
•
•
•
Charge all capacitors to Vin
o lower plate = input voltage Vin
o upper plate = ground
For ADC, Switch
o leftmost C (MSB) to +Vref
o other C’s to -Vref
o ground switch open
Comparator determines if
Michael David Bryant
ME 348C/392Q Mechatronics 1
33
11/1/07
University of Texas at Austin
A/D Parallel Flash ADC converters
Vin
+
Vref
-
2/3 Vref
+
R
-
decoding
logic
( 1 level)
.
LSB
+
R
MSB
-
1/3 Vref
R
latch (switches on)
Speeds exceed 500 MHz: up to 4 GHz for 4 bit converter
Voltage dividing resistors R create 2n voltage levels or “bins”
Comparators ⇒ which "bin" contains input
Big Problem: need (2n -1) resistors & comparators for 2n bins
⇒ requires large silicon area on chip
⇒ usually limited to 3 to 6 bits
Other problems:
parasitic capacitance at each resistor limits bandwidth
many resistors increase power consumption
Michael David Bryant
ME 348C/392Q Mechatronics 1
34
11/1/07
University of Texas at Austin
Pipelining
• Sample & Hold (S/H)
• Multiple conversion stages
• 1 or 2 bit conversions @ each stage
o Flash converters do ADC
o DAC converts bits to voltage
o Subtract bit voltage from input, create residue
o Amplify residue
o Next stage does next bits
o Order: MSB to LSB
• Pipeline: Samples flow through, 1 stage at a time
Advantages
N to 2N COMPARATORS
High sampling frequency, with > 8 bits
Drawbacks
Complexity
Power consumption
Michael David Bryant
ME 348C/392Q Mechatronics 1
35
11/1/07
University of Texas at Austin
Sigma Delta ΣΔ (Delta Sigma ΔΣ) Converters
For low frequency signals
Output: pulses of constant
amplitude & duration
Interval between pulses
proportional to input voltage.
Higher input voltage @ 1
⇒ Greater slope of integrator
output (~ramp) voltage @4
⇒ More frequent comparator
triggers & spikes @5
⇒ Shorter intervals between
pulses @2 & @3
Count pulses: count ~ input
voltage
Michael David Bryant
ME 348C/392Q Mechatronics 1
36
11/1/07
University of Texas at Austin
Hybrid Digital/Analog Systems
Noise perspective: analog & digital systems incompatible
analog contaminated by digital pulses ⇒ AC noise via
power supply feedback
stray C 's
ground loops
digital contamination
analog ⇒ lower frequency filtering
reduced digital pulses
Prescription: Isolate systems
1.
Separate analog & digital grounds
2.
Connect digital & analog at ONE point ONLY
(avoid ground loops)
3.
Provide separate analog & digital supply voltages
4.
Electrostatic shielding (Faraday cage) around
analog circuit. Connect one end only to analog
ground
5.
At especially sensitive interconnections, consider
electro-optic coupling
6.
Consider using emitter coupled logic (ECL) in
digital section for less spurious signal generation
7.
If analog & digital on same IC, separate with wells
(pn junctions)