OPTICAL INTERCONNECTS TO SILICON CMOS:
INTEGRATED OPTOELECTRONIC MODULATORS
AND SHORT PULSE SYSTEMS
A DISSERTATION
SUBMITTED TO THE DEPARTMENT OF APPLIED PHYSICS
AND THE COMMITTEE ON GRADUATE STUDIES
OF STANFORD UNIVERSITY
IN PARTIAL FULFILLMENT OF THE REQUIREMENTS
FOR THE DEGREE OF
DOCTOR OF PHILOSOPHY
Gordon Arthur Keeler
December 2002
 Copyright by Gordon Arthur Keeler 2003
All Rights Reserved
ii
I certify that I have read this dissertation and that in my opinion it is fully adequate,
in scope and quality, as dissertation for the degree of Doctor of Philosophy.
__________________________________
David A. B. Miller, Principal Advisor
I certify that I have read this dissertation and that in my opinion it is fully adequate,
in scope and quality, as dissertation for the degree of Doctor of Philosophy.
__________________________________
Robert L. Byer
I certify that I have read this dissertation and that in my opinion it is fully adequate,
in scope and quality, as dissertation for the degree of Doctor of Philosophy.
__________________________________
Krishna C. Saraswat
Approved for the University Committee on Graduate Studies
__________________________________
iii
ABSTRACT
The performance of silicon CMOS integrated circuits has increased dramatically over
the past three decades due to the steady reduction in transistor feature sizes. For these
advances to continue, a new hurdle must be overcome: the stagnant performance of the
electrical wiring used between and within computers. Optical interconnects promise to
solve many of the challenges imposed by electrical interconnects because of the favorable
physics governing optical signaling. However, several practical issues have yet to be
addressed. This dissertation describes several investigations that were performed at the
optoelectronic device level that may hasten a commercial implementation of optical
interconnects. Additionally, this work contains the results of several system-level
experiments that could increase the benefits of optical interconnects in digital systems.
The approaches taken in existing optical networks will need to be radically altered for
use in future optical interconnects. Factors such as cost, bandwidth density, and power
dissipation will necessitate the dense integration of two-dimensional optoelectronic
device arrays with conventionally-processed silicon CMOS chips. Hence, arrays of
surface-normal GaAs-based electroabsorption modulators and photodiodes were
fabricated and flip-chip bonded directly to CMOS microelectronics. The process steps
developed for fabricating the quantum-well modulators will be highlighted in this
dissertation, and the performance characteristics of the integrated optoelectronic devices
will be discussed. Resonant-cavity enhancement was used to increase the low-voltage
performance of the modulators, making them compatible with future generations of
CMOS. Devices that were fabricated using a Fabry-Perot cavity-tuning technique will be
described, as well as a novel modulator design that employs a first-order cavity to
maintain a broad spectral bandwidth at very low voltages.
Using these integrated optoelectronic components, a free-space chip-to-chip optical
interconnect demonstrator was constructed. This multi-channel optical link allowed
system-level experiments to be performed. The work described herein shows that
iv
ultrafast techniques can provide several benefits in an optically-interconnected system.
Bit error rate measurements were used to quantify the improvement in receiver sensitivity
that can be achieved by employing “short pulse signaling” instead of the conventional
non-return-to-zero (NRZ) data format. The short pulse duration and low jitter output of a
modelocked laser enables the concept of data resynchronization (i.e., the removal of
transmitter skew and jitter), which was demonstrated using the link. The results of a short
pulse pump-probe experiment will also be presented, in which precise time-domain
measurements of circuit delay are used to determine the latency of interconnect
transmitters and receivers. Finally, several additional advantages of using short pulses for
optical interconnection will be described.
v
ACKNOWLEDGMENTS
One often supposes that a doctoral degree requires several years to be dedicated
solely to a single research topic. However, during my first year at Stanford, I was given
some valuable advice: “Know everything about something, and something about
everything.” And while my time at Stanford enabled me to achieve the level of technical
focus needed to write this dissertation, it also broadened my life immeasurably in many
ways. This is in large part because of the friends and colleagues that I have met, people
who have become an important part of my life over the past six-or-so years.
The work that I present in this dissertation is only one piece of a larger collaborative
effort by several people. I am grateful for the assistance of Bianca Nelson and Diwakar
Agarwal, my collaborators for all of the systems-level experiments presented here and
elsewhere. Together, we struggled through the problems of making complete systems
functional, and dividing up our work so that all three of us were content – not a trivial
task. Despite the lack of senior students to lead our way, I am happy to report that we
were successful in obtaining three doctoral degrees. I would also like to thank Noah
Helman, who was my collaborator for the optoelectronic device fabrication and testing.
His sense of humor was a great comfort in the cleanroom, particularly on the occasions
when a failed process step or dropped wafer undid several days of processing. The other
optical interconnect folks, Christof Debaes, Aparna Bhatnagar, and Ray Chen, were also
very helpful in making this work come together. Additionally, I appreciate the assistance
of the MBE folks: Petar Atanackovic, Thierry Pinguet, Vijit Sabnis, and Mark Wistey.
I learned a great deal from my advisor, Professor David Miller, although much of
what he taught me is not specific to physics or engineering. While he can answer almost
any question about optoelectronic devices, his unrivaled leadership skills are what make
him unique. As an advisor, he gives his students respect and independence. And although
he keeps very busy, he’s always been available when I’ve needed advice.
vi
I appreciate the help of the faculty and staff who helped with this work. My reading
committee, Professor Robert Byer and Professor Krishna Saraswat, kindly read and
corrected my dissertation. Thanks also to Professor Yoshihisa Yamamoto and Professor
Mike McGehee, both of whom served on my defense committee. Tom Carver performed
innumerable depositions for me, and is an amazing resource for processing questions of
all kinds. I also wish to thank Ingrid Tarien and the Applied Physics staff, Paula Perron
and Claire Nicholas, who have been very helpful and supportive over the years.
The members of the Miller group have made this a wonderful place to work. In some
ways, this is a two-edged sword: I can get almost any technical question answered
without leaving my office – but I can also spend the day in my office without getting any
work done at all, because there are so many fun and interesting people to talk to. So,
thanks also to: Hatice Altug, Sameer Bhalotra, Henry Chin, Volkan Demir, Onur Fidaner,
Martina Gerken, Yang Jiao, Sungchul Kim, Helen Kung, Jon Roth, Ryohei Urata,
Michael Wiemer, and Micah Yairi. Additionally, I’d like to thank all of my other friends,
including those back in Canada, who helped me get here and get through this degree. In
particular, thanks to Ali Mokhberi, Keith O’Brien, Kevin Phillips, and Thierry Pinguet
for all of the diversions and encouragement.
Finally, I wish to thank my family for all of their love and support. Kathy, Mom, and
Dad encouraged me to do my best since I was a kid, but seem to be proud no matter what
I do. I’m very fortunate to be part of such a close family, and know that they’re always
there for me. Thanks also to Syrus, and to Greg, Sheryl, and Dennis, who are part of my
recently-larger-but-still-close family. Most importantly, I’d like to thank Bianca
Elizabeth Nelson Keeler. Bianca plays so many roles I can’t count them all. As a
colleague and collaborator, her organization is unparalleled. Together we wrote papers,
did experiments, and had a great time. As a wife and partner, Bianca’s the most
supportive and caring person I know. I am amazingly fortunate to have met such a
wonderful friend, and I couldn’t imagine a better person to share my life with. Thanks for
your friendship and for your love.
vii
TABLE OF CONTENTS
List of Tables .................................................................................................................... xi
List of Figures.................................................................................................................. xii
Chapter 1: Introduction ....................................................................................................1
References...........................................................................................................................4
Chapter 2: Optical Interconnect Fundamentals .............................................................5
2.1 Problems with Electrical Wires ...............................................................................5
2.1.1 Capacity Limitations.......................................................................................5
2.1.2 Interconnect Density .......................................................................................7
2.1.3 Design Challenges ..........................................................................................8
2.1.4 Timing.............................................................................................................9
2.1.5 Power Dissipation .........................................................................................10
2.2 Advantages of Optical Interconnects .....................................................................11
2.2.1 Interconnect Capacity ...................................................................................12
2.2.2 Interconnect Density .....................................................................................12
2.2.3 Design Issues ................................................................................................14
2.2.4 Timing...........................................................................................................15
2.2.5 Power Dissipation .........................................................................................16
2.2.6 New Approaches...........................................................................................17
2.3 Realizing Optical Interconnects to Silicon CMOS ................................................17
2.3.1 Device Integration: Rationale and Benefits ..................................................18
2.3.2 Device Integration: Techniques ....................................................................19
2.3.3 Optical Output Devices.................................................................................21
2.3.4 Optical Input Devices ...................................................................................24
2.3.5 Optics, Transmission Media, and Packaging................................................25
2.3.6 Circuits for Optical Interconnects.................................................................26
viii
2.4 Interconnect Demonstration Systems ....................................................................27
2.4.1 Chip-to-Chip Demonstrations.......................................................................27
2.4.2 Short Optical Pulses and Optical Interconnects............................................28
References.........................................................................................................................30
Chapter 3: MQW Modulator Design, Fabrication, and Integration ..........................34
3.1 Principles of Operation ..........................................................................................34
3.1.1 Semiconductor Optical Absorption...............................................................35
3.1.2 The Quantum Confined Stark Effect ............................................................36
3.1.3 Integrated Surface-Normal Electroabsorption MQW Modulators ...............37
3.2 Wafer Design, Growth, and Testing ......................................................................39
3.2.1 Wafer Growth and Design ............................................................................39
3.2.2 Wafer Testing and Results ............................................................................41
3.3 Device Fabrication .................................................................................................44
3.4 Integration Technique ............................................................................................46
3.5 Performance of Integrated Devices........................................................................48
References.........................................................................................................................54
Chapter 4: Low-Voltage, Resonant-Cavity Modulators ..............................................55
4.1 Resonant-Cavity Modulators .................................................................................56
4.1.1 The Theory of Fabry-Perot Resonators.........................................................56
4.1.2 Resonant-Cavity Modulator Analysis...........................................................57
4.2 Standard MQW Modulators and Resonant-Cavity Enhancement .........................60
4.2.1 AFPM Device Fabrication ............................................................................60
4.2.2 Tuning the Cavity Resonance .......................................................................62
4.3 First-Order Resonant-Cavity Modulators ..............................................................66
4.3.1 Problems with a DBR-Based Design............................................................66
4.3.2 Proposed Device: FOAM..............................................................................68
4.3.3 Electrical Modeling of FOAM......................................................................70
4.3.4 Optical Modeling of FOAM .........................................................................72
4.4 FOAM Fabrication, Testing, and Integration Results............................................76
ix
4.4.1 Fabrication and Integration Process Steps ....................................................76
4.4.2 Optical and Electrical Test Results ...............................................................78
4.4.3 Discussion and Future Improvements...........................................................79
References.........................................................................................................................82
Chapter 5: Short Pulse Optical Interconnects ..............................................................84
5.1 Reasons for Short Pulse Interconnects...................................................................84
5.2 Short Pulse Interconnect Demonstration Link.......................................................85
5.3 The Benefits of Short Pulse Signaling ...................................................................88
5.3.1 Receiver Sensitivity Improvement................................................................88
5.3.2 Signal Retiming ............................................................................................91
5.3.3 Additional Link Benefits...............................................................................94
5.4 Other Applications of Short Pulses........................................................................96
5.4.1 Optical Clock Distribution............................................................................96
5.4.2 Measurements with High Temporal Precision..............................................98
5.4.3 Single-Source WDM Optical Interconnect .................................................101
References.......................................................................................................................103
Chapter 6: Summary .....................................................................................................105
Appendix A: MQW Modulator Processing ................................................................108
A.1 Lithography Procedure........................................................................................108
A.2 Wafer Structure for Resonant-Cavity Tunable Modulators................................109
A.3 Wafer Test Structures..........................................................................................109
A.4 Device Process Steps ..........................................................................................112
A.5 Flip-Chip Bonding ..............................................................................................118
A.6 Substrate and Etch Stop Removal.......................................................................119
A.7 Cavity Tuning and Epoxy Removal....................................................................120
Appendix B: Modeling Modulator Reflectivity ..........................................................122
References.......................................................................................................................127
x
LIST OF TABLES
Chapter 3
Table 3.1
Design of the Fabry-Perot modulator epitaxial structure........................41
Chapter 4
Table 4.1
Summary of Fabry-Perot modulator performance..................................64
Table 4.2
Design of the FOAM modulator epitaxial structure ...............................76
Appendix A
Table A.1
Epitaxial growth instructions for Fabry-Perot modulator wafers .........109
Table A.2
Deposition instructions for n-type Ohmic contacts with no
diffusion barrier layer ...........................................................................110
Table A.3
Deposition instructions for p-type Ohmic contacts with no
diffusion barrier layer ...........................................................................111
Table A.4
Deposition instructions for reflective p-type Ohmic contacts
with a diffusion barrier layer for indium...............................................113
Table A.5
Deposition instructions for CMOS gold contacts with a
diffusion barrier layer for aluminum.....................................................118
xi
LIST OF FIGURES
Chapter 2
Figure 2.1
Schematic diagram of a free-space optical interconnect.........................14
Figure 2.2
Illustration of a typical flip-chip bonding process ..................................21
Chapter 3
Figure 3.1
Optical absorption in a quantum well .....................................................36
Figure 3.2
Operation of a surface-normal electroabsorption modulator ..................38
Figure 3.3
Schematic diagram of a modulator integrated to silicon CMOS ............39
Figure 3.4
Mesa structures for testing of the epitaxial wafer...................................42
Figure 3.5
Electrical I-V curves from epitaxial wafers ............................................43
Figure 3.6
Absorption coefficient vs. wavelength for a representative
epitaxial wafer.........................................................................................44
Figure 3.7
Quantum well modulator process flow ...................................................45
Figure 3.8
Scanning electron micrographs of devices after fabrication...................46
Figure 3.9
Scanning electron micrographs of devices after integration...................47
Figure 3.10 Simulated contrast ratio and change in reflectivity vs.
wavelength for a double-pass modulator ................................................49
Figure 3.11 Measured modulator reflectivity vs. wavelength for various
applied voltages ......................................................................................50
Figure 3.12 Integrated array of modulators in forward bias to show yield ................51
Figure 3.13 Modulator eye diagram at 800 Mb/s.......................................................52
Chapter 4
Figure 4.1
Schematic diagram of an asymmetric Fabry-Perot modulator ...............58
Figure 4.2
Total reflectivity vs. effective back mirror reflectivity for three
Fabry-Perot modulators .........................................................................59
Figure 4.3
Schematic diagram of an AFPM integrated to silicon CMOS................61
xii
Figure 4.4
Measured reflectivity vs. wavelength before and after tuning of
the resonant cavity ..................................................................................63
Figure 4.5
Contrast ratio and change in reflectivity vs. wavelength for an
integrated AFPM.....................................................................................64
Figure 4.6
Simulated and measured reflectivity vs. wavelength for
different applied voltages........................................................................65
Figure 4.7
Illustration of mirror penetration length in a DBR .................................67
Figure 4.8
The effect of mirror penetration in a first-order AFPM..........................68
Figure 4.9
Schematic diagram of the FOAM modulator..........................................69
Figure 4.10 Band diagram of the FOAM modulator..................................................71
Figure 4.11 Simulated contrast ratio vs. mirror thickness vs. wavelength for
the FOAM modulator..............................................................................73
Figure 4.12 Simulated change in reflectivity vs. mirror thickness vs.
wavelength for the FOAM modulator.....................................................74
Figure 4.13 Simulated reflectivity vs. wavelength for the optimal FOAM
modulator design.....................................................................................75
Figure 4.14 FOAM modulator process flow ..............................................................77
Figure 4.15 Scanning electron micrographs of FOAM modulators before
and after integration ................................................................................78
Figure 4.16 Reflectivity vs. wavelength for different FOAM devices
integrated to silicon.................................................................................79
Chapter 5
Figure 5.1
Photograph of the short pulse interconnect demonstration link..............86
Figure 5.2
Single-channel eye diagram from the receiver chip of the link
at 80 Mb/s ...............................................................................................88
Figure 5.3
Timing diagram for the sense-amplifier receiver....................................89
Figure 5.4
Link BER measurements at 400 Mb/s for NRZ and short-pulse
link operation, demonstrating receiver sensitivity enhancement............90
Figure 5.5
Conceptual illustration of skew and jitter removal using short
pulses.......................................................................................................92
Figure 5.6
Demonstration of jitter removal in the short pulse link ..........................93
xiii
Figure 5.7
Demonstration of skew removal in the short pulse link .........................94
Figure 5.8
Conceptual illustration of receiverless optical clock injection ...............97
Figure 5.9
Schematic diagram of the receiver/transmitter circuit used in
latency measurements .............................................................................99
Figure 5.10 Schematic of the pump-probe setup......................................................100
Figure 5.11 Circuit delay measurements as a function of supply voltage................101
Figure 5.12 Illustration of an optical interconnect that employs singlesource wavelength division multiplexing .............................................102
Appendix A
Figure A.1 Illustration of the tiling method for spinning photoresist onto
small CMOS chips ................................................................................117
Figure A.2 Lithography alignment method for CMOS chips and small
holes ......................................................................................................117
Appendix B
Figure B.1 Calculated refractive index vs. wavelength for different applied
voltages .................................................................................................126
xiv
CHAPTER 1: INTRODUCTION
Over the past 30 years, the electronics industry has improved the performance of
silicon-based integrated circuits at an astounding rate. Gordon Moore of Intel noted in the
1970’s that the number of transistors per integrated circuit was growing exponentially in
time, and his prediction that it would continue at such a pace is known as Moore’s Law.
Using recent guidelines set by the Semiconductor Industry Association in its Technology
Roadmap [1], it seems feasible that the electronics industry will continue along this
relentless path well into the future – provided some critical roadblocks are removed.
These include excessive power dissipation, insufficient communication bandwidth, signal
delay, and timing uncertainty, just to name a few. Many of these obstacles, which will
have a major impact on the scaling of silicon electronics within only a few years, stem
from the physical limitations of electrical interconnects.
The building blocks of silicon electronics are transistors and interconnects: the
transistors perform logic operations, while the interconnects transfer digital information.
The performance of transistors has steadily been improved by the shrinking of their
dimensions. Interconnect performance, on the other hand, does not typically get better
when sizes are reduced. Electrical interconnects were improved in the past by changing
the technology used to fabricate the wiring layers. An analysis of the physics governing
the issues, however, shows that the ultimate limitations have physical, not technological,
origins, and that these limits are rapidly approaching [2]. In a landmark paper in 1984,
Goodman et al. advocated the use of optical links as a way to circumvent the problems of
electrical signaling [3]. These “optical interconnects” are still the most promising
candidate to solve the challenges imposed by electrical wiring, both for off-chip and
possibly on-chip applications. Chapter 2 of this dissertation discusses the physical
limitations of electrical interconnects, and how an optical approach can remove or
minimize the problems they impose.
1
Optical signaling techniques are well-developed in telecommunications, where the
problems of electrical wires were encountered some time ago. However, for optics to be
considered a practical solution for the silicon microelectronics industry, the techniques
used in existing optical networks must be radically altered. Factors such as bandwidth,
density, power, and cost necessitate an approach that easily integrates two-dimensional
arrays of small, low-capacitance optoelectronic devices with conventionally-processed
silicon CMOS chips. The approach that was taken in this work was to flip-chip bond
arrays of surface-normal quantum-well modulators directly to CMOS. Chapter 3
discusses the fabrication, integration, and characterization of these optoelectronic
modulators and photodiodes.
Unfortunately, the two most important parameters used to characterize the modulators
described in Chapter 3 – namely, change in reflectivity and contrast ratio – both diminish
as operating voltages are lowered. Due to the continued scaling of CMOS, chip supply
voltages have dropped to the point where modulator performance is exceedingly poor.
Chapter 4 describes two new resonant-cavity modulators, intended for use in future
optically-interconnected systems, that show enhanced performance at low operating
voltages.
Using the ability to integrate dense arrays of optoelectronic devices and silicon
CMOS circuits, it was possible to realize the ultimate goal of this work: to demonstrate
and analyze a complete optical interconnect system implementation. Several high-speed,
multi-channel chip-to-chip optical links were demonstrated that rival work in other
research facilities. More interesting, however, is the novel system approach that was
created by operating these systems with the short optical pulses of a modelocked laser.
As Chapter 5 will illustrate, “short pulse optical interconnects” can improve link
performance and add system functionality. Notable features that were investigated
include: receiver sensitivity enhancement, improvement of interconnect timing, optical
clock distribution, precise measurements of circuit latency, and the use of wavelengthdivision multiplexing with a single source. The results of several systems-level
experiments will be described; all rely on the devices described in the previous chapters.
2
This thesis is meant to provide a thorough rationale behind my research effort, a
detailed look at the techniques used to fabricate, integrate, and analyze the optoelectronic
devices, and some examples of new and exciting system benefits made possible with the
use of modelocked lasers. It is my hope that this dissertation will illuminate, to every
reader, something new in the field of optical interconnects.
3
REFERENCES
1. Semiconductor Industry Association, International Technology Roadmap for
Semiconductors, 2001 Edition, http://public.itrs.net/Files/2001ITRS/Home.htm.
2. D. A. B. Miller, Int. J. Optoelectronics, 11, 155 (1997).
3. J. W. Goodman, F. J. Leonberger, S.-Y. Kung, and R. A. Athale, Proc. IEEE, 72, 850
(1984).
4
CHAPTER 2: OPTICAL INTERCONNECT FUNDAMENTALS
Silicon CMOS integrated circuits will continue to improve at a rapid pace as their
feature sizes are reduced. While the physics governing the transistor favors this size
reduction, the performance of the wires used for electrical interconnects does not
significantly improve using this type of scaling. Thus, a new approach to signaling and
clock distribution will be needed to take CMOS circuit performance beyond the limits
imposed by electrical interconnects. Optical interconnects have the potential to
circumvent these limitations, provided a number of technological issues can be
addressed.
This chapter discusses the major problems with electrical interconnects, particularly
those of low capacity, high power dissipation, and timing uncertainty. It is shown that an
optical approach can potentially reduce or eliminate all of these problems. To fully
realize such benefits, dense arrays of optoelectronics must be integrated closely with
silicon circuits. The essential components of an optical link, including appropriate
optoelectronic input/output (I/O) devices, circuits, and current integration techniques are
explained. Previous interconnect research, particularly in the areas of optical modulators
and experimentally-demonstrated systems, is described in order to familiarize the reader
with the background fundamentals. Later chapters will call upon this information while
delving into the specific details of the experiments.
2.1 PROBLEMS WITH ELECTRICAL WIRES
2.1.1 CAPACITY LIMITATIONS
Electrical interconnects for silicon CMOS circuits come in two main varieties: offchip and on-chip interconnects. The limitations imposed by off-chip interconnects and by
the longest on-chip “global” wires are the most immediate, a fact that is particularly
evident when considering data bandwidth requirements. High interconnect bandwidth, or
capacity, is of critical importance as circuit performance increases because the need to
5
move large amounts of data increases with higher clock speeds and greater circuit
complexity. It is well known that transistor performance increases in essentially all
metrics as the dimensions and operating voltages are reduced. However, an analysis of
the physics governing electrical wires subjected to scaling has established [1] that
standard electrical interconnect performance is ultimately related only to the
“architectural aspect ratio” of the wire for a given type of interconnect. For a wire of
length l and cross-sectional area A, the “architectural aspect ratio” is given by l /vA, and
the maximum capacity of the electrical interconnect can be written as B bits/s, with [1]:
B = Bo
A
(bits/s)
l2
(2.1)
where Bo ~ 1016 (bits/s) for a typical on-chip (RC-type) line and Bo ~ 1015 (bits/s) for a
typical off-chip (LC-type) line1. Taking the simplest approach to CMOS scaling and
reducing all the dimensions of a system, the circuit performance increases but the
interconnect aspect ratio, and therefore its capacity, is left unchanged. Thus, electrical
interconnects cannot keep up with the device performance enhancements provided by
scaling, and the problem is worst for the high-aspect ratio global and off-chip wires. In
typical next-generation designs, system complexity is also increased and the system size
(i.e., both chips and boards) is increased or remains the same, further escalating the
performance disparity between logic and interconnects.
The aspect ratio problem occurs because an electrical interconnect, even with a
voltage step function at the input, has a finite risetime at the output due to resistive losses
and line capacitance. This slow risetime causes intersymbol interference (ISI) that closes
the output “eye diagram” at the receiver, making it difficult or impossible to determine
what value was originally sent. On-chip global RC lines now use repeater amplifiers,
1
For most electrical interconnects used on-chip, the bulk resistance of the wire tends to
dominate the effects of inductive impedance. The signal rise time on these wires is
comparable to the RC propagation delay at the frequencies used on-chip, and the wires
are referred to as RC lines. Off-chip, interconnect dimensions are different and
signaling tends to be limited by the skin-effect. In these “LC” transmission lines,
inductive impedance dominates.
6
because the standard RC interconnect already has insufficient bandwidth at current clock
rates. Repeaters can permit quite high interconnect capacity, but they add significant
problems in terms of propagation delay and power dissipation; furthermore, repeaters
cannot easily be used to increase interconnect capacity for off-chip interconnects.
Finite wire capacity given by the aspect ratio limit may not fundamentally limit onchip signaling rates for a while; many circuit designers feel that sophisticated techniques,
such as equalization, will permit bandwidth increases sufficient for future CMOS
applications [2]. However, designing a complex high-capacity interconnect at the expense
of power, latency, and circuit area is not a favorable approach when other signaling
technologies exist that are better in terms of these important metrics.
2.1.2 INTERCONNECT DENSITY
Perhaps as important as the capacity of a single interconnect is the aggregate capacity
of multiple interconnects. Increasing pin counts and using parallel data channels has often
resolved capacity problems. Off-chip I/O was historically performed using electrical wire
bonds that were relegated to the chip edge, although this approach has been replaced by
flip-chip packaging that places pads across the surface of the chip to achieve higher pin
counts. Increasingly, many of these electrical pads are needed for supply and ground
connections. Because each of the pads has significant inductance, using multiple
connections to minimize the effects of pad parasitics is the best way to supply the large
amounts of power required by state-of-the-art chips. As CMOS power requirements
increase, the fraction of I/O pads available for signal interconnects is not expected to
increase [3]. Also, while the output driver circuits required for high-capacitance off-chip
interconnects will necessarily remain fairly large, extremely dense I/O pads, approaching
a pitch of 20 µm by 2005 [3], will be necessary in the future. Thus, while denser signal
interconnects will be needed, they will be increasingly difficult to provide.
Long on-chip interconnects face similar throughput problems, in that interconnect
counts and densities must be increased to increase overall capacity. However, since most
of the space in current CMOS interconnect levels is filled with minimum-size wires,
7
neither interconnect numbers nor densities can be improved significantly. Scaling the
system dimensions will not improve interconnect performance because of the aspect ratio
limit. Instead, more complicated approaches will be needed to increase on-chip
bandwidth, including adding more wiring levels, implementing new system architectures,
breaking the line into shorter length segments through the use of repeater amplifiers, or,
conceivably, using more sophisticated signaling (e.g., equalization or multi-level coding).
2.1.3 DESIGN CHALLENGES
Distance-dependent loss and distortion, which lead to some of the capacity problems
mentioned above, have other serious implications in interconnect design. The magnitude
of the loss on electrical lines can be quite significant in high-speed circuit board traces.
Frequency-dependent loss also occurs, and the combination of these problems means that
long, high-bandwidth electrical interconnects must be carefully designed with a system
perspective. An off-chip interconnect designed to operate at a few hundred megahertz
will likely not work at higher frequencies, so a newly-designed link may be needed to
work at different speeds or on different length scales. These issues, together with chip
fabrication limitations, permit the use of only a relatively small number of designintensive off-chip I/Os and on-chip global wires, and necessitate the use of interconnect
hierarchies. Such a concept places restrictions on circuit design, because it requires the
designer to compartmentalize circuit functions at the expense of optimal performance.
Some design challenges arise from the tendency for electrical signals to interact with
one another. Interconnects are typically routed in a complex fashion on silicon ICs,
because electrical wires will short one another if they come in contact. Even routing
wires closely to one another presents a problem, because of the electromagnetic crosstalk
that results from capacitive coupling. Single interconnects present several design
challenges at high speeds, including the occurrence of wave reflections that must be
avoided using impedance matching techniques. Off-chip interconnects require large
drivers because of high pin inductance and capacitance. The currents required to drive
these interconnects can cause power supply noise and ground bounce. Electrostatic
discharge (ESD) is always an issue with I/O pads, and extra ESD protection circuitry is
8
required to prevent accidental circuit destruction. As will be discussed, most of these
design issues are completely avoided through the use of optics.
2.1.4 TIMING
Signal timing uncertainty becomes a greater problem as silicon circuits improve and
clock rates increase. The two main types of uncertainty, inter-channel skew and intrachannel jitter, have a few different origins. Process variations in transistors and in wiring
lead to skew that cannot easily be anticipated during layout. Changing thermal
environments on chip can cause substantial jitter, because device and wire resistances
depend on ambient temperatures. Additionally, because gate delay varies with voltage,
supply noise leads to signal jitter. Frequency- and distance-dependent loss and distortion
result in slow output transitions that are particularly problematic in long, high-speed
interconnects. Because power supply noise and process variations create input threshold
voltage variation, these finite slew rates can lead to greater skew and jitter. Together, all
of these effects can lead to timing uncertainty that can be a significant fraction of a clock
cycle at current processor speeds.
The signal integrity issues that occur with electrical interconnects for data transfer can
cause extreme problems in clock distribution networks, where sharp, well-timed clock
edges are critical for proper performance. Clock distribution currently accounts for a
large fraction of the power dissipated on CMOS processors, and this fraction is expected
to get larger in the future. This is because the difficulties in obtaining very low clock
skew across large chip areas have been overcome by placing complex, power-intensive
clock distribution networks on chips, including large clock grids and H-tree networks.
Charging and discharging the large capacitance presented by these structures consumes a
large amount of energy. As the limits of electrical interconnects draw nearer, clocking
will become even more problematic. Raising the fraction of the power budget devoted to
clocking cannot indefinitely remain the solution.
Latency, the time taken to send a piece of information from one point to another, is a
particularly important parameter for on-chip interconnects. The latency of global
9
interconnects is already too high to send data across a microprocessor within a single
clock cycle, so pipelining is employed. Low latency interconnects permit larger areas of
synchronicity, making circuit design easier and requiring fewer power-hungry latches.
Using realistic scaling assumptions [4], it is likely that signal propagation velocity on the
best repeatered RC lines will actually decrease in the future [5][6]. Combined with larger
chips and shorter clock periods, the transit time for optimized global interconnects may
reach ten or more clock cycles [6]. It is also important to consider that timing problems
get worse as latency increases, because a constant fractional deviation in propagation
velocity causes a larger absolute uncertainty. Due to the limits they place on chip design
and maximum clock frequencies, the timing issues mentioned herein may possibly
present a larger bottleneck for future silicon performance than capacity limitations of
electrical interconnects.
2.1.5 POWER DISSIPATION
On-chip energy use is important in two respects: absolute power dissipation, which is
particularly important in laptops and other portable devices; and power density, which
affects local and overall chip temperature. High temperatures adversely affect long-term
reliability due to increased electromigration and dopant diffusion, and local temperature
fluctuations influence device and interconnect performance because of the corresponding
changes in physical parameters. To achieve the highest-possible performance in future
generations of CMOS electronics, it will be necessary to carefully govern the power
devoted to interconnect issues.
One improvement that scaling provides, both for silicon devices and for
interconnects, is a reduction in the energy required for a given level of performance. A
typical analysis says that when scaling all dimensions by the factor a, both the
interconnect capacitance and the supply voltage decrease by a. Assuming the clock
frequency increases by the same factor, we can estimate the energy requirement to send
data through an interconnect by considering its dynamic power dissipation:
10
1
Pdynamic = CV 2 f
2
(2.2)
Thus, the power dissipated by a single electrical interconnect will decrease by a factor
a 2 as a system is scaled down, which is confirmed by a more detailed analysis [7] when
frequency scaling is taken into account.
While greater interconnect density and lower power dissipation is achieved by
scaling, chip sizes tend to remain constant or increase over time because of substantial
increases in complexity. Even without added functionality, extra circuitry must be added
to overcome many of the design challenges of higher frequency designs, including
repeaters to compensate for the relative increase in interconnect delay. Thus, despite the
benefits of scaling, new generations of CMOS usually have greater power dissipation
than their predecessors.
Progressively worse timing uncertainty, particularly troublesome in clock distribution
networks, must be overcome by complex schemes to reduce skew and jitter. Current
state-of-the-art chips can devote 35% or more of their total power budget to clock
distribution alone [8][9]. Thus, it appears that many of the roadblocks caused by
electrical interconnects have been postponed at the expense of power dissipation. As the
relative power devoted to these problems increases, it is clear that such an approach
cannot continue without seriously impacting the performance of silicon electronics, and
that a new approach will be needed to alleviate the looming interconnect bottleneck.
2.2 ADVANTAGES OF OPT ICAL INTERCONNECTS
Optical signaling techniques, which have been used in telecommunications networks
for many years, have recently begun to dominate in new local area network installations,
and are also being used for connections to some high-bandwidth computer peripherals.
Silicon circuit designers are beginning to face many of the same electrical problems seen
at these longer length scales and are recognizing that the benefits of optical interconnects
make them a potential solution to the electrical interconnect problems described above.
11
This section highlights some of the advantages that optics offers over conventional
electrical interconnects.
2.2.1 INTERCONNECT CAPACITY
A single optical link can carry vast amounts of data, as seen in long-distance fiber
communications, where a single fiber can be used to transit greater than 1 Tb/s of
information. Unlike their electrical counterparts in CMOS that use baseband
transmission, optical signals are encoded on an extremely high frequency carrier. Over
short distances where optical losses are low (e.g., 2-3 dB/km in a single-mode fiber at
850 nm), the capacity of a single interconnect channel could potentially be as high as
hundreds of Tb/s if appropriate technology existed. Optical links do not suffer from the
“aspect ratio limit” that was discussed earlier for electrical interconnects, and so a move
to optics would greatly increase single channel interconnect capacity. It is not physical
limitations, but practical ones, that limit achievable optical data rates to lower values.
The capacity of an optical channel is essentially independent of length at the distances
used within a computer because of the low losses in optical transmission. Thus, while
long on-chip electrical links now require repeatering to attain a high bandwidth, long
optical links do not. This implies a few advantages for on-chip interconnects: the benefits
of low latency, lower power dissipation, and simpler link design. An optical link has a
signal propagation velocity that is some significant fraction of the speed of light and
essentially constant at all data rates. Thus, above some data rate, an optical approach will
achieve a lower latency relative to an electrical one because it is not handicapped by
repeater delays. Recent studies [7][10][11] have begun looking at the relative latency
between electrical and optical interconnects, and show that optical interconnects can have
comparable latency to electrical ones for lengths greater than a few centimeters.
2.2.2 INTERCONNECT DENSITY
To achieve a high off-chip interconnect density, each I/O channel must consume a
very small area and be easily routed between chips. Optics is ideal for such high density
12
interconnects because of several reasons. At the silicon chip, emitters and detectors can
theoretically be extremely small surface-normal devices, whose density is limited by the
wavelength of light: the most common optoelectronic devices use wavelengths for which
diffraction-limited spots could be around 1 µm in diameter. Currently, the devices are
many times larger than this but are still quite small compared to typical electrical pads.
Optically-interconnected CMOS chips have already been fabricated with extremely high
device densities: in one case, with over 4,000 I/O devices on a single 7 mm x 7mm
silicon chip [12].
Free-space optical links provide an attractive method of achieving high interconnect
densities. Unlike electrical wires, optical beams can be refocused and can cross without
interaction. Simple bulk optics can provide easy packaging for free-space systems with
high interconnect counts, and a system using more than 60,000 beams has been
demonstrated [13] to support this concept. Figure 2.1 illustrates a simple unidirectional
chip-to-chip free-space optical interconnect that uses standard bulk optics and surfacenormal optoelectronic devices. Because optical fibers have reasonably large diameters,
waveguided approaches may not increase the achievable interconnect density for short
distances (e.g., centimeters to tens of centimeters) when compared to electrical methods.
However, it is possible that the development of wavelength-division multiplexing
(WDM) techniques at the interconnect level may enable this benefit. This topic will be
considered in more detail in Chapter 5.
13
Figure 2.1. Simplified schematic of a unidirectional free-space chip-to-chip optical
interconnect. A single diode laser is used as the optical source, and surface-normal
modulators at the transmitter chip encode data on each of several beams generated by a
diffractive optical element. Imaging lenses relay the modulated beams to an array of
photodetectors on the receiver chip. A polarizing beamsplitter (PBS) can be used to
reduce system losses.
2.2.3 DESIGN ISSUES
The low distance- and frequency-dependent losses of optical interconnects mean that
interconnect data rates are not limited by link lengths, but by the speeds of driving
circuitry and optoelectronics. Because the performance of an optical fiber is not
bandwidth dependent for the distances inside machines, changing the data rate of a link
requires only faster devices, and not a complete rework as in the electrical case.
Additionally, because every optical channel can travel equivalently long distances,
designers can avoid the need for interconnect hierarchies.
Optical waves tend to have very little interaction with one another. Thus, whereas
crosstalk and interference is always problematic in electrical signaling, optical beams can
touch, cross, and travel beside each other without inducing noise or signal coupling. The
inherent voltage isolation provided by optical interconnects precludes the ESD damage
that can occur with electrical connections. Using optical interconnects permits all
electrical I/O pads to be used for supply and ground. Impedance matching becomes a
simple process, because the optical equivalent of line termination in a point-to-point
optical link is a simple anti-reflection (AR) coating on the detector. Additionally, an
optical approach allows the use of simple beamsplitters for fanout to multiple points,
whereas an electrical bus requires careful impedance matching. Finally, an interesting
14
design technique afforded by optics is the possibility of non-contact testing, which can
increase profit margins by allowing high-speed yield testing before packaging is
performed. Such an approach was demonstrated several years ago with monolithicallygrown optoelectronic detectors to investigate internal signals on silicon bipolar circuits
with high timing precision [14], and can be considered an extension of optical signal
monitoring techniques that are currently employed by Intel Corporation [15].
2.2.4 TIMING
Most of the effects that introduce skew and jitter in electrical links are absent or much
reduced in the optical case. Intra-channel skew is potentially very low: a free-space
approach that keeps every channel length equal is simple to implement; also, the
negligible frequency-dependent loss of an optical approach allows extremely sharp edges
to be transmitted, which can reduce the skew resulting from process variations at the
receiver. Thermal effects, even in waveguide-based optical interconnects, introduce little
timing uncertainty relative to electrical approaches [4] because of the small dependence
of refractive index on temperature. Thus, essentially the only unavoidable interconnect
timing uncertainty is caused at the (electrical) ends of the physical link, either by
transistor variations in transmitter or receiver circuits, or because of turn-on delay
fluctuations if a directly-modulated laser is used.
Because such low jitter and skew can be obtained using optical signaling instead of
electrical techniques, optical clock distribution is a very promising initial application for
widespread use of optics in commercial computational machines. Conventional optical
techniques have the potential to provide a very precise clock phase throughout extremely
large systems (e.g., to within 10 picoseconds inside a 10-square-meter room [4]). Thus,
optical clocking could largely help to solve the power dissipation problems caused by
electrical clock distribution in current chips, because it would eliminate most of the onchip circuits needed to overcome the electrical timing limitations.
15
2.2.5 POWER DISSIPATION
As pointed out earlier, power dissipation has the potential to become a large problem
for future silicon CMOS chips. Thus, while optics offers many advantages over electrical
approaches, a practical assumption is that the power dissipated in an opticallyinterconnected system needs to be lower than, or at least equal to, a similar system with
electrical interconnects before it can gain acceptance in the industry. Currently, the best
optical interconnect links demonstrated in research environments use only a few
milliwatts of power per channel [16]. As transistor performance improves with scaling,
the power dissipated by the driver and receiver circuits will decrease. However, to reduce
power dissipation further, optoelectronic devices with lower thresholds and lower
operating voltages need to be developed. Improved device integration techniques will
also be required, to reduce the parasitic capacitance and inductance seen by the circuits.
Interconnect power dissipation is a function of many parameters, and is difficult to
properly model its effects at the system level. However, a recent attempt has been made
[7] to compare the power requirements of electrical and optical interconnects, both onand off-chip, using some of the leading optical approaches. Assuming parameters from
the 0.5-µm CMOS technology, a break-even point was determined (i.e., the length at
which optics requires less energy than electrical signaling). It was shown to be around
1-3 centimeters for on-chip interconnects, and it was shown that optics uses less energy at
all distances for off-chip interconnects. Also, their predictive models show that using ascaling assumptions, optical interconnect energy scales down faster than electrical
interconnect energy by a factor of a [7]. This indicates that optical signaling will continue
to improve compared to electrical links in terms of power dissipation.
The large power budget devoted to electrical clock distribution may also be avoided
through optical clock distribution. By placing the optical clock transmitter off-chip, a
high-quality clock can be delivered to many points on the chip without the need for
current power-intensive electrical distribution networks. This approach has the potential
to allow the continued scaling of CMOS integrated circuits, reducing the timing and
power restrictions seen in today’s designs.
16
2.2.6 NEW APPROACHES
Besides solving the limitations imposed by electrical interconnects, optics has the
potential to make entirely new concepts feasible in silicon microelectronics. One
radically new approach is the use of extremely short optical pulses from ultrafast
modelocked lasers. Since optical channels can transmit data with a very high frequency
content, it is possible to use optical pulses with picosecond widths for communication
within a computer. Ultrafast pulses can be very beneficial with respect to timing, because
the very sharp edges on short pulse optical signals enable systems that greatly exceed the
absolute timing levels obtainable with a conventional electrical approach. The use of
modelocked lasers for optical interconnects to silicon integrated circuits will be discussed
at length in a later chapter.
Wavelength-division multiplexing (WDM) is another signaling concept new to the
field of microelectronics, one that also relies on the large information capacity of optical
interconnects. Since the technique is widespread in telecommunications, many
technologies exist that could be developed for use in silicon optical interconnects. WDM
would be useful from a packaging perspective, allowing many separate channels to be
carried by a single fiber. This would enable much higher interconnect densities for
waveguided approaches, and remove any capacity limitations imposed by packaging.
Also, because expensive optical packaging is likely one of the biggest drawbacks of
optical interconnects, WDM would be useful in reducing the costs associated with optical
fiber alignment.
2.3 REALIZING OPTICAL INTERCONNECTS TO SILICON CMOS
The required elements in an optically-interconnected system include the
optoelectronic I/O devices, the electronics used to interface with these devices, and the
physical link itself (i.e., the transmission medium, and, possibly, some passive optical
components). For optics to provide a practical solution to the interconnect bottleneck, any
implementation of optical interconnects must simultaneously achieve high performance
and low cost. This requirement puts restrictions on the devices that can be considered in a
17
practical system, and also on the type of techniques used for device integration and
optical system packaging. The following section will describe the appropriate devices,
circuits, and optics for use in optical interconnects, as well as integration benefits and
techniques.
2.3.1 DEVICE INTEGRATION: RATIONALE AND BENEFITS
If optical interconnects are to achieve a high level of performance at reasonable cost,
it is desirable to employ a simple manufacturing process that can tightly combine the
advanced CMOS circuits with optimized optoelectronic I/O devices. The use of siliconbased optoelectronics would be ideal from many perspectives, as it would allow
monolithic integration of circuits and devices on a common substrate. However, because
the indirect bandgap of silicon makes it an extremely inefficient light emitter,
performance requirements prevent the use of silicon transmitter devices. Despite various
research efforts that have improved the light-emitting qualities of silicon [17], it is
unlikely that efficient silicon output devices can be used for optical interconnects to
silicon chips without a significant technological breakthrough, combined with major
modifications of the CMOS process. On the other hand, optoelectronic devices made
from III-V semiconductor materials are extremely advanced in terms of efficiency, speed,
and manufacturability, which suggests that these are the proper devices to use for optical
interconnects, provided they can be successfully integrated with conventional silicon
CMOS circuits.
The need for a high bandwidth-density product and low power dissipation lead to the
requirements of small, fast optoelectronics that are fabricated in dense two-dimensional
arrays. Surface-normal operation is also highly desirable, as it allows high interconnect
counts and simple packaging techniques. Integrating the devices very closely with the
corresponding electronics (i.e., output drivers or receiver amplifiers) is also critical to
achieve high-bandwidth and low-power operation. Short electrical connections reduce the
inductance and capacitance seen by the circuits, allowing high-speed operation, and,
particularly in optical receivers, lower power dissipation because of reduced detector
capacitance. An ideal hybrid integration solution would also allow the process steps of
18
both the optoelectronic device and CMOS circuit fabrication to remain unmodified from
their respective optimized states.
2.3.2 DEVICE INTEGRATION: TE C HNIQUES
Monolithic hybrid integration could perhaps give the highest performance by
reducing parasitic capacitances. There have been previous attempts at monolithic
integration of modulators and electronics using, for example, the FET-SEED process in
which both devices and circuits were fabricated on a III-V substrate [18]. Of course,
mainstream optical interconnects require a silicon CMOS substrate. While limited work
has shown that monolithic integration of GaAs-based modulators [19] on silicon is
possible by carefully preparing the substrate, most attempts to grow high-quality III-V
materials on actual silicon CMOS wafers have been unsuccessful. Recent work from
Motorola Labs has shown that it may be possible to grow thin (=100 Å) layers of highquality GaAs films on silicon by employing a somewhat lattice-matched interlayer [20],
although there have been no long-term studies done yet on devices fabricated from such
layers. Thus, a hybrid integration approach will be necessary until further development
takes place in the field of materials research.
Most current commercial techniques that use silicon circuits to drive III-V
optoelectronic devices involve connections using short bond wires and carefully-designed
circuit board traces. However, flip-chip bonding, an approach common in electrical
packaging, has several advantages and is the subject of increasing research in the
industrial and academic arenas. Flip-chip bonding substantially reduces the length of the
electrical connections, thereby lowering both capacitance and inductance, and thus allows
higher speeds and a reduction in power dissipation. It permits the dense integration of
many optoelectronic devices (e.g., over 16,000 I/O devices on a chip [21]). Additionally,
it enables entire device arrays to be integrated in a single operation, perhaps on a waferscale [22]. Alignment accuracy of better than 1 µm is now possible with commerciallyavailable bonders [23], potentially providing the tolerances required to align fibers to
single-mode waveguide devices.
19
While the majority of flip-chip bonding processes have been developed by industry
and are proprietary, the basic approach involves only a few steps. 1. Circuits and device
arrays are fabricated separately, typically with two coplanar contacts for each device. 2.
The contact pads of one or both chips are metalized to create the needed wetting layers,
diffusion barriers, and the appropriate materials to act as a solder. The solder bumps act
as electrical contacts, and, in many cases, provide mechanical support for the devices
following integration. Typical flip-chip processes employ indium solders that are bonded
to gold [24], gold-gold bonding [25], and gold-tin eutectic alloys [26]. 3. The device
array and CMOS chip are aligned in a flip-chip bonder and bonding is performed,
generally by applying pressure and elevating the chip temperature to soften or melt the
solder. During this “reflow” process, the surface tension of the liquid solder may be used
to achieve even better alignment [27]. 4. Following bonding, it is common practice to
remove the III-V substrate by using selective wet [24] or dry [28] etch processes, which
remove the often opaque substrate and alleviate thermal problems due to any mismatch in
the thermal expansion coefficients of the two materials. Alternatively, some researchers
have left the substrate in place and used devices grown on transparent substrates [29] or
taken advantage of the transparent CMOS substrate available using the silicon-oninsulator (SOI) technology [30]. Figure 2.2 shows an illustration of a typical flip-chip
bonding process for quantum well modulator/photodiodes.
20
Figure 2.2. Illustration of a typical flip-chip bonding process for optoelectronic device
integration with silicon CMOS chips. Steps 1-4 correspond to details listed in the text.
Many different devices have been hybridly integrated in this fashion, including input
devices such as charge-coupled-device detector arrays [31], infrared detectors for
imaging [32], and detectors connected to high-speed receivers [24].
Vertical-cavity
surface-emitting lasers (VCSELs) [33], light-emitting diodes (LEDs) [34], and multiplequantum-well optical modulators [24] have all been flip-chip bonded to provide optical
outputs.
2.3.3 OPTICAL OUTPUT DEVICES
The interconnect performance requirements, in addition to the constraints of the
hybrid integration process, help to determine the appropriate optoelectronic devices for
use in optical interconnects. There are essentially two competing technologies for highperformance, high-density output devices: VCSELs and multiple-quantum-well (MQW)
optical modulators. Both have been successfully integrated in large arrays with good
yield and performance. Also, both are superior to LEDs because they have higher
quantum efficiency, larger bandwidth, and coherent outputs. Operating wavelength has
21
little importance in choosing a suitable output device, because the optical losses that
restrict operation to certain wavelength bands in conventional optical networks are
negligible at the length scales required by optical interconnects.
VCSELs are the output device used in many recent approaches, and enable point-topoint links with the simplest coupling optics. The reduction of threshold currents through
the use of oxide confinement has solved the problem of excess power dissipation, making
VCSEL-based interconnects comparable in power usage to modulator-based approaches.
Oxide confinement should also reduce the problem of turn-on delay, which occurs when
the devices are driven from zero bias [35]. The biggest challenges for VCSELs will likely
arise due to the reduction in on-chip CMOS voltages, from yield problems for large
arrays, and in strict wavelength control. As a light emitter, a VCSEL requires a minimum
voltage drive approximately equal to or larger than the material bandgap – around 1.5
Volts for the most common 850 nm devices grown today. With technology scaling, it is
predicted that operating voltages will be only 1.2 Volts by 2003, and less than 0.8 Volts
by 2011 [3] (i.e., significantly less than the bandgap of even a 1.5 µm emitter). This will
necessitate the inclusion of additional, high-voltage lines on chips to drive or pre-bias the
VCSELs, a non-ideal solution. Yields of VCSEL arrays have improved to the point
where researchers have performed the integration of 8x8 arrays with all devices
functional [36]. It is hoped that yield problems of even larger device arrays may be
solved by careful wafer growth and process improvements, although the complexity of
VCSEL designs (and the chance of defects causing premature device fatality due to the
high current densities) exceeds that of modulators by an appreciable amount. Poor
wavelength control of integrated VCSELs poses a problem in systems using diffractive
optics or wavelength-division multiplexing techniques. Wavelength control during
fabrication is a problem similar to that of obtaining high yields, and on-chip temperature
fluctuations can result in wavelength drift of devices following integration.
MQW modulators based on the quantum confined Stark effect [37] have been
researched extensively for use as optical interconnect I/O devices in the past. They have
been shown to work at speeds exceeding 20 GHz [38], sufficient for interconnect
22
applications in the foreseeable future. Typically, the devices are simple reverse-biased pi-n diodes that operate both as transmitters and as photodiodes, thereby simplifying
integration. Very high device counts and yields (e.g., greater than 99.9% for a chip with
over 4,000 devices [12]) have been demonstrated, suggesting that fabrication issues are
not a factor that would prevent commercialization. Chapter 3 will discuss the principles
of MQW modulator operation, as well as experimental details about the design,
fabrication, integration with CMOS, and testing of these modulators.
The two main challenges in implementing MQW modulator-based optical
interconnects are the reduced contrast ratio at low voltages and the increased optical
system complexity as compared to VCSELs. The optical complexity added by
modulators is due to the fact that a separate optical source and an optical beamsplitter are
required. This drawback, however, can actually be advantageous in several respects. By
placing the emitter off-chip, thermal effects can be managed with less difficulty. The
laser can be wavelength-stabilized more easily than for an on-chip array of VCSELs,
allowing the use of precise WDM channels [39]. This approach also allows the use of
modelocked laser pulses [40], details of which will be discussed in Chapter 5.
Low contrast ratio results from the finite absorption change that can occur in a thin,
surface-normal modulator. Due to the electric field-dependency of the quantum confined
Stark effect, the reduction in CMOS voltages leads to a decrease in device performance.
In the past, the limited contrast ratio has been overcome through the use of differential
signaling. This technique makes the link very noise immune but reduces I/O density by a
factor of two. However, when the contrast ratio decreases below about 2:1, noise
becomes more of a limiting factor. Future devices will likely require the use of
approaches like Fabry-Perot cavity designs [41], or stacked n-i-p-i- diode structures [42]
to perform adequately. Chapters 3 highlights research into fabricating and integrating
MQW modulators for optical interconnects, including a new fabrication technique that
improves the contrast ratio through the use and tuning of a resonant optical cavity.
In Chapter 4, this approach is taken a step further. Using the guidelines set by the
industry in the International Technology Roadmap for Semiconductors, it is apparent that
23
the CMOS supply voltages used in future microelectronics will continue to decrease. As
will be explained, the performance of a typical MQW modulator steadily declines as its
operating voltage is decreased, which creates a problem for future system designers. The
use of a resonant optical cavity can enhance this performance for low-voltage operation;
however, previous devices using this concept have suffered from greatly reduced optical
bandwidths. Thus, a modulator with good low-voltage performance (i.e., about 1 Volt)
and wide spectral bandwidth has been designed and investigated, and will be described
further in Chapter 4.
2.3.4 OPTICAL INPUT DEVICES
Optoelectronic input devices, or photodetectors, are much simpler to construct from a
device perspective. Silicon-based devices, while not feasible as transmitters, are quite
possible for use as detectors, with a few caveats. Silicon photodiodes that are to be
fabricated on-chip using conventional CMOS processing have severe design limitations
because of the tight constraints already in place for optimizing transistor performance.
Most optical signals are in the infrared because the output devices generally work best at
these wavelengths, but the absorption length of silicon is quite long there (e.g., nearly
10 µm at 850 nm [43]). Since the diode depletion lengths are limited to only about a
micron using CMOS processes, carriers are created below the depletion regions and
result in “long tails” on the detector signals, making them poor performers at high bit
rates. Some attempts to improve the performance of these detectors have included using
novel spatially-modulated, electrically-differential designs [44], buried collection
junctions [16], and fabrication on SOI wafers, where the thin (~100 nm) silicon layer has
no substrate effects. While all of these approaches yield detectors with low responsivity
in the infrared, they could be particularly interesting for applications like optical clock
distribution, where integrated transmitters are not required.
Photodiodes fabricated from III-V semiconductors, especially GaAs p-i-n diodes, are
the most common optical input device currently under investigation. This approach,
typical in the telecommunications arena, yields devices with high bandwidth and
responsivity. When quantum well modulators are used as output devices, the same
24
devices operate well as photodiodes. The major differences between devices currently
used in long-distance optical communications and those designed for interconnects are
the stricter requirements on high density and low capacitance. Both of these conditions
lead to the desire for small devices that can achieve low power consumption and high
bandwidth densities.
Decreasing the size of conventional p-i-n photodiodes does yield devices with
reduced capacitance, and results from this approach are presented in Chapter 3. Another
approach for obtaining low-capacitance devices is to use metal-semiconductor-metal
(MSM) detectors. These simple devices use interdigitated metal “fingers” deposited on an
undoped semiconductor to create back-to-back Schottky barriers, thereby forming an
extremely low-capacitance photodetector. Large arrays of these devices have been
hybridly-integrated to silicon CMOS [45] with high yields and have the significant
advantage that they achieve very low capacitance without sacrificing detector size. This
relaxes alignment tolerances and creates a more manufacturable system.
2.3.5 OPTICS, TRANSMISSION ME D IA, AND PACKAGING
Optical fibers, which are the transmission media used in most current optical
communication systems, compete with free-space propagation as the transmission
medium for optical interconnects to silicon CMOS. Fibers and planar waveguides each
have significant advantages: fibers can provide simple, flexible links for use within a
digital system, and planar waveguides can be fabricated using accurate photolithographic
techniques. Almost all commercial optical interconnect links, including Gigabit-ethernet,
currently use fiber optics. Planar waveguide-based interconnects are being investigated
using both hybrid [46] and monolithic [47] integration techniques. However, because of
the high interconnect counts and short length scales involved in chip-to-chip
interconnection, combined with the difficulty of achieving the tight fiber waveguide
alignment tolerances required in such a system, many optical interconnect
implementations forgo the waveguided approach for a free-space one.
25
Free-space optical interconnects use air or other transparent media (i.e., glass) for
beam propagation, and simple optics (i.e., mirrors, lenses, and beamsplitters) to perform
beam steering and focusing. Diffractive optical elements can be used to perform more
complex functions, such as beam array generation. Bulk macro-optic components have
often been used in the past, where the demonstration of a working link was the primary
goal. Optomechanical concerns were primarily those of stability and ease-of-use, and the
stainless steel baseplates and bulk optics that will be described in later chapters are
examples of this approach. Concerns about practical packaging techniques, costs, and
reliability, have been avoided in most previous work, because it is a difficult problem to
solve from an academic perspective.
Recent work demonstrates that the dense hybrid integration techniques required for
optoelectronic devices may be extended to include passive optical components, greatly
enhancing packaging techniques. Elements such as diffractive [48] and refractive
microlenses [49], which have been fabricated by numerous groups, can be attached to
optoelectronic chips for free-space interconnects. Numerous optical components,
including beamsplitters, micromirrors, microlenses and optical gratings have been
integrated on a single transparent substrate for this purpose [50], and wafer-scale
attachment techniques that significantly reduce packaging costs have been demonstrated
[22][51]. Additionally, active micro-opto-electro-mechanical systems (MOEMS) have
been fabricated for use in optical interconnect applications [52] that can potentially ease
alignment issues for complex free-space systems on a single chip. It seems likely that
hybrid integration will thus allow the realization of complete optical interconnect systems
with a more elegant and inexpensive fabrication process than the demonstration systems
that have been shown in the past.
2.3.6 CIRCUITS FOR OPTICAL INTERCONNECTS
The circuits required by an optical interconnect are conceptually simple: their
functions are to drive the optical transmitters and to convert received optical inputs to
electrical signals. The appropriate circuits are thus called transmitter drivers, and
receivers, and they must integrated closely to the optoelectronics for reasons mentioned
26
above. Transmitter drivers for modulators are usually voltage output circuits, while for
VCSELs, they are current-based drivers (that may need additional biasing circuits).
Optical receivers, which are typically more complicated to design than transmitter drivers
(and can be the subject of an entire thesis) are used to amplify the small-signal voltages
created by photodetectors to the full-swing CMOS logic levels required by digital
circuits. They are analog circuits that must be optimized carefully with trade-offs
between power dissipation, area, speed, and sensitivity. The two types of receivers used
in this work are based on transimpedance amplifiers and sense amplifiers; the first is a
typical current-to-voltage converter, while the second is a clocked circuit that compares
the two inputs of a differential signal during a short integration period. Both have
particular advantages that suggest use in specific applications, and both were used in the
work that will be described in a later chapter.
All of the circuits used in this work were fabricated in conventional silicon CMOS
processes. The receivers and transmitter drivers that provide the desired modulator
biasing and receiver voltage gain were designed for roughly gigabit-per-second operation
with small area and low power consumption. Optical channels are differential to account
for the low contrast ratio of the MQW modulators with CMOS operating voltages.
Several digital circuits were used in the interconnect experiments as well, generally to
simplify obtaining measurements. More details of specific circuits used in this work will
be described when necessary, particularly during the system results chapter.
2.4 INTERCONNECT DEMONSTRATION SYSTEMS
2.4.1 CHIP-TO-CHIP DEMONSTR A TIONS
In addition to those described in this thesis, there have been a substantial number of
optically-interconnected systems demonstrated experimentally. Many of the systems are
highlighted in proceedings of the annual Optics in Computing conference, or in various
journals about the optical sciences (see, for example, special issues on optical
interconnects in the IEEE Journal of Selected Topics in Quantum Electronics [53] and
27
Proceedings of the IEEE [54]). Previous demonstrations have shown chip-to-chip optical
links that achieve very high channel counts and high I/O bandwidths, both with VCSELs
[55] and with quantum well modulators [56]. On-chip systems [57] have also been
investigated to demonstrate the potential for optics to alleviate global wiring issues. Most
of these systems use free-space approaches, but only begin to address the packaging
problems that are a barrier to commercialization.
The soon-to-be commercial 10-Gigabit Ethernet approaches taken by industry have
demonstrated that low-cost optical packaging is possible with low-channel-count fiberbased links. Denser integration and new packaging techniques will be required in
optically interconnected systems for future CMOS applications. One promising approach
is the recent flip-chip bonding of optoelectronics to transparent-substrate silicon-oninsulator CMOS circuits by researchers at Peregrine Semiconductor [30]. CMOS circuits
fabricated on SOI are particularly good for analog functions because the absence of a
silicon substrate reduces parasitic capacitances. The approach is ideal for making highspeed, noise-immune optical links (e.g., 3.125 Gb/s transmission has been demonstrated,
with >10 Gb/s predicted by 2003 using devices bonded to SOI circuits [30]), and has the
added benefit of allowing optical transmission through the chip itself. The process would
easily lend itself to integration with the passive optical elements mentioned earlier,
making it very attractive for commercial packaging of dense, two-dimensional, free-space
optical links. Such an approach, while not the subject of this thesis, would be an excellent
topic for future systems research.
2.4.2 SHORT OPTICAL PULSES AND OPTICAL INTERCONNECTS
In addition to conventional high-bandwidth chip-to-chip links, it is possible to
consider many interesting interconnect demonstrations that present new system designs
and architectures. For example, ultrafast optical techniques (i.e., using very short laser
pulses) are potentially very useful in the field of long-distance telecommunications.
Using ultrashort pulses could allow very high bit rates to be achieved through timedivision multiplexing (TDM). Interestingly, however, the use of short optical pulses also
28
provides many benefits in optical interconnect applications, where serial data rates are
relatively low.
Modelocked lasers have the potential to provide optical pulses that are very short and
with very low jitter compared to typical electrical signals. These characteristics make
short laser pulses from such sources ideal for many timing applications, and
advantageous in areas such as latency reduction and receiver sensitivity enhancement.
While some of these benefits have been proposed in the past, few experimental results
exist to quantify short pulse advantages in interconnect applications. Chapter 5 will
provide the details of several experiments and demonstrations that probe the use of short
optical pulses in optical interconnects.
29
REFERENCES
1. D. A. B. Miller, and H. M. Özaktas, J. Parallel Distrib. Comput., 41, 42 (1997).
2. M. Horowitz, C.-K. K. Yang, and S. Sidiropoulos, IEEE Micro, 18, 12 (1998).
3. Semiconductor Industry Association, International Technology Roadmap for
Semiconductors, 2001 Edition, http://public.itrs.net/Files/2001ITRS/Home.htm.
4. P. Kapur, J. P. McVittie, and K. C. Saraswat, IEEE Trans. Electron. Dev., 49, 590
(2002).
5. D. A. B. Miller, Proc. IEEE, 88, 728 (2000).
6. P. Kapur, G. Chandra, J. P. McVittie, and K. C. Saraswat, IEEE Trans. Electron.
Dev., 49, 598 (2002).
7. G. I. Yayla, P. J. Marchand, and S. C. Esener, Applied Optics, 37, 205 (1998).
8. D. W. Bailey and B. J. Benschneider, IEEE J. Solid-State Circuits, 33, 1627 (1998).
9. C. J. Anderson, J. Petrovick, J. M. Keaty, J. Warnock, G. Nussbaum, J. M. Tendier,
C. Carter, S. Chu, J. Clabes, J. DiLullo, P. Dudley, P. Harvey, B. Krauter, J. LeBlanc,
L. Pong-Fei, B. McCredie, G. Plum, P. J. Restle, S. Runyon, M. Scheuermann, S.
Schmidt, J. Wagoner, R. Weiss, S. Weitzel, and B. Zoric, International Solid State
Circuits Conference 2001, San Francisco, California, p. 232 (2001).
10. D. Agarwal, and D. A. B. Miller, IEEE Lasers and Electro-Optics Society Annual
Meeting 2001, San Diego, California, p. 812 (2001).
11. E. D. Kyriakis-Bitzaros, N. Haralabidis, Y. Moisiadis, M. Lagadas, A. Georgakilas,
and G. Halkias, Opt. Eng., 40, 144 (2001).
12. A. L. Lentine, K. W. Goossen, J. A. Walker, L. M. F. Chirovsky, L. A. D’Asaro, S. P.
Hui, B. J. Tseng, R. E. Leibenguth, J. E. Cunningham, W. Y. Jan, J. M. Kuo, D. W.
Dahringer, D. P. Kossives, D. Bacon, G. Livescu, R. L. Morrison, R. A. Novotny, and
D. B. Buchholz, IEEE J. Sel. Top. Quantum Electron., 2, 77 (1996).
13. F. B. McCormick, T. J. Cloonan, F. A. P. Tooley, A. L. Lentine, J. M. Sasian, J. L.
Brubaker, R. L. Morrison, S. L. Walker, R. J. Crisci, R. A. Novotny, S. J. Hinterlong,
H. S. Hinton, and E. Kerbis, Appl. Opt., 32, 5153 (1993).
30
14. J. D. Morse, R. P. Mariella, G. D. Anderson, and R. W. Dutton, IEEE Electron
Device Lett., 12, 379 (1991).
15. M. Paniccia, R. M. Rao, and W. M. Yee, J. Vacuum Science Technol. B, 16, 3625
(1998).
16. T. K. Woodward, and A. V. Krishnamoorthy, Electron. Lett., 34, 1252 (1998).
17. L. C. Kimerling, K. D. Kolenbrander, J. Michel, and J. Palm, Solid State Phys., 50,
333 (1997).
18. D. A. B. Miller, M. D. Feuer, T. Y. Chang, S. C. Shunk, J. E. Henry, D. J. Burrows,
and D. S. Chemla, IEEE Photon. Technol. Lett., 1, 61 (1989).
19. J. E. Cunningham, K. W. Goossen, J. A. Walker, W. Jan, M. Santos, and D. A. B.
Miller, J. Vacuum Science Technol. B, 12, 1246 (1994).
20. D. S. Burgess, Photonics Spectra, 35, 22 (2001).
21. T. L. Worchesky, K. J. Ritter, R. Martin, and B. Lane, Appl. Opt., 35, 1180 (1996).
22. K. Giboney, J. Simon, L. Mirkarimi, B. Law, G. Flower, S. Corzine, M. Leary, A.
Tandon, C. Kocot, S. Rana, A. Grot, K.-J. Lee, L. Buckman, and D. Dolfi, IEEE
Lasers and Electro-Optics Society Annual Meeting 2001, San Diego, California, p.
859 (2001).
23. Suss MicroTec Automatic Flip Chip Bonder, model FC150, technical specifications.
24. K. W. Goossen, J. A. Walker, L. A. D’ Asaro, S. P. Hui, B. Tseng, R. Leibenguth, D.
Kossives, D. D. Bacon, D. Dahringer, L. M. F. Chirovsky, A. L. Lentine, and D. A.
B. Miller, IEEE Photon. Technol. Lett., 7, 360 (1995).
25. T. S. McLaren, S. Y. Kang, W. Zhang, T.-H. Ju, and Y.-C. Lee, IEEE Trans.
Components, Packaging, and Manufacturing Technol. B, 20, 152 (1997).
26. C. C. Lee, C. Y. Wang, G. S. Matijasevic, IEEE Trans. Components, Hybrids, and
Manufacturing Technol., 14, 407 (1991).
27. T. Hayashi, IEEE Trans. Comp., Hybrids, and Manufac. Technol., 15, 225 (1992).
28. R. J. Olson Jr., M. F. Taylor, R. J. Williams, T. S. Faska, and M. Sundaram, 1999
GaAs MANTECH Conference, Vancouver, Canada, p. 179 (1999).
29. E. M. Strzelecka, D. A. Louderback, B. J. Thibeault, G. B. Thompson, K. Bertilsson,
and L. A. Coldren, Appl. Opt., 37, 2811 (1998).
31
30. C. B. Kuznia, D. J. Albares, M. Pendleton, M. Wong, M. Englekirk, T. Le, S. Thai,
M. P. Divakar, R. Weiss, J. Cable, and R. E. Reedy, IEEE Lasers and Electro-Optics
Society Annual Meeting 2001, San Diego, California, p. 810 (2001).
31. Y. Kondoh, and M. Saito, IEICE Trans. Communications Electronics Information
and Systems, 74, 2355 (1991).
32. D. A. Scribner, M. R. Kruer, and J. M. Killiany, Proc. IEEE, 79, 66 (1991).
33. A. V. Krishnamoorthy, L. M. F. Chirovsky, W. S. Hobson, R. E. Leibenguth, S. P.
Hui, C. J. Zydzik, K. W. Goossen, J. D. Wynn, B. J. Tseng, J. Lopata, J. A. Walker, J.
E. Cunningham, and L. A. D’Asaro, IEEE Photon. Technol. Lett., 11, 128 (1999).
34. R. Bockstaele, T. Coosemans, C. Sys, L. Vanwassenhove, A. Van Hove, B. Dhoedt, I.
Moerman, P. Van Daele, R. G. Baets, R. Annen, H. Melchior, J. Hall, P. L.
Heremans, M. Brunfaut, and J. Van Campenhout, IEEE J. Sel. Top. Quantum
Electron., 5, 224 (1999).
35. L. A. Coldren, and S. W. Corzine, Diode Lasers and Photonic Integrated Circuits,
John Wiley and Sons, Inc., New York (1995).
36. R. Pu, E. M. Hayes, C. W. Wilmsen, K. D. Choquette, H. Q. Hou, and K. M. Geib, J.
Opt. A, Pure Appl. Opt., 1, 324 (1999).
37. D. A. B. Miller, D. S. Chemla, T. C. Damen, A. C. Gossard, W. Wiegmann, T. H.
Wood, and C. A. Burrus, Phys. Rev. B, Condens. Matter, 32, 1043 (1985).
38. C. C. Barron, C. J. Mahon, B. J. Thibeault, and L. A. Coldren, Opt. Quant. Electron.,
25, S885 (1993).
39. E. A. De Souza, M. C. Nuss, W. H. Knox, and D. A. B. Miller, Opt. Lett., 20, 1166
(1995).
40. G. A. Keeler, D. Agarwal, B. E. Nelson, N. C. Helman, and D. A. B. Miller,
Conference on Lasers and Electro-Optics 2002, Long Beach, California (2002).
41. R. H. Yan, R. J. Simes, and L. A. Coldren, IEEE Photon. Technol. Lett., 1, 273
(1989).
42. X. Wu, K. H. Gulden, M. Thomas, J. S. Smith, J. R. Whinnery, S. Malzer, P. Kiesel,
M. Kneissl, and G. H. Dohler, Appl. Phys. Lett., 62, 152 (1993).
32
43. S. M. Sze, Physics of Semiconductor Devices, p. 750, Wiley Interscience, New York
(1981).
44. D. Coppee, W. Pan, J. Stiens, R. Vounckx, and M. Kuijk, Solid-State Electronics, 43,
609 (1999).
45. Y Liu, Optics in Computing 1998, Brugge, Belgium, in Proceedings of SPIE, PV
3490, p. 528 (1998).
46. S. Matsuo, T. Nakahara, K. Tateno, and T. Kurokawa, IEEE Photon. Technol. Lett.,
8, 1507 (1996).
47. C. H. Henry, G. E. Blonder, and R. F. Kazarinov, J. Lightwave Technol., 7, 1530
(1989).
48. H. Thienpont, V. Baukens, R. Buczynski, H. Ottevaere, B. Volckaers, C. Debawa, P.
Tuteleers, P. Vynck, A. Hermanne, I. Veretennicoff, M. Taghizadeh, and M. Hanney,
Trends in Optics and Photonics 2000, Quebec City, Canada, p. 269 (2000).
49. S. Haselbeck, H. Schreiber, J. Schwider, and N. Streibl, Opt. Eng., 32, 1322 (1993).
50. J. Jahns, Proc. IEEE, 82, 1623 (1994).
51. M. R. Feldman, IEEE Lasers and Electro-Optics Society Annual Meeting 2001, San
Diego, California, p. 497 (2001).
52. L. Y. Lin, S. S. Lee, K. S. J. Pister, and M. C. Wu, IEEE Photon. Technol. Lett., 6,
1445 (1994).
53. IEEE J. Sel. Top. Quantum Electron., 5 (1999)
54. Proc. IEEE, 88 (2000).
55. T. Maj, A. G. Kirk, D. V. Plant, J. F. Ahadian, C. G. Fonstad, K. L. Lear, K. Tatah,
M. S. Robinson, and J. A. Trezza, Appl. Opt., 39, 683 (2000).
56. D. V. Plant, B. Robertson, H. S. Hinton, W. M. Robertson, G. C. Boisset, N. H. Kim,
Y. S. Liu, M. R. Otazo, D. R. Rolston, and A. Z. Shang, IEEE Photon. Technol. Lett.,
7, 1057 (1995).
57. M. W. Haney, M. P. Christensen, P. Milojkovic, G. J. Fokken, M. Vickberg, B. K.
Gilbert, J. Rieve, J. Ekman, P. Chandramani, and F. Kiamilev, Proc. IEEE, 88, 819
(2000).
33
CHAPTER 3: MQW MODULATOR DESIGN, FABRICATION, AND
INTEGRATION
Although optical interconnects offer many advantages over electrical wires, they will
continue to be topics of research in the laboratory until several challenges are met. One
such barrier to commercialization is that only a few companies have begun to develop the
techniques required to integrate silicon CMOS and the necessary optoelectronic devices.
In fact, since dense optoelectronic integration is not currently used in products, the dense
arrays of optoelectronics required for optical interconnect applications are extremely
difficult to acquire from commercial vendors.1 Thus, in order to perform investigations of
optical interconnect concepts and systems, it was necessary to fabricate and integrate the
appropriate optoelectronic devices in-house. As stated in the previous chapter, optical
output devices are the most difficult optoelectronic components to produce with high
yields. The growth and fabrication of VCSELs can be particularly challenging due to the
complexity involved. Multiple quantum well (MQW) modulators, on the other hand, are
amenable to high-yield array integration (even in a university research environment), and
still afford the advantages of high density, high speed, and low power consumption. This
chapter will outline the principles of operation of these devices, the materials
considerations, the fabrication and integration techniques that were developed during this
work, and will summarize the performance of the resulting devices.
3.1 PRINCIPLES OF OPERATION
All of the integrated optoelectronic devices described in this dissertation rely on the
optical absorption in semiconductors. What follows is a brief summary of the
semiconductor physics that was employed in the design of the devices, as well as the
1
Note, however, that the techniques used to fabricate dense, two-dimensional arrays of
VCSELs, modulators, and detectors, have certainly been developed, and can be found
in some detail in the literature. As optical interconnects find more commercial
applications, device fabrication may not be one of the larger problems.
34
engineering used to achieve the modulator performance required for use in an opticallyinterconnected system.
3.1.1 SEMICONDUCTOR OPTICAL ABSORPTION
Electrons and their oppositely-charged counterpart, holes, are the charge carriers in
semiconductor crystals. A good introduction to the typical behavior and interaction of
these carriers in a semiconductor can be found in many elementary texts [1]. A basic
picture is that carriers can exist in either the valence or conduction band; these bands,
which arise from the repeating potential of the crystal lattice, are separated by the
material’s inherent bandgap energy. An undoped semiconductor, known as an intrinsic
one, has essentially all of the electronic states in the valence band filled by electrons, with
no electrons in the higher-energy conduction band. Semiconductors that are intentionally
doped with atoms to provide an excess of electrons or holes are called n-type and p-type
semiconductors, respectively. The extra carriers present in these doped materials are
somewhat free to move around, leading to electrical conduction. A p-n diode, formed by
placing p-type and n-type semiconductors adjacent to one another, tends to conduct
current only when biased in the forward direction. It is under reverse bias, where little
current flows, that our p-type/intrinsic/n-type (or p-i-n) modulators are used.
The bandgap energy of many semiconductors is approximately equal to the energy of
a single optical photon in the visible or near-infrared portion of the spectrum. Perhaps not
surprisingly, electrons and holes can interact with photons that have an energy similar to
this bandgap. When photons with sufficient energy travel through a semiconductor, they
are absorbed and cause the promotion of electrons from the valence to conduction band
(and the corresponding creation of holes in the valence band). Alternatively, electrons in
the conduction band can recombine with holes in the valence band to emit a photon.
These interactions must conserve momentum, and consequently the most efficient
carrier/photon interactions occur in so-called direct bandgap materials, such as gallium
arsenide, that allow appropriate transitions to occur easily.
35
A few final complications to the physics of optical absorption within a semiconductor
include the addition of excitons and quantum wells. When an electron and a hole exist
simultaneously and in close proximity, they often form a single, closely-coupled particle
known as an exciton (which is somewhat analogous to a hydrogen atom with a lower
binding energy). A quantum well is a thin region (~100 Å) of smaller-bandgap
semiconductor material (the well) sandwiched between two higher-bandgap materials
(the barriers). The barriers tend to confine the electron wavefunction, which is used to
describe carrier position within the semiconductor from a quantum mechanical
perspective, within the quantum well. This results in a localization of carriers within the
well and leads to discrete energy sub-bands and a modified density of states. Combined
with quantum selection rules that determine allowed transitions, as well as the existence
of the light and heavy holes, this physics can explain most salient features of the optical
absorption versus energy relationship used by quantum well modulators. Figure 3.1
illustrates the basic optical absorption process in a quantum well, as well as an idealized
schematic of the optical coefficient, α, versus energy that results when some of the
consequences of excitons are omitted for simplicity.
Figure 3.1. Optical absorption in a quantum well. Absorption of an incident photon
causes an electronic transition between quantized energy states in the well, and gives rise
to the staircase-like dependence of absorption on photon energy. The envelope of the
absorption profile arises from the density of states, which is proportional to vE.
3.1.2 THE QUANTUM CONFINED S TARK EFFECT
Optical absorption in a semiconductor enables the fabrication of photodetectors,
which act to convert incident photons to electrical carriers that can be sensed by an
36
external circuit. A p-i-n photodiode is a simple and common photodetector that typically
has high speed and responsivity because of efficient absorption and a significant internal
electric field that enables collection of most photogenerated carriers. While a static
absorption profile is useful in making a photodiode, it is the ability to alter that absorption
profile with an applied electric field that makes electroabsorption modulators possible. In
bulk semiconductors, this phenomenon is known as the Franz-Keldysh effect, and is
essentially a movement of the absorption edge to lower energies because of excitonic
linewidth broadening (i.e., a reduction in exciton lifetime) [2]. While this effect is
somewhat weak, the absorption change is strong enough to make waveguide modulators
because of their long semiconductor/photon interaction length.
In a modulator that relies upon surface-normal operation, the interaction length is
significantly reduced and a stronger change in absorption is required to achieve sufficient
modulation depth. The effect used by most devices to provide this large ∆α is known as
the quantum-confined Stark effect (QCSE) [3]. The QCSE occurs when an electric field
is applied in the direction perpendicular to a quantum well. As in the Franz-Keldysh
effect, the electric field acts to pull apart the exciton. In a quantum well, however, the
barriers confine the carriers and keep the exciton intact, leading to a substantial reduction
in lifetime broadening. The electric field also causes a Stark effect shift of the quantum
well energy levels, which again moves the absorption to lower energies. This effect can
be seen in the measured data shown later in this chapter.
3.1.3 INTEGRATED SURFACE-NO R MAL ELECTROABSORPTION MQW MODULATORS
To make an electroabsorption modulator using the quantum-confined Stark effect, the
typical approach is to place an absorbing quantum well region in the intrinsic layer of a pi-n diode. Doing so creates the typical p-i-n photodiode structure commonly used in
communications, and enables large fields to be placed across the quantum wells without
inducing large currents. By applying a static reverse bias across the diode,
photogenerated carriers are efficiently swept out of the intrinsic region and the device
acts as a photodetector. Varying this bias causes a modulation in the optical absorption,
resulting in an optical modulator.
37
Surface-normal operation of MQW modulators (as opposed to waveguide operation),
is an effective way to achieve the high device density and simple optical coupling
required for dense optical interconnection. To increase the absorption of the photons in
the device, surface-normal modulators often use an absorbing region that contains many
(e.g., 50-200) quantum wells. Figure 3.2 illustrates the operating principle of a
(reflective) electroabsorption modulator. Such devices are typically operated at either the
low-field or high-field excitonic absorption peak position (known as the λ0 and
λ1 operating points), where the absorption change is largest. This change in absorption is
accompanied by a small change in the real refractive index. The index change is
insignificant in most surface-normal devices, but can be important in waveguide devices
and in small resonant cavities, and will be discussed further in the next chapter. Quantum
well modulators can be integrated to electronics in two-dimensional arrays by flip-chip
bonding, and Figure 3.3 shows a schematic of the integrated modulators described in this
work. Because the devices can operate both as modulators and as photodiodes,
fabrication and integration of a single device array adds both optical input and output
capabilities to an electronic chip.
Figure 3.2. Operation of a surface-normal reflection electroabsorption modulator.
Changing the reverse bias across the intrinsic region alters the absorption characteristics,
allowing voltage-controlled beam modulation. Typical GaAs-based quantum well
structures are designed for operation at a wavelength of approximately 850 nm.
38
Figure 3.3. Schematic of a quantum well modulator integrated to silicon CMOS.
Coplanar contacts enable simple integration to electrical pads on the chip. The reflective
p-contact is used to send the input beam through the absorptive quantum wells in the
intrinsic region twice.
3.2 WAFER DESIGN, GROWTH, AND TESTING
Most semiconductor optoelectronic devices are fabricated on thin (i.e., ~500 µm),
single-crystal semiconductor substrates, using even thinner (i.e., ~10’s to 1000’s of
Ångstroms thick) epitaxial layers of other semiconductors as the active materials. The
structures used in this work were grown on a gallium arsenide substrate using solidsource molecular beam epitaxy (MBE). Because the GaAs substrate is opaque at the
wavelengths of interest in this work, it was removed after device integration to leave only
the thin epitaxial devices integrated on the electronic chip. The purpose of this section is
to briefly discuss the design, growth, and testing of the epilayers used for MQW
modulator fabrication.
3.2.1 WAFER GROWTH AND DES IGN
The growth of epistructures by solid-source MBE is a well-known technique, and
details of the process can be found elsewhere [4]. While there are several choices of
semiconductor that could be used to fabricate electroabsorption modulators, all devices
described in this thesis were based on the GaAs/AlGaAs semiconductor family. The
39
growth and processing techniques already developed for the gallium arsenide system are
more advanced than for any other compound semiconductor, and most fundamental
properties can be found in the literature [5]. These facts, combined the availability of
wafer growth facilities, makes GaAs the ideal material choice.
To design the modulator wafer epitaxial structure, all optical absorption phenomena
and quantum effects mentioned at the beginning of this chapter (as well as additional,
more detailed behavior) can be used to model the device’s optical absorption in response
to an applied electric field. In practice, however, a semi-empirical model that uses a
combination of calculated and experimentally-derived absorption data is a more efficient
way to design devices. Chapter 4 and Appendix B describe the numerical simulations
used in modeling improved modulator designs, but the basic structure of the modulators
was first designed by assuming a simple double-pass device. Quantum well absorption
data was taken from the literature for various well widths, and was compared to transfermatrix numerical calculations to verify that the chosen quantum well and barrier
thickness properly matched the desired absorption energy.
In order to use existing diode lasers (with an output wavelength of 850 nm), the GaAs
well width was chosen to be 95 Å, and the Al0.3Ga0.7As barrier thickness was 30 Å. Given
an intrinsic region with such a repeated structure, an analysis of exciton shift versus
electric field showed that a design with 50 wells would achieve a satisfactory trade-off
between exciton shift and total absorption (i.e., optical bandwidth and modulation depth)
for a 3-Volt operating swing. Doping levels in the p+ and n+ regions were chosen to
allow low-resistance ohmic contacts to the diode, and a high aluminum-content AlGaAs
layer was placed at the bottom of the epistructure as an etch stop layer, allowing easy
substrate removal following integration. Table 3.1 shows the final wafer design. The thin
GaAs cap layer at the surface of the structure was added to prevent oxidation of the
p-AlGaAs layer underneath, and the GaAs buffer layer is used to protect the n-AlGaAs
layer after integration and etch stop removal (as well as for cavity tuning in Chapter 4).
40
Table 3.1. Design of the modulator epitaxial structure.
Description
Material
Thickness (Å)
Dopant (cm-3)
p cap layer
GaAs
100
[Be]=1.0x1019
p layer
p-Al0.3Ga0.7As
2,030
[Be]=1.0x1019
GaAs
Al0.3Ga0.7As
95
30
—
n layer
n-Al0.3Ga0.7As
5,000
[Si]=4.4x1018
buffer layer
GaAs
500
—
etch stop layer
Al0.85Ga0.15As
2,800
—
i (MQW) layer
50 x
undoped (100) GaAs substrate
3.2.2 WAFER TESTING AND RES U LTS
To test both the material quality and the optical and electrical characteristics of the
structure, several test structures were fabricated on different parts of each grown wafer.
Due to difficulties in obtaining high quality material (and to help calibrate the MBE
growth rates), many (i.e., ~15-20) wafers were processed and tested before the
modulators could be fabricated. Standard ohmic contacts were placed on different
portions of the wafer to test electrical characteristics. Most n-doped layers exhibited quite
good performance, with very low resistance (i.e., a few ohms) between contacts. P-doped
layers typically showed higher resistance and poorer ohmic behavior, indicating a lower
doping density than was intended. This issue was resolved by increasing the doping
density of the 100 Å GaAs cap layer.
In order to test electrical diode performance and optical characteristics, device mesas
with top contact rings (p-contacts) and bottom contact rings (n-contacts) were fabricated.
The mesa test structure is shown in Figure 3.4. Diode I-V curves were obtained for a
large number of devices by electrical probing. Poor p-contacts contributed to the high
turn-on voltage of several early wafers, and poor intrinsic layer material quality was
41
evident in the low reverse-breakdown voltage of many devices (i.e., ~5 Volts). These
problems were finally resolved when good wafers were obtained (i.e., wafers #662 and
#472). Figure 3.5 shows the electrical characteristics of diodes on a few different wafers,
and includes the proper diode-like behavior, which was measured on wafer #662.
Figure 3.4. Mesa test structure used to characterize the epitaxial wafer. Mesa dimensions
are 300 µm x 300 µm.
42
0.006
wafer 662
wafer 419
0.004
wafer 646
wafer 647
0.002
0
-0.002
-15
-10
-5
0
5
Voltage (V)
Figure 3.5. Diode electrical characteristics for various wafers. Wafer #662 exhibits both a
low forward turn-on voltage and negligible reverse breakdown and leakage current. (The
limit on current at high forward bias is set deliberately in the measuring instrument to
avoid device damage.)
Optical absorption testing was performed by combining electrical probing with
optical probing under a wavelength-tunable Titanium:sapphire laser beam. Photocurrent
measurements were performed on the mesa structures as a function of wavelength and
applied bias, with the higher-quality material exhibiting the expected strong excitonic
absorption at the proper transition energies and a QCSE shift with little excitonic
broadening at high fields. The effective absorption coefficient of the intrinsic MQW
layer, a(?,V), was calculated from this data using the relationships:
S (λ , V ) =
and
S (λ , V ) =
I ph (λ , V )
Pinc
eηext λ
1 − e −α ( λ ,V ) L 
hc 
(3.1)
(3.2)
43
where S is the diode responsivity, Iph is the measured photocurrent, Pinc is the incident
optical power, ?ext is the external quantum efficiency, and L is the intrinsic layer
thickness. The assumptions were also made that: 1) There is no absorption outside of the
intrinsic region, 2) All photogenerated carriers are collected, and, 3) The uncoated
semiconductor/air interface reflects 32% of the incident beam, giving ?ext = 0.68. The
resulting absorption coefficient versus wavelength at various applied voltages is shown in
Figure 3.6. Included is the absorption profile of bulk GaAs as taken from the literature
[6][7] for comparison.
14000
0V
1V
2V
3V
4V
5V
6V
GaAs bulk
Absorption Coefficient (cm-1)
12000
10000
8000
6000
4000
2000
0
825
835
845
855
865
875
885
Wavelength (nm)
Figure 3.6. Absorption coefficient versus wavelength, as calculated from photocurrent
measurements for different applied biases (for wafer #472).
3.3 DEVICE FABRICATION
The quantum well modulators were fabricated in arrays intended for integration
directly onto silicon CMOS chips. The devices are 40 µm x 80 µm in size and use
coplanar n-contacts and p-contacts to facilitate flip-chip bonding. Each two-dimensional
array of diodes contains 200 modulators with a device pitch of 62.5 µm x 125 µm. Using
44
a seven-mask process, hundreds of modulator arrays were fabricated in parallel from a
section of the previously-tested GaAs wafer. While the devices closely resemble
modulators fabricated earlier by Lucent [8], the process used in our work was developed
almost entirely from scratch. Figure 3.7 illustrates the fabrication process flow and the
caption provides an overview of the processing steps. (A more complete discuss of the
process flow and fabrication techniques can be found in Appendix A.) After processing
was completed, the devices were ready to be integrated to electronics by flip-chip
bonding. Figure 3.8 shows two scanning electron micrographs of a processed modulator
array prior to integration.
(c)
(b)
(d)
(a)
(e)
(g)
(f)
Figure 3.7. The quantum well modulator process flow. Beginning with a section of the 2inch GaAs wafer (a), a timed etch was used to open windows into the n-doped region (b).
In these windows, a 20 µm x 20 µm n-type Ohmic contact was deposited and annealed
(c). A smaller, reflective gold p-type Ohmic contact was then deposited (d), and used in
combination with a photoresist mask to perform a self-aligned active area definition etch
(e) to reduce device capacitance. 3-6 µm of indium was deposited onto the contacts for
use as a flip-chip solder bond (f), and the device was isolated from its neighbors using a
mesa etch (g).
45
Figure 3.8. Scanning electron micrographs of quantum well devices following
fabrication.
3.4 INTEGRATION TECHN IQUE
As mentioned in Chapter 2, flip-chip bonding is currently the most effective method
of performing dense hybrid integration of III-V optoelectronics and silicon CMOS
electronics. The quantum well modulator arrays were integrated to several different
silicon CMOS chips in this manner. The digital and analog CMOS circuits, some of
which will be described in more detail in Chapter 5, were designed with a common flipchip bonding pad array that matched the fabricated device specifications. Because the
uppermost metal level of CMOS is typically aluminum, each chip required a preparatory
metalization step to allow indium/gold bonding. The CMOS bonding pads were covered
with a chromium/copper/gold layered structure to provide, respectively, a sticking layer,
a gold/aluminum diffusion barrier, and an indium bonding layer.
Flip-chip integration followed the typical process briefly outlined in Chapter 2. Both
a CMOS chip and a cleaved array of devices were visually aligned in a commercial flipchip bonder to an alignment accuracy of better than ± 2 µm. A bonding pressure
46
corresponding to 1-2 grams/bump was applied for several seconds, often at an elevated
temperature (but below the melting point of indium at ~180 °C) to improve the electrical
properties of the contacts. A low-viscosity epoxy was wicked between the bonded chips
to provide mechanical support and to protect both chips during the subsequent etch steps.
After curing the epoxy, the gallium arsenide substrate was removed using a combination
of selective and non-selective wet chemical etching. The substrate etch stopped on the
high-aluminum-content AlGaAs etch stop layer, exposing isolated MQW modulators
integrated to the silicon chip. An epoxy removal step was used to expose the CMOS wire
bond pads for chip packaging and testing. Figure 3.9 shows scanning electron
micrographs of device arrays after bonding and substrate removal, both on an electrical
test chip and on a functional silicon CMOS chip.
Figure 3.9. Scanning electron micrograph of a quantum well modulator array on (a) a
silicon test structure, and, (b) a functional CMOS chip (note the uppermost level of metal
wiring).
47
3.5 PERFORMANCE OF INTEGRATED DEVICES
The double-pass, surface-normal MQW modulators were designed to achieve
maximum modulation depth with a limited (i.e., ~3 Volts) operating voltage swing. Using
the highly-reflective p-contact as a mirror (and assuming a gold reflectivity of 92% at 850
nm [9]) the anticipated device performance was calculated with the absorption coefficient
data shown previously. Figure 3.10 shows the two most important parameters used to
measure optical performance, namely, change in reflectivity and contrast ratio, defined
as:
∆R = RON − ROFF
(3.3)
and
CR =
RON
ROFF
(3.4)
where RON and ROFF are the modulator reflectivity in the low-absorption and highabsorption states. These plots are for operation between 0 and 3 Volts, and neglect the
reflection at the semiconductor/air interface on top of the device.
48
2.5
0.4
0.3
∆R
CR
2
0.2
1.5
0.1
0
1
-0.1
0.5
-0.2
-0.3
830
0
835
840
845
850
855
860
865
Wavelength (nm)
Figure 3.10. Simulated device performance based on measured absorption coefficients
and assuming a simple double-pass device. Note the anticipated peak performance of ? R
~35% and a contrast ratio of 2:1.
The reflectivity curves measured on actual integrated devices exhibited several effects
in addition to the idealized case shown above. One such effect is a lower overall
reflectivity due to added losses that result from imperfect contact reflectivity (because of
metallic diffusion occurring at the Au/GaAs interface), scattering at the top surface of the
device, and the reflective losses that occur because the devices were not anti-reflection
(AR) coated. AR-coating was not attempted because of difficulties in finding a deposition
process that used a temperature compatible with processed CMOS chips. This lack of
AR-coating had another significant impact: it created an optical cavity whose resonance
was situated at a random wavelength. Absorption is enhanced at the cavity resonance
position and weakened for off-resonance wavelengths, significantly changing the
performance of the device.2 With no effective method to control the Fabry-Perot cavity
thickness, the device performance parameters depended somewhat on substrate etch
2
This effect can be used as an advantage, as is discussed further in Chapter 4, but was
accepted as an inconvenience with the present devices.
49
times and position on the original gallium arsenide wafer. Figure 3.11 shows the
measured reflectivity of a typical modulator, with the Fabry-Perot cavity resonances
apparent at wavelengths of 832 nm and 883 nm (and far from the excitonic absorption
peak positions from 843 nm to 854 nm). Modulator change in reflectivity for 3-Volt
swings ranged from about 0.10 to 0.25 for all measured devices, while maximum contrast
ratio was typically only about 1.6:1. By forward-biasing the diodes and causing LED
emission to occur, the device yield within single arrays was investigated. Through careful
processing, yields approaching 100% were routinely achieved. Figure 3.12 shows a
bonded diode array in forward bias.
0.9
0 Volts
1 Volt
2 Volts
3 Volts
4 Volts
5 Volts
6 Volts
0.8
0.7
0.6
0.5
0.4
0.3
0.2
0.1
0
830
840
850
860
870
880
890
Wavelength (nm)
Figure 3.11. Representative measured device reflectivity versus wavelength for various
applied voltages. Operating wavelengths for the modulator (i.e., between about 844 nm
and 855 nm) do not coincide with the Fabry-Perot resonance peak positions.
50
Figure 3.12. Integrated array of quantum well diodes in forward bias. Optical emission
was used to investigate device yield, which exceeds 97% on this chip.
Measured device responsivity, which was obviously wavelength-dependent, was
measured to be in the range of 0.2 A/W to 0.3 A/W for wavelengths corresponding to the
modulator operating wavelengths. For devices with an active area of 40 µm x 40 µm (i.e.,
modulators fabricated before the self-aligned etch was developed), the capacitance was
calculated to be about 260 fF. This value was confirmed to within ± 10% with three
different experimental techniques: (1) Direct measurement with a C-V plotter, (2) by
measuring the voltage created while integrating photocurrent-generated charge on the
photodiode capacitance using a electrical voltage sampler [10], and, (3) by measuring the
frequency of an inverter-based ring oscillator loaded by the diode capacitance, following
[11]. Despite this somewhat-high device capacitance, the modulators were able to operate
at respectably high speeds when integrated to CMOS drivers. Figure 3.13 shows the
modulator output eye diagram at 800 Mb/s for a device flip-chip bonded to a CMOS chip
with inverter-based drivers that were designed in a 0.5 µm technology. When used as
photodiodes, the devices also allowed CMOS receivers to function at high speeds with
assorted receiver designs (e.g., transimpedance amplifier receivers and various types of
sense amplifier integrating receivers), in one case, as high as 1.6 Gb/s [12].
51
Figure 3.13. Modulator output eye diagram measured at 800 Mb/s, using a 0.5 µm CMOS
driver and pseudo-random data. The driver was undersized for the capacitance of the
modulator (~260 fF), leading to highly-sloped transitions between bits.
The modulators described to this point are similar to those developed at Lucent
Technologies [8], but include improvements on that basic design. For example, a much
smaller active region was used to reduce the device capacitance by over an order of
magnitude, yet uses a simple fabrication technique (i.e., the self-aligned etching process
shown in Figure 3.7 (e)). With a calculated capacitance of only ~10 fF, these devices will
allow much higher I/O rates to be achieved with lower optical power, and should enable
the investigation of new interconnect concepts, such as receiverless optical clock
injection.
Because supply voltages will continue to be reduced with future CMOS scaling,
another important improvement to the basic MQW modulator is the enhancement of
optical performance, particularly contrast ratio (which degrades at low operating
voltages). Two modulators that address this issue will be described in the next chapter.
Both intentionally use a Fabry-Perot cavity with the resonance wavelength overlapping
the excitonic absorption peak to increase performance. The first design employs the
structure described in this chapter, plus a cavity resonance tuning technique developed to
overcome growth errors. The second device design targets much lower operating
voltages, and achieves both a high finesse and a wide spectral bandwidth by using a first52
order cavity. The simpler devices that were described in this chapter, however, do have
sufficient performance to allow systems-level interconnect testing, and all of the
experiments that will be described in Chapter 5 employ the standard integrated MQW
modulators described here.
53
REFERENCES
1. See, for example, C. Kittel, Introduction to Solid State Physics, sixth ed., John Wiley
and Sons, Inc., New York (1986).
2. J. D. Dow, and D. Redfield, Phys. Rev. B, 1, 3358 (1970).
3. D. A. B. Miller, D. S. Chemla, T. C. Damen, A. C. Gossard, W. Wiegmann, T. H.
Wood, and C. A. Burrus, Phys. Rev. Lett., 53, 2173 (1984).
4. See, for example, A. Cho (ed.), Molecular Beam Epitaxy, American Institute of
Physics, Woodbury (1994).
5. R. E. Williams, Modern GaAs Processing Methods, Artech House, Boston (1990).
6. E. D. Palik, Handbook of Optical Constants of Solids, Academic Press, Orlando, vol.
1, pp. 438-439 (1985).
7. D. D. Sell, H. C. Casey Jr., and K. W. Wecht, J. Appl. Phys., 45, 6 (1974).
8. K. W. Goossen, J. A. Walker, L. A. D’Asaro, S. P. Hui, B. Tseng, R. Leibenguth, D.
Kossivies, D. D. Bacon, D. Dahringer, L. M. F. Chirovsky, A. L. Lentine, and D. A.
B. Miller, IEEE Photon. Technol. Lett., 7, 360 (1995).
9. M. J. Weber (ed.), CRC Handbook of Laser Science and Technology, CRC Press,
Inc., Boca Raton, vol. 4, pp. 185-219 (1995).
10. A. Emami, personal communication.
11. A. V. Krishnamoorthy, T. K. Woodward, R. A. Novotny, K. W. Goossen, J. A.
Walker, A. L. Lentine, L. A. D’Asaro, S. P. Hui, B. Tseng, R. Leibenguth, D.
Kossives, D. Dahringer, L. M. F. Chirovsky, G. F. Aplin, R. G. Rozier, F. E.
Kiamilev, and D. A. B. Miller, Electron. Lett., 31, 1917 (1998).
12. A. Emami, D. Liu, G. A. Keeler, N. C. Helman, and M. Horowitz, 2002 VLSI
Symposia on Technology and Circuits, Honolulu, Hawaii (June 11-15, 2002).
54
CHAPTER 4: LOW-VOLTAGE RESONANT-CAVITY MODULATORS
The surface-normal modulators currently used in optical interconnect demonstrations
(i.e., devices driven by CMOS chips with a supply voltage greater than or equal to about
2.5 Volts) will have exceedingly poor performance at future operating voltages. This
problem arises because the band-edge shift of the quantum-confined Stark effect, which
is used by most surface-normal electroabsorption modulators, has a quadratic dependence
on electric field. Using a thinner intrinsic region would keep the electric field high at
lower voltages, but using fewer quantum wells would provide less optical absorption;
thus, a thinner intrinsic region would cause modulator performance to suffer, and both
decrease the system noise margin and increase the required laser power. Alternative
designs that achieve greater modulation depth and contrast ratio at low voltages have
been proposed. Among the more promising approaches are the so-called n-i-p-i
modulators, and asymmetric Fabry-Perot modulators (AFPM).
N-i-p-i modulators are a conceptually simple extension of the p-i-n modulator with
several intrinsic regions grown in an interleaved p-i-n-i-p-i-n… diode structure. Actual
devices have been challenging to fabricate, because properly reverse-biasing all of the
electrically-parallel diodes is difficult unless all contacts are of very high quality.
Moderate success has been demonstrated through the use of shadow mask growth
techniques [1] and through the use of selective side mesa contacts [2]. Despite these
achievements, however, most fabrication attempts have yielded devices with rather high
leakage currents. In addition, the capacitance of n-i-p-i modulators increases quickly as
more layers are added to the stack.
Asymmetric Fabry-Perot modulators, on the other hand, are fabricated using the same
design principles as the standard MQW p-i-n modulator, and can achieve the same low
leakage currents and low capacitance. Rather than adding more quantum wells to increase
the optical absorption, an AFPM employs a resonant cavity to increase the effective
quantum well-photon interaction length. This chapter discusses investigations into
resonant cavity quantum well modulators for use in future silicon CMOS optical
55
interconnects. Two device designs are described, both of which build on the work
described in Chapter 3. They achieve improved performance at low operating voltages,
are straightforward to grow and fabricate, yet can be easily integrated with silicon
electronics.
4.1 RESONANT CAVITY MODULATORS
4.1.1 THE THEORY OF FABRY-PEROT RESONATORS
Optical resonators can be analyzed from several different mathematical perspectives.
For an AFPM that uses planar mirrors large enough with respect to the optical beam to
ignore diffractive effects, a wave optics approach can provide an essentially complete and
sufficient description. A full analysis of resonator optics can be found in several
fundamental optics texts [3][4], but what follows are the basic details required for a
reasonable investigation into resonant cavity modulators.
A lossless optical resonator with mirrors separated by a distance L will support
standing waves with wavelengths:
λm =
2L
m
(4.1)
where m is the order of the cavity mode, and ? m represents the wavelength in the cavity
medium. The spacing between modes, known as the free spectral range, (? ?)fsr, is given
by:
(∆λ ) fsr =
λ λ2
=
m 2L
(4.2)
Note that for a lossless cavity (i.e., with no absorption by the cavity medium and large
enough mirrors of unity reflectivity), the linewidth of each mode is zero. When optical
losses occur, however, this linewidth becomes finite. The cavity finesse, F , is a function
of the electric field round-trip attenuation factor, R :
56
F =
π R
1 −R
(4.3)
which, for F >>1, can be used to relate the free spectral range to the linewidth:
F =
(∆λ ) fsr
(∆λ ) fwhm
(4.4)
where (? ?)fwhm is the resonance linewidth, or full-width at half-maximum of the resonant
wavelength peak. The finesse depends on losses that occur in the cavity, and decreases as
losses increase. The value of R (as used in the definition of finesse) is:
R = r1r2 exp(−α L)
(4.5)
where r1 and r2 are the reflection coefficients of the top and bottom mirrors, a is the
(intensity) absorption coefficient of the cavity medium, and L is the thickness of the
cavity.
Wavelengths near a resonance (i.e., within the resonance linewidth) effectively spend
more time within the cavity medium than in a simple double-pass design. Thus, a FabryPerot cavity can be used to enhance the performance of an electroabsorption modulator at
resonant wavelengths by effectively “multiplying” the absorption of the device due to the
increased photon interaction length. It should be remembered, however, that although
resonant cavities have the ability to improve optical performance in terms of change in
reflectivity and contrast ratio, the enhancement is typically at the expense of another
important parameter, optical bandwidth.
4.1.2 RESONANT-CAVITY MODULATOR ANALYSIS
The concept of using a resonant cavity to enhance modulator performance is quite
straightforward, and a substantial amount of previous work can be found in the literature
[5]. The first reflective asymmetric Fabry-Perot MQW modulator was described in [6],
and was, like essentially all devices that have been described since, a simple p-i-n
modulator with DBR mirrors placed around it. Figure 4.1 illustrates the basic device,
57
which is closely related to the standard MQW modulator shown in Figure 3.2. The
reflectivity of an AFPM can be shown to obey the following relationship when operated
on-resonance:
 R f − Rb ,eff
RT = 
 1 − R f Rb ,eff





2
(4.6)
where RT is the total reflectivity, Rf is the front mirror reflectivity, and
Rb ,eff = Rb exp(-2α L)
(4.7)
is the effective back mirror reflectivity. Typically, the actual back mirror reflectivity, Rb,
is as high as possible to decrease insertion losses. The remaining portion of Rb,eff
represents the absorption occurring within the modulator. Figure 4.2 shows RT as a
function of Rb,eff to illustrate the behavior of an AFPM. When Rf and Rb,eff are made equal,
RT goes to zero. Hence, the OFF-state of an AFPM can have a very low reflectivity, and
the device can achieve a high contrast ratio.
Figure 4.1. Conceptual illustration of an asymmetric Fabry-Perot quantum well
modulator.
58
Figure 4.2. Reflectivity of an AFPM as a function of Rb,eff for three different front mirror
reflectivities. Increasing the absorption in the device shifts the operating point from A to
B (for a modulator with Rf=0.3), yielding a high change in reflectivity and contrast ratio.
As seen in the plot, the operating point on each curve is modified by changing the
absorption, a, of the modulator (i.e., varying Rb,eff). With only a small change in
absorption, an extremely high contrast ratio can be obtained by using a reflectivity
minimum as one operating point. A large ? R can be achieved by operating where the
slope of the curve is large. Contrast ratios in excess of 100:1 and changes in reflectivity
exceeding 68% have been demonstrated [7][8], although these extreme performance
characteristics have typically used either high drive voltages or high-finesse cavities.
Thus, even though the value of ? a obtained with low-voltage operation may be small,
a high-finesse cavity (i.e., one with a large Rf) can be used to provide strong resonant
enhancement. However, while this improves the resulting modulator characteristics at the
resonant wavelength, it also reduces the spectral bandwidth of the modulator because of
the sharper resonance. A narrow bandwidth leads to design problems for practical
interconnect systems: The wavelength of the laser source must be precisely matched to
the operating wavelength of the modulator, and modulator temperature must be
59
controlled because of the variation in bandgap energy with temperature (e.g., about
0.28 nm/°C for GaAs at room temperature [9]). A narrow spectral bandwidth also
precludes use of the modulator in simple WDM systems (i.e., the system will instead
require different devices for each wavelength channel), and it makes wafer growth more
challenging, as will be described below. Thus, the cavity finesse of an AFPM is, like
most properties of an MQW modulator, one of many variables that should be optimized
for a given system implementation.
4.2 STANDARD MQW MODULATORS AND RESONANT-CAVITY
ENHANCEMENT
With few exceptions [10], the modulator-based optical interconnects demonstrated in
the past have employed standard double-pass devices despite the benefits of resonant
cavity enhancement. This is likely because the narrow spectral bandwidth of the AFPM
devices restricts system design, but also due to the more complicated growth that an
AFPM requires. To obtain a working device, the cavity resonance must overlap the
exciton absorption peak. Such an overlap requires a precise cavity thickness; however,
modeling shows that a small growth error (i.e., <1% deviation from the desired thickness)
will cause a shift in the cavity resonance position larger than the width of the exciton
peak itself. Equally problematic is the thickness variation across a wafer. Since both of
these errors are around a few percent in typical epitaxial growth, AFPM fabrication can
be challenging. In order to fabricate functional Fabry-Perot modulators despite these
problems, a new fabrication approach was developed to compensate for errors in cavity
thickness.
4.2.1 AFPM DEVICE FABRICAT ION
For the devices described in Chapter 3, a resonant cavity was inadvertently formed
between the reflective metal contact (the bottom mirror) and the semiconductor/air
interface above it (which acts as the top mirror). The reasonably low cavity finesse does
not restrict the spectral bandwidth of the modulator, but it can provide performance
60
enhancement if the cavity resonance is placed at the proper wavelength. Figure 4.3
illustrates the basic design of this AFPM. As will be discussed, one benefit of the cavity
structure shown here is that its thickness is not fixed during growth as for designs with
two epitaxial mirrors. An additional advantage of the design over the conventional AFPM
is that it circumvents the problem of growing doped Bragg mirrors with low series
resistance.
Figure 4.3. Illustration of the asymmetric Fabry-Perot modulator fabricated in this work.
To align the cavity resonance and exciton absorption peak without using iterative and
careful growth, a combination of GaAs surface oxidation and selective wet chemical
etching was used to thin the Fabry-Perot cavity following flip-chip integration. With this
technique, the cavity can also be tuned chip-by-chip as needed. Thus, this postintegration cavity resonance compensation allows use of the entire wafer despite
thickness variations from wafer center to edge. Previously, other groups demonstrated
post-growth tuning techniques that included: an extra layer deposition step to compensate
wafer thickness errors [11], controlled timed etching of the wafer [12], and timed etching
of DBR-based devices after fabrication but without bonding [13]. However, this is the
first approach to allow cavity tuning of the modulators following integration. It enables
iterative testing and tuning of the actual bonded devices rather than the unfinished wafer,
and can be done separately for each chip.
61
The epitaxial structure described in Chapter 3 was used, with the cavity designed to
be slightly thicker than desired by adding a thin sacrificial GaAs buffer above the etch
stop. The diodes were fabricated and integrated as described previously. A highlyselective wet etch (4:1 citric acid:hydrogen peroxide) was used to remove the opaque
GaAs substrate. This etch stops on the high-aluminum-content etch stop layer with a
selectivity of greater than 1000:1 [14]. Concentrated hydrochloric acid and water, which
etches AlGaAs over GaAs with an even greater selectivity (i.e., around 107:1 for
AlAs:GaAs [15]) was used to remove the etch stop layer.
4.2.2 TUNING THE CAVITY RESONANCE
The cavity tuning procedure was performed following etch stop removal. Rather than
using a timed etch to thin the cavity, a series of “tuning cycles” was employed, allowing
more precise control of the cavity resonance. A single tuning cycle consists of 30-second
dips into hydrogen peroxide and then hydrochloric acid and water (1:1 ratio). The process
works by oxidizing a thin layer of GaAs and subsequently stripping it off with HCl. The
procedure has an additional benefit: It was shown to reduce the rms surface roughness to
only about 2 Å over areas significantly larger than the modulator arrays [16].
Optical and electrical probing was performed to test the devices. After substrate
removal, with the protective epoxy still in place (and no modulator bias applied),
reflectivity curves were measured using a tunable Ti:sapphire laser. Cavity tuning was
then used to bring the Fabry-Perot resonance to the proper wavelength. Figure 4.4
illustrates the effects of cavity tuning. The graph shows device reflectivity before tuning
and after 2 and 10 tuning cycles. Each set of curves represents data taken from several
modulators distributed across the array. Modeling shows that the translation of the
resonance peak (about 0.75 nm/tuning cycle) is consistent with an etch depth/cycle of
~20 Å. This corresponds to an error compensation of approximately 0.1%/tuning cycle.
Also evident in Figure 4.4 is the uniformity across the array, as seen by the close
grouping of all curves within a data set.
62
1
0.8
Reflectivity
after 10
tuning cycles
0.6
0.4
after 2
tuning cycles
0.2
before tuning
0
830
840
850
860
870
880
890
Wavelength (nm)
Figure 4.4. Device reflectivity before cavity tuning, after 2 tuning cycles, and after 10
tuning cycles.
Following tuning, the epoxy was removed with a CF4/O2 plasma to expose the
electrical probe pads. The device reflectivity versus wavelength was then measured for
different applied voltages. Curves derived from this data are shown in Figure 4.5 for a
representative device. The measurements illustrate that using an offset bias of 3 Volts and
a swing of only 2.5 Volts, the devices can achieve an absolute change in reflectivity of
about 20% over 10 nm and a contrast ratio of about 6:1 over 5 nm. Higher voltages give
even better performance, with contrast ratios greater than 10:1 and ? R around 30% for
operation between 0 and 5 Volts. A summary of the device performance is shown in
Table 4.1, which includes the characteristics of a standard double-pass p-i-n modulator
for comparison.
63
0.4
8
7
CR for 2 - 5.5 V
6
CR for 3 - 5.5 V
∆ R for 2 - 5.5 V
0.3
∆ R for 3 - 5.5 V
0.2
5
4
0.1
3
0
2
-0.1
1
-0.2
0
830
840
850
860
Wavelength (nm)
870
880
830
840
850
860
Wavelength (nm)
870
880
Figure 4.5. Measured wavelength dependence of (a) contrast ratio, and, (b) change in
reflectivity for an integrated asymmetric Fabry-Perot modulator after cavity tuning.
Table 4.1. Fabry-Perot modulator performance at various operating voltages, compared to
a standard double-pass, non-resonant cavity device (shown in red).
Operating voltage:
2.5 Volts
2.5 Volts
(non-AFPM)
3.5 Volts
5 Volts
Contrast ratio
(over 5 nm)
6:1
1.3:1
7:1
8:1
Reflectivity change
(over 10 nm)
20 %
10 %
25 %
30 %
DC bias
3 Volts
3 Volts
2 Volts
1 Volt
To verify that optimal performance was achieved by cavity tuning, the modulator
reflectivity was simulated numerically using an optical transfer matrix approach.
(Appendix B describes the details of the simulations and discusses how the physical
parameters were derived.) The validity of the model is supported by close agreement with
experimental data, which is shown in Figure 4.6. Additional simulation results suggest
that cavity tuning to within a few etch cycles (i.e., within about ±0.3% of the proper
cavity thickness) is sufficient for good performance. Thus, the technique is reasonably
simple to perform. Modeling also predicts a lower reflectivity minimum than was
observed for many devices in each array. It is suspected that metallic diffusion between
64
the gold and indium layers reduces the bottom mirror reflectivity; the modeled
performance matches the measured reflectivity best when the interface quality is reduced
in the modeling. Additional barrier metals (i.e., copper and nickel) have since been added
to the reflective metal contact to avoid this effect.
1
Reflectivity
0.8
0.6
0 Volts
2 Volts
3 Volts
5.5 Volts
0.4
0.2
0
830
840
850
860
870
880
890
Wavelength (nm)
Figure 4.6. Simulated (circles) and measured (solid lines) reflectivity versus wavelength
for an integrated asymmetric Fabry-Perot modulator following cavity tuning.
The AFPM devices described in this section show better performance than the
standard double-pass modulators used in most previous systems and those described in
Chapter 3. The tunable resonant cavity makes the devices simpler to grow, thereby
increasing wafer yield. However, the design does have some unfortunate flaws. The
bottom gold mirror has reflectivity lower than that of a DBR mirror, resulting in a higher
insertion loss than found in devices with epitaxial mirrors. Additionally, the fixed cavity
finesse (set by the ~30% reflectivity of the semiconductor/air interface) limits the
performance of the device at lower voltages. While the tunable AFPM is useful in current
systems, an improved design would be desirable for use with the much lower CMOS
supply voltages that will be used in the near future (e.g., only 0.6 Volts by 2011 [17]).
65
4.3 FIRST-ORDER RESONANT-CAVITY MODULATORS
Ideally, a newly-designed modulator would exhibit good optical performance at low
voltages while maintaining the advantages of the standard MQW modulator (i.e., simple
to grow, fabricate and integrate, high-yield, surface-normal, low power dissipation, and
capable of high speed operation). Of several interesting modulator concepts that were
considered, a single design was investigated because of its anticipated performance and
complementary nature to previous designs. The remainder of this chapter will discuss the
details of the new modulator, which has a high finesse but a broad spectral bandwidth.
This combination is possible because of the extremely short cavity length (e.g., less than
one-half wavelength). We believe it should be possible to fabricate and integrate this
device using the techniques developed earlier, and because it operates with a true firstorder cavity, the modulator is an improvement on existing designs for reasons that will be
discussed.
4.3.1 PROBLEMS WITH A DBR-BA S ED DESIGN
Almost all AFPM modulators have employed epitaxially-grown DBR mirrors on both
sides of the cavity. DBR mirrors have higher reflectivity than metal ones, enabling the
fabrication of modulators with low insertion losses (i.e., losses that result from the
residual absorption of lossy mirrors). As mentioned previously, resonant cavity devices
have a significant drawback at low voltages. Because the absorbing cavity becomes quite
thin (i.e., to sufficiently shift the absorption edge with low bias), the finesse must be
increased to maintain enough overall absorption. A high cavity finesse leads to a narrow
optical bandwidth, making the device less appealing from the perspective of system
design.
As CMOS supply voltages decrease below 1 Volt, the absorbing MQW layer of an
AFPM would need to become extremely thin. Here, the cavity finesse/bandwidth tradeoff is complicated by the phenomenon of DBR mirror penetration. Because a DBR relies
upon the combined reflections that occur at each interface of the multilayer stack, an
optical field effectively passes some distance into the stack before it is fully reflected.
66
This penetration length, Lpen, which accounts for the phase change of the optical field
upon reflection from a DBR mirror, can be calculated using [18]:
 mλ mλ  1
L pen = 
+
tanh ( 2mr )

 4n1 4n2  4mr
(4.8)
where the layer interface reflectivity, r, is given by
r=
n2 − n1
,
n2 + n1
(4.9)
m represents the number of mirror periods, and n1 and n2 are the refractive indices of the
alternating layers. Figure 4.7 illustrates the phenomenon.
Figure 4.7. Mirror penetration length for a distributed Bragg reflector.
The influence of DBR penetration on the bandwidth of an optical resonator can be
seen as follows. Using equations 4.2 and 4.4, the full-width at half-maximum of the
resonance can be written as:
(∆λ ) fwhm =
λ2
λ
=
2 LF F m
(4.10)
67
Thus, for a given wavelength and cavity finesse, the resonant linewidth is inversely
proportional to cavity length. Using a shorter, or lower-order cavity, maximizes the
useful spectral bandwidth of an asymmetric Fabry-Perot quantum well modulator. Even
the shortest cavity, however, is considerably longer when penetration depth is taken into
account.
For a DBR stack of Al0.3Ga0.7As/AlAs with R=0.95, the effective DBR penetration
length at ?=850 nm is Lpen ˜ 4(?/2). Thus, for a high-finesse DBR-based AFPM with a
first-order absorbing region, the actual cavity length is roughly nine half-wavelengths.
The resulting resonance linewidth is 9x narrower than with zero mirror penetration. This
effect was noted as a drawback in short-cavity AFPM designs by previous authors [8],
and is illustrated in Figure 4.8.
Figure 4.8. The effect of DBR mirror penetration in a “first-order” asymmetric FabryPerot modulator with AlGaAs/AlAs mirrors. Mirror penetration increases the effective
cavity length by a factor of nine, significantly reducing the resonant linewidth.
4.3.2 PROPOSED DEVICE: FOAM
Unlike DBR mirrors, metallic mirrors have little appreciable penetration depth. Thus,
in order to achieve a large spectral bandwidth using low operating voltages, the decision
was made to fabricate a true first-order modulator using metal mirrors. Although the
device would have higher insertion losses than typical DBR-based designs, the broader
spectral bandwidth was deemed to have greater system importance.
68
To maximize the single-pass absorption in such a short cavity, a novel electrical
biasing scheme is proposed: Because the p- and n-regions of a typical p-i-n diode
structure provide no useful absorption, the layers were completely omitted from the
design. Instead, the upper and lower metal mirrors are used to directly apply the electrical
bias across the absorbing MQW intrinsic region. Thus, the electrical structure is metalintrinsic-metal, or m-i-m (as opposed to the conventional p-i-n). The modulator became
known as the FOAM modulator, an acronym for “First-Order Asymmetric Fabry-Perot
m-i-m” modulator. Figure 4.9 shows a schematic diagram of the FOAM modulator
concept.
Figure 4.9. Schematic diagram of the FOAM modulator. The first-order cavity is not
significantly affected by mirror penetration, keeping the resonant linewidth large. Only a
few quantum wells fit in the intrinsic region between the metal mirrors/contacts.
The FOAM modulator has, as its major advantage, a much larger resonant linewidth
than a conventional DBR-based AFPM. Compared to the example shown above, a
FOAM modulator with the same finesse would have almost a ten-fold improvement.
There are two significant disadvantages to the design, however. The first is the lower
reflectivity of metal mirrors. Gold was chosen as the mirror material due to its high
reflectivity in the infrared, good conductivity, and physical stability. Unfortunately, even
gold mirrors contribute some unwanted absorption during multiple reflections in the
69
cavity (particularly when the optical wave is incident from the semiconductor side), and
the added insertion loss may be significant. Secondly, the device poses some interesting
fabrication challenges. Such a thin structure (e.g., the semiconductor thickness might be
only 60-70 nm in total) could easily crack or break during fabrication and flip-chip
bonding, and slight over-etching during substrate removal would destroy the device. The
epitaxial growth of the device is considerably easier than for a DBR-based p-i-n structure,
but fabrication complexity is somewhat increased because the top mirror must be
deposited following integration. It is interesting to note that while no previous FabryPerot modulators have employed partially-transparent Schottky contacts as their upper
mirror, the combination of gold mirror/contact has been used successfully in high-speed
resonant cavity GaAs photodiodes [19] and resonant cavity light-emitting diodes
[20][21].
4.3.3 ELECTRICAL MODELING O F FOAM
Before fabricating the FOAM modulator, extensive modeling and calculations were
performed to ensure there was a significant probability of success. The electrical
characteristics of the device were considered first. The structure is somewhat analogous
to the well-known planar metal-semiconductor-metal, or MSM, devices commonly used
as photodetectors. In an MSM detector, two sets of interdigitated metal fingers are
deposited on an undoped or lightly-doped semiconductor. An applied electric field acts to
sweep the photogenerated carriers out of the depleted semiconductor. The metalsemiconductor interfaces are rectifying Schottky contacts, so little dark current flows
between the electrodes when they are biased.
The gold contacts of the FOAM modulator give it similar electrical characteristics to
an MSM device, although the stacked planar structure results in a higher capacitance. The
metal-semiconductor band lineup, which can ideally be calculated from the work function
of the two materials, is actually a result of surface charges and interface states in real
Schottky diodes [22]. These effects tend to pin the metal energy band to a certain fraction
of the bandgap, and (although it depends on surface defects and the deposition technique)
this value has been shown to be roughly Eg/3 (for Au/n-GaAs) to 2Eg/3 (for Au/p-GaAs)
70
[23]. Because of the low carrier concentration in the intrinsic region, the semiconductor
energy band is relatively flat. The symmetry of the device means there is no preferred
bias direction. Finally, because the device lacks the built-in potential found in a standard
p-i-n modulator, the photogenerated carriers that are created when no field is applied are
not automatically swept away. This can lead to easier absorption saturation, which will be
discussed in more detail at the end of the chapter. Figure 4.10 illustrates the electrical
band diagram of a FOAM modulator.
Figure 4.10. Electrical band diagram of the FOAM modulator with five quantum wells in
the intrinsic region. The device is shown with (a) no electrical bias, and, (b) with a bias
applied.
The two most commonly-analyzed components of DC current that apply to this
device (e.g., thermionic emission from a metal contact into the semiconductor and carrier
tunneling through the semiconductor) should be extremely small. The thickness of the
intrinsic region is large enough to ignore most effects of carrier tunneling, and the height
of the Schottky barrier is sufficient to prevent any significant DC current at room
temperature. However, published work on MSM detectors has shown that surface traps
can increase the amount of tunneling current that occurs [24], and that surface charges
can increase thermionic emission due to Schottky barrier lowering [25]. Thus, the actual
dark current will result from surface effects that are difficult to model in advance.
Ignoring saturation and carrier transit rates within the device, the maximum
modulation rate of the device depends on its capacitance, its resistance, and on the
71
impedance of the driving circuit. The resistive elements of the device include the flipchip bonding pads and the thin gold top mirror. The sheet resistance of a 200 Å gold film
– roughly the thickness of the top mirror – is only ~5 O/square [26], while the resistance
of the flip-chip pads has been measured to be only a few Ohms. This yields an anticipated
contact resistance of roughly 5-10 O. It can easily be shown that the device capacitance
(assuming an area of 400 µm 2 and a thickness of 650 Å) would be roughly 650 fF. (Note
that reducing the areal dimensions as in Chapter 3 can dramatically decrease this value.)
Assuming a desired modulation rate of 10 Gb/s, a voltage driver with an output
impedance of about 150 O would be required, which can be easily designed in CMOS.
Thus, electrically, the FOAM modulator seems to present no significant problems
preventing its use in an optically-interconnected system.
4.3.4 OPTICAL MODELING OF FOAM
Extensive optical modeling of the FOAM modulator was performed using the optical
scattering matrix approach. As discussed in Appendix B, the absorption coefficients and
refractive indices of gold were taken from the literature, while values for the absorbing
MQW region were measured and calculated using the Kramers-Kronig relations.
Simulations show that the optical performance is very dependent on the thickness of both
the gold top mirror and the absorbing regions. By altering the layers somewhat, the cavity
finesse can be adjusted to achieve the optimal performance and the Fabry-Perot
resonance can be placed at the proper wavelength.
Interestingly, the optical phase change arising from metal mirror reflections has a
reasonably significant impact on modulator design. This phase change, F , which is
analogous to the penetration depth of a DBR (though not nearly so large), depends on the
metal thickness, optical wavelength, and the angle of incidence. The added phase acts to
increase the cavity thickness by a factor F ?/2p, so the spacer thickness of a “first-order
cavity” is actually somewhat less than ?/2. Optimization through modeling indicates that
an appropriate cavity thickness is around 650 Å. Because the cavity is thinner than
originally expected, the FOAM modulator should operate with extremely low voltages;
however, because the cavity incorporates less absorption, the device needs a rather high
72
finesse to compensate (i.e., the finesse of a typical design is about 17). Simulations were
performed to determine the proper cavity finesse; Figures 4.11 and 4.12 show the contrast
ratio and change in reflectivity as a function of wavelength and top mirror thickness for a
device with a 650-Å MQW region.
Figure 4.11. Simulated contrast ratio for a FOAM modulator with a MQW cavity
thickness of 650 Å. Operation is between 0 and 0.6 Volts.
73
Figure 4.12. Simulated change in reflectivity for a FOAM modulator with a MQW cavity
thickness of 650 Å. Operation is between 0 and 0.6 Volts.
From these calculations, it is apparent that a promising modulator design incorporates
a highly reflective bottom gold mirror (modeled as >3000 Å), a MQW cavity region of
650 Å, and a top gold mirror of about 180 Å. Since the cavity is very thin, only five
quantum wells will fit in the intrinsic layer1. Figure 4.13 illustrates the simulated
performance of the structure when operated between 0 and 0.6 Volts (i.e., the expected
CMOS supply by 2011 [17]). The resonance linewidth is very wide, at roughly 40 nm. A
maximum change in reflectivity of 10% is obtained, with ? R=5% over 10 nm. By
achieving low reflectivity in the absorbing state, the device also has a good contrast ratio,
with CR=2.5:1 over the same 10 nm.
1
The region was still modeled as a quasi-bulk layer, with the indices of refraction
determined in Appendix B. A better model would use per-well optical absorption.
74
Figure 4.13. Simulated optical reflectivity for a FOAM modulator with a 180-Å thick top
mirror and a MQW region thickness of 650 Å. Blue curve is for 0-V bias and red curve is
for 0.6-V bias.
Because the added optical phase from the mirror reflections depends on the top mirror
thickness, changing the cavity finesse also alters the resonance wavelength. To make the
design flexible, a 100-Å GaAs buffer was placed at the bottom of the structure to allow
tuning of the cavity (using the process described earlier). While this buffer layer can help
compensate for growth errors, it is most useful for adjusting the resonant wavelength
position for devices in which the cavity finesse is altered.
Additional simulation results show that angular dependence is small, even with
reasonably large changes in incident angle. Thus, a tightly-focused Gaussian beam can be
used without an appreciable loss in performance. A DBR-based AFPM with such high
finesse, on the other hand, would have a much greater angular variation because of its
narrow Fabry-Perot resonance.
75
4.4 FOAM FABRICATION, TESTING, AND INTEGRATION RESULTS
4.4.1 FABRICATION AND INTEGR A TION PROCESS STEPS
The epitaxial structure of the FOAM modulator is very simple and straightforward to
grow; the wafer layers are shown in Table 4.2. Unlike other AFPM devices, its
fabrication requires integration and substrate removal. Thus, it relaxes growth
constraints, but has a somewhat process-intensive design. The techniques used to
fabricate FOAM modulators are similar to those described in Chapter 3 (and Appendix
A) for fabricating standard MQW modulators. Figure 4.14 illustrates the basic process
flow. Devices and coplanar contacts were designed with the same pitch as in previous
work so that the FOAM devices could be integrated to existing test structures. Figure
4.15 shows SEM views of the modulators before flip-chip bonding and after fabrication is
complete.
Table 4.2. Design of the FOAM modulator epitaxial structure.
Description
Material
Thickness (Å)
cap layer
GaAs
20
top barrier layer
Al0.3Ga0.7As
40
GaAs
Al0.3Ga0.7As
95
30
extra bottom barrier
Al0.3Ga0.7As
10
buffer layer
GaAs
100
etch stop layer
Al0.85Ga0.15As
2,000
i (MQW) layer
5x
76
(c)
(b)
(a)
(d)
(e)
(f)
Figure 4.14. FOAM modulator process flow. Beginning with a section of the 3-inch
GaAs wafer (a), a timed etch is used to etch mesas through the MQW region and partially
into the etch stop layer (b). Next, two ~0.5 µm-thick gold contacts are deposited on each
device (c), with one contact placed such that it overlaps the edge of a mesa – after
substrate and etch stop removal, this contact will be exposed to contact the top mirror.
The devices are flip-chip bonded to test structures for testing (d). Rather than the indium
bonding method developed earlier, a direct gold-gold bond is used. While this technique
requires higher bonding temperatures (e.g., 300 °C), it avoids the potential decrease in
mirror reflectivity resulting from gold/indium intermixing. The substrate and etch stop
layers are removed using the selective wet etching process described previously and the
cavity tuning process is used to achieve the desired modulator thickness (e). Finally, a
partially-transmitting top mirror/contact of gold is deposited on each device (f). Note that,
although both gold contacts are touching the same side of the device, this does not “short
out” the device because the contacts are Schottky diodes, and the semiconductor material
is substantially not conducting anyway.
77
Figure 4.15. Scanning electron micrographs of FOAM modulators, (a) before integration,
and, (b) after fabrication is complete.
4.4.2 OPTICAL AND ELECTRICAL TEST RESULTS
In order to investigate the impact of layer thickness on optical reflectivity, several
arrays of devices with different cavity thicknesses were fabricated. As seen in Figure
4.16, the Fabry-Perot resonance shifts to shorter wavelengths for thinner optical MQW
regions. While the overall profile of the measured device reflectivity approximately
agrees with simulations, the resonance minima were not as low as expected. This effect,
which reduces the maximum attainable contrast ratio, could have several sources: The
optical absorption data (which was taken from a wafer with more quantum wells to
simplify the measurement) could be lower than anticipated and provide less internal
device absorption. Also likely is that the metal mirror losses were greater than predicted
by modeling. Thin gold films have been shown to exhibit a variable degree of optical
scattering due to surface roughness [27]. Additionally, the interface between gold and
GaAs typically displays some non-ideal optical characteristics when oxides are present,
due to the diffusion of gold into the semiconductor surface [28].
78
0.8
Reflectivity
0.6
0.4
0.2
0
800
820
840
860
880
900
Wavelength (nm)
Figure 4.16. Reflectivity vs. wavelength for four devices from a poorly-etched FOAM
array that displayed a variation in cavity thickness across the sample. Top mirror
thickness was 240 Å. Measurements were performed with no applied bias.
Despite several fabrication attempts, electrically-induced modulation of the optical
beam was not observed for any device, and no photocurrent could be measured by
probing. The devices did absorb light as expected, as evidenced by the excitonic
absorption features visible in the reflected spectrum. Therefore, it is believed that poor
electrical contacts limit the device performance. Since the gold-gold bonding process is
not well-characterized, it is possible that most of the coplanar flip-chip pads did not make
electrical contact with the underlying electrical test structure. Additionally, there may
have been exceedingly high resistance between the deposited top mirror and its coplanar
contact pad due to a poor-quality interface.
4.4.3 DISCUSSION AND FUTURE IMPROVEMENTS
While the FOAM modulator was shown to have some promising characteristics (i.e.,
wide spectral bandwidth and high contrast ratio), this preliminary study shows that
several challenges must be addressed before it can be practical. Most of the problems that
were encountered stem from fabrication difficulties, and could potentially be solved with
79
more effort. For example, improving the electrical contacting process would lead to
improved modulation. Added optical losses due to surface roughness and GaAs/Au
intermixing could be reduced by an improved gold deposition procedure.
Even if its optical performance is improved, the FOAM modulator is a poor choice
for an integrated photodetector because of its high capacitance and low responsivity. If
the devices are used in future optical interconnects, better detectors (e.g., MSMs) will
need to be integrated to the electronics as well. To avoid a multi-step flip-chip bonding
approach, it would be relatively simple to combine the two structures on a single epitaxial
wafer, thereby lowering integration complexity and reducing materials requirements. An
undoped GaAs layer and additional etch stop could be added above the FOAM
epistructure for MSMs, but etched away in the positions where modulators were desired.
Modeling shows that other designs could also yield interesting results. For example, a
second- or third-order cavity could be employed to increase the overall change in
modulator reflectivity without decreasing the contrast ratio or spectral bandwidth
(although a thicker cavity would require a larger operating voltage). Alternatively, new
approaches to decreasing the effect of DBR mirror penetration could be employed. For
instance, the use of oxidized AlAs/AlGaAs mirrors has proven successful in some initial
studies [29][30], while the addition of a metal layer can be used reduce the number of
periods required to achieve a high reflectivity DBR. A novel concept could be the use of
angled beam propagation in a resonant cavity, with lossless reflections that use total
internal reflection from semiconductor/air interfaces.
Finally, modeling verifies that the device performance depends critically on the
change in absorption that can be obtained within the cavity. Because the cavity used here
includes only five quantum wells and has no built-in potential (as found in standard p-i-n
structures), an interesting method of achieving a large ? a could be to take advantage of
optical absorption saturation. Typically, large optical energies are required to saturate
standard MQW modulators, in part because the built-in field helps quickly remove
photogenerated carriers. However, an unbiased FOAM structure would saturate at much
lower input energies. (Measurements in this work were performed using low optical
80
powers to intentionally avoid this effect.) An applied electric field would somewhat
alleviate the saturation by sweeping out the carriers, potentially causing a large ? a for a
very small applied bias (and without employing the quantum-confined Stark effect). Such
a device, which may or may not use quantum wells, could work over a large wavelength
range. This self-loss-modulation mechanism is similar to the cross-loss-modulation that is
employed in a recently-demonstrated GaAs-based AFPM designed for ultrafast alloptical switching [31].
81
REFERENCES
1. G. H. Döhler, G. Hasnain, and J. N. Miller, Appl. Phys. Lett., 49, 704 (1986).
2. K. W. Goossen, J. E. Cunningham, W. Y. Jan, and D. A. B. Miller, IEEE Photon.
Technol. Lett., 5, 181 (1993).
3. M. Born, and E. Wolf, Principles of Optics, 6th ed., Permagon Press, New York
(1986).
4. B. E. A. Saleh, and M. C. Teich, Fundamentals of Photonics, John Wiley & Sons,
Inc., New York (1991).
5. See, for example, the review article on resonant cavity enhanced photonic devices: M.
S. Ünlü, and S. Strite, Appl. Phys. Reviews, 78, 607 (1995).
6. R. J. Simes, R. H. Yan, R. S. Geels, L. A. Coldren, J. H. English, A. C. Gossard, and
D. G. Lishan, Appl. Phys. Lett., 53, 637 (1988).
7. K.-K. Law, R. H. Yan, L. A. Coldren, and J. L. Merz, Appl. Phys. Lett., 57, 1345
(1990).
8. K.-K. Law, M. Whitehead, J. L. Merz, and L. A. Coldren, Electron. Lett., 27, 1863
(1991).
9. J. S. Blakemore, J. Appl. Phys., 53, 520 (1982).
10. J. A. Trezza, K. Kang, J. S. Powell, C. G. Garvin, and R. D. Stack, Proc. SPIE, 3292,
94 (1998).
11. K. W. Goossen, J. E. Cunningham, W. Y. Jan, and J. Centanni, Appl. Phys. Lett., 66,
1041 (1995).
12. R. Wu, Z. Chen, H. Chen, W. Gao, and J. Zhao, IEEE J. Quantum Elec., 33, 2071
(1997).
13. K. Fobelets, B. Kelly, P. Horan, and J. Hegarty, Semicond. Sci. Technol., 11, 582
(1996).
14. M. Tong, D. G. Ballegeer, A. Ketterson, E. J. Roan, K. Y. Cheng, and I. Adesida, J.
Electron. Mater., 21, 9 (1992).
15. Zh. I. Alferov, S. A. Gurevich, M. N. Mizerov, and E. L Portnoi, Sov. Phys. Tech., 20,
1617 (1976).
82
16. C. Zhang, D. Lubyshev, T. N. Jackson, D. L. Miller, and T. S. Mayer, J. Electrochem.
Soc., 146, 1597 (1999).
17. Semiconductor Industry Association, International Technology Roadmap for
Semiconductors, 2001 Edition.
18. L. A. Coldren, and S. W. Corzine, Diode Lasers and Photonic Integrated Circuits,
John Wiley & Sons, Inc., New York (1995).
19. E. Özbay, M. S. Islam, B. Onat, M. Gökkavas, O. Aytü, G. Tuttle, E. Towe, R. H.
Henderson, and M. S. Ünlü, IEEE Photon. Technol. Lett., 9, 672 (1997).
20. B. Corbett, L. Considine, S. Walsh, and W. M. Kelly, IEEE Photon. Technol. Lett., 5,
1041 (1993).
21. S. T. Wilkinson, N. M. Jokerst, and R. P. Leavitt, Appl. Opt., 34, 8298 (1995).
22. J. A. Ellis, and P. A. Barnes, Appl. Phys. Lett., 76, 124 (2000).
23. R. F. Pierret, Semiconductor Device Fundamentals, Addison-Wesley, Natick, MA
(1996).
24. M. Klingenstein, J. Kuhl, J. Rosenzweig, C. Moglestue, A. Hülsmann, Jo. Schneider,
and K. Köhler, Solid-State Electron., 37, 333 (1994).
25. J. Burm, and L. F. Eastman, IEEE Photon. Technol. Lett., 8, 113 (1996).
26. L. Lecko, and R. Hrach, Int. J. Electron., 77, 989 (1994).
27. R. R. Zito, W. S. Bickel, and W. M. Bailey, Thin Solid Films, 114, 241 (1984).
28. A. D. Rakic, A. B. Djurišic, J. M. Elazar, and M. L. Majewski, Appl. Opt., 37, 5271
(1998).
29. H.-E. Shin, Y.-G. Ju, H.-W. Song, D.-S. Song, I.-Y. Han, J.-H. Ser, H.-Y. Ryu, Y.-H.
Lee, and H.-H. Park, Appl. Phys. Lett., 72, 2205 (1998).
30. J.-H. Shin, I.-Y. Han, and Y.-H. Lee, IEEE Photon. Technol. Lett., 10, 754 (1998).
31. H. S. Loka, and P. W. E. Smith, IEEE J. Quantum Electron., 36, 100 (2000).
83
CHAPTER 5: SHORT PULSE OPTICAL INTERCONNECTS
The fabrication and integration steps developed in previous chapters enable the
addition of optical functionality to silicon CMOS chips. Using some relatively simple
circuits to interface with the optoelectronic devices, it is now possible to build complete
optical links for the purpose of experimental testing. While several different chips and
links were tested during the course of this work, this chapter will primarily describe a
series of experiments that investigate the benefits of short optical pulses for opticallyinterconnected systems.
5.1 REASONS FOR SHORT PULSE INTERCONNECTS
The design of electrical interconnects between and within silicon microelectronic
chips is becoming increasingly difficult as clock speeds continue to increase. At gigahertz
frequencies, the propagation of electrical signals on CMOS wiring and printed circuit
board (PCB) traces is severely impacted by frequency- and distance-dependent loss and
distortion. Conversely, the propagation of optical signals is virtually unaffected by their
modulation frequency and propagation distance. This advantage enables a radically new
method of signaling within computers: using ultrashort pulses, which cannot be generated
or propagated by conventional electrical means. Extremely short optical pulses can be
produced by modelocked lasers, which readily provide pulse widths of picoseconds or
less, repetition rates from megahertz to hundreds of gigahertz, and reasonably high
powers (i.e., up to a few Watts) [1].
Short pulses from a modelocked laser can provide many benefits in an opticallyinterconnected system. Precise timing is a particularly important advantage. Several
authors have investigated the concept of optical clock distribution [2][3], and some have
proposed the use of modelocked lasers for the task [4]; the low skew and jitter that this
approach offers make it a promising entry point for optics into silicon microelectronics.
Data transmission is another area where short pulses can yield advantages in an optically84
interconnected system [5][6]. To date, the vast majority of optical interconnects that have
been demonstrated or proposed have employed continuous-wave (cw) lasers, either
driven directly or externally modulated. The use of a modelocked laser in conjunction
with a modulator-based optical interconnect enables a new, low duty-cycle return-to-zero
(RZ) data format, which can be referred to as “short pulse signaling”. Short pulse
signaling can provide several benefits over the conventional non-return-to-zero (NRZ)
approach.
The details of a complete chip-to-chip optical interconnect demonstrator that employs
short pulse signaling are described in Section 5.2. Section 5.3 discusses the results of
system testing, including a measurement of receiver sensitivity enhancement, and a
demonstration of signal retiming. In addition, other link benefits, such as reduced power
dissipation, receiver latency reduction, and time-division multiplexing (TDM), are
discussed. Section 5.4 highlights other applications of ultrafast optical pulse trains for
silicon CMOS microelectronics, beginning with optical clock distribution. Because
modelocked lasers can provide a very low-jitter clock, they are also useful for precise
non-contact chip testing on short time scales; the results of a pump-probe style
measurement of circuit delay are described. Finally, a demonstration link that uses a
modelocked laser as a broadband source for chip-scale wavelength-division multiplexing
(WDM) is briefly discussed.
5.2 SHORT PULSE INTERCONNECT DEMONSTRATION LINK
In order to demonstrate the benefits of short pulses for optical interconnection, an
optical test link was created. Figure 5.1 shows a photograph of the setup. Two silicon
CMOS circuits with integrated optoelectronics are interconnected in the free-space,
multi-channel link. The interconnect is a simple chip-to-chip imaging design that uses
standard bulk optics (i.e., lenses, beamsplitters, quarter-wave plates, and Risley prisms).
The optical components are centered in cylindrical steel cells and mounted on stainless
steel slotted baseplates for stability [7]. A diffractive optical element is used to generate
85
an array of beams from a single input laser beam, which allows several channels to be
operated simultaneously with the same source. The interconnect laser can be either a
modelocked source or a cw source, allowing a comparison of system performance
between the two cases.
Figure 5.1. Photograph of the short pulse interconnect demonstration link. A single laser
(not shown in the photo) is used to operate many interconnect channels through the use of
a diffractive optical element. The beams are modulated by reflective electroabsorption
modulators on the transmitter chip and imaged on the receiver chip using polarizing
optics to minimize losses.
The chips used in the link were designed in a 0.5-µm silicon CMOS technology. Each
chip includes linear arrays of transmitter drivers and receivers, as well as several digital
test circuits. The transmitter drivers are simple inverter-based designs that change the
bias across the integrated electroabsorption modulators. Two types of receiver were used
in the link: integrating “sense-amplifier” (clocked) receivers [8], and transimpedanceamplifier (asynchronous) receivers similar to previous designs [9]. Electrical output
signals from the receivers can be sent to on-chip digital test circuits, to electrical output
pads, and to additional transmitter drivers that enable high-speed optical readout from the
receiver chip.
86
Digital functions on the chip include a number of convenient bit-error rate (BER)
testing circuits. Each transmitter channel in a linear array can be independently driven
with data from a 222-1 pseudo-random bit sequence (PRBS) generated on-chip. After it is
transmitted through the optical link, the received data can be compared to expected
values that are generated by a complementary PRBS circuit on the receiver chip. Hence,
the link BER can be measured, allowing a quantitative evaluation of system performance
as interconnect parameters are varied.
The optoelectronic modulators and photodiodes used in the demonstration system are
those described in Chapter 3. For 3.3-V operation, the modulator contrast ratio is about
2:1 and centered at 850 nm. Because of the limited contrast ratio, optically-differential
signaling (i.e., two beams per channel) is employed. The spectral bandwidth of the
modulators is wide enough (about 5 nm) that they can efficiently modulate even very
short optical pulses, which tend to have a broadened optical spectrum.
Two short-pulse optical sources were used in the experiments. The first is a
commercial modelocked Ti:sapphire femtosecond laser with a pulse width of
approximately 100 fs and a repetition rate of 80 MHz. The second is an activelymodelocked external cavity diode laser with a spectral linewidth of about 0.7 nm and a
pulse width of less than 35 ps. (The pulse width measurement was limited by detector
bandwidth, and is likely much shorter [10].) The diode laser repetition rate is variable – it
can be modelocked at harmonics of the 200 MHz fundamental frequency in order to drive
the link at high data rates, and has been operated above 3 GHz. The wavelength of each
laser was adjusted to achieve optimum performance with the integrated modulators.
During link operation, data was transmitted between the chips at the repetition rate of
the modelocked laser. The CMOS circuits were electrically clocked at the same
frequency, with the clock phase adjusted such that the short pulses were incident on the
modulators while their output was valid. Thus, each pair of modulators in a channel
encodes a data bit onto the amplitude of each optical pulse. Figure 5.2 shows an eye
diagram from a single channel of the short pulse interconnect at 80 Mb/s. In this case, the
87
transimpedance receivers were used with an average received optical power of
approximately 100 µW per beam. The electrical outputs of the receiver circuits were used
to drive additional modulators, and high-speed optical readout was performed using a
separate cw laser and optical detector. Unlike the sense-amplifier receivers, the
transimpedance outputs are neither clocked nor latched; thus, the output can be seen to
relax to the off state with a characteristic time constant of ~1 ns. (The transimpedance
receiver was designed for 1 Gb/s operation, at which speed the receiver output would
appear as a typical NRZ signal.)
Figure 5.2. Single-channel eye diagram from the receiver chip of the short pulse
interconnect at 80 Mb/s. The signal shown here is the optical output from a modulator on
the receiver chip. Hence, this data represents signal transmission through the complete
short pulse optical link, followed by optical re-transmission to a high-speed oscilloscope.
5.3 THE BENEFITS OF SHORT PULSE SIGNALING
5.3.1 RECEIVER SENSITIVITY IMPROVEMENT
The sensitivity of an optical interconnect receiver (i.e., the minimum optical energy
required to achieve a given bit-error rate) is typically worse than for a
telecommunications receiver, because very small circuit sizes and low power budgets
limit the maximum gain available. Additionally, the on-chip environment is noisy from
the digital circuit noise in the system, making very sensitive receivers problematic.
88
However, the use of short pulses can potentially decrease optical power requirements.
This improvement in receiver sensitivity will lower power dissipation, and could decrease
the overall circuit size if fewer gain stages are needed.
To demonstrate this principle experimentally, the on-chip BER tester was used to
compare link performance between conventional NRZ signaling (i.e., using the cw laser)
and short-pulse signaling (i.e., using the modelocked diode laser). The link was operated
at 400 Mb/s, and the sense-amplifier receivers were tested first. These receivers operate
using both phases of the electrical clock – Figure 5.3 illustrates the timing diagram.
While the clock is LOW, the detector photocurrent is integrated on a low-capacitance
input node and the output is held HIGH. When the clock goes HIGH, positive feedback is
used to evaluate the integrated charge, and the output goes to the proper state. This value
is latched for the remainder of the clock cycle by a subsequent circuit.
Figure 5.3. Timing diagram for the sense-amplifier receiver. Clock LOW corresponds to
the integrating phase, while clock HIGH triggers the evaluation phase. The receiver
electrical output follows the optical input after evaluation.
The link was operated first with the modelocked diode laser, and then with a cw diode
laser tuned to the same central wavelength. In all other respects, operating conditions
were unchanged. Figure 5.4 shows a BER plot for the link as a function of transmitted
signal power. The measurements show that an improvement in receiver sensitivity of
89
3.3 dB was obtained through the use of short pulses. Two separate effects provide this
enhancement. The first gain, which ideally is 3 dB, is due to more efficient use of energy
by the receiver. Because the integration phase corresponds to only half of the clock
period, any input energy that arrives during the evaluation phase is wasted. Using shortpulse RZ signaling, or RZ signaling with a very well-timed pulse avoids the loss.1 The
remaining 0.3 dB gain is attributed to RC speed limitations of the transmitters – the
modulator output eye diagram begins to close when using NRZ signaling at these data
rates, with the maximum signal amplitude achieved only at the center of the bit. When
short pulses are used, they can sample the data at the center of the bit and transmit the
maximum signal.
Figure 5.4. Measured single-channel bit-error rate at 400 Mb/s for NRZ and short-pulse
link operation. A power savings of 3.3 dB is obtained when the interconnect is operated
with the modelocked diode laser.
1
Note that while increasing the duty-cycle of the integrating phase would help reduce the
loss, the evaluation phase must be long enough to ensure sufficient amplification, and
the output data must be valid long enough to be sampled by a subsequent latch.
90
The sensitivity of transimpedance-amplifier receivers can also be substantially
enhanced with short pulses, albeit by a different mechanism [11][12]. It has been shown
that the sensitivity of commercial transimpedance receivers can be improved by greater
than 5 dB when using short pulse signaling [11]. When using optical pulses whose
bandwidth is higher than that of the receiver front-end, the impulse response of the
receiver is obtained. Thus, for a given optical energy, the receiver drives the largest
possible voltage swing and gives the sharpest rising and falling edges [11].
Receiver performance gain depends on the capacitive load of the photodiodes, and the
capacitance of the integrated photodiodes used in the link (e.g., about 260 fF) is higher
than expected during design of the circuits. Therefore, sensitivity enhancement was not
observed for the transimpedance-amplifier receivers. However, simulations show that by
reducing the diode capacitance to 40 fF, a receiver sensitivity improvement of 5 dB
should be possible.
5.3.2 SIGNAL RETIMING
To exploit the bandwidth of a multi-channel parallel interconnect fully, one must
ensure good signal synchronization between and within channels. Differences in signal
timing (either static differences or variable changes) are known as interchannel skew and
timing jitter. This timing uncertainty can limit the maximum data rate of parallel
interconnects. Such variations are present in the signals sent to the output modulators of a
transmitter chip due to process variations, clock skew, gate delays from dissimilar
circuits, and changing local conditions on-chip. Using electrical techniques to minimize
such problems increases design complexity, but the extremely short pulse duration and
low-jitter periodicity of a modelocked laser can be used to remove essentially all
transmitter-related skew and jitter [13].
To perform signal retiming (as shown in Figure 5.5), short optical pulses should be
placed at the center of the bit in the timing reference frame of the transmitter chip. An
actively modelocked laser pulse train typically has very low jitter. Thus, a short pulse
91
interconnect can remove the jitter that occurs on the transmitter chip by instantaneously
sampling the output state of a modulator with great precision – theoretically up to ±1/2 of
a bit of jitter can be removed. Static skew in a multi-channel parallel link can be removed
in a similar fashion: an array of well-timed short pulse beams can sample every
modulator simultaneously. After retiming is achieved, the signals can be propagated
without jitter and skew.
Figure 5.5. Illustration of (a) jitter removal, and, (b) skew removal from the transmitter
outputs using optical short pulses from a modelocked laser. The laser output has very low
jitter, and optical distribution of the beams creates very little interchannel skew.
To demonstrate these concepts using the demonstration link, skew and jitter were
intentionally added to the data at the transmitter chip. Electrical data from a pattern
generator was provided to the transmitters rather than using the on-chip PRBS generator.
First, jitter was added, with a magnitude of up to 3/8 of the bit period. The NRZ optical
interconnect transferred all of this jitter to the receiver. However, as shown in Figure 5.6,
the short pulse interconnect removed the transmitter jitter.
92
Figure 5.6. Jitter removal from a single interconnect channel at 80 Mb/s. The upper trace
shows the electrical input signal, while the lower trace shows the optical readout of the
receiver. The unlatched transimpedance-amplifier receiver output returns to the LOW
state with its characteristic time constant.
Neighboring transmitter channels in the array can be simultaneously operated with
different electrical data. In this case, two square waves were intentionally skewed by 3/8
of a bit relative to one another. Figure 5.7 shows the optical outputs of two channels
measured directly after the transmitter chip (i.e., intercepted halfway through the link).
One beam is shown from each differential channel, first for the cw and then for the short
pulse interconnect. While the interchannel skew remains for the NRZ interconnect, the
short pulse interconnect effectively removes all skew.
93
Figure 5.7. Skew removal for two channels operating at 80 Mb/s, using electrical inputs
that are skewed by 3/8 of a bit period. The interconnect is operated using (a) a cw laser,
and (b) a modelocked laser. Because the data was measured between the transmitter and
receiver chips, the ~2:1 contrast ratio of the modulators is evident in (b). The finite width
of the short pulses is due to the limited bandwidth of the optical detectors used for
testing.
5.3.3 ADDITIONAL LINK BENEFI T S
Many additional benefits can be obtained by operating an optical link using short
pulse signaling. Perhaps one of the most common uses of short pulses in
telecommunications is for time-division multiplexing. This technique allows an optical
fiber to carry more data than a single transmitter has the bandwidth to provide. Recent
94
experimental electrical links have also employed TDM to attain high aggregate data rates
[14]. However, in most electrical interconnects, it is the wiring bandwidth and not the
speed of the devices that typically limits the maximum signaling rate. In contrast, optical
channels have so much bandwidth that they are very difficult to use efficiently. To
achieve higher data rates than a single transmitter can obtain (i.e., 10 Gb/s for a state-ofthe-art VCSEL), TDM can be performed using modulators and short optical pulses. As in
the fastest electrical links, one of many clock phases would drive each transmitter in an
array. The modulators could be sampled with a phase-delayed array of optical pulses and
the bits interleaved on a single fiber. A simple demultiplexing approach at the receiver
chip could use gated receivers and the same multiphase clock. (This simple approach
would, however, suffer from optical losses.)
Short pulse signaling with modulator-based interconnects can be more energy
efficient than conventional NRZ signaling. With short pulses, optical power is only
incident on the modulator when the output is valid, while NRZ signaling places power on
the devices during the output transitions as well. This wastes energy at the transmitter
chip because the modulators dissipate electrical power proportional to the absorbed
optical power. It also wastes energy at the receiver chip, where the slow transmitted
edges contribute to poorer receiver sensitivity (as described earlier).
The delay, or signal latency, of an optical link is an important parameter that should
be minimized. It can be separated into three components: transmitter latency, propagation
delay, and receiver latency. In most cases the propagation delay is the largest component,
but receiver latency can be comparable in magnitude for short links such as on-chip
interconnects [15]. By simulating the receiver designs used in this work, we have shown
[16] that the use of short pulse signaling can substantially reduce the latency of the
receiver types used for optical interconnection.
A final link benefit is that larger synchronous areas can be achieved with short pulse
signaling. Particularly in free-space systems, optical path lengths can be fixed with great
precision. Optically-interconnected systems can therefore be designed to have extremely
95
low skew. Even very large systems could be operated synchronously [5] with a
centralized optical clock, and data signals whose timing is derived from the same
modelocked source. The timing phase of such a system would be very well defined
throughout, because the optical pulses from a modelocked laser have such sharp edges
and low jitter.
5.4 OTHER APPLICATIONS OF SHORT PULSES
5.4.1 OPTICAL CLOCK DISTRIBUTION
While many benefits can be achieved by using short pulses to transmit data within a
system, optical clock distribution (OCD) could very well be the most alluring application.
The clock in a digital system is used to synchronize logic operations; it is typically
operated just below the frequency at which the circuits begin to fail. However, due to the
limitations of electrical signaling, it is becoming increasingly difficult to provide a highquality clock to all points on a chip. An extremely large fraction of the power dissipated
by microprocessors – greater than 33% in a recent design [17] – is now devoted to the
problem of clock distribution. In order to keep a 10 GHz microprocessor operating within
acceptable timing margins (i.e., with a clock timing uncertainty of less than 10%), future
chips will require a distributed clock with no more than 10 ps of combined skew and
jitter. While this presents an enormous challenge for future electrical clock distribution
schemes, such timing precision may be achieved reasonably easily with optics. Very
good control of signal path lengths can be obtained by optical distribution. Additionally,
potentially inexpensive external cavity modelocked lasers have been demonstrated with
picosecond pulse widths and sub-picosecond timing jitter [18], making them an ideal
timing source.
For OCD to become a commercial reality, it must be shown that optics can provide
ample performance at a reasonable cost. To satisfy this condition, several key issues need
to be addressed. Inexpensive optical packaging and integration techniques that are
compatible with CMOS fabrication processes must be developed. Appropriate optical
96
detectors do exist, including the integrated III-V devices described here, III-V integrated
MSM detectors [19] and silicon detectors that can be designed in a standard CMOS
process [20]. However, detectors with low-enough capacitance have only recently been
integrated with CMOS.
The receivers used for OCD are of critical importance, because they can easily
increase power dissipation and add skew and jitter to the local clock. One attractive
solution is the use of very low-capacitance photodetectors in a “receiverless” fashion
[21]. As shown in Figure 5.8, this approach uses a totem pole of photodiodes, and places
temporally-staggered optical pulses on the detectors. The photocurrent is rapidly
integrated on the low-capacitance node, creating a rail-to-rail clock signal with precise
timing. A modelocked laser would provide the lowest jitter signal, and no subsequent
gain stages are present to add skew or jitter.
Figure 5.8. The concept of receiverless optical clock injection. A pair of pulse trains from
a modelocked laser is incident on a pair of photodiodes. When the pulses are staggered by
half the bit period, a low-jitter square wave appears at the center node. The use of lowcapacitance photodetectors reduces the energy required to produce a clock signal with
full logic levels.
In this way, optics could provide a method of distributing a high integrity clock to
thousands of points, thereby eliminating many of the complicated electrical schemes
required today. However, while OCD would reduce the design time and on-chip power
dissipation related to clock distribution, some degree of electrical distribution will be
97
necessary. Millions of latches will still be used in future microprocessors, and electrical
wires and buffers will drive them. Thus, even an optically-distributed clock will have
some amount of skew and jitter added before it reaches the latch level. A significant
advantage of the optical distribution method, however, is that the very precise clock can
be provided without buffers to key points on the chip. For example, the high data-rate
electrical interconnects that employ time-division multiplexing would benefit from very
the precise timing of short pulses.
5.4.2 MEASUREMENTS WITH HIG H TEMPORAL PRECISION
The low jitter and short pulse duration of a modelocked pulse train enable another
interesting application for optically-interconnected systems: precise, non-contact on-chip
timing measurements. Modelocked lasers have long been used to measure ultrafast
physical phenomena with very high precision. For measurements of silicon
microelectronics, the use of optically-triggered photoconductors to perform on-chip
electrical sampling is an interesting approach [22]. Low-temperature-grown GaAs
photoconductors serve can serve as extremely fast electrical pass-gates [23], and
integrating these devices to CMOS would enable high-speed analog sampling without
heavily loading the circuit. This approach is currently being investigated for use in
photonically-assisted analog-to-digital converters [24].
Another approach, the well-known technique of pump-probe testing, could be very
useful for testing electronic chips that have both optical input and output capabilities. To
demonstrate this technique, a silicon chip with integrated optoelectronics was employed.
It is similar to the chips described earlier, but fabricated in a 0.25-µm CMOS technology.
The measurement was designed to determine the electrical latency of a circuit that
consists of a transmitter driver and transimpedance receiver [25]. The circuit was chosen
because its delay, together with the delay of optical signal propagation, accounts for the
entire latency of an optical link. The latency is difficult to measure by electrical means
because of CMOS speed limitations and the capacitive loading effects of probing. Thus,
98
it was measured with the optical pump-probe approach. A schematic of the circuit under
test is shown in Figure 5.9.
Figure 5.9. Simplified schematic diagram of transimpedance-based receiver and
transmitter driver circuit used in the latency measurements. Full logic levels are
generated by the receiver at the point indicated. The functions of the optical test beams
are described in the text.
The measurement was performed in an optical pump-probe setup, using the ~100 fsduration pulses of the modelocked Ti:sapphire laser. Figure 5.10 shows the experimental
setup. Pseudo-differential input data, comprised of a repetitive optical pulse train (pump
beam) and a continuous-wave diode laser beam (balance beam), was incident on the
detector pair of the optically-differential receiver. The output voltage of the circuit was
another pulse train, whose pulses were broadened by the limited bandwidth of the circuit
and time-delayed by the latency of the circuit. The transmitter driver output voltage
controlled the modulator reflectivity, which was optically sampled with a short pulse
readout beam (probe beam). The intensity of the modulated probe beam could then be
measured using a lock-in amplifier. By varying the relative delay between the pump and
probe, the temporal response of the optoelectronic circuit was mapped with picosecond
resolution.
99
Figure 5.10. Schematic of the optical pump-probe setup used for interconnect latency
measurements.
The results are shown in Figure 5.11 for different supply voltages. The measured
latency, defined as the delay between the input and the 50% transition of the output, was
found to be about 550 ps. This simple measurement technique can easily be extended to
other circuits. By adding circuits between the receiver and transmitter driver shown in
Figure 5.9 (i.e., at the internal node with CMOS logic levels), one could perform a
precise measurement of its electrical delay with the receivers used to “generate” the
digital logic. This technique would make it possible to measure even very small delays,
such as the switching time of a single minimum-size inverter.
100
Figure 5.11. Data from a series of pump-probe delay measurements as a function of
supply voltage.
5.4.3 SINGLE-SOURCE WDM OP T ICAL INTERCONNECT
A final but intriguing application of ultrashort optical pulses is the concept of singlesource wavelength-division multiplexing. In telecommunications, WDM has enabled
very high data rates to be transmitted on a single optical fiber. At shorter length scales,
four-channel “wide” WDM appears to be a cost-effective approach for 10-Gigabit
Ethernet. There, it achieves a high aggregate bandwidth with cheaper, lower-performance
devices than a single 10-Gb/s link would require [26]. Applying WDM to waveguidebased optical interconnects may lower the cost and complexity of packaging by reducing
fiber counts.
Optoelectronic devices that would allow WDM at the interconnect level include
either multi-wavelength laser arrays or modulators in conjunction with a broadband
source. Multi-wavelength VCSEL arrays typically rely on complicated growth
techniques, and although some such arrays have been fabricated [27], wavelength control
101
during fabrication has remained difficult. An additional problem lies in the stability of
integrated transmitter wavelengths as the CMOS chip temperature changes. Using a
single, broadband source located off-chip, and performing spectral slicing to define the
wavelength channels can reduce this problem [28].
The concept is shown in Figure 5.12. This complete, chip-to-chip interconnect was
demonstrated at reasonably high data rates [29]. It uses a modelocked laser as a
broadband WDM source, and employs spectral slicing by modulating each wavelength
component with a separate reflective electroabsorption modulator. The WDM
interconnect benefits from many of the short pulse signaling advantages mentioned in
earlier sections. Additionally, an analysis of the limitations discovered during
construction and testing of the link has motivated further research, including the lowvoltage broad-spectral-bandwidth modulator described in Chapter 4, the use of improved
optomechanics, and an effort to develop modulators for use at the longer wavelengths of
conventional optical networks.
Figure 5.12. The broadband output of a modelocked laser can be used for single-source
WDM by employing spectral slicing. Each wavelength is modulated by a separate
integrated device and multiplexed into a single fiber.
102
REFERENCES
1. P. J. Delfyett, L. T. Florez, N. Stoffel, T. Gmitter, N. C. Andreadakis, Y. Silberberg,
J. P. Heritage, and G. A. Alphonse, IEEE J. Quantum Electron., 28, 2203 (1992).
2. B. D. Clymer and J. W. Goodman, Opt. Eng., 25, 1103 (1986).
3. J. H. Yeh, R. K. Kostuk, and K. Y. Tu, J. Lightwave Technol., 13, 1566 (1995).
4. P. J. Delfyett, D. H. Hartman, and S. Z. Ahmad, J. Lightwave Technol., 9, 1646
(1991).
5. D. A. B. Miller, Int’l J. of Optoelectronics, 11, 155 (1997).
6. D. A. B. Miller, Proc. IEEE, 88, 728 (2000).
7. F. B. McCormick, F. A. P. Tooley, J. L. Brubaker, J. M. Sasian, T. J. Cloonan, A. L.
Lentine, S. J. Hinterlong, and M. J. Heron, SPIE Proc., 1533, 88 (1991).
8. D. Agarwal, unpublished results.
9. T. K. Woodward, A. V. Krishnamoorthy, A. L. Lentine, K. W. Goossen, J. A.
Walker, J. E. Cunningham, W. Y. Jan, L. A. D’Asaro, L. M. F. Chirovsky, S. P. Hui,
B. Tseng, D. Kossives, D. Dahringer, and R. E. Leibenguth, IEEE Photon. Technol.
Lett., 8, 422 (1996).
10. J. P. van der Ziel, J. Appl. Phys., 52, 4435 (1981).
11. L. Boivin, M. C. Nuss, J. Shah, D. A. B. Miller, and H. A. Haus, IEEE Photon.
Technol. Lett., 9, 684 (1997).
12. P. J. Winzer and A. Kalmar, J. Lightwave Technol., 17, 171 (1999).
13. G. A. Keeler, B. E. Nelson, D. Agarwal, and D. A. B. Miller, IEEE Photon. Technol.
Lett., 12, 714 (2000).
14. C.-K. K. Yang, V. Stojanovic, S. Modjtahedi, M. A. Horowitz, and W. F. Ellersick,
IEEE J. Solid State Circuits, 36, 1684 (2001).
15. C. Debaes, M. Vervaeke, V. Baukens, W. Meeus, P. Tuteleers, M. Brunfaut, J. Van
Campenhout, and H. Thienpont, Proc. SPIE, 4652C (2002).
16. D. Agarwal and D. A. B. Miller, IEEE Lasers and Electro-Optics Annual Meeting
2001, San Diego, California, p. 812 (2001).
103
17. D. W. Bailey and B. J. Benschneider, IEEE J. Solid State Circuits, 33, 1627 (1998).
18. C. M. DePriest, T. Yilmaz, A. Braun, J. Abeles, and P. J. Delfyett, IEEE J. Quantum
Electron., 38, 380 (2002).
19. M. K. Hibbs-Brenner, Y. Liu, R. Morgan, and J. Lehman, IEEE Lasers and ElectroOptics Summer Topical Meeting 1998, Monterey, California, p. 3 (1998).
20. T. K. Woodward and A. V. Krishnamoorthy, IEEE J. Sel. Top. Quantum Electron., 5,
146 (1999).
21. C. Debaes, D. Agarwal, A. Bhatnagar, H. Thienpont, and D. A. B. Miller, Proc. SPIE,
4654 (2002).
22. W. R. Eisenstadt, R. B. Hammond, and R. W. Dutton, IEEE T. Electron. Dev., 32,
364 (1985).
23. S. Gupta, J. F. Whitaker, S. L. Williamson, G. A. Mourou, L. Lester, K. C. Hwang, P.
Ho, J. Mazurowski, and J. M. Ballingall, J. Electron. Mater., 22, 1449 (1993).
24. R. Urata, R. Takahashi, V. A. Sabnis, D. A. B. Miller, and J. S. Harris, IEEE Photon.
Technol. Lett., 13, 717 (2001).
25. G. A. Keeler, D. Agarwal, C. Debaes, B. E. Nelson, N. C. Helman, H. Thienpont, and
D. A. B. Miller, IEEE Photon. Technol. Lett., 14, 1214 (2002).
26. 10 Gigabit Ethernet Technology Overview White Paper, 10 Gigabit Ethernet
Alliance, Newport Beach, California (2002).
27. C. J. Chang-Hasnain, J. P. Harbison, C. E. Zah, M. W. Maeda, L. T. Florez, N. G.
Stoffel, and T. P. Lee, IEEE J. Quantum Electron., 27, 1368 (1991).
28. E. A. De Souza, M. C. Nuss, W. H. Knox, and D. A. B. Miller, Opt. Lett., 20, 1166
(1995).
29. D. Agarwal, G. A. Keeler, B. E. Nelson, and D. A. B. Miller, IEEE Lasers and
Electro-Optics Annual Meeting 1999, San Francisco, California, 2, p. 828 (2001).
104
CHAPTER 6: SUMMARY
Although reducing the dimensions of a CMOS transistor tends to enhance its
performance, the benefits of scaling do not extend to the electrical wires of integrated
circuits. Several approaches to alleviate the limitations of electrical wiring have been
proposed for future digital systems, including the use of new system architectures and
advanced electrical signaling concepts. These techniques, however, increase system cost
and design complexity, and fail to solve the fundamental problems of electrical
interconnects. It is likely that a new physical signaling method will be required in the
near future, and the most promising is the incorporation of optical signaling within a
computer.
The physical differences between optical and electrical signaling methods give rise to
many advantages commonly attributed to optical interconnects. The high carrier
frequency of optics, for example, means that very dense, high-capacity links are possible
using optics. However, to obtain the high bandwidths and high channel counts required
by future microprocessors, dense optoelectronic integration will be needed. While
monolithic optoelectronic integration holds some promise, hybrid integration is currently
the most feasible way to add optical functionality to a CMOS chip. Hence, a flip-chip
bonding technique was developed to hybridly integrate optoelectronic devices to silicon
electronics as a portion of this work. Optoelectronic arrays, each with hundreds of
devices, were successfully bonded to silicon with high yields. From this work, it appears
that using the technique for reticle- and wafer-level integration should be relatively
straightforward, provided the bonding continues to be performed without large changes in
temperature (which would be an issue due to the coefficient of thermal expansion
mismatch between the two substrates).
Only a few optoelectronic transmitters have the performance needed by future optical
interconnect applications. The use of VCSELs can simplify optical packaging, but may
not provide the bandwidth required by future systems, and arrays of VCSELs can be
105
difficult to fabricate with high yields. Surface-normal electroabsorption modulators can
be fabricated with much greater yields, simplify the integration (i.e., because they also
function as photodetectors), allow the use of short pulses, and can provide ample
performance in most applications. In fact, the modulators integrated to CMOS in this
work allowed the construction and operation of a multi-channel, high-bit-rate
demonstration system using two hybridly-integrated CMOS chips. Unfortunately,
modeling shows that when CMOS supply voltages are reduced in future generations, the
performance of these modulators will decline below unacceptable levels.
The use of resonant cavity enhancement may help to extend the useful life of surfacenormal MQW modulators by increasing their performance at low voltages. The tunablecavity design described in Chapter 4 shows that asymmetric Fabry-Perot modulators can
be rather easy to fabricate despite the challenging growth. This resonant-cavity device
obtains a high contrast ratio and change in reflectivity with current voltage levels. Within
a few years, as on-chip voltages drop below 1 Volt, a new modulator design will be
needed. The proposed FOAM modulator shows promise as a very-low-voltage
modulator, but more extensive modeling and testing remains to be done.
While future systems will require improved optoelectronic devices, existing
technology can be used to make functional optical links. A series of experiments were
performed on the chip-to-chip multi-channel optical interconnect demonstrator, and they
show that short optical pulses have many benefits in such a system. Short pulse signaling,
which makes use of the ultrashort, low-jitter pulses from a modelocked laser, was
achieved by modulating the optical pulses with the flip-chip-bonded electroabsorption
modulators. By measuring the BER of the link, it was experimentally verified that short
pulse signaling improves receiver sensitivity when compared to conventional NRZ
signaling. Signal retiming (i.e., skew and jitter removal) was also demonstrated using the
link.
By combining the low jitter of a modelocked laser with the low skew that
accompanies free-space optics, optical signals can be delivered with very high temporal
106
precision. For this reason, optical clock distribution and precise temporal measurements
of circuits are two very attractive applications of short pulses. In this work, a pump-probe
measurement of circuit latency with picosecond resolution was demonstrated, and a
receiverless optical clocking technique was described. Finally, a novel system that uses
the broad spectral bandwidth of ultrashort pulses for single-source wavelength division
multiplexing was discussed.
Optical interconnects could solve many of the signaling challenges expected for
future silicon CMOS integrated circuits. However, before optical interconnects become a
reality, the cost versus performance trade-off must clearly favor such a paradigm shift.
Packaging remains an important concern, but hybrid integration of optoelectronic devices
will help to address this issue. With progress in optoelectronic device engineering,
improved device yields and higher performance at low voltages will also occur. From a
systems perspective, the use of ultrashort optical pulses may offer even greater
advantages than those of “conventional” optical interconnects. These concepts will
become more practical when the compact, high-repetition-rate modelocked diode lasers
currently in the laboratory are commercialized. Given the many questions that have yet to
be answered, the eventual physical incarnation of optical interconnects still remains
unknown. However, it seems clear that the future of optical interconnects is very bright.
107
APPENDIX A: MQW MODULATOR PROCESSING
This appendix contains the processing techniques that were developed to fabricate
and integrate the GaAs MQW modulators presented in this work. While several of the
process steps can be performed using alternative techniques (i.e., with different etch
recipes), the following process flow avoids many of the unforeseen and innumerable
problems that were encountered along the way.
A.1 LITHOGRAPHY PROCEDURE:
a) Solvent clean (acetone, methanol, isopropanol, water). N2 dry gently.
b) Heat for 10 min at 90 °C on hot plate to evaporate residual water.
c) Spin HMDS adhesion promoter, then AZ4620 photoresist (PR). Spinner chuck
should be set at 5000 rpm for 40 seconds.
d) Remove PR from backside of wafer.
e) Bake for 10-15 min at 90°C on hot plate.
f) Align on Karl Suss and expose for 36 seconds at ~9.11 on UV lamp. (Remember
to record your exposure in the log book, including the intensity during that 36 s.)
g) Develop in AZ400K developer solution for ~3.5 min. (AZ400K should be diluted
1:4 in DI water.)
h) Check progress under microscope. Exposed photoresist should be removed. Any
remaining PR should appear as colorful “rings” (like oil rings.) If PR is not
completely removed in the appropriate areas, continue to develop and check
accordingly.
i) If wet etching is to be performed next, or anything that could be affected by
residual water, bake 10 min at 90 °C.
108
A.2 WAFER STRUCTURE FOR RESONANT-CAVITY TUNABLE MODULATORS
Table A.1. Growth instructions for Fabry-Perot modulator wafers. Layers are listed in
order of growth, starting with the substrate.
GaAs substrate (n+ or S.I.)
500 Å GaAs cleaning layer (n+)
[Si]=4.4e+18
2800 Å Al0.9Ga0.1As etch stop (n+)
[Si]=1.1e+19
500 Å GaAs buffer layer (2nd etch stop) (n+)
[Si]=4.4e+18
5000 Å Al0.3Ga0.7As (n+)
[Si]=4.4e+18
30 Å Al0.3Ga0.7As (undoped)
50 periods of:
95 Å GaAs
30 Å Al0.3Ga0.7As
2000 Å Al0.3Ga0.7As (p+)
[Be]=1.0e+19
100 Å GaAs (p+)
[Be]=1.0e+19
A.3 WAFER TEST STRUCTURES
a) N-contacts
i) Lithography (mesa positive PR, mesa size = 3) – leaves PR to protect
rectangles where mesas will remain. To test etch calibration prior to etching
full wafer, cleave a small piece and etch as below, measuring etch depth with
alpha step profilometer.
ii) Wet Etch – Etch in H2SO4:H2O2:H2O (1:8:160). Calibration of this etch at
room temperature is ~2200 Å/min. Etch should end in n-AlGaAs (between
~8380 Å and 13380 Å which implies etching for about 4.7 min for the current
‘standard wafer’). Typically, we use the following procedure:
109
(1) Draw 40 mL of H2O.
(2) Add 2 mL of H2SO4 (sulfuric acid). Mix.
(3) Draw 10.5 mL of that mixture into another beaker. This should contain 10
mL water and 0.5 mL of sulfuric acid.
(4) Add 70 mL water for a total of 80 mL water, then add 4 mL hydrogen
peroxide. Mix.
(5) Allow to cool to room temp.
(6) Drop wafer in mixture for ~4.7 min. Do not stir or agitate.
(7) Rinse thoroughly in DI water.
iii) Remove PR with acetone (solvent clean) and test depth with profilometer.
iv) Lithography (ring contact, mesa size = 4).
v) Plasma asher for 15 seconds to descum for contacts.
vi) Give to Tom for deposition of n-type Ohmic contacts. Specify oxide etch (1:1
HCl/water, 15 sec, DI rinse, N2 dry) unless you are afraid of etching down
right through the n+ layer. Deposit n-type contacts, as in Table A.2.
Table A.2. Deposition instructions for n-type Ohmic contacts with no barrier.
3000 Å Au
100 Å Ni
236 Å Au
63 Å Ge
102 Å Au
108 Å Ge
substrate
vii) Liftoff – leave in acetone for >30 min. Remove with bursts of acetone from
solvent bottles or “gentle ultrasound” (i.e., little bursts).
viii) Anneal for about 30 seconds at 450 °C.
ix) Test n-contacts on clean room probe station using semiconductor parameter
analyzer. I-V curve should appear linear (i.e., Ohmic).
110
b) P-contacts
i) Lithography (ring contact, size = 3) on top of mesas.
ii) Plasma asher for 15 seconds to descum for contacts.
iii) Give to Tom for deposition of p-type Ohmic contacts. Specify oxide etch (1:1
HCl/water, 15 sec, DI rinse, N2 dry). Deposit p-type Ohmic contacts, as in
Table A.3.
Table A.3. Deposition instructions for p-type Ohmic contacts with no barrier.
3000 Å Au
150 Å Cr
substrate
iv) Liftoff (as above).
v) Test p-contacts and p-i-n diode structure on clean room probe station using
semiconductor analyzer. I-V curve should appear linear (i.e. Ohmic) for p-top connections and diode-like for p-to-n connections.
c) Testing optical properties
i) At the probe station, with tunable Ti:sapphire laser, check exciton peak of
multiple quantum well structure. Ideally, the lowest exciton peak (1st electron
to 1st heavy hole) would appear at 850 nm. Exciton peaks ideally will not
broaden much with applied voltage.
ii) Check shift of exciton peak with applied voltage between about 0-6V. To do
this, use the two lock-ins to measure device photocurrent and laser reference,
vs. λ and vs. V. A useful Labview program was created to automate the
process.
iii) Calculate index of refraction for each curve. Can do with the difference in
absorption coefficient between your sample (which is calculated from the
photocurrent measurement above) and that of bulk GaAs. A C++ program to
do this Kramers-Kronig calculation was also created.
111
iv) Calculate ideal voltage shift at which to operate modulator in order to
maximize reflectivity (R) and change in reflectivity (DR). Can use the
transfer-matrix method, such as in GAK’s computer simulations. See if
everything looks OK, then continue to processing.
A.4 DEVICE PROCESS STEPS
a) N-holes (mask name: WIDE N-ETCH)
i) Lithography – to open up n-holes for etchant to enter. NOTE: air bubbles can
remain in the holes during etching. This screws up the etch, causing less than
100% yield. The fix is to use water to pre-wet the wafer, i.e., spray it with the
water gun for a while before trying to etch. Then put it into the etchant wet,
vigorously shaking the wafer to remove the thin water film. Ultrasound will
damage the PR!
ii) Wet Etch – Etch in H2SO4:H2O2:H2O (1:8:160). Calibration of this etch at
room temperature is ~2200 Å/min. It is safer, however, to calibrate the etch
every time (on a small corner of the wafer), since the etch rate seems to vary
about 20% or so. Calculate the depth of the etch for this rate. (For current
wafer, etch should end in n-AlGaAs between ~8380 Å and 13380 Å, which
implies etching for about 4.7 min.) Use procedure outlined above for mixing
the solution. Solvent clean and dry.
b) N-contacts (mask name: P-OHMIC (for p-up))
i) Lithography – makes holes for the n-Ohmic deposition to stick to. Everything
else lifts off.
ii) Plasma asher for 15 seconds to remove PR scum.
iii) Give to Tom for n-contact deposition. Assuming you want to use the pcontacts as a mirror, don’t worry about the indium barrier on top of this layer.
Specify oxide etch (1:1 HCl/water, 15 sec, DI rinse, N2 dry) unless you are
afraid of etching down right through the n+ layer. Deposit n-type contacts, as
in Table A.2.
iv) Liftoff (as above) using acetone and possibly ultrasound.
112
c) Anneal, Test
i) Anneal using RTA in CIS, 450 °C, 30 seconds. Do a practice run first, since
the RTA often fails.
ii) Test n-contacts on probe station.
d) P-contacts (mask name: N-OHMIC (for p-up), or new mask for 8x8, 12x12 pads)
i) Lithography – makes holes for the p-ohmic deposition to stick to. Everything
else lifts off.
ii) Plasma asher for 15 seconds to remove PR scum.
iii) Give to Tom for reflective p-contact deposition with barrier layer (see Table
A.4). Key points: The p-contact also acts as a reflective surface underneath the
GaAs modulator. To maximize the reflectivity, we use gold as the reflective
surface, and therefore skip the Cr sticking layer (which would lower R). Also,
we try to avoid annealing the contacts, so they are done after the n-contacts.
Finally, the indium used for flip-chip solder could alloy with the gold, again
lowering the reflectivity. Therefore, we include a barrier layer, such as nickel
or copper, to stop In diffusion.
Table A.4. Deposition instructions for reflective p-type Ohmic contacts (with In barrier).
2000 Å Au
500 Å Ni (or Cu)
2000 Å Au
substrate
iv) Liftoff (as above) using acetone and possibly ultrasound.
v) Test electrical characteristics.
e) Self-aligned p-etch (mask name: P-ETCH)
113
i) This step decreases the size of the device active area, lowering device
capacitance. The p-contacts that were just deposited will act as the selfaligned mask for the small active area.
ii) Lithography – to cover the rest of the wafer (especially the n-contact side) but
open holes around the p-contacts.
iii) Dry etching with PlasmaQuest in CIS clean room. Use anisotropic dry etch
for GaAs/AlGaAs using BCl3 and Cl2 as the active etchants and significant RF
power for straight side-walls. The recipe titled “gordona1” is likely the latest
and greatest version. One recipe that works:
400 W ECR, 10 W RF
10 sccm Ar, 15 sccm BCl3, and 1 sccm Cl2
Etch rate is roughly 0.17 µm/min, and we want to etch through the p-region
(i.e., 2100 Å) into the intrinsic. (Going into the n-region could be unsafe if the
n-hole etch overlaps this one.) So 2-3 minutes is probably fine.
f) Indium Deposition (mask name: NP CONTACTS #2 (bigger holes), or the new
mask for smaller p-contact holes)
i) Lithography – opens both contacts for indium solder bumps. Everything else
lifts off.
ii) Bring to CISX. Using our evaporator, deposit 3-6 microns of indium.
iii) Liftoff.
g) Mesa Etch (mask name: MESA ETCH)
i) Lithography – covers both contacts and significant surrounding area. We etch
away everything else, down beyond the etch stop layer. Thus, following
substrate removal, only the mesas will remain on the chip.
ii) Hardbake – important! To avoid burning the photoresist in the PlasmaQuest,
we do a photoresist hardbake after developing. Using a hotplate, bake the PR
mesas at 140 °C for 30 minutes.
iii) Dry etching with PlasmaQuest in CIS clean room. Use anisotropic dry etch
for GaAs/AlGaAs using BCl3 and Cl2 as the active etchants and significant RF
114
power for straight side-walls. The recipe titled “gordona1” is likely the latest
and greatest version. One recipe that works:
400 W ECR, 10 W RF
10 sccm Ar, 15 sccm BCl3, and 1 sccm Cl2
Etch rate of roughly 0.17 µm/min means a 15 minute etch (900 sec) will etch
about 2.5 microns, sufficient for an average wafer.
iv) Photoresist stripping – this step takes more time because of the hardbake and
plasma etching. Acetone alone will not work. Instead, use 1165 photoresist
remover, a.k.a. N-methyl-2-pyrrolidone. Remove the resist in a covered
beaker of 1165 at 65 °C for 60 minutes. Key: you must give the beaker several
seconds (~10 sec) of ultrasound agitation a few times during the hour soak.
This removes those hangy bits around the mesa edges. A plasma ashing at the
end may also prove quite helpful.
h) Array Protection (mask name: ARRAY PROT)
i) To avoid covering up the wire bonding pads on the CMOS chip, we must
remove the arrays of devices that surround the central array of devices. This
can be done using a large photoresist square to protect the main array. Use the
quarter of the mask that has ~1.5 mm solid squares. Also, overexpose the
resist, because it is likely to be extra thick at the edges and in between
unwanted mesas. (i.e., 1813 with 40 second exposure, or 4620 with 45
seconds)
ii) Etch away the unwanted stuff. Sulfuric acid:hydrogen peroxide:water (1:8:1)
for 1 minute.
iii) Solvent clean to remove the photoresist.
i) Cleave modulator arrays
i) Cleave between the arrays (i.e., through the spot where there used to be an
array directly next to the desired array), leaving about a 5 mm x 5 mm square
of GaAs.
115
ii) To cleave without damaging devices or smashing the indium, hold the wafer
by its edges with tweezers. Working on a microscope slide is helpful.
Carefully scribe through an array at an edge. Now hold the scribe line over the
edge of the slide and use the scribe tip to push down on the GaAs bit (on
something unimportant).
j) Prepare Si/CMOS chips – gold on Al pads (mask name: FLIPCHIPG1)
i) Lithography – to open holes for Au deposition. Indium will stick better to
gold, but Al and Au will mix to form a non-conductive ‘purple plague’. Make
sure to deposit a barrier layer.
(1) Clean and prebake the CMOS to dry it.
(2) Spinning PR will be complicated due to the fact that the huge edge bead
will impede the exposure, due to the small size of the chips (2mm x 2mm).
To compensate:
(3) Spin PR thin onto a glass slide piece to be used as “glue”. A few drops of
AZ4620 @ 1000 rpm, 40 seconds is pretty good.
(4) Place Si/CMOS chip in center of PR as flat as possible.
(5) Tile the surrounding area with square pieces of blank Si, such that all
edges of the Si/CMOS chip are touching a piece of blank Si. This will
allow the edge bead to form completely on the blank Si pieces, and not on
the center Si/CMOS chip, which is all we care about. (See Fig. A.1.)
(6) Bake the whole mess for ~110 sec @ 90 °C to firm it up for spinning.
(7) Spin on as in standard lithography, then remove Si pieces by pushing them
away from the chip (or tangentially from it) with tweezers. The CMOS
may come off too, but it can be stuck down to another cover slip. Now do
the standard lithography post-bake.
(8) Alignment technique – You must try to align the CMOS chip rotationally
and in the y-direction by looking through an open part of the mask next to
the pad array. Then, using a high-power objective, look through the tiny
pad holes and count the 20 Aluminum pads go past on the CMOS chip
(see Fig. A.2).
116
(9) Overdevelop (~0.7-0.8 min) in case the PR was extra thick.
(10) There is a good chance that an edge bead will be too soft, stick to the
mask, and pull off. This exposes the CMOS pads, which could be
disastrous if they get shorted by the metallization. Cover these spots by
dabbing on some partly-dried up PR from the spinning process. Use the
tips of a sharp pair of tweezers, and be careful not to mess up the rest of
the chip.
(11) Overbake (20-25 min) the whole thing a bit to harden the PR “glue”
under your chip, which will otherwise bubble and make Tom upset.
Figure A.1. Tiling method for spinning PR onto small CMOS chips.
Figure A.2. Alignment method for CMOS chip and small holes.
117
k) Continue with standard lithography procedure:
i) Plasma asher for 15 seconds to descum PR.
ii) Give to Tom for gold deposition with barrier layer. Specify oxide etch (1:1
HCl/water, 15 sec, DI rinse, N2 dry). Deposit contacts as in Table A.5.
Table A.5. Deposition instructions for CMOS contacts with Al diffusion barrier.
3000 Å Au
1000 Å Ni (or Cu)
150 Å Ti (or Cr)
substrate
A.5 FLIP-CHIP BONDING
a) Use our flip-chip bonder in CIS. We have found that using a bonding pressure
(mass) of 0.5-1 gram/bump is good for these indium bumps. We have tried from
0.5-4.0 grams though, and it is unclear if the force is particularly important. We
currently use times of approximately 1 minute. Some amount of heating (but
below the melting point of 180 °C) works well.
b) Wick in epoxy. This provides additional mechanical strength for the modulators
after substrate removal, and stops any wet etchants from attacking the modulators
from the side during substrate removal (and also protects the CMOS – key point:
the Al pads will be etched by almost any acid). The current epoxy type is TRABOND BA-2113:
i) Mix epoxy. Try to avoid introducing any bubbles. The best way is to skip the
mixing container altogether. Instead, cut both ends of the tube and squeeze it
into a small disposable dish, stirring gently.
ii) Apply dabs to edge of Si/GaAs interface. The best way we’ve tried is to dip
about 1 cm of a glass fiber into the epoxy and let it run down in a small bead.
Be careful not to get epoxy on either the GaAs back surface, or on the
microscope slide during the curing process or you will never get the chip off!
118
iii) Cure for 4 hours at 65 °C (or longer to ensure complete hardness).
A.6 SUBSTRATE AND ETCH STOP REMOVAL
a) Non-selective removal. This is a fast wet etch to remove most of the substrate,
leaving about 50 µm to remove selectively. Use H2SO4:H2O2:H2O (1:8:1) for very
fast etching (5 mm/min). Make sure it cools first to get more repeatable rates.
About 30 minutes in here tears through a lot of substrate. (Note: it seems to matter
if the GaAs is bigger than the Si CMOS or vice versa. When the GaAs wafer
piece is larger, 30 minutes is good in the fast wet etch. When the Si is larger, it
can take up to 60-70 minutes.)
b) Selective substrate etch. This should stop on the AlGaAs etch stop layer, leaving
the modulators behind on the CMOS. Use Citric Acid:Hydrogen Peroxide (4:1).
This etch is supposed to be 1000 times selective in etching GaAs over AlGaAs.
Actual etch rates from papers:
i) GaAs, ~4000 Å/min (can be faster at elevated temperatures)
ii) AlAs, ~1 Å/sec
iii) Al.60Ga.40As, ~5-10 Å/sec (from our experience)
(1) If you have no citric acid, it is prepared from 1 part anhydrous citric acid
to 1 part water. A bottle should last for a year or something. Mixing takes
a while (a day or so).
(2) Prepare the citric/peroxide mixture and be sure to stir it well.
(3) Do a 1:1 HCl/water dip for 60 seconds, DI water dip for 30 seconds, touch
to wipers to dry but don’t blow dry! (An oxide layer will completely stop
the citric acid etch from working.)
(4) Etch until you hit the etch stop. Stop. This could take 4-8 hours. Recent
average: 5.5. Now the mesas should all be exposed. Yay!
c) Remove the etch stop.
i) For a high-aluminum content AlGaAs layer (i.e., 90%), you can use
HCl/water at 1:1. After about 60 seconds, it should stop on the GaAs buffer.
119
ii) The formula that seems to succeed with our 60% Al etch stop is KI/I2/H20
(27.8 g KI + 16.25 g I2 + 25mL water).
(1) Supposedly etches Al0.3Ga0.7As at 2µm/min and GaAs at 0.1 µm/min, with
a huge increase for higher aluminum content.
(2) Note that this is a black liquid that stains everything, including the epoxy.
(3) Due to the high etch rate, we estimate that this etch should be done in only
a few seconds. It seems that 10 seconds is fine.
(4) This worked really well the first time we tried it (i.e. right after mixing the
solution for the first time.) Since then we have tried using the same bottle,
but the properties change over time. Mixing it fresh is the best approach.
(5) Note that this is also the same recipe for the gold etchant. Therefore, any
exposed gold will be removed.
A.7 CAVITY TUNING AND EPOXY REMOVAL
a) At this point, you can tune the thickness of the resonant cavity by doing
successive H2O2 and HCl/water dips, which should remove about 10 Å/cycle of
GaAs and also smooths the surface. Experimentally, we have seen the expected
shift of the Fabry-Perot peak using this tuning method. In order to see this, you
should scan the reflectivity on the probe station before cavity tuning, determine
the required number of dips (at ~0.75 nm/cycle shift towards shorter ?) and
proceed.
b) Epoxy removal using the Phlegmatron plasma asher in Ginzton. This step is
necessary to remove the epoxy from on top of the CMOS wire bonding pads.
Using process #5, set the Gas 1 at 83% and Gas 2 at 17%. About 10 minutes
should be sufficient, but it seems that overheating causes the epoxy to burn,
turning it a bit crispy-looking. If this happens, it will likely NEVER come off and
you’re out of luck. Solution: if this starts to occur, use short (i.e., 2 min) steps, and
repeat many times until the epoxy is removed.
120
c) Wire bond using thermally- and electrically-conducting epoxy in the appropriate
package. A small spacer under the chip will help raise the height relative to the
package top for testing with short focal length objectives.
121
APPENDIX B: MODELING MODULATOR REFLECTIVITY
In order to understand the effects of tuning the cavity thickness and to specify the
proper wafer designs before they were grown, the reflectivity of both the integrated
asymmetric Fabry-Perot modulator and the FOAM modulator was extensively simulated
by numerical methods. The optical scattering matrix approach that was used followed the
formalism described in [1][2] for a Fabry-Perot interferometer, but was extended to
include multiple absorbing layers of arbitrary thickness and refractive index. All layers
were assumed to be linear, isotropic, and homogeneous (including the active MQW
region, which was modeled as a single layer), and the optical beams were taken to be
plane waves (typically at normal incidence).
E+(z) and E-(z) represent the complex amplitude of the forward- and backwardtraveling optical plane waves at the position z. The total electric field at z is given by:
 E + ( z )
E ( z) =  −

 E ( z )
(B.1)
The total electric field at a final position, zf, can be related to the initial field at zi by:
 E + ( zi )   S11
 −
=
 E ( zi )   S 21
+
S12   E ( z f ) 


S 22   E − ( z f ) 


(B.2)
or, more simply,
E(zi) = S E(zf)
(B.3)
where S is the 2x2 scattering (or transfer) matrix that represents the influence of the
layers between zi and zf. When the characteristics of each layer are known, the scattering
matrix can be written as an ordered combination of matrices Lj and Iij. These matrices
account for the effects of traveling through layer j, and the transmission and reflection
that occur at the interface between layers i and j. Thus, for a device with j layers,
122
S = I12 L2 I 23 L3 ...Li I ij
(B.4)
The 2x2 interface matrix, Iij, is written as a function of the Fresnel transmission and
reflection coefficients, tij and rij:
I ij =
11

tij  rij
rij 
1 
(B.5)
with (for TE polarizations)
rij =
N i cos θ i − N j cosθ j
N i cos θ i + N j cosθ j
(TE)
tij = 1 + rij (TE)
(B.6)
(B.7)
and (for TM polarizations)
rij =
N j cos θ i − N i cosθ j
N j cos θ i + N i cosθ j
tij = 1 − rij (TM)
(TM)
(B.8)
(B.9)
where Nj is the complex index of refraction of layer j, ?j is the angle of propagation in
layer j, and the Stokes relations
rij = − rji
tij t ji = 1 − rij
(B.10)
2
(B.11)
are employed.
The 2x2 propagation matrix, Lj, is given by:
123
0
 exp(i β j )

Lj = 
0
exp(−i β j ) 

(B.12)
where
βj =
2π
N j d j cosθ j
λ
(B.13)
accounts for the phase shift and attenuation that occurs in the medium. Here, dj is the
thickness of layer j, and ?j is determined using Snell’s Law:
N i sin θ i = N j sin θ j
(B.14)
TT and RT give the overall transmission and reflection of the device described by the
matrix S, with:
TT =
1
S11
(B.15)
RT =
S21
S11
(B.16)
and
Thus, an asymmetric Fabry-Perot multiple quantum well modulator can be modeled
as a simple multilayer stack, provided the thickness and refractive index (as a function of
wavelength and applied bias) of each layer is known. The complex refractive index, N,
which includes both real and imaginary (absorptive) parts, is given by:
N = n − ik
(B.17)
where n is the real refractive index (i.e., n=c/v), and k is the imaginary part of the
refractive index that accounts for absorption or gain within the medium. The relationship
between the absorption coefficient, a, and the imaginary refractive index, k, is:
124
α=
4π k
λ0
(B.18)
where ?o represents the wavelength in free space.
Optical absorption coefficients for the MQW intrinsic region of the wafer were
determined experimentally as a function of wavelength and applied electric field (as
discussed in Chapter 3), and can be seen in Figure 3.6. Absorption coefficients and real
refractive indices for the remaining GaAs and AlxGa1-xAs layers were calculated from
and retrieved from the literature [3][4][5]. Published values for gold were also used [6],
and the GaAs/Au interface was assumed to be ideal (i.e., that no metallic intermixing had
taken place).
To determine the real refractive index for the MQW intrinsic region, a differential
Kramers-Kronig (KK) transformation approach was employed. In general, the KK
relation can be used to relate n and k to one another for a given material. However, here
we use the fact that the absorption profile (i.e., imaginary refractive index) of the
quantum well active layer differs only slightly from that of gallium arsenide over the
entire energy spectrum. Because the difference is almost entirely near the bandgap, the
real refractive index can be assumed similar for both materials except near that energy
region. Thus, a differential KK transformation can be used to generate ? n if ? k is known
between the two layers.
The experimentally-derived MQW absorption coefficients were compared to the
values known for GaAs, and the difference was taken over the known wavelength range
to find ? k. A numerical Kramers-Kronig transformation was applied and the resulting
values for ? n were added to the known refractive index of GaAs. This yielded the
approximate wavelength-dependent real refractive index for the active region (as a
function of wavelength and bias), which is shown in Figure B.1.
125
Refractive index
3.7
0 Volts
1 Volt
2 Volts
3 Volts
4 Volts
5 Volts
6 Volts
bulk GaAs
3.65
3.6
3.55
825
835
845
855
865
Wavelength (nm)
875
885
Figure B.1. Calculated real refractive index for the quantum well intrinsic region as a
function of wavelength and bias voltage (for wafer #472). The values for GaAs are
shown for comparison.
Using the complex refractive indices for each layer and the desired layer thicknesses,
the device performance was simulated by calculating the total reflectivity, RT, from the
optical scattering matrix. The effects of altering the layer thicknesses could be easily
investigated, and device optimization was performed. Selected simulation results can be
found in Chapter 4 of this dissertation.
126
REFERENCES
1. M. Born, and E. Wolf, Principles of Optics, 6th ed., Permagon Press, New York
(1986).
2. J. J. Monzón, L. L. Sánchez-Soto, and E. Bernabeu, Appl. Opt., 30, 4126 (1991).
3. S. Gehrsitz, F. K. Reinhart, C. Gourgon, N. Herres, A. Vonlanthen, and H. Sigg, J.
Appl. Phys., 87, 7825 (2000).
4. E. D. Palik, ed., Handbook of Optical Constants of Solids, Academic Press, Orlando,
vol. 1, pp. 438-439 (1985).
5. D. D. Sell, H. C. Casey Jr., and K. W. Wecht, J. Appl. Phys., 45, 6 (1974).
6. E. D. Palik, ed., Handbook of Optical Constants of Solids, Academic Press, Orlando,
vol. 1, pp. 275-294 (1985).
127