www.fairchildsemi.com
RC4200
Analog Multiplier
Features
Description
• High accuracy
• Nonlinearity – 0.1%
Temperature coefficient – 0.005%/°C
• Multiple functions
• Multiply, divide, square, square root, RMS-to-DC
conversion, AGC and modulate/demodulate
• Wide bandwidth – 4 MHz
• Signal-to-noise ratio – 94 dB
The RC4200 analog multiplier has complete compensation
for nonlinearity, the primary source of error and distortion.
This multiplier also has three onboard operational amplifiers
designed specifically for use in multiplier logging circuits.
These amplifiers are frequency compensated for optimum
AC response in a logging circuit, the heart of a multiplier,
and can therefore provide superior AC response.
The RC4200 can be used in a wide variety of applications
without sacrificing accuracy. Four-quadrant multiplication,
two-quadrant division, square rooting, squaring and RMS
conversion can all be easily implemented with predictable
accuracy. The nonlinearity compensation is not just trimmed
at a single temperature, it is designed to provide compensation over the full temperature range. This nonlinearity
compensation combined with the low gain and offset drift
inherent in a well-designed monolithic chip provides a very
high accuracy and a low temperature coefficient.
Applications
• Low distortion audio modulation circuits
• Voltage-controlled active filters
• Precision oscillators
Block Diagram
I2
Q2
I1
Q1
–
+
VOS1
–
VOS2
+
+
–
Q3
Q4
I3
I4
RC4200
65-4200-01
REV. 1.2.1 6/14/01
RC4200
PRODUCT SPECIFICATION
Functional Description
The RC4200 multiplier is designed to multiply two input
currents (I1 and I2) and to divide by a third input current (I4).
The output is also in the form of a current (I3). A simplified
circuit diagram is shown in the Block Diagram. The nominal
relationship between the three inputs and the output is:
I1 I2
I 3 = --------I4
(1)
The three input currents must be positive and restricted to a
range of 1 µA to 1 mA. These currents go into the multiplier
chip at op amp summing junctions which are nominally at
zero volts. Therefore, an input voltage can be easily
converted to an input current by a series resistor. Any
number of currents may be summed at the inputs. Depending
on the application, the output current can be converted to a
voltage by an external op amp or used directly. This capabilty of combining input currents and voltages in various
combinations provides great versatility in application.
Inside the multiplier chip, the three op amps make the
collector currents of transistors Q1, Q2 and Q4 equal to their
respective input currents (I1, I2, and I4). These op amps are
designed with current source outputs and are phase-compensated for optimum frequency response as a multiplier. Power
drain of the op amps was minimized to prevent the introduction of undesired thermal gradients on the chip. The three op
amps operate on a single supply voltage (nominally -15V)
and total quiescent current drain is less than 4 mA. These
special op amps provide significantly improved performance
in comparison to 741-type op amps.
The actual multiplication is done within the log-antilog
configuration of the Q1-Q4 transistor array. These four
transistors, with associated proprietary circuitry, were
specially designed to precisely implement the relationship.
kT I CN
V BEN = ------- In --------Q I SN
Previous multiplier designs have suffered from an additional
undesired linear term in the above equation; the collector
current times the emitter resistance. The ICrE term introduces a parabolic nonlinearity even with matched transistors.
Fairchild Semiconductor has developed a unique and proprietary means of inherently compensating for this undesired
ICrE term. Furthermore, this Fairchild Semiconductor developed circuit technique compensates linearity error over temperature changes. The nonlinearity versus temperature is
significantly improved over earlier designs.
From equation (2) and by assuming equal transistor junction
temperatures, summing base-to-emitter voltage drops around
the transistor array yields:
I1
I2
I3
I4
KT
-------- In ------- = In ------- – In ------- – In ------I S1
I S2
I S3
I S4
q
= 0
(3)
This equation reduces to:
I S1 I S2
I1 I2
--------- = --------------I S3 I S4
I3 I4
(4)
The rate of reverse saturation current IS1IS2/IS3IS4, depends
on the transistor matching. In a monolithic multiplier this
matching is easily achieved and the rate is very close to
unity, typically 1.0±1%. The final result is the desired
relationship:
I1 I2
I 3 = --------I4
(5)
The inherent linearity and gain stability combined with low
cost and versatility makes this new circuit ideal for a wide
range of nonlinear functions.
(2)
Pin Assignments
I2
1
8
I1
VOS2
2
7
VOS1
–VS
3
6
GND
I3 (Output)
4
5
I4
65-4200-07
2
REV. 1.2.1 6/14/01
PRODUCT SPECIFICATION
RC4200
Absolute Maximum Ratings
Parameter
Min.
Max.
1
Unit
Supply Voltage
-22
V
Input Current
-5
mA
Storage Temperature Range
RC4200/4200A
-55
+125
°C
Operating Temperature Range
RC4200/4200A
0
+70
°C
Notes:
1. For a supply voltage greater than -22V, the absolute maximum input voltage is equal to the supply voltage.
2. Observe package thermal characteristics.
Thermal Characteristics
(Still air, soldered into PC board)
8-Lead Plastic DIP
8-Lead SOIC
Maximum Junction Temperature
+125°C
+125˚C
Maximum PD TA < 50°C
468mW
300mW
Thermal Resistance θJC
—
—
Thermal Resistance θJA
160°C/W
240˚C/W
For TA > 50°C Derate at
6.25mW/°C
4.17mW/˚C
Electrical Characteristics
(Over operating temperature range, VS = -15V unless otherwise noted)
4200A
Parameters
Test Conditlons
Total Error as Multiplier
TA = +25°C
Min.
Typ.
Untrimmed1
Versus Temperature
Versus Supply (-9 to -18V)
50µA ≤ I1,2,4 ≤ 250 µA,
TA = +25°C
Input Current Range
(I1, I2 and I4)
Typ.
±2.0
With External Trim
Nonlinearity2
4200
Max. Min.
±3.0
%
±0.2
±0.2
%
±0.005
±0.005
%/°C
±0.1
±0.1
%/V
±0.1
1.0
Max. Units
1000
1.0
±0.3
%
1000
µA
Input Offset Voltage
I1 = I2 = I4 = 150 µA
TA = +25°C
±5.0
±10
mV
Input Bias Current
I1 = I2 = I4 = 150 µA
TA = +25°C
300
500
nA
Average Input Offset
Voltage Drift
I1 = I2 = I4 = 150 µA
±50
Output Current Range (I3)3
REV. 1.2.1 6/14/01
1.0
1000
±100 µV/°C
1.0
1000
µA
3
RC4200
PRODUCT SPECIFICATION
Electrical Characteristics (continued)
(Over operating temperature range, VS = -15V unless otherwise noted)
4200A
Parameters
Test Conditlons
Frequency Response,
-3dB point
Supply Voltage
Supply Current
4200
Min.
Typ.
Max. Min.
Typ.
Max. Units
-18
4.0
-15
-9.0
4.0
-15
-9.0
MHz
V
4.0
mA
-18
4.0
I1 = I2 = I4 = 150 µA
TA = +25°C
Notes:
1. Refer to Figure 6 for example.
2. The input circuits tend to become unstable at I1, I2, I4 < 50 µA and linearity decreases when I1, I2, I4 > 250 µA
(eq. @ I1 = I2 = 500 µA, nonlinearity error ≈ 0.5%).
3. These specifications apply with output (I3) connected to an op amp summing junction. If desired, the output (I3) at pin (4) can
be used to drive a resistive load directly. The resistive load should be less than 700Ω and must be pulled up to a positive
supply such that the voltage on pin (4) stays within a range of 0 to +5V.
Applications Discussion
Current Multiplier/ Divider
Dynamic Range and Stability
The basic design criteria for all circuit configurations using
the RC4200 multiplier is contained in equation (1), that is,
The precision dynamic range for the RC4200 is from +50
µA
to +250 µA inputs for I1, I2 and I4. Stability and accuracy
degrade if this range is exceeded.
I1 I2
I 3 = --------I4
To improve the stability for input currents less than 50 µA,
filter circuits (RSCS) are added to each input (see Figure 2).
The current-product-balance equation restates this as:
I1 I2 = I3 I4
(6)
R1
8
VX
R1
VX
8
+
I1
I1 =
VX
R1
7
VY
I4 =
R2
VY
R2
4
2
3
6
1
I2
CS
A
4
2
3
–VS
I3
–VS
Figure 1. Current Multiplier/Divider
65-4200-02
RS
CS
RC4200
VY
RS
Ammeter
I2
I2 =
VZ
R4
+VZ
I4
7
+VZ
1
+
I1
CS
+
I4
RC4200
R2
RS
R4
5
R4
5
RS = 10k Ohms
CS = 0.005 µF
6
I3
RO
VO
+VS
–
A1
+
–VS
65-4200-03
Figure 2. Current Multiplier/Divider with Filters
Amplifier A1 is used to convert the I3 current to an output
voltage.
Multiplier: Vz = constant ≠ 0
Divider: Vy = constant ≠ 0
4
REV. 1.2.1 6/14/01
PRODUCT SPECIFICATION
RC4200
Voltage Multiplier/Divider
R1
Resistors Ra and Rb extend the range of the VX and VY
inputs by picking values such that:
8
VX
R4
5
VZ
I1
I4
7
V X (max.) V REF
and I 1 (max.) = ------------------------ + -------------- = 250 µA,
Ra
R1
RC4200
R2
1
VY
I2
V Y (min.) V REF
also I 2 (min.) = ----------------------- + -------------- = 50 µA,
R2
Rb
4
2
3
6
I3
VO
RO
–VS
VXVY
V V
= O Z
R 1R 2
R OR 4
V X ( min. ) V REF
I 1 ( min. ) = ------------------------ + -------------- = 50 µA,
R1
Ra
65-4200-04
V Y (max.) V REF
and I 2 (max.) = ------------------------ + -------------- = 250 µA.
Rb
R2
Resistor RC supplies bias current for I3 which allows the
output to go negative.
Figure 3. Voltage Multiplier/Divider
Resistors RCX and RCY permit equation (6) to balance, ie.:
VX VY R0 R4
Solving for V 0 = -------------------------------------VZ
R1 R2
V   V REF
 V 0 V REF V X
 V X V REF  V Y V REF
Y
 -------- + ----------------  -------- + ---------------- =  ------- + ---------------- + ------------- + -------------  ----------------
R   RD 
R
R
R 
R
R  R

 R1
CY
CX
C
b
0
a
2
For a multiplier circuit V Z = V R = cons tan t
V
V V
V V
V V
REF
Y REF
X REF
Y X
------------------ + ------------------------- + ------------------------- + ---------------- =
R R
R R
R R
R R
a b
2 a
1 b
1 2
R0 R4
Therefore: V 0 = V X V Y K where K = --------------------VR R1 R2
2
V
V V
V V
V V
REF
0 REF
X REF
Y REF
------------------------ + ------------------------- + ------------------------- + ---------------R R
R R
R
R
R R
c d
0 d
cx d
CY d
For a divider circuit V Y = V R = cons tan t
VX
VR R0 R4
Therefore: V 0 = -------- K where K = --------------------VZ
R1 R2
Cross-Product Cancellation
Cross-products are a result of ths VXVR and VYVR terms.
To the extend that R1Rb = RCXRD, and R2Ra = RCYRd
cross-product cancellation will occur.
Extended Range
The input and output voltage ranges can be extended to
include 0 and negative voltage signals by adding bias
currents. The RSCS filter circuits are eliminated when the
input and biasing resistors are selected to limit the respective
currents to 50 µA min. and 250 µA max.
Extended Range Multiplier
+VREF
RA
VX
(Input)
RB
RC
8
R1
RD
5
I1
4
2
3
6
VO
(Output)
RO
I3
+VS
–VS
RC4
R0 Rd
where K = ---------------------------V REF R 1 R 2
V X ( min. ) ≤ V X ≤ V X (max.)
1
I2
V 0 V REF
VY VX
---------------- = --------------------- or V 0 = V X V Y K
R0 Rd
R1 R2
Inputs:
RC4200
VY
(Input)
The offset caused by the VREF2 term will cancel to the
extent that RaRb = R0Rd, and the result is:
Resistor Values
I4
7
R2
Arithmetic Offset Cancellation
∆V X = V X (max.) – V X (min.)
V Y ( min. ) ≤ V Y ≤ V Y (max.)
∆V Y = V Y (max.) = V Y (min.)
V REF = Constant (+7V to +18V)
–VS
RCX
65-4200-05
V0
K = ---------------- ( Design Requirements )
VX VY
Figure 4. Extended Range Multiplier
REV. 1.2.1 6/14/01
5
RC4200
PRODUCT SPECIFICATION
∆V X
∆V Y
V REF
R 1 = ----------------- , R 2 = ----------------- , R d = ----------------200µA
200µA
250µA
Multiplying Circuit Offset Adjust
10K ≤ R5 = R9 = R16 ≤ 50K
∆V X V REF
R a = -------------------------------------------------------------------------------250µA∆V X – 200µA V X ( max. )
R7 = R11 = R14, = 100Ω
R6 = R10 = 100Ω (VS/0.05)
∆V X V REF
R b = -------------------------------------------------------------------------------250µA∆V Y – 200µA V Y ( max. )
R15 = 100Ω (VS/0.10)
R8 = R1 | | Ra
R12 = R2 | | Rb
Ra Rb
R1 Rb
R2 Ra
R c = ------------- , R CX = -------------, R cy = ------------Rd
Rd
Rd
R13 = R0 | | RC | | RCX | | RCY
∆V X ∆V Y K
R 0 = ----------------------------160µA
+VREF
Ra
Rb
Rc
R1
VX
(Input)
XOS
+VS
R6
I1
R8
100 Rd
5
R19
R20 ZOS
R17
I4
7
R18
R5
–VS
R7
0.1 µF
–VS
VY
(Input)
8
+VS
Rd
RC4200
R17–R20 can be used to help cancel
crossproduct errors caused by resistor
product mismatch.
1
+VS
R2
I2
2
R9
R10
YOS
R11
–VS
RO
4
R12
0.1 µF 3
6
VO
(Output)
I3
–VS
RCY
–
RCX
RC5534
+
+VS
0.1 µF
R13
R16 VOS
R15
R14
–VS
65-4200-06
Figure 5. Multiplying Circuit Offset Adjust
Procedure
1.
Set all trimmer pots to 0V on the wiper.
3.
2.
Connect VX input to ground. Put in a full scale square
wave on VY input. Adjust XOS(R5) for no square wave
on V0 output (adjust for 0 feedthrough).
Connect VY input to ground. Put in a full scale square
wave on VX input. Adjust YOS(R9) for no square wave
on V0 output (adjust for 0 feedthrough).
4.
Connect VX and VY to ground. Adjust VOS(R16) for 0V
on V0 output.
6
REV. 1.2.1 6/14/01
PRODUCT SPECIFICATION
RC4200
Extended Range Divider
+VREF
+VREF
Ra
R1
VX
(Input)
Rb
Resistor Values
Rd
Rc
R az
Inputs:
8
R4
5
I1
VX(min.) ≤ VX ≤ VX(max.)
VZ
(Output)
I4
7
4
2
6
VO
(Output)
RO
Outputs:
V0 (min.) ≤ V0 ≤ V0 (max.)
∆V0 = V0 (max.) = V0 (min.)
I3
+VS
V0 VZ
K = -------------- ( Design Requirement )
VX
-VS
RC5534
R
VZ(min.) ≤ VZ ≤ VZ(max.)
VREF = Constant (+7V to +18V)
1
I2
∆VX = VX(max.) = VX(min.)
∆VZ = VZ(max.) = VZ(min.)
RC4200
Multiplier
3
Notice that it is necessary to match the above resistor crossproducts to within the amount of error tolerable in the output offset, i.e., with a 10V F.S. output, 0.1% resistor crossproduct match will give 0.1% x 10V. untrimmable output
offset voltage.
-VS
ao
∆V 0
∆V REF
∆V Z
R 0 = ----------------- , R b = ------------------ , R 4 = ----------------750µA
250µA
200µA
65-4200-08
Figure 6. Extended Range Divider
As with the extended range multiplier, resistors Raz and Rao
are added to cancel the cross-product error caused by the
biasing resistors, i.e.
 V 0 V REF  V Z V REF
 V X V 0 V Z V REF  V REF
 -------- + ---------- + ---------- + ----------------  ---------------- =  ------- + ----------------  -------- + ----------------
R 
R R
R   Rb 
 R0
 R 1 R ao R az
D
C
4
a
2
V
V V
V V
V V
REF
Z REF
0 REF
X REF
------------------------- + ------------------------ + ------------------------- + ---------------- =
R R
R R
R R
R R
a b
az b
ao b
1 b
2
V
V V
V V
V V
REF
0 Z
0 REF
Z REF
---------------- + ------------------------ + ------------------------- + ---------------R R
R R
R R
R R
c d
0 4
0 d
4 c
∆V 0 V REF
R c = -----------------------------------------------------------------------------750µA∆V 0 – 700µA V 0 ( max. )
∆V X V REF
R d = ------------------------------------------------------------------------------250µA∆V Z – 200µA V Z ( max. )
Rc Rd
Rc R4
R0 Rd
R a = ------------- , R az = ------------- , R ao = ------------Rb
Rb
Rb
∆V 0 ∆V Z
R 1 = ---------------------600µAK
To cancel cross-product and arithmetic offset:
RaoRb = R0Rd, RazRb = R4Rc and RaRb = RcRd
and the result is:
V0 VZ
VX
V X V REF
---------------------- = -------------- or V 0 = -----------R0 R4
VZ K
R1 Rb
V REF R 0 R 4
where K = ---------------------------R1 Rb
REV. 1.2.1 6/14/01
7
RC4200
PRODUCT SPECIFICATION
Divider Circuit with Offset Adjustment
+VREF
Rb
Ra
R1
VX
(Input)
V X (Offset)
X OS
I1
R8
R6
R5
VZ (Offset)
R11
-VS
1
-VS
0.1 µF
I2
R9
3
0.1 µ F
-VS
RO
4
2
R19
R20
R12
R13 Z OS
RC4200
Multiplier
R21 = Rb
YOS
R18
+VS
R10
7
R7
+VS
I4
VZ
(Input)
R4
5
8
+VS
Rd
Rc
R AX
6
VO
(Output)
I3
-VS
R
ao
0.1 µ F
+VS
R14
R16
R18-R21 can be used in place of R9 to help
cancel gain error due to resistor product
mis-match (See Appendix 1).
R17 V OS
V O (Offset)
R15
-VS
65-1878
General
10K ≤ R5 = R13 = R17 ≤ 50K
R7 + R8 ≈ R1 | | Ra | | Raz | | Rao
R6 ≈ R7 (VS/0.05)
R9 = Rb
R10 ≈ 100 x R4
R11 = 20K
R12 = 100K
R14 + R15 ≈ R0 | | Rc
R16 ≈ R15 (VS/0.10)
Example: Two-Quad Divider
V0 = K(VX/VZ), K = k, VREF = +VS = +15V
-10 ≤ VX ≤ +10, therefore ∆VX = 20
0 ≤ VZ ≤ +10, therefore ∆VZ = 20
-10 ≤ V0 ≤ +10, therefore ∆V0 = 20
R0 = 26.7K
R1 = 333K
Rb = 60K
R5, R13, R17 = 10K
R4 = 50K
R7, R15 = 1K
Rc = 37.5K
R8, R11 = 20K
Rd = 300K
R6, R9, R16 = 300K
Ra = 187.5K
R10 = 4.7M
Raz = 31.25
R12 = 100K
Rao = 133K
Figure 7. Divider Circuit with Offset Adjustment
8
REV. 1.2.1 6/14/01
PRODUCT SPECIFICATION
RC4200
Divider Circuit Offset Adjustment Procedure
1.
Set each trimmer pot to 0V on the wiper.
2.
Connect VX (input) to ground. Put a DC voltage of
approximatey 1/2 VZ (max.) DC on the VZ (input) with
an AC (squarewave is easiest) voltage of 1/2 VZ (max.)
peak-to-peak superimposed on it. Adjust XOS (R5) for
zero feedthrough. (No AC at V0)
Square Root Circuit V0 = N√VX
+V REF
Ra
Rc
Rb
R1
8
VX
(Input)
R4
5
I1
V z (Max.)
Rd
I4
7
RC4200
Multiplier
1/2 V z (Max.)
1
1/2 Vz (Max.)
I2
4
2
0V
3
3.
6
RO
I3
+VS
-VS
Connect VX (input) to VZ (input) and put in the
1/2 VZ(max.) DC with an AC of approximately 20 mV
less than VZ(max.).
R ao
-VS
Adjust ZOS (R13) for zero feedthrough.
65-1877
Figure 8.
V z (Max.)
2V V
2
V V
V 2 V V
V
V
V V
0 REF
0 REF
0
0 REF
REF
REF
X REF
------------------------- + ---------------- + ------------------------ = -------------- + ------------------------ + ------------------------ + ---------------R R
R R
R R
R R
R R
R R
R R
c 4
0 4
ao b
a b
c d
1 b
0 d
1/2 Vz (Max.)
0V
If R R = R R and R R R R + R R R R = R R R R
a b
c d
ao b 0 d
ao b c 4
c d 0 4
~
~ 10 mV
65-1868
4.
5.
V
R R
V V
V 2
REF 0 4
X REF
0
Then -------------- = ------------------------- or V 2= V K where K = ------------------------------0
X
R R
R R
R R
1 b
1 b
0 4
Return VX (Input) to ground and connect VZ(max.)
DC on VZ(input). Adjust output VOS(R17) for VO =
0VO
and V
Connect VX (input) to VZ (input) and and in VZ (max.)
DC. (The output will equal K.) Decrease the input
slowly until the output (V0 - K) deviates beyond the
desired accuracy. Adjust ZOS to bring it back into tolerance and return to Step 4. Continue steps 4 and 5 until
VZ reduces to the lowest value desired.
V
0
N = ------------- ( Design Requirements )
V
X
Notice that as the input to VX and VZ gets closer to zero (an
illegal state) the system noise will predominate so much that
an integrating voltmeter will be very helpful.
0
0≤V
R
1
X
= N V
X
where N =
K
≤ V ( max. )and V ( max. ) = N V ( max. )
X
0
X
V ( max. ) 2
0
= ---------------------------2
74µA N
V
REF
R = R = ---------------a
d
50µA
R
b
R
R
R
REV. 1.2.1 6/14/01
VO
(Output)
4
V
REF
= R = ----------------c
150µA
V ( max. )
0
= -----------------------50µA
ao
0
V ( max. )
0
= -----------------------125µA
V ( max. )
0
= -----------------------225µA
9
RC4200
PRODUCT SPECIFICATION
Square Root Circuit Offset Adjust
+V REF
R1
8
VX
(Input)
XOS
R8
7
R5
R4
5
I4
I1
+VS
R6
Rd
Rc
Rb
Ra
RC4200
Multiplier
R7
+VS
1
-VS
0.1 µ F
R17 = Rb
YOS
R14
I2
2
R15
R16
R9
RO
4
3
0.1 µ F
-VS
6
VO
(Output)
+VS
I3
-VS
R
0.1 µF
ao
-VS
+VS
R10
R12
R14-R17 can be used in place of R9 to help
reduce linearity error due to resistor product
mis-match (See Appendix 1).
R13 V OS
R11
-VS
65-1876
Figure 9. Square Root Circuit Offset Adjust
10K ≤ R 5 = R 13 ≤ 50K
R 7 = 100Ω
VS
R 6 = R 7 ---------0.05
R 8 = R 1 || R a || R ao
Procedure
1.
Set both trimmer pots to 0V on the wiper.
2.
Put in a full scale (0 to VX(max.) squarewave on VX
input. Adjust XOS(R5) for proper peak-to-peak amplitude on V0 output. (Scaling adjust)
3.
Connect VX input to ground. Adjust VOS(R13) for 0V
on V0 output.
R9 = Rb
R 10 = R 0 || R C
R 11 = 100Ω
VS
R 12 = R 11 ------0.1
10
REV. 1.2.1 6/14/01
PRODUCT SPECIFICATION
RC4200
Squaring Circuits V0 = K VX2
+V REF
Ra
Rb
R1
8
VX
(Input)
Rd
Rc
5
I1
I4
7
RC4200
Multiplier
R1
1
I2
RO
4
2
3
6
VO
(Output)
I3
+VS
-VS
RCX
RC5534
-VS
65-1875
Figure 10. Squaring Circuit
V X2 2V X V REF V REF 2 V 0 V REF V REF 2 V X V REF
-------- + ------------------------- + -------------- = --------------------- + -------------- + ---------------------R1 Ra
R0 Rd
Rc Rd
Rc Rd
R1 2
R a2
if R a2 = R c R d and R 1 R a = 2R CX R D
V X2
R0 Rd
V 0 V REF
then --------------------- = --------2 or V 0 = KV X2 where K = ---------------------2
R0 Rd
R1
V REF R 1
VX(min.) ≤ VX ≤ VX(max.)
∆VX = VX(max.) – VX(min.)
V0
K = --------2 (Design Requirement)
VX
∆V X
R 1 = ----------------200µA
∆V X V REF
R a = -------------------------------------------------------------------------------250µA∆V X – 200µA V X ( max. )
V REF
R d = ----------------250µA
R a2
R c = -----Rd
R1 Ra
R cx = ------------2R d
∆VX 2 K
R 0 = ------------------160µA
REV. 1.2.1 6/14/01
11
RC4200
PRODUCT SPECIFICATION
Squaring Circuits Offset Adjust
+VREF
Ra
VX
(Input)
Rb
R1
8
I1
R5
R1
R7 =
100 Rd
5
I4
7
I2
2
3
-VS
RO
4
0.1 µ F
R10 Z OS
R7-R10 can be used to cancel all
linearity errors caused by input
offsets and resistor product
mis-match (See Appendix 1).
1
R6
R9
R8
RC4200
Multiplier
0.1 µF
+VS
Rd
Rc
VO (Output)
I3
6
-VS
R CX
+VS
+VS
R14
R16
VOS R13
-VS
-VS
R15
0.1 µ F
65-1874
Figure 11. Squaring Circuit Offset Adjust
10K ≤ R 10 = R 11 ≤ 50K
R 8 , R 15 = 100Ω
R 9 , R 14
VS
= 100Ω ------0.1
R 5 , R 6 = R 1 || R a
Procedure
1.
Set both trimmer pots to 0V on the wiper.
2.
Put in a full scale (±VX) squarewave on VX input.
Adjust ZOS(R10) for uniform output.
3.
Connect VX input to ground. Adjust VOS(R11) for 0V
on V0 outputs.
R 16 = R 0 || R c || R a
12
REV. 1.2.1 6/14/01
PRODUCT SPECIFICATION
RC4200
Appendix 1—System Errors
Errors Caused by Input Offsets
There are four types of accuracy errors which affect overall
system performance. They are:
V0 =
• Nonimearity—Incremental deviation from absolute
accuracy. See Note 1.
• Scaling Error—Linear deviation from absolute accuracy.
• Output Offset—Constant deviation from absolute
accuracy.
• Feedthrough.—Cross-product errors caused by input
offsets and external circuit limitations. See Note 2.
This nonlinearity error in the transfer function of the
RC4200 is ±0.1% maximum (±0.03 maximum for the
RC4200A). That is,
1
R0R4 VXVY
±
V V
± VXVOSY ± V0VOSZ ± VOSXVOSY
VZ
VZ Y OSX
R0R4
VY Feedthrough
VX Feedthrough
Scaling Error
Output Offset Error
System errors can be greatly reduced by externally trimming
the input offset voltages of the RC4200. (±3.0% F.S. for
RC4200 and ±0.1% for RC4200A.)
+VS
I1 I2
I 3 = --------- ± 0.1% F.S. ( 4 )
I4
VX
R1
8
R4
R1
7
100 R4
ZOS
RC4200
Multiplier
-VS
+VS
VY
R2
1
-VS
R2
4
RO
VO
2
VX VY R0 R4
V 0 = ---------------- ------------- ± 3.0% F.S. ( 3 ) ( 4 )
VZ R1 R2
VZ
+VS
X OS
The other system errors are caused by voltage offsets on the
inputs of the RC4200 and can be as high as ±3.0% (±2.0%
for RC4200A).
5
3
6
-VS
-VS
Ideal Op-Amp
V OS = 0
R1
R4
5
8
VX
I1
65-1870
VZ
I4
If XOS = XOSX, YOS = YOSY, ZOS = -VOSZ,
7
RC4200
Multiplier
R2
VX VY R0 R4
(3)
then V O ---------------- ------------- ±0.3% F.S.
VZ R1 R2
1
VY
I2
4
2
3
6
I3
RO
VO
+VS
Extended Range Circuit Errors
-VS
Ideal Op-Amp
V OS = 0
65-1871
Figure 12.
Notes:
1. The input circuits tend to become unstable at
I1, I2, I4 < 50 µA and linearity decreases when I1, I2, I4 >
250 µA (e.g., @ I1 = I2 = 500µA nonlinearity error ≈ 0.5%).
2. This section will not deal with feedthrough which is
proportional to frequency of operation and caused by stray
capacitance and/or bandwidth limitations. (refer to
Figure 12.)
3. Not including resistor tolerance or output offset on the
operational amplifier.
4. For 50 µA ≤ I1, I2, I4 ≤ 250 µA.
REV. 1.2.1 6/14/01
Figure 13. RC4200 with Input Offset Adjustment
The extended range configurations have a disadvantage in
that additional accuracy errors may be introduced by resistor
product mismatching.
Multiplier
An error in resistor product matching will cause an
equivalent feedthrough or output offset error. See Figure 6.
R1Rb = RCXRd ±α, VX feedthrough (VY = 0) = IαVX
R2Ra = RCYRd ±β, VY feedthrough (VX = 0) = ±βVY
RaRb = RCRd ±γ, V0 offset (VX = VY = 0) = ±γVREF*
Note:
* Output offset errors can always be trimmed out with the
output op amp offset adjust, VOS (R16).
13
RC4200
Reducing Mismatch Errors
You need not use 0.01% resistors to reduce resistor product
mismatch errors. Here are a couple of ways to obtain
maximum accuracy out of the extended range multiplier
(see Figure 4) using 1% resistors.
Method 1
VX feedthrough, for example, occurs when VY = 0 and
VOSY ≠ 0. This VX feedthrough will equal ±VXVOSY.
Also, if VOSZ ≠ 0, there is a VX feedthrough equal to
VXVOSZ. A resistor-product error of α will cause a VX
feedthrough of ±αVX. Likewise, VY feedthrough errors are:
±VYVOSX, ±VYVOSZ and ±βVY
Total feedthrough:
±VXVOSY ±VYVOSX ±αVX ±βVY ±(VX + VY) VOSZ
By carefully abusing XOS(R5), YOS(R9) and ZOS(R20) this
equation can be made to very nearly equal zero and the
feedthrough error will practically disappear.
A residual of set will probably remain which can be trimmed
outwith VOS(R16) at the output of amp.
Method 2
Notice that the ratios of R1Rb:RCXRd and R2Ra:RCYRd are
both dependent of Rd also that R1, R2, Ra and Rb are all
functions of the maximum input requirements. By designing
a multiplier for the same input ranges on both VX and VY
then R1 = R2, RCX = RCY and Ra = Rb. (Note: it is acceptable to design a four quadrant multiplier and use only two
quadrants of it.)
14
PRODUCT SPECIFICATION
Select Rd to be 1% or 2% below (or above) the calculated
value. This will cause α and β to both be positive (or negative) by nearly the same amount. Now the effective value of
Rd can be trimmed with an offset adjustment ZOS(R20) on
pin 5.
This technique causes: a slight gain error which can be compensated with the R0 value, and an output of offset error that
can be trimmed with VOS(R16) on the output op amp.
Extended Range Divider
The only cross-product error of interest is the VZ
feedthrough (VX = 0 and VOSX ≠ 0) which is easily adjusted
with XOS(R5). See Figure 6.
Resistor product mismatch will cause scaling errors (gain)
that could be a problem for very low values of VZ. Adjustments to YOS(R18) can be made to improve the high gain
accuracy.
Square Root and Squaring
These circuits are functions of single variables so
feedthrough, as such, is not a consideration. Cross product
errors will effect incremental accuracy that can be corrected
YOS(R14) or ZOS(R10). See Figure 9 and Figure 11.
REV. 1.2.1 6/14/01
PRODUCT SPECIFICATION
RC4200
Appendix 2—Applications
Therefore, the rms value of Asinωt becomes:
Design Considerations for RMS-to-DC Circuits
A
V rms = ------2
Average Value
Consider Vin = Asinωτ. By definition,
V AG =
RMS Value for Rectified Sine Waves
Consider Vin = |A sin ωt|, a rectified wave. To solve,
T
--2
integrate of each half cycle.
∫0 VIN dt
1
2
i.e. --- TV in dt =
T 0
∫
Where T = Period
ω = 2πf
1
--T
2π
= -----T
VIN
T
--- 2
2A sin 2 ωt
∫0
T
dt+
∫T--- ( –Asinωt ) dt
2
2
1
2
2
This is the same as --- TA sin ωt dt
1
∫0
A
so, |Asinωt| rms = Asinωt rms
t
0
2
V AG = --T
T
2
T
65-1873
T
--2
∫0 A sin ωt dt
2A 1
= ------- – ---- cos ωt
T ω
Practical Consideration: |Asinωt| has high-order harmonics;
Asinωt does not. Therefore, non-ideal integrators may cause
different errors for two approaches.
(a)
VIN
T
--2
(b)
0
VIN
Low Pass
Filter
a2
V O = VIN rms
2
VIN
Absolute
Value
VIN
VO
a2
b
Low Pass
Filter
2A
= ------- [ – cos ( π ) + cos ( 0 ) ]
2π
A VG V IN2
65-4200-09
2
Average Value of Asinωt is --- A
π
Figure 14.
2
RMS Value
V IN
Avg ---------V0
Again, consider VIN = Asinωt
V rms =
VO =
1
--T
V AVG =
T
∫0 [ VIN ]2 dt
implies V 0 =
= V0
Avg ( VIN
V rms for Asinωtdt:
T
V0 =
V rms =
1
--T
V rms =
A
-----T
V rms =
A T 1
------ --- – ------- sin2 ωt
2 2 4ω
V rms =
A T
------ --2 2
V rms =
A
-----2
Avg VIN
2
)
2
∫0 A sin ωt dt
2 T
∫0
2
2
1 1
--- – --- cos 2 cos 2 ωt dt
2 2
2
T
0
2
2
REV. 1.2.1 6/14/01
15
RC4200
PRODUCT SPECIFICATION
+V REF
100K
100K
VIN
100K
60K
167K
8
300K
100K
8
5
300K
100K
200K
5
13.3K
7
RC4200A
Multiplier
50K
100K
7
22 µ F
10K
X2
1
RC4200A
Multiplier
X
1
50K
250K*
4
60K
2
44.4K**
4
VOUT
2
3
3
6
6
1/2
RC5532
-VS
-VS
83.3K
0.1 µF
1/2
RC5532
0.1 µF
80K
45.5 K
30K
+VS
15K
+VS
30K
10K
10K
100
-VS
*Determines sacle factor (K) for X 2 function.
**Determines sacle factor (K) for X function.
100
-VS
65-1869
+Vs = +VREF = +15V
-Vs = -15V
Figure 15. RMS to DC Converter VOUT=√VIN2
Amplitude Modulator with A.G.C.
In many AC modulator applications, unwanted output
modulation is caused by variations in carrier input amplitude. The versatility of the RC4200 multiplier can be utilizes
to eliminate this undesired fluctuation. The extended range
multiplier circuit (Figure 4) shows an output amplitude
inversely proportional to the reference voltage VREF.
VX VY R0 Rd
i.e., V 0 = ---------------- ------------V REF R 1 R 2
By making VREF proportional to VY (where VY is the carrier input) such that:
V REF = V H =
∫ ( VY )
Then the denominator becomes a variable value that automatically provides constant gain, such that the modulating
input (VX) modulates the carrier (VY) with a fixed scale
factor even though the carrier varies in amplitude.
16
If VH is made proportional to the average value of Asinωt
(i.e., 2A/π) and scaled by a value of π/2 then:
VH=A
and if: VX = Modulating input (VM)
and: VY Carrier input (Asinωt)
R0 Rd
Then: V0 = K VM sinωt where K = ------------R1 R2
The resistor scaling is determined by the dynamic range of
the carrier variation and modulating input.
The resistor values are solved, as with the other extended
range circuits, in terms of the input voltages.
Input voltages:
Modulation voltage (VM): 0 ≤ VM ≤ VX(max.)
Carrier (VY): VY = Asinωt
Carrier amplitude fluctuation (∆A):
A(min.) sint ≤ VY ≤ A(max.) sinΩωt
Dynamic Range (N): A(max.)/A(min.),
A(max.) = VH(max.) and A(min.) = VH(min.)
REV. 1.2.1 6/14/01
PRODUCT SPECIFICATION
RC4200
Ra
Ra
R1
VM
+VS
5
8
R1 Ra
30K
Ra
7
Ra
10K
100
0.1 µF
-VS
VY =
A SIN ω t
R2
+V S
RO
RC4200
Multiplier
1
R2 Ra
30K
2
4
10K
0.1 µF
100
3
1/4
RC4156
6
-VS
-VS
0.1 µ F
R1
VO =
VM sin ω t
+VS
R*
R2
10K
R3
30K
30K
C1
470
-VS
1/2 R3
15K
R3
30K
R3
30K
1N914
1/4
RC4156
p R3 47K
2
1/4
RC4156
VH = p AVG A sin ω t = A
2
*R1
R2
1N914
Ra
RO
65-1866
Figure 16. Amplitude Modulator with A.G.C.
The maximum and minimum values for I1 and I2 lead to:
V X ( max. ) V H ( max. )
I 1 (max.) = ------------------------- + ------------------------- = 250µA
R1
Ra
Example 1
VY = Asinωt 2.5V ≤ A ≤ 10V, therefore N = 4
0V ≤ VM ≤ 10V, therefore VX(max.) = 10V
K = 1, therefore V0 = VM sinωt
V H ( min. )
I 1 (min.) = ------------------------ = 50µA V M( min. ) = 0
Ra
V X (max.)
10V
R 1 = ------------------------ = -------------- = 200K
50µA
50µA
A ( max. ) V H ( max. )
I 2 (max.) = --------------------- + ------------------------- = 250µA
R2
Ra
A(max.)
10V
R 1 = -------------------- = -------------- = 200K
50µA
50µA
V H ( min. )
I 2 (min.) = ------------------------ = 50µA
Ra
For a dynamic range of N, where
A ( max. )
N = --------------------- < 5,
A ( min. )
These equations combine to yield:
V X (max.)
A(max.)
R 1 = --------------------------------- , R2 --------------------------------- ,
( 5 – N )50µA
( 5 – N )50µA
R1 R2
A(min.)
R a = ------------------- and R O = K -------------,
50µA
Ra
REV. 1.2.1 6/14/01
A(min.)
2.5V
R a = ------------------- = -------------- = 50K
50µA
50µA
R1 R2
200K × 200K
R O = K ------------- = 1 --------------------------------- = 800K
Ra
50K
Example 2
VY = Asinωt 3 ≤ A ≤ 6, therefore N = 2
0V ≤ VM ≤ 8V, therefore VX(max.) = 8V
K = 0.2, therefore V0 = 0.2 VM sinwt
so:
R1 = 53.3K, R2 = 40K
Ra = 60K and R0 = 7.11K
17
RC4200
PRODUCT SPECIFICATION
Inputs
VZ
R1
VX
I4
VOS1
7
R2
1
VY
I2
Rs
VOS2
100
-VS
50 mV
Gain
Adj.
4
Cs
+VS
RO
0.1 µF
100
I3
2
0.1 µ F
3
-VS
Where K =
VOS3
0.1 µF
6
+VS
RO
100 µV
-VS
VX VY
K
Vz
65-1867
R O R4
R1 R2
Limited Range, First Quadrant Applications
Thermal Symmetry
The following circuit has the advantage that cross-product
errors are due only to input offsets and nonlinearity error is
sightly error is slightly less for lower input currents.
The circuit also has no standby current to add to the noise
content, although the signal-to-noise ratio worsens at very
low input currents (1-5 µA) due to the noise current of the
input stages.
The RSCS filter circuits are added to each input to improve
the stability for input currents below 50 µA.
Caution!
The bandpass drops off significantly for lower currents
(<50 µA) and non-symmetrical rise and fall times can cause
second harmonic distortion.
18
Output
VO
1/4
4156
RS = 10K, C S = 0.005 µF
Vs =
-VS
50 mV
RC4200
Multiplier
R1
50 mV
100 R4
5
Cs
+VS
+VS
R4
I1
Rs
-VS
VOS4 ADJ
8
Thermal
Symmetry
Line
I2
1
8
I1
VOS2
2
7
VOS1
–VS
3
6
GND
Output I3
4
5
I4
65-0070
The scale factor is sensitive to temperature gradients across
the chip in the lateral direction. Where possible, the package
should be oriented such that forces generating temperature
gradients are located physically on the line of thermal symmetry. This will minimize scale-factor error due to thermal
gradients.
REV. 1.2.1 6/14/01
PRODUCT SPECIFICATION
250 µA dc
5
Vz
+1
4200
1
4
2
3
* Peak to Peak
250 µA dc
Vo
6
-1
-3
-5
-7
65-1863
VY
+3
200 µA ac* 8
150 µA dc
7
Relative Output (dB)
Vx
RC4200
-9
-15V
-11
10
10
2
10
3
10
4
10
5
10
6
10
7
Frequency (Hz)
5
8
250 µA dc
+3
Vz
7
VY
200 µA ac* 1
4200
150 µA dc
4
2
3
Vo
6
-15V
* Peak to Peak
+1
-1
-3
-5
-7
65-1864
250 µA dc
Relative Output (dB)
Vx
-9
-11
10
10
2
10
3
10
4
10
5
10
6
10
7
Frequency (Hz)
5 83.4 µA ac*
167 µA dc
8
+3
Vz
7
VY
250 µA dc
4200
1
4
2
3
* Peak to Peak
-15V
6
Vo
+1
-1
-3
-5
-7
65-1865
250 µA dc
Relative Output (dB)
Vx
-9
-11
10
10
2
10
3
10
4
10
5
10
6
10
7
Frequency (Hz)
Figure 18. Outputs
REV. 1.2.1 6/14/01
19
RC4200
PRODUCT SPECIFICATION
300
3
4
200
I4 ( µA)
4 nA
150
3 nA
2.5 nA
2 nA
100
1.0 nA
50
50
1.2 nA
100
150
150
A
5n
A
6n
A
7n
A
9n
A
11 n
A
15 n
100
1.5 nA
250
300
200
nA
25 nA
50
50
150
100
I2 ( µA)
200
65-1862
200
65-1861
I1 ( µA)
5 nA
2n
A
250
nA
250
250
I1 ( µA)
Figure 19a. Output Noise Current (I3)
vs. Input Currents (I1, I2) for I4 = 250µA
Figure 19b. Output Noise Current (I3)
vs. Input Currents (I4, I1) for I2 = 250µA
Multiplier Configuration
V V
Vo = X Y
10
200
150
VY = 0
VX = 10 sin ω t
100
50
VX = 0
VY = 10 sin ω t
0
1.0
10
100
1K
10K
100K
65-1860
AC Feedthrough (mVP-P)
250
1M
Frequency (Hz)
Figure 20. AC Feedthrough vs. Frequency
20
REV. 1.2.1 6/14/01
PRODUCT SPECIFICATION
RC4200
Mechanical Dimensions
8-Lead SOIC Package
Inches
Symbol
Millimeters
Min.
Max.
Min.
Max.
A
A1
B
C
D
.053
.004
.013
.008
.189
.069
.010
1.35
0.10
0.33
0.20
4.80
1.75
0.25
E
e
H
h
L
N
α
ccc
.150
.158
.050 BSC
3.81
4.01
1.27 BSC
.228
.010
.016
5.79
0.25
0.40
.020
.010
.197
.244
.020
.050
8
0.51
0.25
5.00
6.20
0.50
1.27
8
0°
8°
0°
8°
—
.004
—
0.10
8
Notes:
Notes
1. Dimensioning and tolerancing per ANSI Y14.5M-1982.
2. "D" and "E" do not include mold flash. Mold flash or
protrusions shall not exceed .010 inch (0.25mm).
3. "L" is the length of terminal for soldering to a substrate.
4. Terminal numbers are shown for reference only.
5
2
2
5. "C" dimension does not include solder finish thickness.
6. Symbol "N" is the maximum number of terminals.
3
6
5
E
1
H
4
h x 45°
D
C
A1
A
SEATING
PLANE
e
B
REV. 1.2.1 6/14/01
–C–
LEAD COPLANARITY
α
L
ccc C
21
RC4200
PRODUCT SPECIFICATION
Mechanical Dimensions (continued)
8-Lead Plastic DIP Package
Inches
Symbol
Millimeters
Min.
Max.
Min.
Max.
A
A1
—
.015
.210
—
—
.38
5.33
—
A2
B
B1
C
D
.115
.014
.045
.008
.348
.005
.300
.240
.195
.022
.070
.015
.430
—
.325
.280
2.93
.36
1.14
.20
8.84
.13
7.62
6.10
4.95
.56
1.78
.38
10.92
—
8.26
7.11
D1
E
E1
e
eB
L
.100 BSC
—
.430
.115
.160
2.54 BSC
—
10.92
2.92
4.06
8°
8°
N
Notes:
Notes
1. Dimensioning and tolerancing per ANSI Y14.5M-1982.
2. "D" and "E1" do not include mold flashing. Mold flash or protrusions
shall not exceed .010 inch (0.25mm).
3. Terminal numbers are for reference only.
4. "C" dimension does not include solder finish thickness.
5. Symbol "N" is the maximum number of terminals.
4
2
2
5
D
4
1
5
8
E1
D1
E
e
A2
A
A1
C
L
B1
22
B
eB
REV. 1.2.1 6/14/01
RC4200
PRODUCT SPECIFICATION
Ordering Information
Part Number
Package
Operating Temperature Range
RC4200N
8-Lead Plastic DIP
0°C to +70°C
RC4200AN
8-Lead Plastic DIP
0°C to +70°C
RC4200M
8-Lead SOIC
0°C to +70°C
RC4200AM
8-Lead SOIC
0°C to +70°C
DISCLAIMER
FAIRCHILD SEMICONDUCTOR RESERVES THE RIGHT TO MAKE CHANGES WITHOUT FURTHER NOTICE TO
ANY PRODUCTS HEREIN TO IMPROVE RELIABILITY, FUNCTION OR DESIGN. FAIRCHILD DOES NOT ASSUME
ANY LIABILITY ARISING OUT OF THE APPLICATION OR USE OF ANY PRODUCT OR CIRCUIT DESCRIBED HEREIN;
NEITHER DOES IT CONVEY ANY LICENSE UNDER ITS PATENT RIGHTS, NOR THE RIGHTS OF OTHERS.
LIFE SUPPORT POLICY
FAIRCHILD’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES
OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD SEMICONDUCTOR
CORPORATION. As used herein:
1. Life support devices or systems are devices or systems
which, (a) are intended for surgical implant into the body,
or (b) support or sustain life, and (c) whose failure to
perform when properly used in accordance with
instructions for use provided in the labeling, can be
reasonably expected to result in a significant injury of the
user.
2. A critical component in any component of a life support
device or system whose failure to perform can be
reasonably expected to cause the failure of the life support
device or system, or to affect its safety or effectiveness.
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© 2001 Fairchild Semiconductor Corporation