AUGUST 1997
INSTRUCTION MANUAL
40-226A
REL 356
VERSION 1.00
NUMERICAL CURRENT DIFFERENTIAL
LINE PROTECTION SYSTEM
ABB POWER T&D COMPANY INC.
POWER AUTOMATION AND PROTECTION DIVISION
4300 CORAL RIDGE DRIVE
CORAL SPRINGS, FL 33065
Version 1.00
I.L. 40-226
REL 356 REVISION NOTICE
DATE
REV. LEVEL
8/97
RELEASE
8/97
A
PAGES REMOVED
14, 15, 27, 51, 53, 54, 56,
57, 59, 66, 161, 162, 175,
183
PAGES INSERTED
14, 15, 27, 51, 53, 54, 56, 57,
59, 66, 161, 162, 175, 183
CHANGE SUMMARY:
A CHANGE BAR ( ) LOCATED IN THE MARGIN REPRESENTS A
TECHNICAL CHANGE TO THE PRODUCT.
A STAR (*) LOCATED BY THE SUB NUMBER OR FIGURE NUMBER
REPRESENTS A TECHNICAL CHANGE TO
THE DRAWING.
REL 356
Version 1.00
Instruction Manual 40-226
!
CAUTION
It is recommended that the user of REL 356 equipment become acquainted with the information in this instruction manual before energizing the
system. Failure to do so may result in injury to personnel or damage to the
equipment, and may affect the equipment warranty. If the REL 356 relay system is mounted in a cabinet, the cabinet must be bolted to the floor, or otherwise secured before REL 356 installation, to prevent the system from tipping
over.
All integrated circuits used on the modules are sensitive to and can be
damaged by the discharge of static electricity. Electrostatic discharge precautions should be observed when handling modules or individual components.
ABB does not assume liability arising out of the application or use of
any product or circuit described herein. ABB reserves the right to make changes to any products herein to improve reliability, function or design. Specifications and information herein are subject to change without notice. All possible
contingencies which may arise during installation, operation, or maintenance,
and all details and variations of this equipment do not purport to be covered by
these instructions. If further information is desired by purchaser regarding a
particular installation, operation or maintenance of equipment, the local ABB
representative should be contacted.
© Copyright
ABB Power T&D Company Inc.
Published 1994, 1995, 1996,
1997
All Rights reserved
ABB does not convey any
license under its patent rights
nor the rights of others.
i
REL 356
Instruction Manual 40-226
Version 1.00
Equipment Identification
The REL 356 equipment is identified by the Catalog Number on the
REL 356 chassis nameplate. The Catalog Number can be decoded by using Catalog Number Table 3-1 (see Section 3, page 35).
Production Changes
When engineering and production changes are made to the REL 356
equipment, a revision notation (Sub #) is reflected on the appropriate schematic diagram, and associated parts information. A summary of all Sub #s
for the particular release is shown below.
Equipment Repair
Repair work is done most satisfactorily at the factory. When returning
equipment, carefully pack modules and other units, etc. All equipment
should be returned in the original packing containers if possible. Any damage due to improperly packed items will be charged to the customer.
Document Overview
Section 1 (page 1) provides the Product Description, which includes software functions. Section 2 (page 9) provides Specifications and External
Connections. Section 3 (page 13) presents applications with related Catalog Numbers for ordering purposes. REL 356 Installation, Operation and
Maintenance are described in Section 4 (page 37) with related Setting Calculations in Section 5 (page 61). Appendices A thru K (beginning on page
81) include related module circuit descriptions. Acceptance Tests are described in Appendix L. Oscillographic Data Definitions are defined in Appendix M and System Diagrams are included at the back of the book.
Contents of Relay System
The REL 356 Relay System includes the style numbers, listed below, for
each module. Addenda pages may be included (representing future revisions).
Module Style
•
•
•
•
Backplane - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - 1611C26
Microprocessor - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - 1611C22
(Sub-Backplane Xfmr)- - - - - - - - - - - - - - - - - - - - - - - - - - - - - 1502B28
Display - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - 1609C01
• Interconnect - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - 1611C25
• Power Supply- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - 1611C24
• Relay Output - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - 1611C27
• Analog Input - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - 1611C23
• Contact Input - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - 1611C28
• Modem - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - 1612C01
• CODEC - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - 1615C33
• Digital Comm. Interface- - - - - - - - - - - - - - - - - - - - - - - - - - - - 1615C43
REL 356
ii
TABLE OF CONTENTS
PART I:
BASICS
1
2
3
4
PRODUCT DESCRIPTION
. . . . . . . . . . . . . . . . . . . .1
1.1
INTRODUCTION . . . . . . . . . . . . . . . . . . . . . .1
1.2
REL 356 CONSTRUCTION
1.3
REL 356 MODULES . . . . . . . . . . . . . . . . . . . . .1
1.4
SELF-CHECKING SOFTWARE . . . . . . . . . . . . . . . .5
1.5
UNIQUE REMOTE COMMUNICATION . . . . . . . . . . . .6
. . . . . . . . . . . . . . . . .1
SPECIFICATIONS . . . . . . . . . . . . . . . . . . . . . . . .9
2.1
TECHNICAL . . . . . . . . . . . . . . . . . . . . . . . .9
2.2
EXTERNAL CONNECTIONS . . . . . . . . . . . . . . . . 10
2.3
CONTACT DATA . . . . . . . . . . . . . . . . . . . . . 10
2.4
9600 bps AUDIO TONE COMMUNICATION CHANNEL . . . . 10
2.5
56/64 kbs DIGITAL COMMUNICAITON . . . . . . . . . . . 10
2.6
Optional G.703 Interface . . . . . . . . . . . . . . . . . . 11
2.7
OPTIONAL COMPUTER/NETWORK INTERFACE . . . . . . 11
2.8
CHASSIS DIMENSIONS AND WEIGHT . . . . . . . . . . . 11
2.9
ENVIRONMENTAL DATA . . . . . . . . . . . . . . . . . 11
APPLICATIONS AND ORDERING INFORMATION . . . . . . . . 13
3.1
INTRODUCITON . . . . . . . . . . . . . . . . . . . . . 13
3.2
CURRENT DIFFERENTIAL LOGIC . . . . . . . . . . . . . 13
3.3
RECLOSE INITIATE LOGIC . . . . . . . . . . . . . . . . 15
3.4
RELAY FUNCTIONS
3.5
OPTIONAL BACK-UP . . . . . . . . . . . . . . . . . . . 18
. . . . . . . . . . . . . . . . . . . 16
INSTALLATION, OPERATION AND MAINTENANCE . . . . . . . 37
4.1
SEPARATING THE INNER AND
OUTERCHASSIS . . . . . . . . . . . . . . . . . . . . . 37
4.2
TEST PLUGS AND FT-14 SWTICHES. . . . . . . . . . . . 37
4.3
EXTERNAL WIRING. . . . . . . . . . . . . . . . . . . . 37
4.4
REL 356 FRONT PANEL DISPLAY . . . . . . . . . . . . . 38
4.5
FRONT PANEL OPERATION. . . . . . . . . . . . . . . . 38
4.6
JUMPER CONTROL. . . . . . . . . . . . . . . . . . . . 44
4.7
NETWORK INTERFACE
4.8
OSCILLOGRAPHIC DATA . . . . . . . . . . . . . . . . . 45
4.9
REL 356 SETTINGS . . . . . . . . . . . . . . . . . . . . 46
. . . . . . . . . . . . . . . . . 45
4.10 MONITORING FUNCTIONS . . . . . . . . . . . . . . . . 46
4.11 TARGET (FAULT DATA) INFORMATION . . . . . . . . . . 46
4.12 COMMUNICATION CHANNEL TESTING . . . . . . . . . . 46
4.13 ROUTINE VISUAL INSPECTION . . . . . . . . . . . . . . 47
iii
REL 356
TABLE OF CONTENTS (Continued)
4.14 ACCEPTANCE TESTING . . . . . . . . . . . . . . . . . .47
4.15 NORMAL PRECAUTIONS . . . . . . . . . . . . . . . . . .48
4.16 DISASSEMBLY PROCEDURES . . . . . . . . . . . . . . .48
5
PART II:
PART III:
SETTING CALCULATIONS . . . . . . . . . . . . . . . . . . . .61
5.1
INTRODUCTION . . . . . . . . . . . . . . . . . . . . . .61
5.2
RELAY SYSTEM SETUP . . . . . . . . . . . . . . . . . .61
5.3
OSCILLOGRAPHIC INFORMATION . . . . . . . . . . . . .62
5.4
CURRENT DIFFERENTIAL - LOGIC SETTINGS. . . . . . . .63
5.5
CURRENT DIFFERENTIAL - ALGORITHM . . . . . . . . . .64
5.6
FAULT LOCATOR BLINDERS AND DISTANCE
PROTECTION COMMON SETTINGS . . . . . . . . . . . .67
5.7
BACK-UP SYSTEM SETTINGS . . . . . . . . . . . . . . .68
5.8
ZONE-2 AND ZONE-3 SETTINGS . . . . . . . . . . . . . .70
5.9
OUT-OF-STEP LOGIC SETTINGS . . . . . . . . . . . . . .72
APPENDIXES
A
BACKPLANE MODULE . . . . . . . . . . . . . . . . . . . . . .81
B
INTERCONNECT MODULE . . . . . . . . . . . . . . . . . . . .85
C
RELAY OUTPUT MODULE . . . . . . . . . . . . . . . . . . . .89
D
CONTACT INPUT MODULE
E
MICROPROCESSOR MODULE . . . . . . . . . . . . . . . . . .99
F
DISPLAY MODULE
G
POWER SUPPLY MODULE. . . . . . . . . . . . . . . . . . .115
H
ANALOG INPUT MODULE . . . . . . . . . . . . . . . . . . .119
I
MODEM MODULE . . . . . . . . . . . . . . . . . . . . . . .127
J
CODEC MODULE . . . . . . . . . . . . . . . . . . . . . . .139
K
DIGITAL COMMUNICATION INTERFACE . . . . . . . . . . . .145
L
ACCEPTANCE TESTS . . . . . . . . . . . . . . . . . . . . .153
M
COMPUTER COMMUNICATION . . . . . . . . . . . . . . . . .167
. . . . . . . . . . . . . . . . . . .95
. . . . . . . . . . . . . . . . . . . . . .111
DRAWINGS
SYSTEM DIAGRAMS. . . . . . . . . . . . . . . . . . . . . . . . .173
REL 356
iv
TABLE OF CONTENTS (Continued)
List of Figures
Figure NumberPage Number
1-1
1-2
Layout of REL 356 Modules Within Inner And Outer Chassis - - - - - - - - - - - - - - - - - - - 7
Block Diagram of REL 356 Relay - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - 8
2-1
REL 356 Outline Drawing- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - 12
3-1
3-2
3-3
3-4
3-5
3-6
3-7
3-8
3-9
3-10
3-11
3-12
3-13
REL 356 Fault Recognition - - - - - - - - - - - - - - - - - - Symmetrical Component Filter - - - - - - - - - - - - - - - - Mho Characteristics for Single Phase-to-Ground Fault DetectionMho Characteristics for Three-Phase Fault Detection - - - - - Mho Characteristics for Phase-to-Phase Fault Detection- - - - Logic diagram - - - - - - - - - - - - - - - - - - - - - - - - Logic Diagram - - - - - - - - - - - - - - - - - - - - - - - - Logic Diagram - - - - - - - - - - - - - - - - - - - - - - - - Loss of Potential Block Logic - - - - - - - - - - - - - - - - - Zone 2 and Zone 3 Back-up System - - - - - - - - - - - - - Optional Directional Overcurrent Units - - - - - - - - - - - - Blinders for the Out-of-step Logic - - - - - - - - - - - - - - - OST And OSB Logic Diagram - - - - - - - - - - - - - - - - -
4-1
4-2
REL 356 Backplate - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - 58
Block Diagram of REL 356 Relay - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - 59
5-1
5-2
5-3
5-4
5-5
Esk0253
Esk0254
Esk0347
Esk0348
Esk0349
A-1
A-2
A-3
REL 356 Backplane Module PC Board - - - - - - - - - - - - - - - - - - - - - - - - - - - - - 82
REL 356 Backplane/transformer Module PC Board - - - - - - - - - - - - - - - - - - - - - - - 83
REL 356 Backplane/transformer Module Schematic - - - - - - - - - - - - - - - - - - - - - - - 84
B-1
B-2
REL 356 Interconnect Module PC Board - - - - - - - - - - - - - - - - - - - - - - - - - - - - 86
REL 356 Interconnect Module Schematic - - - - - - - - - - - - - - - - - - - - - - - - - - - - 87
C-1
C-2a
C-2b
C-2c
REL 356 Relay Output Module PC Board - - - - - - - - REL 356 Relay Output Module Schematic (Sheet 1 of 3)
REL 356 Relay Output Module Schematic (Sheet 2 of 3)
REL 356 Relay Output Module Schematic (Sheet 3 of 3)
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76
77
78
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91
92
93
94
REL 356
TABLE OF CONTENTS (Continued)
Figure Number
Page Number
D-1
D-2
REL 356 Contact Input Module PC Board - - - - - - - - - - - - - - - - - - - - - - - - - - - - 96
REL 356 Contact Input Module Schematic - - - - - - - - - - - - - - - - - - - - - - - - - - - 97
E-1
E-2
E-3
E-4
E-5a
E-5b
E-5c
E-5d
E-5e
E-5f
E-5g
REL 356 Microprocessor Module Block Diagram - REL 356 Processor 1 Memory Map - - - - - - - - REL 356 Processor 2 Memory Map - - - - - - - - REL 356 Microprocessor PC Board - - - - - - - - REL 356 Microprocessor Schematic (Sheet 1 of 7)
REL 356 Microprocessor Schematic (Sheet 2 of 7)
REL 356 Microprocessor Schematic (Sheet 3 of 7)
REL 356 Microprocessor Schematic (Sheet 4 of 7)
REL 356 Microprocessor Schematic (Sheet 5 of 7)
REL 356 Microprocessor Schematic (Sheet 6 of 7)
REL 356 Microprocessor Schematic (Sheet 7 of 7)
F-1
F-2
REL 356 Display Module PC Board
(Sheet 7 of 7) - - - - - - - - - - - - - - - - - - - - - - 112
REL 356 Display Module Schematic - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - 113
G-1
G-2
REL 356 Power Supply PC Board - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - 117
REL 356 Power Supply Schematic (See inside back cover) - - - - - - - - - - - - - - - - - - - 118
H-1
H-2
H-3a
H-3b
H-3c
H-3d
Analog Input Module Block Diagram - - - - - Analog Input Module PC Board - - - - - - - - Analog Input Module Schematic (Sheet 1 of 4)
Analog Input Module Schematic (Sheet 2 of 4)
Analog Input Module Schematic (Sheet 3 of 4)
Analog Input Module Schematic (Sheet 4 of 4)
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- 121
- 122
- 123
- 124
- 125
I-1
I-2
I-3
I-4a
I-4b
I-4c
REL 356 Modem Block Diagram - - - - - Modulation Diagram At 9600 Bps - - - - - REL 356 Modem PC Board - - - - - - - - REL 356 Modem Schematic (Sheet 1 of 3)
REL 356 Modem Schematic (Sheet 2 of 3)
REL 356 Modem Schematic (Sheet 3 of 3)
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- 133
- 134
- 135
- 136
- 137
J-1
J-2
J-3
Block Diagram - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - 139
CODEC Module Schematic (See inside back cover) - - - - - - - - - - - - - - - - - - - - - - - 141
REL 356 CODEC Module- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - 143
K-1
K-2
K-3
K-4
K-5
K-6
Digital Communication Internal Schematic (Direct Digital Fiber Optic Multi-mode) Digital Communication Internal Schematic (Direct Digital Fiber Optic Single-mode)Digital Communication Component Location - - - - - - - - - - - - - - - - - - Component Location - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - Internal Schematic - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - Component Location - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
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- 147
- 148
- 149
- 150
- 151
S-1
S-2
S-3
S-4
S-5
S-6
S-7
Block Diagram - - - - - - - - - - - Logic Diagram (1 of 3) - - - - - - - Logic Diagram (2 of 3) - - - - - - - Logic Diagram (3 of 3) - - - - - - - Zone 2 and Zone 3 Back-up System Optional Directional Overcurrent Units
OST and OSB Logic Diagram- - - - -
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- 177
- 179
- 181
- 183
- 185
- 187
REL 356
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- 102
- 102
- 103
- 104
- 105
- 106
- 107
- 108
- 109
- 110
TABLE OF CONTENTS (Continued)
List of Tables
Table Number
Page Number
3-1
REL 356 Catalog Numbers - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - 35
3-2
REL 356 Accessories- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - 36
3-3
Faulted Phase Selection - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - 36
4-1
Test Mode Functions - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - 41
4-2
Binary-to-Hexadecimal Conversion - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - 42
4-3
Setting Functions - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - 49
4-4
Setting Information - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - 54
4-5
Monitoring Functions - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - 54
4-6
Target (Fault Data) Information - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - 55
I-1
Second, Third and Fourth Data Bits Determine Phase Change - - - - - - - - - - - - - - - - - 131
I-2
First Data Bit Determines Amplitude - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - 131
Trademarks
All terms mentioned in this book that are known to be trademarks or service marks are listed below. In addition, terms
suspected of being trademarks or service marks have been appropriately capitalized. ABB Power T&D Company Inc.
cannot attest to the accuracy of this information. Use of a term in this book should not be regarded as affecting the
validity of any trademark or service mark.
IBM and PC are registered trademarks of the International Business Machines Corporation.
WRELCOM is the registered trademark of the ABB Power T&D Company Inc.
INCOM is the registered trademark of the Westinghouse Electric Corporation
vii
REL 356
Instruction Manual 40-226
Version 1.00
NOTES
REL 356
viii
GLOSSARY
Numerics
2GF . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74
3I0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72
3R . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
3RI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49
A
ALDT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69
ALRB . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67
IGH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69, 72
IGL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69, 79, 81
IOM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72, 73
IPH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68, 72
IPL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68, 78, 81
ITRG . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66
ITU . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19, 143
K
KBPS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70
B
BFI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9, 49, 51
BI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76
C
CALM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49
CCITT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
CHTB. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69
CODEC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6, 9
CTER . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52
CTR . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24, 65, 66
CTYP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65
L
LDF . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69
LDFL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69
LDT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23, 69
LOI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
LOPB . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24, 72
N
NORB . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67
NSEQ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72
O
D
DCI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5, 6, 9
DIR . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72
DIRU . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72
DTT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
DTYP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71
E
EEPROM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7, 49
EPROM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7, 9
F
FALM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49
FDO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27, 68
FDOG . . . . . . . . . . . . . . . . . . . . . . 28, 69, 72, 80, 83
FDOP . . . . . . . . . . . . . . . . . . . . . . . . . 27, 72, 80, 83
OPBKR . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68
OPBR . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23, 67
OS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77, 87
OS3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87
OSB . . . . . . . . . . . . . . . . . 27, 28, 75, 76, 84, 86, 87
OSC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66
OSOT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77, 87
OST . . . . . . . . . . . . . . . . . 27, 28, 75, 77, 83, 84, 86
OST1 . . . . . . . . . . . . . . . . . . . . . . . . . 76, 77, 86, 87
OST2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77, 86, 87
OST3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77, 87
P
PANG . . . . . . . . . . . . . . . . . . . . . . . . . 71, 73, 79, 82
PDIF . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78, 81
Q
QAM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
G
GANG . . . . . . . . . . . . . . . . . . . . . . . . . 71, 73, 79, 82
I
ICH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78, 81
IDER . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52
ix
R
RAM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7, 10, 49
RB . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22, 49
RBEN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
RCVR . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52
REL 356
GLOSSARY
RIFT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
RLSD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69
ROM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9, 49, 50
RP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65
RS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
RT . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27, 76, 86, 87
RU . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76, 86, 87
S
SBP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
SLGF . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26, 27
SNR . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52
SRI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22, 49
SRT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50
ST . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9, 18
SYER . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52
T
T2G . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74
T2P . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74
T3G . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75
T3P . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75
TALM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49
TOG . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28, 72, 73
TRGG . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66
TRGP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66
TRIP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66
TTRI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70
TTRP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70
U
UNID . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70
REL 356
x
V
VLN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
VTR . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24, 66
W
WAYI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84
WAYO . . . . . . . . . . . . . . . . . . . . . . . . . . . 84, 86, 87
X
XCL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70
XCLK . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70
XMTR . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52, 69
XPUD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24, 71
Z
Z2GF . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74, 80, 82
Z2GR . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74, 80, 83
Z2P . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74, 79, 82
Z3GF . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75, 80, 82
Z3GR . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75, 80, 83
Z3P . . . . . . . . . . . . . . . . . . . . . . . . . . . 74, 75, 80, 82
Zad . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82
Zadj . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79, 82
ZGF . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
ZGf . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73
ZGR . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
ZGr . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73
Zl0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79, 82
Zl1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79, 82
ZP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27, 73
ZR . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71, 79, 82
ZSEQ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72
Zsl1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79, 82
Version 1.00
I.L. 40-226
Section 1. PRODUCT DESCRIPTION
INTRODUCTION
The REL 356 relay assembly is a numerical (fully digital) current differential transmission line
protection system, with optional distance back-up protection and oscillographic capability. The
following communication options are provided:
• 9600 bps Audio tone
• 56/64 kbps Digital communication
1.2
REL 356 CONSTRUCTION
The standard nomenclature for ABB relay protection equipment is as follows:
• Cabinet – contains fixed-racks, swing-racks, or open racks
• Rack – contains one or more chassis (e.g., the REL 356)
• Chassis – contains several modules (e.g., Microprocessor or Power Supply)
• Module – contains a number of functional circuits (on printed circuit board)
• Circuit – a complete function on a printed circuit board (e.g., analog-to-digital conversion)
• The REL 356 relay assembly consists of an outer-chassis and an inner-chassis which slides
into the outer-chassis. The REL 356 conforms to the following dimensions and weight (also
see Section 2, begining on page 9):
• Height 7" (requires 4 rack units @ 1.75" each); 177 mm
•
Width 19"; 483 mm
•
Depth 13.6"; 345 mm
•
Weight 38 Lbs; 17.5 kg
All of the relay circuitry, with the exception of the input isolation transformers and first-line surge
protection, are mounted on the inner chassis, to which the front panel is attached. The outer
chassis has a Backplate, which is a receptacle for all external connections, including Digital
Communication Interface. Two optional FT-14 switches are mounted in the two peripheral areas of the outer chassis (see Figure 4-1, on page 58). The FT-14 switches permit convenient and
safe disconnection of trip, ac and dc input circuits, and provide for injection of test signals.
1.3
REL 356 MODULES
The inner and outer chassis, together, contain standard modules, plus the optional relay output
for single pole trip applications. The Backplane module and Digital Communication Interface
(DCI) are connected to the Backplate (outer chassis). The remaining modules are attached to
the inner chassis:
•
•
•
•
REL 356
Interconnect module
Relay Output module
Contact Input module
Microprocessor module
1
CHAPTER 1
1.1
CHAPTER 1
I.L. 40-226
Version 1.00
•
•
•
•
•
Display module
Power Supply module
Analog Input module
Modem module for a 9600 bps Audio Tone Channel only
CODEC module for 56/64 kbps Digital Communication only
Circuit descriptions for each module, may be found in Appendices A thru I, in accordance with
the list in the Preface to this document (see “Contents of Relay System”, REL-356).
1.3.1
Backplane Module
The Backplane Assembly includes three voltage transformers, three current transformers, four
filter chokes and surge protection capacitors.
The Backplane Module (see Appendix A) receives all external connections and connects directly
to the Interconnect module, thru plug-in connectors (J11, J12, J13); and to the Relay Output
and Contact Input modules, mounted on the Interconnect module (via connectors JA1, JA2,
JA3, JA4), which provide the connections between the inner and outer chassis.
Backplane Module provides connection to DCI module used for 56/64 kbps Digital Communications.
The INCOM/PONI®* is mounted on the Backplate of the outer chassis and is connected to the
Backplane module (via connector J4).
1.3.2
Interconnect Module
The Interconnect module (see Appendix B, on page 85) becomes the floor of the REL 356 inner
chassis; it provides electrical connections from and to all other modules: from the Backplane
(at the rear), to the Analog Input and Power Supply modules (at left and right, respectively), to
the Relay Output and Contact Input modules in the center, and to the Modem, Microprocessor
and Display modules at the front of the inner chassis.
The Interconnect module receives inputs VA G , VB G , VC G , IA, IB, IC from the Backplane module
and feeds them to the Analog Input module.
1.3.3
Relay Output Module
There are three versions of this module (they are installed on the Interconnect module):
• Option
• Base 1
• Base 2
(See Appendix C, on page 89, for contact output functions)
The Option version is used for extended contact output
*. “INCOM” stands for INtegrated COMmunications, a product of The Westinghouse Electric Corporation. The “PONI”
acronym stands for Product Operated Network Interface.
2
REL 356
Version 1.00
1.3.4
I.L. 40-226
Contact Input Module
• Contact inputs contaminated by external noise, and logic level inputs
to the Microprocessor module
(See Appendix D, for more details)
1.3.5
Microprocessor Module
This module contains two processor systems (connected via the Dual Port RAM), which perform two main functions:
• Processor 1 samples the analog inputs and provides the operator interface
• Processor 2 is the protection processor
Each processor system (P1 and P2) contains the following elements:
• Microprocessor
—
16 bit microcontroller (Intel 80C196) operating at 12 MHz.
• EPROM
—
an ultraviolet erasable read-only memory for program storage.
• RAM
—
a read-write, static, random access volatile memory for performing data storage.
Processor 1 (P1) has access to:
• EEPROM
—
• Real-Time Clock —
1.3.6
electrically erasable, read-write non-volatile memory for settings and fault-data storage.
is accessed by Processor 1, to time-stamp the events.
Display Module
The Display module interfaces with the Processor 1 system of the Microprocessor module. The
Display module contains:
• 2 blue-vacuum fluorescent alphanumeric displays for value and function fields (each
field has 4 characters)
• 7 LEDs (with 7 corresponding keys for selection purposes) provide function interpretation capabilities
(See Section 4REL-356, and Appendix F, on page 111, for further details)
1.3.7
Power Supply Module
Three different styles of power supply boards are required to accommodate the input voltage
ranges listed below. The REL 356 relay is capable of continued operation during a 200 msec
voltage dip from the dc battery input; the magnitude of this voltage dip is also shown on the next
page:
REL 356
3
CHAPTER 1
This module provides an opto-isolated interface between:
I.L. 40-226
Version 1.00
CHAPTER 1
Nominal
Battery (Vdc)
Input
Range (Vdc)
Voltage
Dip (Vdc)
48/60
38-70
28
110/125
88-145
73
220/250
176-280
146
As an option this module contains two independent power supplies, with diode-auctioneered
outputs for reliability purposes; both supplies are powered from a dc battery voltage.
The switching power supply, operating at 25 kHz, generates transformer-isolated voltages as
follows:
System
Voltage
Circuitry Supplied
System
Voltage
Circuitry Supplied
System
Voltage
8.5 Vdc
Processor Board
+5 Vdc Supply
-12 Vdc
Analog circuitry
-24 Vdc
Channel Modem
VF Display COPS
Chips
+12 Vdc
Analog Circuitry
+24 Vdc
Channel Modem,
PONI Module
6.5 Vac
Vacuum Fluorescent
Display Filament
Circuitry Supplied
See Appendix G , begining on page 115, for further details
1.3.8
Analog Input Module
This module (see Appendix H) interfaces with the voltage and current transformers that are
mounted on the Backplane module. These transformers provide the following ac values: VA,
VB, VC, IA, IB, IC. These values are applied to active third-order Butterworth antialiasing filters,
with a cut-off frequency determined by the Nyquist criterion and the system sampling rate. Values IA, IB, IC are summed to produce 3I0.
All 7 inputs (VA, VB, VC, IA, IB, IC, 3I0) are connected to the multiplexer and to the A/D converter.
The A/D converter is a self-calibrating 12-bit (plus sign), with an internal track-and-hold amplifier. Additionally, the autoranging circuitry provides 16 bits of dynamic range needed to measure high fault current values.
1.3.9
Modem Module (9600 bps Audio Tone Option)
This module (see Appendix I) interconnects two REL 356 systems, located at each end of the
protected line. A 4-wire communication channel of sufficient quality to provide reliable data interchange is required. The modem, operating at a carrier frequency of 1700 Hz, conforms to
ITU V.29 standards, and provides a communication speed of 9600 bps.
The modem is under the control of an on-board digital signal processor and interfaces, via a
parallel bus, with the Microprocessor module.
The analog signals (transmit and receive levels), and digitally-encoded S/N ratio, are also available to the Microprocessor module. The modem transmit level is controlled by the Microprocessor module via the above-mentioned parallel bus.
4
REL 356
Version 1.00
I.L. 40-226
1.3.10 CODEC (56/64 kbps Digital Communication Option)
CODEC (Coder/Decoder) provides digital communication capability at 56 or 64 kbps.
The CODEC is under the control of an on-board digital signal processor and interfaces via a
parallel bus with the Microprocessor module.
1.3.11 Digital Communication Interface DCI (56/64 kbps Digital Communication Option)
This module converts 5V logic level serial input and output data lines to/from CODEC module
into one of the optional interfaces:
• Fiber Optic, 820 nm Multi Mode cable with ST connectors
• Fiber Optic, 1300 nm, Single Mode cable with ST connectors
• Direct Digital conforming to RS 422/RS 530 communication standards
1.3.12 Contact Outputs
• 4 make contacts (2 trip, 2 BFI); 8 additional optional contacts when extended contact output
option is used
• Reclose initiate (2 Form A)
• Reclose initiate (2 Form A)
• Reclose block (2 Form A)
• General start (1 Form A)
• System failure alarm (1 Form B)
• Trip alarm (2 Form A)
• Channel alarm (1 Form A)
1.4
SELF-CHECKING SOFTWARE
a. Digital Front-end A/D Converter Check
REL 356 continually monitors its ac input subsystems using multiple A/D converter calibrationcheck inputs. Failures of the converter trigger alarms.
b. Program Memory Check Sum
Immediately upon power-up, the relay does a complete ROM (EPROM) checksum of program
memory.
c. Power Up RAM Check
Immediately upon power-up, the relay does a complete RAM memory read/write tests.
REL 356
5
CHAPTER 1
This module (see Appendix J, begining on page 139) interconnects two REL 356 systems, located
at each end of the protected line.
I.L. 40-226
Version 1.00
CHAPTER 1
d. Nonvolatile RAM Check
All settings and targets are stored in nonvolatile RAM in three identical arrays. These arrays are
continuously checked by the program. If all three array copies disagree, a nonvolatile RAM failure is detected.
1.5
UNIQUE REMOTE COMMUNICATION (WRELCOM) PROGRAM
Two optional types of remote interface can be ordered.
• RS232C for single point computer communication.
• INCOM for local network communication.
A special PC software (WRELCOM RCP and OSCAR) program are available for obtaining or
sending the setting information to the REL 356. The REL 356 front panel shows two fault
events (last and previous faults), but the remote communication, 16 fault events and 3 records
of oscillographic data can be obtained and stored. Each record of the oscillographic data contains 8-cycle information (1-prefault and 7-post-fault), with 7 analog inputs and 24 digital data
(at the sampling rate of 12 per cycle).
(Refer to Appendix M, begining on page 167, for more detailed information.)
6
REL 356
Version 1.00
REL 356
∆ Digital Comm Interface
XFMR
CONTACT INPUT BD.
RELAY OUTPUT BDS.
INTERCONNECT BD.
FT-14
BACKPLANE BD.
POWER SUPPLY
FT-14
ANALOG INPUT BD.
PONI
∆ CODEC ❊ Modem
PROCESSOR BD.
DISPLAY BD.
∆ 56/64 bps Digital Comm. Option Only
❊ 9600 bps audio Tone Channel Option Only
I.L. 40-226
Figure 1-1: Layout of REL 356 Modules within Inner and Outer Chassis
7
CHAPTER 1
CHAPTER 1
I.L. 40-226
8
OPTIONAL
SPARE
SPARE
REL 356
Figure 1-2: Block Diagram of REL 356 Relay
Version 1.00
DIFFERENTIAL
PROTECTION
DISABLE
Version 1.00
I.L. 40-226
Section 2. SPECIFICATIONS
TECHNICAL
Nominal ac Voltage(VLN) at 60 Hz
69.3 V rms
Nominal ac Current (In)
1 or 5 A rms
Rated Frequency
50 or 60 Hz
CHAPTER 2
2.1
Maximum Permissible ac Voltage:
• Continuous
160 V rms
— (limited by maximum Input to A/D converter)
• 10 Second
240 V rms
— (limited by input transformer flux density)
Maximum Permissible ac Current:
• Continuous
3 x Nominal Current
— (limited by thermal characteristics)
• 1 Second
Operational
160 A rms - 5A nominal
32 A rms - 1A nominal
— (limited by maximum input
to the A/D converter)
Thermal
100 x Nominal Current
dc Battery Voltages:
Nominal
Input Range
60/48 Vdc
38 - 70 Vdc
110/125 Vdc
88 - 140 Vdc
220/250 Vdc
176 - 280 Vdc
dc Burdens:
Battery
15 W normal
40 W tripping
ac Burdens:
Volts per Phase
Current per Phase
0.02VA at 70 Vac
0.45VA at 5 A
9
I.L. 40-226
Version 1.00
2.2 EXTERNAL CONNECTIONS
Terminal blocks located on the rear of the chassis suitable for #14 square tongue lugs.
CHAPTER 2
Wiring to FT-14 switches suitable for #12 wire lugs.
2.3 CONTACT DATA
Trip Contacts — make & carry 30 A for 1 second, 10 A continuous capability, break 50 watts
resistive or 25 watts with L/R = .045 seconds.
• Non-Trip Contacts
1 A Continuous
0.1A Resistive Interrupt Capability
Contacts also meet IEC - 255-6A, IEC - 255-12, IEC -255-16, BS142-1982.
2.4 9600 bps AUDIO TONE COMMUNICATION CHANNEL
Operating Speed:
Standard Compliance:
Carrier Frequency:
Modulation:
Transmit Level:
Receiver Sensitivity:
Audio Tone Channel
Requirement:
9600 Bits per second
ITU V.29
1,700 Hz
QAM - Quadrature
Amplitude modulation
-1 dBm to -15 dBm
Adjustable in 2 dBm steps
-33 dBm
4 wire, AT&T 3002,
C2 conditioning or better
2.5 56/64 kbs DIGITAL COMMUNICATION
Operating Speed:
56 or 64 kbits/sec
2.5.1 Direct Digital Option
RS422/RS485 (electrical)
RS 530 (mechanical)
Standards Compliant
2.5.2 Fiber Optic Options
2.5.2.1
Wave Length
Fiber Optic Connector:
Cable:
Transmitter Output:
Receiver Input:
820 nm
ST
Multi-Mode
-18 dBm minimum (into 50/125 µm cable)
-28 dBm minimum
Wave Length:
Fiber Optic Connector:
Cable:
1300 nm
ST
Single Mode
2.5.2.2
10
I.L. 40-226
Transmitter Output:
— Short Reach Option:
— Medium Reach Option:
— Long Reach Option:
(into 9/125 µm cable)
-20 dBm minimum
-10 dBm minimum
0 dBm minimum
Receiver Input:
- 32 dBm minimum
- 11 dBm maximum
(MAXIMUM INPUT POWER, NOT TO BE EXCEEDED,
DETERMINED BY RECEIVER SATURATION)
CHAPTER 2
Version 1.00
2.6 Optional G.703 Interface
The external G.703 interface adapter complies with CCITT (ITU) G.703 co-directional, 64 kbps
specification.
For details refer to I.L. 40-201.7
2.7 OPTIONAL COMPUTER/NETWORK INTERFACE
• RS232C/PONI
— for single point computer communications
• INCOM/PONI
— for local network communications using INCOM network
2.8 CHASSIS DIMENSIONS AND WEIGHT
Height 7" (177.8 mm) 4 Rack Units (See Figure 2-1, page 12)
Width 19" (482.6 mm)
Depth 14" (356 mm) including terminal blocks
Weight 38 lb. (17.5 kg)
2.9 ENVIRONMENTAL DATA
Ambient Temperature Range
• For Operation
— 20°C to +60°C
• For Storage
— 40°C to +80°C
Insulation Test Voltage 2.8 kV, dc, 1 minute (3.2 kV dc, 1 sec) ANSI, C37.90 IEC-255-5
Open contacts 1400 Vdc continuous
Impulse Voltage Withstand 5 kV Peak, 1.2/50 microseconds, 0.5 Joule, (IEC-225-5)
Surge Withstand Voltage 3 kV, 1 MHz (ANSI C37.90.1, IEC-255-22-1)
Fast Transient Voltage 4 kV, 10/100 ns Withstand (ANSI C37.90.1, IEC 255-22-4)
EMI Field Strength Withstand 25 MHz-1GHz, 10V/m Withstand (ANSI C37.90.2)
Emission Tests (EN 50081-1)
11
CHAPTER 2
I.L. 40-226
12
Figure 2-1: REL 356 Outline Drawing
Version 1.00
Sub 2
2427F04
Version 1.00
I.L. 40-226
Section 3. APPLICATIONS AND ORDERING INFORMATION
INTRODUCTION
The REL 356 is a dual-microprocessor based, composite sequence filter, current differential
protection system. The REL 356 operates on the principles inherited from previous successful
current differential relaying systems; but, adapted and improved using numerical techniques.
The REL 356 is a communication channel dependent system with wide choice of analog and
digital communication options.
The REL 356 is a high speed relaying system; suitable for application to any voltage level. Its
principle of operation makes it ideal for short lines and tapped lines with a power transformer,
where traditional distance protection fails.
An optional distance-type relaying system has been included to provide back-up for a loss of
communication channel. This back-up system is similar to a zone 2 and zone 3 distance units
and logic for a distance non-pilot relaying system. Phase and ground distance units are included.
The current differential protection is inherently immune to systems’ swings and the relay will
block the tripping. However if trip is desired, blinders have been provided for detecting this condition. OST (Out-of-Step Trip) is included. Trip under OST conditions may be selected via a relay setting even when the communication channel is sound and the system is in current
differential mode.
An Overcurrent tripping function is also included in the relaying system. The “Highset” overcurrent function activates the trip outputs when the phase (IPH) or the ground (IGH) threshold units
detect currents above the settings. These units may be supervised (its recommended that they
be supervised) by the directional units. The phase units are supervised by FDOP and the
ground unit is supervised by FDOG. Of course the connection of external voltage transformers
to REL 356 is required to activate directional units.
The REL 356 also requires the connection to Voltage Transformers (vt’s) for out-of-step trip,
distance protection, fault location, loss of potential and loss of current detection.
Because of the settings ranges available in the relaying system, it is possible to accommodate
different ct ratios at the terminals of the transmission line.
The REL 356 relay has the capability, through its channel modem, to accurately measure, the
communication channel-delay. A continuous channel delay measurement with optional delay
compensation is provided. The user, however, can choose fixed channel delay via relay system
settings.
3.2
CURRENT DIFFERENTIAL LOGIC
3.2.1
Composite Sequence Filter
Current only systems, like the REL 356, compare the currents measured at the terminals of the
transmission line. In a current differential system, like the REL 356, the phasor relationship determines whether the condition is internal or external.
13
CHAPTER 3
3.1
I.L. 40-226
Version 1.00
For an internal fault, the currents are essentially “in phase” at the terminals of the transmission
line. For an external fault; the currents are 180˚ out of phase. Figure 3-1 illustrates the concept.
CHAPTER 3
The REL 356 combines the phase current (IA, IB and IC) measured at the protective relaying
terminal into a single quantity. This quantity is an output of Symmetrical Component Filter which
is proportional to the weighted sum of the sequence components. Figure 3-2 illustrates this filter.
The quantity IT, therefore, is defined as:
IT = C0I 0 – C 1I 1 + C2I 2
(3.1)
The quantity IT is itself a sine wave. The C1 (positive sequence weighting coefficient), C2 (negative sequence weighting coefficient) and C0 (zero sequence weighting coefficient) are system
settings that control the sensitivity of the relaying system.
3.2.2
Current Differential Algorithm
The quantity IT is converted into the phasor quantity ITL using discrete Fourier Transform (DFT)
cosine filter (see logic diagram figure 3-7, on page 28).
This quantity ITL is:
• Applied to Communication Transmitter and sent to the remote receiver where it is received
as ITR. Note that due to communication propagation delay, ITR is delayed with respect to
ITL.
• Applied to current differential protection algorithm after compensation for the above mentioned communication propagation delay.
The two phasor quantities:
ITL - Local
ITR - Remote
Are thus available at both relays and the below described algorithm is executed:
The operate (OP) quantity is the absolute value of the vectorial sum of ITL and ITR.
OP = /ITL + ITR/
equ. (1)
The restraint or bias (RES) quantity is the sum of absolute scalar values of ITL and ITR.
Res = /ITL/ + /ITR/
equ. (2)
The TRIP decision:
if [OP - 0.7 x RES] ≥ OTH then TRIP
where
14
OTH is the system setting establishing operating threshold.
equ. (3)
Version 1.00
I.L. 40-226
The choice of 0.7 multiplier allows for balance point at nearly 90˚ displacement of ITL and ITR
as illustrated:
ITL
CHAPTER 3
Assume ITR = ITL
OP
OP =
2 ITL ≈ 1.4 ITL
90˚
ITR
RES
ITR
ITL
RES = ITR + ITL = 2 ITL
OP - 0.7 RES = 1.4 x ITL - 0.7 x 2 ITL = 0
3.3
RECLOSE INITIATE LOGIC
3.3.1
Reclosing Logic
REL 356 provides 3-phase Reclose Initiate contact outputs to be used with an external reclosing relay. A Reclose Block (RB) contact output is also provided. The relaying system will block
the reclosing relay if reclosing into a permanent fault.
The Reclose Block Enable (RBEN) setting has the following options:
• NORB –
No reclosing block.
• ALRB
Reclose block for all types of faults.
–
With 52b contact open (closed breaker) the sequence of operation is:
Fault applied >>Pilot Trip>>Reclose initiate (SRI or 3RI).
With 52b closed (open breaker) the sequence becomes:
52b closed >>Fault applied>>Pilot Trip>>RIFT>>Reclose Block.
15
I.L. 40-226
Version 1.00
Explanation:
Closing of 52b before applying fault enables the RIFT logic after 250 msec. The Pilot Trip appears to the relay to be on a first reclose rather than on initial trip, the RIFT prevents a “second”
reclose.
CHAPTER 3
Initial trip is always without 52b (breaker closed), thus a reclose is initiated. When the breaker
opens on the initial trip, 52b closes and RIFT is armed in 250 msec.
When the breaker is closed on the first reclose 52b opens, but is held “on” logically for 500 msec
to the RIFT logic.
A Pilot Trip within that 500 msec is interpreted as having reclosed onto the same fault, and further reclosing is blocked.
3.4
RELAY FUNCTIONS
3.4.1
Open Breaker Function
When the IE (Very Low Set Overcurrent unit, all IEA, IEB, IEC) is not operating or the 52b contact
signal is operated, the relay system will place a special code in the message transmitted to the
remote terminal.
This will tell the remote terminal that the local terminal has the breaker open and any overcurrent detection signifies a fault in the line. The processor will check the incoming data byte and,
if it receives an open breaker code, it will trip if the IL function operates. The open breaker trip
is delayed by an amount equal to the Local Delay Timer (LDT) setting, plus an extra 8 msec
delay for security purposes.
The user may choose to activate the open breaker logic through the absence of IE (any
IAE, IBE or ICE). This is the very low set overcurrent unit which should be set below the
transmission line charging current. The user must be aware that the minimum IE setting
is 0.04 x In (0.2A for 5A ct and 0.04 A for 1 A ct), therefore for lines with low charging
current the above requirement may not be satisfied. For this application the open breaker function must be detected by 52b contacts. The user may also select both 52b and IE
as inputs to the open breaker logic.
NOTE:
16
When using 52b inputs, the reset time of the breaker contacts should be carefully considered. If the contact reset time is too slow (greater than the channel
delay), reclosing will be unsuccessful. The reason is as follows: after a trip,
with both breakers open, one end closes back into the line successfully; the
second end closes in, but has slow-resetting 52b contacts; when the second
closes, load current is established in the line while at the same time the slow
52b reset is causing an OPBR (OPen BReaker) signal to continue to be sent to
the first end; the first end, which had closed earlier, sees load current above
the IPL level and also receives the OPBR signal; if this condition persists for
more than eight msec, the first end will trip out, interrupting the load flow; thus,
the second end reclose will have been unsuccessful. In order to avoid the
problem, the 52b reset time must be less than the sum of LDT (Local Delay
Time) plus eight msec. A similar situation could occur if the first end’s 52b’s
were also sluggish. In that case, as soon as the second end closed in (while
the first end’s 52b’s were still causing OPBR to be sent) it would be seeing load
Version 1.00
I.L. 40-226
and the OPBR signal from the first end, and would immediately trip back out (if
the condition lasts eight msec).
Stub Bus Logic
The system has provisions for an external input for Stub Bus Protection (SBP). If this input is
activated and the IL (Low set overcurrent unit) operates, the local breaker will be tripped. Stub
Bus Trip is delayed by an amount equal to the Local Delay Timer setting plus an extra 8 msec
delay for security purposes.
The system will immediately use the SBP input to transmit an open breaker condition to the other end.
3.4.3
Loss of Potential (LOPB)
This logic is implemented in the relay when the optional back-up distance protection is included.
Loss of Potential Block (LOPB) is used to supervise the distance measurements in the backup
system. When this condition exists, all impedance measuring units will have their outputs
blocked.
The simple logic is shown in Figure 3-7, on page 30. This logic will detect one or two blown fuses, but will fail to detect the unlikely failure of all three phase fuses.
3.4.4
Loss of Current (LOI)
This logic is provided when the backup system is included in the relaying system.
The simple logic (shown in Figure 3-7, on page 30) will detect the loss of one or two current
inputs.
3.4.5
Fault Locator
The REL 356 fault locator feature computes the magnitude and phase angle of the fault impedance and the distance to the fault in both miles and kilometers. The fault impedance is calculated from the voltage and current phasors of the faulted phase(s). Thus, proper faulted phase
selection is essential for good fault locator results. The distance to the fault is computed by multiplying the imaginary part of the fault impedance times (VTR/CTR), the voltage transformer and
current transformer ratios, and dividing by the distance multiplier setting (XPUD). The impedance calculations for the various fault types are:
ZXG
=
VXG / (IX + KI0)
for single line to ground faults,
ZXY
=
(VXG - VYG) / (IX - IY)
for line to line faults, and
ZABC
=
VA / IA
17
CHAPTER 3
3.4.2
I.L. 40-226
Version 1.00
for three phase faults.
CHAPTER 3
(X, Y
=
Any A, B, C phase)
This function is included in REL 356 when the optional distance back-up system is included.
3.4.6
Differential Protection Disable
An opto-isolated input has been provided in the relaying system to disable “Local” and “Remote” differential protection when the input is energized by dc.
3.4.7
Direct Transfer Trip
An Opto-Isolated contact input is provided to transmit DTT Function (if enabled by setting) to
the distant unit.
Reception of DTT code at the distant unit for at least 10 msec will result in 3 pole tripping operation.
3.5
OPTIONAL BACK-UP
3.5.1
DISTANCE RELAYING
The Distance units in the REL 356 relay system are only operative when the communications
channel is unsound. The back-up distance relaying system only includes Zone 2 and Zone 3 of
a conventional non-pilot distance relaying system.
Line measurement techniques applied to each zone include:
• Single Phase-to-Ground fault detection
• 3-Phase fault detection
• Phase-to-Phase fault detection
• Phase-to-Phase-to-Ground fault detection
3.5.1.1
Single Phase-to-Ground
Single Phase-to-Ground fault detection (see Figure 3-1, on page 24) is accomplished by 3 nondirectional phase units (A, B, C). Expressions 1 and 2 (below) are for the operating and reference quantity, respectively. The unit will produce output when the operating quantity leads the
reference quantity.
Z 0L – Z 1L
V XG – I X + ----------------------- I 0 Z FG
Z 1L
and
18
equ. (4)
Version 1.00
I.L. 40-226
Z OL – Z 1L
j V XG + I X + ------------------------ I 0 Z RG


ZL
equ. (5)
3.5.1.2
VXG
= VAG, VBG or VCG
IX
= IA, IB or IC
I0
= zero sequence relay current
Z1L, Z0L
= Positive and zero sequence line impedance in relay ohms.
ZFG
= Forward zone reach setting in secondary ohms for SLGF.
ZRG
= Reverse reach setting in secondary ohms for SLGF.
CHAPTER 3
where
1
--- ( I A + I B + I C )
3
Three Phase
Three phase fault detection (see Figure 3-2, on page 25) is accomplished by the logic operation of one of the three ground units, plus the 3øF output signal from the phase selector
unit.
However, for a 3-phase fault condition, the computation of the distance units will be:
VXG - IXZP
equ. (6)
and
VQ
equ. (7)
VQ = Quadrature Phase Voltages
VCB for phase A
VAC for phase B
VBA for phase C
where
3.5.1.3
VXG
= VAG, VBG, VCG
IX
= IA, IB or IC
ZP
= Zone Reach Settings (Z2P, Z3P) in secondary ohms
Phase-to-Phase
The Phase-to-Phase unit (see Figure 3-3, on page 26) responds to all forward Phase-to-Phase
faults, and some Phase-Phase-to-Ground faults. Expressions 5 and 6 are for operating and
19
I.L. 40-226
Version 1.00
CHAPTER 3
reference quantity, respectively. They will produce output when the operating quantity leads the
reference quantity.
(VAB - IABZP)
equ. (8)
(VCB - ICBZP)
equ. (9)
NOTE:
3.5.2
Phase-to-Phase-to-Ground faults will be detected by the operation of either
Phase-to-Ground or Phase-to-Phase units.
Zone 2 and Zone 3 Distance Relaying
The optional back-up system in REL 356 consists of two zones of distance protection for both
phase and ground faults.
Each zone consists of four distance units that are able to detect all fault types. The impedance
units are three Phase-to- Ground units (ag, bg and cg) and a Phase-to-Phase unit.
The Phase-to-Ground units detect all Single Line-to- Ground Faults (SLGF), three phase faults
and some Phase-to-Phase-to-Ground faults within its operating characteristic. The ZGF and
ZGR (forward and reverse) settings apply to ground faults and the Zp settings apply to 3 Phase
faults.
The Phase-to-phase unit detects all Phase-to-Phase faults and some Phase-to-Phase-toGround faults. Since this unit is inherently directional only the forward reach is used. ZP (forward phase setting) applies to Phase-to-Phase faults.
NOTE:
All Phase-to-Phase-to-Ground faults are covered by the operation of the described units.
For the indication of a phase distance trip the following conditions have to occur:
1. For a Three phase fault, the RT blinder (if the system has OST logic included) and no OSB
and the 3Ph output of the phase selector and any of the Phase-to-Ground units have to
have operated to indicate a three phase fault.
2. For a Phase-to-Phase fault only the Phase-to-Phase unit needs to operate to indicate a
Phase-to-Phase fault.
3. For a Phase-to-Phase-to-Ground fault either the Phase-to-Phase unit or the Phase-toGround units have to operate to indicate a Phase-to-Phase-to-Ground fault.
4. For a single line to ground fault, any of the Phase-to-Ground fault units have to operate to
indicate a Phase-to-Ground fault.
The phase fault detection is supervised by IL, the low set overcurrent unit.
The phase to ground fault detection is supervised by I0m.
Each zone has its own timer to time coordinate with relays further away for step distance relaying. Separate phase and ground timers are provided.
The impedance back-up logic is shown in Figure 3-8, on page 31.
20
Version 1.00
Directional Overcurrent Units
Phase and ground directional units (FDOP and FDOG) may be either in or out. When they are
in, the high-set overcurrent units (IAH, IBH, ICH and IGH) are directional. The ground directional
unit may either be zero sequence polarized or negative sequence polarized.
Zero sequence polarization utilizes the zero sequence components of the currents and voltages into the relay, and the unit operates when 3Io leads 3V0 by more than 30° or lags by more
than 150°. For the operation of these units, it is required that 3I0 > 0.5 amp and 3V0 > 1 Volt.
Negative sequence polarization utilizes the negative sequence components of the currents and
voltages into the relay and the unit has its maximum torque line when I2 leads V2 by 98˚ with
the current 3I2 > 0.5 amp and 3V2 > 3 Volts.
FDOG may be used for detecting high ground resistance faults that may not be detected by any
of the ground distance units. TOG may be blocked or given a definite time for operation once
FDOG has operated and Iom has picked up.
The phase directional unit (FDOP) is based on the angular relationship of a single-phase current and the corresponding pre-fault phase-to-phase voltage phasors. The forward direction is
identified if the current phasor leads the voltage phasor. The pair of current and voltage phasors
which are compared IA and VBA (FDOPA), IB and VCB (FDOPB), IC and VAC (FDOPC). The
three-phase fault detection of zone 2 and 3 are supervised by FDOPA & FDOPB & FDOPC.
The high set currents IAH, IBH, ICH are supervised by FDOPA, FDOPB and FDOPC, respectively.
The logic for FDOG and FDOP is shown in Figure 3-9, on page 32.
3.5.4
Out of Step Trip (OST) and Out of Step Block (OSB) Logic
Out of step detection in REL 356 is achieved by the use of blinders. Only units with optional
back-up have this logic since for the blinder implementation voltage inputs are required.
A two blinder scheme is used for detecting Out of step conditions. The two blinders are called
21 BO (Outer Blinder) and 21 BI (Inner Blinder) and are parallel to the line impedance setting,
i.e., they are tilted by the PANG setting.
The RU and RT settings are the distance perpendicular to the line impedance that the blinders
are displaced from the latter. This is illustrated in Figure 3-10, on page 33. The RT setting is
also for load restriction and if any three phase fault occurs, the inner blinder, 21 BI has to be
activated for tripping and the impedance be in either Zone 2 or Zone 3 reach.
Figure 3-11, on page 34, shows the OST and OSB logic. This logic is being executed constantly
in the relay regardless whether the relaying channel is sound or not. OST logic applies in both
the phase comparison system or in the distance back-up system.
The duration of time it takes 21 BI to operate after 21 BO operates is the indication of an Out
of Step condition. Timer OST1 controls this time. When the timer times out, an Out of Step
21
CHAPTER 3
3.5.3
I.L. 40-226
I.L. 40-226
Version 1.00
condition has been detected. An OSB signal is immediately sent to block the operation of Zone
2 and Zone 3 distance units.
CHAPTER 3
Timer OST2 times the trip after an OST condition has been detected and the trajectory moves
from point 2 to point 3 in Figure 3-16. When OST 2 times out a trip signal is sent if the REL 356
has been set to trip on the way in under out of step conditions.
Timer OST3 starts timing after the inner blinder operates. If the timer has timed out then
tripping will be allowed immediately (with a 20 millisecond time delay) once the outer blinder
(21 BO) resets. Other wise, OST has to time out first. OST3 controls the trip for an OST
condition on the way out, as illustrated by the points 4 and 5 in figure 3-16.
The OSOT timer is an Out of Step Over-ride Timer that bypasses OSB after it has timed
out and lets the relay trip.
22
I.L. 40-226
CHAPTER 3
Version 1.00
1) “Normal Internal Fault”
2) “External Fault”
Figure 3-1. Fault Recognition
IA
IB
Symmetrical
Component
Filter
IC
IT = C0 I0 - C1 I1 + C2 I2
Co, C1, C2
Figure 3-2. Symmetrical Component Filter
23
Version 1.00
CHAPTER 3
I.L. 40-226
jX
B
ZGF
ϒ
ZGR
α
R
FDOG
ZGF:
Forward Reach Setting
ZGR:
Reverse Reach Setting
ϒ:
Maximum Torque Angle
B:
Balance Point
α:
30˚ w/DIRV set to ZSEQ
α:
8˚ w/DIRV set to NSEQ
Sub 5
ESK00042
Figure 3-3. Mho Characteristics for Single Phase-to-Ground Fault Detection
24
I.L. 40-226
CHAPTER 3
Version 1.00
jX
B
ZP
ϒ
R
ZP:
Forward Phase Reach Setting
ϒ:
Maximum Torque Angle (PANG)
B:
Balance Point
Sub 5
ESK00043
Figure 3-4. Mho Characteristics for Three-Phase Fault Detection
25
Version 1.00
CHAPTER 3
I.L. 40-226
Sub 1
9654A15
Figure 3-5.
26
Mho Characteristics for Phase-to-Phase Fault Detection
DISABLE
ITL
CHOK
STUB BUS/OPEN BKR.
TRIP
CH ALARM
SBP
DTT-SEND(1)
OPBK(1)
CD
OPBKR
IL
TRIP
PT
SBOBT
PILOT TRIP
40
0
DC POWER OK
µP SELFCHECK OK
PLT
TRIP
IL
RCV -DISABLE
52b
CHANNEL
ALARM
TA
TRIP
ALARM
FA
FAILURE
ALARM
BK1
BK2
RY1
RY2
BFI-1
BFI-2
BFI-3
BFI-4
BFI-5
BFI-6
BFI
ITR
DTT
RCV-DISABLE
PSE
CHOK
L
L
BK1
BK2
TRIP
CHOK
CA
CHOK
IAE
IBE
ICE
OPBKR
COMM
RECV
PSE
DISABLE
52b
GENERAL
START
LDT + 8
0
SBP
OPBR IE
BOTH
GS
Version 1.00
COMM
XMTR
XMT-DISABLE (1)
150
150
OUT
BKUP IN
SIGNAL TO ACTIVATE
BACKUP SYSTEM
SEBR
BK3
BK4
RY1
RY2
BFI
CH ALARM
PSE
L
L
BK3
BK4
TRIP
BK5
BK6
RY1
RY2
RECL INTO FAULT
PT
52b
RIFT
250
500
BTRP
3PT
BFI
OST
1H
10
0
1. DTT-SEND
2. XMT - DISABLE
3. OPBK
BTRP – BACKUP (DISTANCE) TRIP
ALRB
NOTE:
Bold characters denote system settings
RB
OST – OUT-OF-STEP TRIP
0
200
RI1
27
RI2
* Denotes Change
L
BK6
Figure 3-6. Logic Diagram (1 of 3) *
CHAPTER 3
I.L. 40-226
0
300
RBEN
NORB
L
BK5
RECL BLOCK
DTT
RECL INITIATE
NOTE (1)
Signals to be applied to COMM XMTR
one at a time in order of descending priority:
CHAPTER 3
I.L. 40-226
28
CO C1 C2
Im
Re
IA
Symm.
IB
Transmit only the Imaginary
part of the phasor.
DFT
IT
Cosine
Filter
Comp.
ITL
Filter
IC
Communication Delay Compensation
“Sampling”
LDT
OP = /ITL + ITR/
RES = /ITL/ + /ITR/
Im
Receive only the Imaginary
part of the phasor
Re
Protective
Algorithm
Trip Command
ITR
IF [OP - 0.7 RES] > OTH
CHOK
PLT
Then Trip
OTH
Figure 3-7. Logic Diagram (2 of 3)
Version 1.00
NOTE:
Bold characters denote system settings
OPTO
ISOL
Opto
Isolator
Hardware Inputs
52b
Stub
Bus
Protection
Opto
Isolator
DISABLE
Primary
Input
Power
52b
Backup
Input
Power
SBP
P
Power
Supply
1
N
P
PSE
Power
Supply
2
N
OUT
Opto
Isolator
PHASE A
IAL
IAE
IAH
IACD
VACD
PHASE B
IBL
IBE
IBH
IBCD
VBCD
PHASE C
Target
Reset
ICL
ICE
ICH
ICCD
VCCD
GROUND
Version 1.00
Disable
Pilot
Protection
FDOP OUT
Target Reset
NONDIRECTIONAL
TTRP
OPTO
ISOL
DTTSend
DTT - SEND
IN
OUT
IPH
IN
NOTE:
Bold characters denote system settings
IAHT
IN
FDOP A
DIRECTIONAL
FDOP OUT
OUT
IPH
IN
IBHT
IN
FDOP B
IH
FDOP OUT
HIGH SET
OVERCURRENT
TRIP
OUT
IPH
IN
ICHT
IN
FDOP C
IGL
IGH
IGCD
FDOG OUT
OUT
IGH
IN
FDOG
LOW LEVEL
SUPERVISION
CHANGE DETECTOR
IL
IACD
IBCD
ICCD
IGCD
0
250
VACD
VBCD
VCCD
CD
I.L. 40-226
IAL
IBL
ICL
IGL
IGHT
IN
∆V ∆I
CD
∆I
29
Figure 3-8. Logic Diagram (3 of 3)
CHAPTER 3
CHAPTER 3
I.L. 40-226
Version 1.00
IO
VO
X2
A
N
LOPB
D
A
N
LOI
D
Sub 2
ESK00047
Figure 3-9. Loss of Potential Block and Loss of Current Logic
30
Version 1.00
IL3φ
FDOP
16
OSB
(Z2, BOTH)
OSB
LOPB
(YES)
Load Restriction
3φ
Zone 2
3φ
A
N
D
O
R
T2P
(BLK)
φφ
FDOG
FDOG
φG
OSB
(Z3, BOTH)
T2P
(BLK)
FDOP
IL3φ
3φ
ZONE 3
A
N
D
O
R
T3P
(BLK)
φφ
FDOG
FDOG
φG
T3P
(BLK)
31
Figure 3-10. Zone 2 and Zone 3 Back-up System
CHAPTER 3
I.L. 40-226
Sub 2
2420F06
Sheet 2 (in part)
CHAPTER 3
I.L. 40-226
32
A
N
FDOP
D
LOW LEVEL CURREN
SUPERVISION
FROM
SHEET 1
IAL
A
IBL
N
ICL
D
O
FDOG
IL3φ
IL
R
FDOG
OUT
TOG
BLK
O
φG
R
φA
φφ
3φ
ELEMENTS
Sub 2
2420F06
Sheet 2 (in part)
Version 1.00
Figure 3-11. Optional Directional Overcurrent Units
OPERATING
Version 1.00
ESK000257
I.L. 40-226
Figure 3-12. Blinders for the Out-of-Step Logic
33
CHAPTER 3
CHAPTER 3
I.L. 40-226
34
φ
φ
φ
Figure 3-13. OST and OSB Logic Diagram
Version 1.00
Sub 2
2420F06
Sheet 2 (in part)
Version 1.00
I.L. 40-226
Table 3-1
CATALOG NUMBERING
CATALOG CHARACTER #
1
2
3
4
5
6
7
8
9
10
TYPICAL REL356 CATALOG #
M
C
6
A
1
P
T
F
R
G
TRIP / BFI / RI / RB CONTACTS
CHAPTER 3
REL356 CURRENT DIFFERENTIAL
PROTECTION SYSTEM
(CHARACTER #)
[6] = 6 TRIP, 6 BFI, 4RI, 2RB CONTACTS
[2] = 2 TRIP, 2 BFI, 4 RI, 2 RB CONTACTS
CURRENT INPUT
(CHARACTER #4)
[A] = 1 AMP CT
[B] = 5 AMP CT
BATTERY SUPPLY VOLTAGE
(CHARACTER #5)
[1] = 48/60 VDC SINGLE SUPPLY
[2] = 110/125 VDC SINGLE SUPPLY
[3] = 220/250 VDC SINGLE SUPPLY
[4] = 48/60 VDC DUAL SUPPLIES
[5] = 110/125 VDC DUAL SUPPLIES
[6] = 220/250 VDC DUAL SUPPLIES
DISTANCE BACKUP RELAYING
(CHARACTER #6)
[P] = BACKUP DISTANCE PROTECTION
[N] = NO BACKUP PROTECTION
COMMUNICATION
CHANNEL INTERFACE
(Refer to “Communication Channel
Options” in Specifications
for more details)
(CHARACTER #7)
[T] = 9600 bps Audio Tone Channel
[B] = 9600 bps Audio Tone Channel (British Telcom)
[D] = 56/64 kbs Direct Digital Channel
[H] = 56/64 kbs Fiber Optic, 850 nm, Multimode, ST Connector
[E] = 56/64 kbps 1300 nm, Single Mode Fiber, ST Connector, Short Reach
[M] = 56/64 kbps 1300, Single Mode Fiber, ST Connector, Medium Reach
[L] = 56/64 kbps 1300 nm, Single Mode Fiber, ST Connector, Long Reach
TEST SWITCHES
See Section 2.5
for Details
(CHARACTER #8)
[F] = FT-14 TEST SWITCHES
[N] = NO FT-14 TEST SWITCHES
DATA ACCESS DEVICE
(CHARACTER #9)
[R] = RS-232C
[C] = INCOM
[B] = RS-232C W/IRG PORT
ADDITIONAL FEATURES
(CHARACTER #10)
[G] = OSCILLOGRAPHIC DATA STORAGE
35
I.L. 40-226
Version 1.00
TABLE 3-2. REL 356 ACCESSORIES
CHAPTER 3
FT-14 TEST PLUG
• Right-Side
Style # 1355D32G01
• Left-Side
Style # 1355D32G03
TABLE 3-3. FAULTED PHASE SELECTION
FAULT TYPE
AG
|
|
|
|
|
|
∆IA |
∆IA |
∆IB |
∆IB |
∆IC |
∆IC |
>
>
>
>
>
>
1.5 ∗ |
1.5 ∗ |
1.5 ∗ |
1.5 ∗ |
1.5 ∗ |
1.5 ∗ |
∆IB
∆IC
∆IA
∆IC
∆IA
∆IB
|
|
|
|
|
|
BG
CG
X
X
AB
BC
CA
ABG
BCG
X
X
X
X
X
X
X
X
X
X
X
CAG
X
X
X
X
X
If none of the nine fault types in the table are identified, then a three-phase condition exists. The
comparisons do not differentiate between Phase-to-Phase and Phase-to-Phase-to-Ground faults,
but a simple check for the presence of I0 is employed to make this determination.
| ∆Ix | = | IX - IO - IXL |
36
Version 1.00
I.L. 40-226
Section 4. INSTALLATION, OPERATION AND MAINTENANCE
SEPARATING THE INNER AND OUTERCHASSIS
!
CAUTION
It is recommended that the user of this equipment become acquainted with the
information in these instructions before energizing the REL 356 and associated
assemblies. Failure to observe this precaution may result in damage to the
equipment.
All integrated circuits used on the modules are sensitive to and can be damaged by the discharge of static electricity. Electrostatic discharge precautions
should be observed when operating or testing the REL 356.
!
CAUTION
Use the following procedure when separating the inner chassis from the outer
chassis; failure to observe this precaution can cause personal injury, or undesired tripping of outputs and component damage.
a. Unscrew the front panel screws.
b. Remove the (optional) FT-14 covers if supplied (one on each side of the
REL 356).
c. Open all FT-14 switches.
Do Not Touch the outer contacts of any FT-14 switch; they may be
energized.
d. Slide out the inner chassis.
e. Close all FT-14 switches.
f.
Replace the FT-14 covers.
g. Reverse procedures above when replacing the inner chassis into the outer
chassis.
4.2
TEST PLUGS AND FT-14 SWITCHES
• Test Plugs are available as accessories (see Table 3-2 , on page 36); they are inserted into the
FT-14 switches for the purpose of System Function Tests.
4.3
EXTERNAL WIRING
All external electrical connections pass thru the Backplate (Figure 4-1, on page 58) on the outer
chassis. Seven DIN connectors (J11, J12, J13, JA1, JA2, JA3, JA4) allow for the removal of the
inner chassis from the outer chassis.
37
CHAPTER 4
4.1
I.L. 40-226
Version 1.00
Electrical inputs to the Backplane module, which are routed either directly thru the Backplate or
thru the FT-14 switch to the Backplate include (see Figure 4-1, on page 58):
• VA, VB, VC and VN
CHAPTER 4
• IA/IAR, IB/IBR, IC/ICR
• Power Supply (Battery) Inputs
Primary (IBP, IBN)
Backup (2BP, 2BN)
Analog input circuitry consists of three current transformers (IA, IB, IC) three voltage transformers, (VA, VB and VC), and low-pass filters. The six transformers are located on the Backplane
PC Board (see Appendix A). The primary winding of all six transformers are directly-connected
to the input terminal TB6/1 thru 12 (see Functional Block Diagram, (System Diagrams Section), Figure
S-1 , on page 175); the secondary windings are connected thru the Interconnect module to the
Analog Input module.
As shown in Figure 4-1, dry contact outputs for breaker failure initiation (BFI), reclosing initiation
(RI), reclosing block (RB), failure alarm and trip alarm are located on the Backplane PC Board.
As shown in Figure 4-2, on page 59, the power system ac quantities (Va, Vb, Vc, Vn, Ia, Ib, Ic),
as well as the dc sources are connected to the left side 1FT-14 switch (front view). All the trip
contact outputs are connected to the right-side 2FT-14 switch (front view). Switches 13 and 14
on 2FT-14 may be used for disabling the Breaker Failure Initiation/Reclosing Initiation (BFI/RI)
control logic. (See also external connections, Block Diagram, System Diagrams Section, Figure S-1, on
page 175.)
The INCOM/PONI communication box is mounted thru the Backplate of the outer chassis and
connected to the Backplane module. An RS-232C serial port is provided for remote transmission of target data. The serial port is also available for networking, data communications, and
remote settings (see section 4.7, NETWORK INTERFACE, on page 45).
4.4
REL 356 FRONT PANEL DISPLAY
The front panel display consists of a vacuum fluorescent display set of seven LED indicators,
seven key switches..
4.4.1
Vacuum Fluorescent Display
The vacuum fluorescent display (blue color) contains four alphanumeric characters for both the
function field and the value field. All the letters or numbers are fourteen segment form (7.88mm
x 13mm in size). The display is blocked momentarily every minute for the purpose of self-check;
this will not affect the relay protection function.
A “DISPLAY SAVER” feature turns-off the display if no key activity for 3 minutes is detected.
4.4.2
Indicators
There are 7 LED indicators on the front panel display:
38
Version 1.00
I.L. 40-226
• 1 “relay-in-service” indicator
• 1 “value accepted” indicator
When the “Relay-in-Service” LED illuminates, the REL 356 Relay is in service, there is dc
power to the relay and the relay has passed the self-check and self-test. The LED is turned
“OFF” if the Relay-in-service relay has at least one of the internal failures shown in the “Test”
mode.
The “Value Accepted” LED flashes only once, to indicate that a value has been entered successfully.
The 5 indicators used for the display selection are:
•
•
•
•
•
Settings
Volts/Amps/Angle
LAST FAULT
PREVIOUS FAULT
Test
One of these indicators is always illuminated, indicating the mode selected.
4.4.3
Key Switches
The front panel contains 7 keys:
•
•
•
•
•
•
•
Display Select
Reset Targets
Function Raise
Function Lower
Value Raise
Value Lower
Enter (recessed for security purposes)
The “Display Select” key is used to select one of the five display modes, which is indicated when
the proper LED illuminates. When a fault is detected, the “LAST FAULT” flashes once per second. If two faults are recorded, the “LAST FAULT” flashes twice per second, and the prior fault
will be moved from “LAST FAULT” to “PREVIOUS FAULT”. The new fault data will be stored in
the “LAST FAULT” register. By depressing the “Reset Targets” key, the flashing LED indicators
are cleared, and the LED will revert back to the Metering mode. The information in the “PREVIOUS FAULT” and “LAST FAULT” will not be reset from the front panel key switch, but will be
reset from External Reset (TB5-7 and TB5-8) and the remote reset through the Communication
Interface.
The “Function Raise” and “Function Lower” keys are used to scroll thru the information for the
selected display mode. The “Value Raise” and “Value Lower” keys are used to scroll thru the
different values available for each of the five functions. The “Enter” key is used to enter (in memory) a new value for settings.
39
CHAPTER 4
• 5 display-select indicators
I.L. 40-226
4.5
Version 1.00
FRONT PANEL OPERATION
CHAPTER 4
The front (operator) panel provides a convenient means of checking or changing settings, and
for checking relay unit operations after a fault. Information on fault location, trip types, phase,
operating units, and breakers which tripped become available by using the keys to step thru the
information. Targets (fault data) from the last two faults are retained, even if the relay is deenergized. The operator is notified that targets are available by red flashing LEDs on the front panel; in addition, alarm output-relay contacts are provided for the external annunciators.
The operator can identify nonfault voltage, current and phase angle on the front panel display.
Settings can be checked easily, however, any change to the settings requires the use of the
keys. When relay is in the normal operating mode, it is good practice to set the LED on the
Volts/Amps/Angle mode.
4.5.1
Settings Mode
In order to determine the REL 356 settings that have been entered into the system, continually
depress the “DISPLAY SELECT” key until the “SETTINGS” LED is illuminated. Then depress
the “FUNCTION RAISE” or “FUNCTION LOWER” key, in order to scroll thru the REL 356 SETTINGS functions (see Table 4-3, begining on page 49). For each settings function displayed, depress the “VALUE RAISE” or “VALUE LOWER” key in order to scroll thru the REL 356 values
available for the particular function. (Each value that appears, as each different function appears in the function field, is considered to be the “current value” used for that particular function.)
In order to change the “current value” of a particular settings function, “RAISE” or “LOWER” the
FUNCTION field until the desired function appears (e.g., “RP”). Then “RAISE” or “LOWER” the
values in the VALUE field until the desired value appears. If the “ENTER” key (recessed for security purposes) is depressed, the value which appears in the VALUE field will replace the “current value” in memory; but only if the “VALUE ACCEPTED” LED flashes once to indicate that
the value has been successfully entered into the system.
For reasons of security, a plastic screw is used to cover the ENTER key. A wire can be used to
lock the plastic screw and to prevent any unauthorized personnel from changing the settings.
4.5.2
Metering (Volts/Amps/Angle) Mode
When the Volts/Amps/Angle LED is selected by the “Display Select” key, the phase A, B, C voltages, currents and phase angles are available for on-line display during normal operation. All
measured values can be shown by scrolling the “Raise” or “Lower” key in the FUNCTION field.
The values on the display are dependent on the settings of RP (read primary); RP= YES for the
primary side values and RP = NO for the secondary values. Conditions such as channel receive, channel transmit and loss-of-potential can also be monitored. The function names and
values are shown in Table 4-5, on page 40.
NOTE:
40
All displayed Phase Angles use VA as reference.
Version 1.00
Target (LAST and PREVIOUS FAULT) Mode
The last two Fault records are assessable at the Front panel. The “LAST FAULT” information
is of the most recent fault, the “PREVIOUS FAULT” information is of the fault prior to the
“LAST FAULT”. These displays contain the target information along with the “Frozen” data at
the time of trip. The “LAST FAULT” register shows one or two records stored by flashing the
LED once or twice per second, respectively.
Different types of faults with related descriptions are shown in Table 4-6. As soon as a fault
event is detected, the most recent two sets of target data are available for display. The “LAST
FAULT” is the data associated with the most recent trip event. The “PREVIOUS FAULT” contains the data from the prior trip event. If a single fault occurs, the “LAST FAULT” LED flashes.
If a reclosing is applied and the system trips, the original “LAST FAULT” information will be
transferred to the “PREVIOUS FAULT” memory. The latest trip information will be stored in the
“LAST FAULT” memory, and its LED flashes twice per second. To reset the flashing LEDs, depress the “Reset Targets” key once. To reset the target information in “LAST FAULT” and
“PREVIOUS FAULT”, see the foregoing procedure (in Section 4.4.3, Key Switches, begining on
page 39).
Table 4-1:
Test Mode Functions
There are 2 ways to reset the targets:
• Using the “Target Reset” Contact
Input.
• With the INCOM command, using
the communication channel.
4.5.4
Test Mode Function
The test display mode provides diagnostic and testing capabilities for
REL 356. Relay status display, local
delay time computation, and relay
testing are among the functions provided. The test mode functions are
listed in Table 4-1.
4.5.4.1
Function
STAT
SRT
OPTI
TRIP
BFI
SRI
3RI
RB
GS
FALM
TALM
CALM
Description
Relay Self-Check Status
Monitor Standing Relay Trip Signal
Display Opto Input Status
Relay Test:
Trip Relays
Relay Test:
BFI Relays
Relay Test:
RI Relay (RI1)
Relay Test:
RI Relay (RI2)
Relay Test:
Reclose Block Relay
Relay Test:
General Start Relay
Relay Test:
Failure Alarm Relay
Relay Test:
Trip Alarm Relay
Relay Test:
Channel Alarm Relay
Contact Input Test
The Contact Input module (Appendix D, begining on page 95) can be conveniently tested, using
the Contact Input Test Function.
To activate this function, continually depress the DISPLAY key until the “TEST” LED is illuminated. Then depress the “FUNCTION RAISE’ or “FUNCTION LOWER” key until the word
“OPTI” appears in the FUNCTION field.
The “VALUE” field will display the status of the contact inputs, using two hexadecimal digits, as
explained below.
When the contacts close (voltage is applied across two input terminals), the corresponding bit
is set to binary “1”; an open set of contacts results in a binary “0”. The following correspondence
exists:
41
CHAPTER 4
4.5.3
I.L. 40-226
I.L. 40-226
Version 1.00
FUNCTION
BIT NUMBER
CHAPTER 4
Direct Transfer Trip
Stub Bus
Differential Protection Disable
Target Reset
52b
Not Used
Not Used
Not Used
0
1
2
3
4
5
6
7
For Example:
The functions listed below,
•
•
•
•
•
DTT
Differential Protection Disable
Target Reset
52b contact
Remaining contacts
(closed)
(closed)
(closed)
(closed)
(open)
will result in the following binary pattern:
1101
3210



HEX “Value”
Field Display
0001
7654



Bit Pattern
Bit Number
1
D
For reference, refer to Table 4-2 for the binary-to-hexadecimal conversion.
4.5.4.2
Relay Output Test
Table 4-2:
Binary-to-Hexadecimal Conversion
All relay outputs can be tested using the procedure
described below:
(1) Open the FT switch, using the red handles of the
breaker trip circuits, making sure that the following jumper is not disturbed:
BFI/RECLOSE ENABLE
(2) Install jumper JMI in position 1-2 on the Microprocessor module.
(3) Continually depress the “DISPLAY” key until the
“TEST” LED is illuminated; then depress the
“FUNCTION RAISE” or “FUNCTION LOWER”
key until the words “TRIP” and “RELY” appear in
the FUNCTION and VALUE fields, respectively.
42
BIT NUMBER
3/7
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
2/6
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
1/5
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0/4
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
HEX DIGIT
0
1
2
3
4
5
6
7
8
9
A
B
C
D
E
F
Version 1.00
I.L. 40-226
(4) Activate the “ENTER” key for the desired duration of the output relays operation.
(5) Depress the “FUNCTION RAISE” key to select the following parameters, as desired:
VALUE
FIELD
TRIP
* BFI
* RI (RI1-1,2)
* RI (RI2-1,2)
RB
GS
FALM
TALM
CALM
RELY
RELY
RELY
RELY
RELY
RELY
RELY
RELY
RELY
DESCRIPTION
CHAPTER 4
FUNCTION
FIELD
TRIP (A, B, C)
Breaker Failure Initiate
Single Pole Reclose Initiate
3 Pole Reclose Initiate
Recloser Blocking
General Start
Failure Alarm
Trip Alarm
Channel Alarm
Note: * These outputs are enabled only if a connection is made from TB1-13 to TB1-14.
(6) Activate the “ENTER” key to operate selected output relays.
(7) After completion of this test, restore the system to its operating state by moving JM1 to position 2-3 on the Microprocessor module, and closing the FT switch red handles.
4.5.4.3
Self Check
The results of the system self-check routines are accessible using the following procedure:
a. Continually depress the “DISPLAY” key until the “TEST” LED is illuminated; then depress
the “FUNCTION RAISE” or “FUNCTION LOWER” key until the word “STAT” appears in the
FUNCTION FIELD.
b. The VALUE FIELD will display the status of the relay in hexadecimal Format:
RELAY STATUS
DESCRIPTION
BIT NUMBER
External RAM Failure
EEPROM Failure
ROM Checksum Failure
Dual-Port RAM Failure
0
1
2
3
Analog Input Failure
Processor Failure
± 12V P.S.Fail
Modem Failure
4
5
6
7
EEPROM Warning
Power Supply 1 Failure
Power Supply 2 Failure
Dual Port RAM
Com Status Warning
8
9
10
Failure Detected by Processor 1
Failure Detected by Processor 2
0
0
12
13
14
15
Least Significant Right-Most Position
11
Most Significant Left-Most Position
43
I.L. 40-226
Version 1.00
A bit set to “1” signifies that the corresponding failure has been detected. For example, the following failures will result in a bit pattern:
CHAPTER 4
ROM CHECKSUM
Analog Input
Processor 1
(Bit 2)
(Bit 4)
(Bit 12)
The bit pattern which results is shown below:


Hex “VALUE”
Display
0 1 0 0
3 2 1 0

0 0 0 1 0 0 00 0 0 0 1
15 14 13 12 11 10 9 8 7 6 5 4

Bit Pattern
Bit Number
1
0
1
4
For normal error-free system performance, the “VALUE” field display is “0”.
The status display is generated by “OR”ing, the self-test status from Processor 1 and Processor
2. A zero value indicates that no self-test failure has occurred. A non-zero value in the low byte
(bits 0 to 7) represents an REL 356 failure condition which enables the failure alarm, and disables tripping. A non-zero value in the third character from the right (bits 8 to 11) indicate a selftest-warning which enables the failure alarm, but does not disable tripping. The left-most character (bits 12 to 15) indicates which processor(s) detected the failure.
4.5.4.4
Test Enable
Oscillographic data storage is triggered, when the ENTER key is depressed, while the TEST
mode TEST function is selected on the front panel.
4.5.4.5
Standing Relay Trip
A real-time status monitor of the Standing Relay Trip (SRT) logic signal is provided as a test
mode function. The value of the SRT function is YES if any of the trip relays is enabled, otherwise, the value is “NO”.
!
CAUTION
The user should verify that SRT = “NO” prior to putting the REL 356 in service
after testing.
4.6
JUMPER CONTROL
The following jumpers are set at the factory; the customer normally does not need to move the
jumpers.
44
Version 1.00
4.6.1
I.L. 40-226
Backplane Module
When switch 2FT-14/13 or 2FT-14/14 is opened, the BFI and RI output relays are deenergized
to prevent BFI and RI contact closures during system function test.
4.6.2
Contact Input Module
The factory sets jumpers (JMP1 thru JMP7) for 48 Vdc or 125 Vdc input source.
!
CAUTION
If the customer intends to use a voltage other than 48 Vdc or 125 Vdc, see Contact Input Module Schematic, Appendix D.
4.7
NETWORK INTERFACE
Two options are available for interfacing between REL 356 and a variety of local and remote
communication devices.
• RS-232C/PONI - for single point computer communication
• INCOM/PONI - for local network communication
An IBM PC or compatible computer, with software provided (WRELCOM), can be used to monitor the settings, 16 fault data records, 3 oscillographic records, and metering information. For
a remote setting, SETR should be set to “YES”; then the settings can be changed (remotely)
with a user-defined password. If a user loses his assigned password, a new password can be
installed by turning the REL 356 relay’s dc power supply “OFF” and then “ON”. REL 356 allows
a change of password within the next 15 minutes, by using a default “PASSWORD”.
When in the remote mode, the computer can disable the local setting by showing SET = REM
(in the Metering mode). Then, the setting cannot be changed locally. In this situation, the only
way to change a setting locally would be to turn the dc power “OFF” and then “ON”. The computer will allow for a local setting change within 15 minutes. Refer to the IL 40-603 (Remote
Communication Program) for detailed information.
4.8
OSCILLOGRAPHIC DATA
Refer to ABB Publications:
• IL 40-603 Remote Communication Program
• IL 40-606 Oscillographic and Recording Program
See appendix “M”, begining on page 167, for Oscillographic Data Definitions.
45
CHAPTER 4
An external jumper is permanently-wired to terminals 13/14 of switch 2FT-14.
I.L. 40-226
4.9
Version 1.00
REL 356 SETTINGS
CHAPTER 4
The REL 356 setting mnemonics are in Table 4-3; the appropriate setting information is in Table
4-4, on page 54, i.e., setting name, format, setting range (min, max, step), units and related
notes.
4.10
MONITORING FUNCTIONS
The REL 356 monitoring functions display on-line system information (see Table 4-5, on page 54;
monitoring values and conditions are listed in Table 4-6, on page 55). All angles are computed using
VAG as the reference angle.
4.11
TARGET (FAULT DATA) INFORMATION
The REL 356 stores 16 sets of targets (fault data). All 16 sets are accessible through INCOM®,
but only the two most recent sets of data are accessible from the front panel (see Table 4-5, on
page 54).
The first part of the fault data contains “Yes/No” targets (see Table 4-6), which identify the cause
of the trip and the status of certain system inputs and outputs; the second part of the fault data
contains values, including currents, voltages, fault impedance, and distance to the fault.
4.12
COMMUNICATION CHANNEL TESTING
Monitoring functions (see section 4.10, MONITORING FUNCTIONS, begining on page 46) display the
following communication channel information:
MLDT
—
Provides Communication Delay (in msec)
4.12.1 9600 bps Audio Tone Option Only
XMTR
—
provides transmitter output level (in dBm)
RCVR
—
provides receiver input level (in dBm)
SNR
—
provides signal-to-noise-ratio (in dB)
4.12.2 56/64 kbps Option Only
BERR
Bit Error
DISPLAY VALUE
SYER
CTER
IDER
# of Frames in Error in 512 frames
Synch Error
Channel Trouble
Unit ID Error
4.12.3 Communication Channel Interface
REL 356 processors and intelligent data communication equipment (Modem or Codec) continuously monitor status of communication channel interface used for current differential protection.
46
Version 1.00
I.L. 40-226
The status of receiver and transmitter are displayed in the monitoring function fields CHRX and
CHTX respectively (see Table 4-5, on page 54).
4.12.3.1 Receiver Status
CHRX has the following definitions:
NORM
CHTB
DCER
NODM
IDER
TTRP
–
–
–
–
–
–
DSBL
OPBR
–
–
Normal, error-free reception
Channel trouble, CRC error, excessive noise, corrupted frame, etc.
Failure to communicate with local DCE (modem, codec)
Failure to measure communication delay time
Unit ID error (see 5.5.2.6)
Reception of direct transfer trip code from the remote end
(see 5.5.2.8 and 3.4.7)
Reception of differential protection disable code from the far end (see 3.4.6)
Reception of open breaker information from the remote relay (see 3.4.1)
4.12.3.2 Transmitter Status
The following definitions are used for CHTX:
NORM
TTRP
DSBL
OPBR
DCER
4.13
–
–
–
–
–
Normal state transmission
Transmission of direct transfer trip code to the far end (see 3.4.7 and 5.5.2.8)
Transmission of differential protection disable tothe remote relay (see 3.4.6)
Transmission of open breaker information to the distant unit (see 3.4.1)
Failure to communicate with the local DCE (modem or codec)
ROUTINE VISUAL INSPECTION
With the exception of Routine Visual Inspection, the REL 356 relay assembly should be maintenance-free. A program of Routine Visual Inspection should include:
• Condition of cabinet or other housing
• Tightness of mounting hardware and fuses
• Proper seating of plug-in relays and subassemblies
• Condition of external wiring
• Appearance of printed circuit boards and components
• Signs of overheating in equipment
4.14
ACCEPTANCE TESTING
The customer should perform the REL 356 Acceptance Tests (see Appendix L, begining on page
153) on receipt of shipment.
47
CHAPTER 4
The communication between wwo relays is full-duplex i.e., each realy continuously transmits
and receives serial data.
I.L. 40-226
4.15
Version 1.00
NORMAL PRECAUTIONS
CHAPTER 4
Troubleshooting is not recommended due to the sophistication of the Microprocessor unit.
!
CAUTION
With the exception of checking to insure proper mating of connectors, or setting jumpers, the following procedures are normally not recommended. (If there
is a problem with the REL 356, it should be returned to the factory. See PREFACE.)
4.16
DISASSEMBLY PROCEDURES
a. Remove the inner chassis from the outer chassis, by unscrewing the lockscrew (on the
front panel), and unsnapping the two covers from the FT-14 switches.
NOTE:
The inner-chassis (sub-assembly) slides in and out of the outer chassis from
the front. Mating connectors inside the case eliminate the need to disconnect
external wiring when the inner chassis is removed.
b. Remove the FT-14 switches, mounted by two screws on the side walls.
c.
Remove the front panel (with the Display module) from the inner chassis, by unscrewing
four screws behind the front panel.
d. Remove the Microprocessor module, by loosening six mounting screws, and unplugging
the module from the Interconnect module.
e. Remove the Modem, Relay Output and Contact Input modules by unscrewing 2 mounting
screws from the brackets and unplugging these modules from the Interconnect module.
f.
Remove the Power Supply and Analog Input modules, by first removing the Microprocessor module and the support cross bar.
g. Remove the Backplate, by unscrewing the mounting hardware from the rear of the
Backplate.
48
Version 1.00
I.L. 40-226
Table 4-3:
REL 356 Settings
*
**
Software Version
Rated frequency setting selection
Enable readouts in primary values
Current transformer type: 1A or 5A ct
Current transformer ratio
Voltage transformer ratio
Trigger for storing oscillographic data
Trigger for storing fault target data
Ground current pickup level trigger for OSC and FDAT
Phase current pickup level trigger of OSC and FDAT
Change detector option
Reclose block enable
Open breaker selection
Very low set phase current pickup value in amps
Low set phase current pickup value in amps
High set phase trip current setting in amps
Low set ground current pickup value in amps
High set ground trip current setting in amps
Operating threshold
Zero sequence coefficient
Positive sequence coefficient
Negative sequence coefficient
Enable automatic LDT compensation
Select LDT leader/follower mode
Local delay time setting
Unit ID
Communication speed (56 or 64 kbps)
Transfer Trip
Source of Transmit Clock
Loopback Test
Ohms per unit distance multiplier for fault locator
Modem transmitter level setting
Receiver level signal detect setting
Selection of distance units for XPUD setting
Positive sequence line impedance angle
Zero sequence line impedance angle
Line impedance ratio (Z0L/Z1L)
CHAPTER 4
VERS
FREQ
RP
CTYP
CTR
VTR
OSC
FDAT
TRGG
TRGP
CD
RBEN
OPBR
IE
IPL
IPH
IGL
IGH
OTH
C0
C1
C2
ALDT
LDFL
LDT
UNID
**KBPS
TTRP
**XCLK
LPBK
XPUD
*XMTR
*RLSD
DTYP
PANG
GANG
ZR
9600 bps Audio Tone Option
56/64 kbps Digital Command Option
49
I.L. 40-226
Version 1.00
Table 4-3:
REL 356 Settings (Continued)
CHAPTER 4
BKUP
LOPB
FDOP
FDOG
DIRU
IOM
TOG
Z2P
T2P
Z2GF
Z2GR
T2G
Z3P
T3P
Z3GF
Z3GR
T3G
OST
OSB
RT
RU
OST1
OST2
OST3
OSOT
SETR
TIME
YEAR
MNTH
DAY
WDAY
HOUR
MIN
*
**
50
Backup Protection Enable
Loss-of-potential blocking selection
Directional Overcurrent Phase
Directional Overcurrent Ground
Directional Unit Selection
Medium set ground current pickup value in amps
Timer for Ground Overcurrent Unit
Zone 2 phase distance setting in ohms
Zone 2 phase time delay in seconds
Zone 2 ground forward distance setting in ohms
Zone 2 ground reverse distance setting in ohms
Zone 2 ground time delay in seconds
Zone 3 phase distance setting in ohms
Zone 3 phase time delay in seconds
Zone 3 ground forward distance setting in ohms
Zone 3 ground reverse distance setting in ohms
Zone 3 ground time delay in seconds
Out-of-step trip enable
Enabel out-of-step blocking for backup protection
Inside blinder setting in ohms
Outside blinder setting in ohms
Out-of-step block timer
Out-of-step trip on-the-way-in timer
Out-of-step trip on-the-way-out timer
Out-of-step override timer in milliseconds
Enable INCOM remote setting feature
Enable setting of real time clock
RTC setting year
RTC setting month
RTC setting day
RTC setting day of week
RTC setting hours
RTC setting minutes
9600 bps Audio Tone Option
56/64 kbps Digital Command Option
Version 1.00
I.L. 40-226
Table 4-4:
Setting Information
Format
Min
0.01
Max
Step
VERS
XX.XX
FREQ
50/60
RP
YES/NO
CTYP
XXXX
1
5
4
CTR
XX.XX
30
5000
5
VTR
XXXX
300
7000
10
OSC
TRIP.ITRG/∆V∆I
FDAT
TRIP/ITRG
TRGG
XX.XX
0.1 x In
2.0 x In
TRGP
XX.XX
0.1 x In
CD
∆V∆I
RBEN
NORB/ALRB
OPBR
IE/52B/BOTH
IE
X.XXX
IPL
Units
Notes
99.99
CHAPTER 4
Setting
Hz
Amp
CTYP = In
0.1 x In
Amps
1
2.0 x In
0.1 x In
Amps
1
0.04 x In
0.1 x In
0.002 x In
Amps
1
XX.XX
0.1 x In
0.8 x In
0.02 x In
Amps
1
IPH
XX.XX
0.8 x In
16.0 x In
0.02 x In
Amps
1, 4
IGL
XX.XX
0.1 x In
0.8 x In
0.02 x In
Amps
1
IGH
XX.XX
0.8 x In
16.0 x In
0.02 x In
Amps
1, 4
OTH
X.XXX
0.000
3.950
0.05
C0
X.XXX
0.000
5.000
0.05
C1
X.XXX
0.000
5.000
0.05
C2
X.XXX
0.000
5.000
0.05
ALDT
YES/NO
LDFL
LEAD/FOLO
LDT
XXX.X
32.0
0.1
UNID
XXXX
15
1
**KBPS
64/56
TTRP
IN/OUT
0.0
0
msec
Note 1:
Current settings are per-unit quantities. The setting range is multiplied by the CTYP setting
(in = 1 or 5) for display purposes.
Note 3:
These settings have a “BLK” option for disabling a corresponding function.
Note 4:
These settings have an “OUT” option for disabling the protection.
Note 5:
The impedance setting. The setting ranges shown are for 5 A ct. The displayed setting range is
multiplied by 5 if a 1 A ct is used (CTYP = 1).
Note 6:
9600 bps Audio Tone option.
Note 7:
56/64 kbps Digital Communication option.
7
51
I.L. 40-226
Version 1.00
Table 4-4:
Setting Information (Continued)
CHAPTER 4
Setting
52
Format
**XCLK
INT/EXT
LPBK
YES/NO
*XMTR
XXXX
*RLSD
-43/-33/-26/-16
XPUD
X.XXX
DTYP
MI/KM
PANG
Min
Max
Step
Units
Notes
7
-15
-1
2
dBm
6
dBm
6
0.300
1.500
0.001
ohms
XXXX
40
90
1
deg
GANG
XXXX
40
90
1
deg
ZR
XXX.X
0.1
7.0
0.1
BKUP
IN/OUT
LOPB
YES/NO
FDOP
IN/OUT
FDOG
IN/OUT
DIRU
ZSEQ/NSEQ
IOM
XX.XX
0.1 x In
2.0 x In
0.02 x In
Amps
1
TOG
XX.XX
0.10
9.99
0.01
sec
3
Z2P
XX.XX
0.01
50.00
0.01
ohms
5
T2P
XX.XX
0.00
2.99
0.01
sec
3
Z2GF
XX.XX
0.01
50.00
0.01
ohms
5
Z2GR
XX.XX
0.01
50.00
0.01
ohms
5
T2G
XX.XX
0.10
2.99
0.01
sec
3
Z3P
XX.XX
0.01
50.00
0.01
ohms
5
T3P
XX.XX
0.10
2.99
0.01
sec
3
Z3GF
XX.XX
0.01
50.00
0.01
ohms
5
Z3GR
XX.XX
0.01
50.00
0.01
ohms
5
T3G
XX.XX
0.10
2.99
0.01
sec
3
OST
NO/WAYI/WAYO
OSB
NONE/Z2/Z3/BOTH
RT
XX.XX
1.00
15.00
0.10
ohms
5
Note 1:
Current settings are per-unit quantities. The setting range is multiplied by the CTYP setting
(in = 1 or 5) for display purposes.
Note 3:
These settings have a “BLK” option for disabling a corresponding function.
Note 4:
These settings have an “OUT” option for disabling the protection.
Note 5:
The impedance setting. The setting ranges shown are for 5 A ct. The displayed setting range is
multiplied by 5 if a 1 A ct is used (CTYP = 1).
Note 6:
9600 bps Audio Tone option.
Note 7:
56/64 kbps Digital Communication option.
Version 1.00
I.L. 40-226
Table 4-4:
Setting Information (Continued)
Format
Min
Max
Step
Units
RU
XX.XX
3.00
15.00
0.10
ohms
OST1
XX.XX
0.50
5.0
0.05
cycles
OST2
XX.XX
0.50
4.00
0.05
cycles
OST3
XX.XX
0.50
5.0
0.05
cycles
OSOT
XX.XX
24
240
1
cycles
SETR
YES/NO
TIME
YES/NO
YEAR
XXXX
1980
2079
1
year
MNTH
XX
1
12
1
month
DAY
XX
1
31
1
day
WDAY
SUN/MON/TUES/WED/THUR/FRI/SAT
HOUR
XX
0
23
1
hour
MIN
XX
0
59
1
minute
Notes
Note 1:
Current settings are per-unit quantities. The setting range is multiplied by the CTYP setting
(in = 1 or 5) for display purposes.
Note 3:
These settings have a “BLK” option for disabling a corresponding function.
Note 4:
These settings have an “OUT” option for disabling the protection.
Note 5:
The impedance setting. The setting ranges shown are for 5 A ct. The displayed setting range is
multiplied by 5 if a 1 A ct is used (CTYP = 1).
Note 6:
9600 bps Audio Tone option.
Note 7:
56/64 kbps Digital Communication option.
5
CHAPTER 4
Setting
4
53
I.L. 40-226
Version 1.00
Table 4-5:
Monitoring Functions
Function
Format
Units
REL 356 channel receive status
NORM/OPBR/DSBL/CHTB
CHTX
REL 356 channel transmit status
NORM/OPBR/DSBL
IA
IA metered current magnitude
XXX.X
Amps
∠IA
IA metered current angle
XXXX
deg
VAG
VAG metered voltage magnitude
XXX.X
volts
∠VAG
VAG metered voltage angle
XXXX
deg
IB
IB metered current magnitude
XXX.X
Amp
∠IB
IB metered current angle
XXXX
deg
VBG
VBG metered voltage magnitude
XXX.X
volts
∠VBG
VBG metered voltage angle
XXXX
deg
IC
IC metered current magnitude
XXX.X
Amps
∠IC
IC metered current angle
XXXX
deg
VCG
VCG metered voltage magnitude
XXX.X
volts
∠VCG
VCG metered voltage angle
XXXX
deg
3I0
3I0 metered current magnitude
XXX.X
volts
∠3I0
3I0 metered current angle
XXXX
deg
DATE
Date (month, day)
MM.DD
TIME
Time (hours, minutes)
HH.MM
SET
Setting access status
BOTH/LOC/REM
LOP
Loss-of-potential indication
YES/NO
LOI
loss-of-current indication
YES/NO
OSB
Out-of-step blocking indication
YES/NO
MLDT
Measured local delay time from Modem/CODEC
XXX.X/FAIL
msec
*
XMTR
Channel transit level
XXXX
dBm
*
RCVR
Channel receive level
XXXX
dBm
*
SNR
Channel signal-to-noise ratio
XXXX
dB
**
BERR
Channel Error
Value/SYER/CTER/IDER
CHAPTER 4
CHRX
NOTE:
*
**
54
Description
All angles are computed using VAG as the reference angle.
9600 bps audio tone option
56/64 kbps digital communication option
Version 1.00
I.L. 40-226
Table 4-6:
Target (Fault Data) Information
Description
Format
Units
FTYP
Fault Type
AB/BG/CG/AB/BC/CA/ABC
BK1
breaker current flowed
YES/NO
BK2
breaker current flowed
YES/NO
BK3
breaker current flowed
YES/NO
BK4
breaker current flowed
YES/NO
BK5
breaker current flowed
YES/NO
BK6
breaker current flowed
YES/NO
IAH
High set phase A fault
YES/NO
IBH
High set phase B fault
YES/NO
ICH
High set phase C fault
YES/NO
IGH
High set ground fault
YES/NO
PLT
Pilot Trip
YES/NO
OP
Operating current magnitude
XXX.X
Amps
RES
Restraint current magnitude
XXX.X
Amps
DSBL
Differential protection disabled
YES/NO
RIFT
Reclose-into-fault trip
YES/NO
SBT
Stub-bus trip
YES/NO
OBKT
Open breaker trip
YES/NO
OST
Out-of-step trip
YES/NO
TG
Time overcurrent ground trip
YES/NO
Z2P
Zone 2 phase fault
YES/NO
Z2G
Zone 2 ground fault
YES/NO
Z3P
Zone 3 phase fault
YES/NO
Notes:
*
**
CHAPTER 4
Target
The “YES/NO” targets are displayed only if they are “YES”.
The impedance is dependent upon the CTYP setting. The internal
impedance values are for a 5A ct. The impedance value is multiplied
by 5 if a 1 A ct is used (CTYP = 1).
The angles are not displayed if the magnitude of the value or the
reference is less than 0.5 a or 0.7 rms.
9600 bps Audio Tone Channel
56/64 kbps Digital Communication
55
I.L. 40-226
Version 1.00
Table 4-6:
Target (Fault Data) Information (Continued)
CHAPTER 4
Target
**
Format
Units
TTRP
Direct Transfer Trip
YES/NO
Z3G
Zone 3 ground fault
YES/NO
Z
Fault impedance
XX.XX
ohms
FANG
Fault impedance angle
XXX.X
deg
DMI
Fault distance in miles
XXX.X
mi
DKM
Fault distance in kilometers
XXX.X
km
PFLC
Pre-fault load current
XXX.X
amps
PFLV
Pre-fault voltage
XXX.X
volts
LP
Pre-fault load angle
XXX.X
deg
VAG
VAG fault voltage magnitude
VAG fault voltage angle
XXX.X
XXX.X
volts
deg
VBG
VBG fault voltage magnitude
VBG fault voltage angle
XXX.X
XXX.X
volts
deg
VCG
VCG fault voltage magnitude
VCG fault voltage angle
XXX.X
XXX.X
volts
deg
3V0
3V0 fault voltage magnitude
3V0 fault voltage angle
XXX.X
XXX.X
volts
deg
IA
IA fault voltage magnitude
IA fault voltage angle
XXX.X
XXX.X
amps
deg
IB
IB fault voltage magnitude
IB fault voltage angle
XXX.X
XXX.X
volts
deg
IC
IC fault voltage magnitude
IC fault voltage angle
XXX.X
XXX.X
amps
deg
3I0
3I0 fault voltage magnitude
3I0 fault voltage angle
XXX.X
XXX.X
volts
deg
Notes:
*
**
56
Description
The “YES/NO” targets are displayed only if they are “YES”.
The impedance is dependent upon the CTYP setting. The internal
impedance values are for a 5A ct. The impedance value is multiplied
by 5 if a 1 A ct is used (CTYP = 1).
The angles are not displayed if the magnitude of the value or the
reference is less than 0.5 a or 0.7 rms.
9600 bps Audio Tone Channel
56/64 kbps Digital Communication
Version 1.00
I.L. 40-226
Table 4-6:
Target (Fault Data) Information (Continued)
Description
Format
Units
DATE
Date of fault (month.day)
MM.DD
YEAR
Year of fault
YYYY
TIME
Time of fault (hours.minutes)
HH.MM
SEC
Time of fault (seconds)
XXXX
sec
MSEC
Time of fault (milliseconds)
XXXX
msec
LDT
LDT used at the time of trip
XXX.X
msec
XMTR
Channel transmit level
XXXX
dBm
*
RCVR
Channel receive level
XXXX
dBm
*
SNR
Channel signal-to-noise ratio
XXXX
dB
**
BERR
Channel error
XXXX/FAIL
Notes:
*
**
CHAPTER 4
Target
The “YES/NO” targets are displayed only if they are “YES”.
The impedance is dependent upon the CTYP setting. The internal
impedance values are for a 5A ct. The impedance value is multiplied
by 5 if a 1 A ct is used (CTYP = 1).
The angles are not displayed if the magnitude of the value or the
reference is less than 0.5 a or 0.7 rms.
9600 bps Audio Tone Channel
56/64 kbps Digital Communication
57
CHAPTER 4
I.L. 40-226
58
Diff. Protection
Disable
Version 1.00
Figure 4-1: REL 356 Backplate
Version 1.00
OPTIONAL
SPARE
SPARE
DIFFERENTIAL
PROTECTION
DISABLE
I.L. 40-226
59
Figure 4-2 Block Diagram of REL 356 Relay
CHAPTER 4
CHAPTER 4
60
NOTES
Version 1.00
I.L. 40-226
Section 5. SETTING CALCULATIONS
INTRODUCTION
REL 356 can be set through the front panel Man-Machine Interface (MMI) or through Remote
Communication Computer Software (WRELCOM Local Area Network).
This section will follow the sequence of settings displayed in the front panel display when the
relay system is in the settings mode.
!
CAUTION
Reference will be made to current levels based on 5A secondary line ct’s. For
1A secondary line ct’s multiply the current levels by 0.2.
5.2
RELAY SYSTEM SET UP
5.2.1
SOFTWARE VERSION (VERS)
Indicates the software version in the REL 356.
5.2.2
System Frequency (FREQ)
Select either 60 or 50 Hz, depending on the power system frequency.
NOTE:
5.2.3
It is imperative that the proper selection of frequency is made prior to application of power system currents and voltage.
Readout in Primary Values (RP)
A “YES” setting enables the REL 356 system to display all the monitored voltages and currents
in primary kAmperes and kVolts.
5.2.4
Current Transformer Type (CTYP)
This setting is used for load current monitoring, if the selection is to be displayed in primary kAmperes or secondary amperes.
For Example:
Enter CTYP = 5 if 1200/5 line ct’s are being used.
5.2.5
Current Transformer Ratio (CTR)
This setting is used for load current monitoring, if it is selected to be displayed in primary kAmperes. It has no effect on the protective relaying system.
61
CHAPTER 5
5.1
I.L. 40-226
Version 1.00
For Example:
CHAPTER 5
Set CTR = 240 if 1200/5 line ct’s are being used.
5.2.6
Voltage Transformer Ratio (VTR)
This setting is used for the system voltage monitoring, if it is selected to be displayed in primary
kVolts. It has no effect on the protective relaying system.
For Example:
Set VTR = 575 if 69000 V to 120 V vt’s are being used.
5.3
OSCILLOGRAPHIC INFORMATION
5.3.1
Trigger for Storing Oscillographic Data (OSC)
Indicates trigger for oscillographic data gathering. The user can select the trigger of oscillographic data when:
• TRIP
— The REL 356 system tripped
• ITRG
— The REL 356 system detected the operation of either the TRGP or
TRGG, phase or ground current trigger respectively (see below).
• ∆V, ∆I — The REL 356 system has detected a fault in the system that may not
even be within the protective zone of the relay
The change detector occurs (CD) when current or voltage change between the corresponding
data samples, spaced one power line cycle apart, exceeds 12.5%.
Using of CD as a trigger of oscillographic data is of little practical value when a relay is connected to a “live” power system.
Numerous changes due to sudden load changes, remote switching, distant faults, etc., make
the resulting oscillographic records difficult to relate to events of importance.
5.3.2
Ground Trigger Pick UP Level (TRGG)
This setting controls the level of current magnitude on the ground current, which when exceeded triggers oscillographic data storage.
5.3.3
Phase Trigger Pick Up Level (TRGP)
This setting controls the level of current magnitude, on the phase currents which when exceeded triggers oscillographic data storage.
62
I.L. 40-226
5.4
CURRENT DIFFERENTIAL- LOGIC SETTINGS
5.4.1
Change detector option (CD)
CHAPTER 5
Version 1.00
The user can select the Change Detector of the relay on:
5.4.2
• ∆Ι
— Current change detectors only.
• ∆Ι ∆V
— Current and voltage change detectors.
Reclose Block Enable (RBEN)
The following settings are provided for system flexibility:
• NORB — No Reclose Block for the system. This logic may be provided by external
devices.
• ALRB
5.4.3
— Reclose block will be activated for all types of faults.
Open Breaker (OPBR)
The following settings are available for open breaker keying:
(See Section 3.7.1, on page 18, for recommendations)
• IE
— The keying is initiated when the line current is lower than IE setting.
• 52B
— The keying is initiated when the 52b contact at the local end is closed.
• BOTH — The keying is initiated when either IE is absent or the 52b contact is
closed.
NOTE:
When using 52b inputs, the reset time of the breaker contacts should be
carefully considered. If the contact reset time is too slow (greater than the
channel delay), reclosing will be unsuccessful. The reason is as follows:
after a trip, with both breakers open, one end closes back into the line successfully; the second end closes in, but has slow-resetting 52b contacts;
when the second closes, load current is established in the line while at the
same time the slow 52b reset is causing an OPBR (OPen BReaker) signal
to continue to be sent to the first end; the first end, which had closed earlier, sees load current above the IPL level and also receives the OPBR signal; if this condition persists for more than eight msec, the first end will trip
out, interrupting the load flow; thus, the second end reclose will have been
unsuccessful. In order to avoid the problem, the 52b reset time must be
less than the sum of LDT (Local Delay Time) plus eight msec. A similar situation could occur if the first end’s 52b’s were also sluggish. In that case,
as soon as the second end closed in (while the first end’s 52b’s were still
causing OPBR to be sent) it would be seeing load and the OPBR signal
from the first end, and would immediately trip back out (if the condition
lasts eight msec).
63
I.L. 40-226
Version 1.00
5.5
CURRENT DIFFERENTIAL ALGORITHM
5.5.1
Sequence Coefficients (CØ,C1, C2)
CHAPTER 5
The reader is again referred to equation (3.1)
IT = C0I0 – C 1I1 + C2I2
where:
C0 -
Zero Sequence Coefficient
C1 -
Positive Sequence Coefficient
C2 -
Negative Sequence Coefficient
The recommended Settings are:
C0 = 1.15
C1 = 0.1
C2 = 0.25
Thus providing greatest contribution (ergo sensitivity) from zero sequence rich faults (phase ground), lowest contribution from positive sequence dominant 3-phase faults (and system load)
and finally moderate participation of negative sequence phase-phase faults.
5.5.2
Operating Threshold (OTH)
The recommended setting is OTH = 0.5
5.5.3
5.5.3.1
Current Units
Very Low Set Phase Current Unit (IE)
This unit is used with the Open Breaker (OPBKR) keying logic. It should be set sensitive
enough to pick-up when the local breaker is closed.
Note that the minimum range for this setting is 0.04 x In (0.2 A for 5 A ct). The charging current
of the very short line might be insufficient to operate OPBKR function reliably, 52b option must
be used (see 5.4.3, on page 63).
NOTE:
5.5.3.2
There is 20% hysteresis associated with this setting. The open breaker keying
will start when line current drops below .8 x IE and will remain so until it increases above1.2 x IE.
Low Set Phase Unit (IPL)
The low set overcurrent units perform the function of supervision of fault detectors and also to
prevent the REL 356 system from tripping undesirably under line energization.
64
Version 1.00
I.L. 40-226
CHAPTER 5
The phase (IPL) unit should be set at 1.5 times the net line charging current, but must be at
least .5 A. Net line charging current is herein defined as: the steady state net single-end line
charging phase current, as measured under balanced conditions (all local poles closed and all
remote poles open).
“Net” line charging indicates the distributed capacitive current minus the line-connected
shunt reactor current (if any), since line-connected shunt reactors are within the zone of
protection of the phase comparison and tend to cancel the capacitive current.
5.5.3.3
High Set Phase Overcurrent Unit (IPH)
This unit is provided in the REL 356 system to supplement the phase comparison protection by
providing a non-pilot direct trip capability for high current internal faults. The IPH unit should be
set above the maximum expected external fault current with a security margin.
On lines which do not contain series capacitors, the IPH unit should be set for 1.25 times the
maximum through current for an external three phase fault.
On series compensated lines, the phase IPH unit should be set for the higher of the following
two calculated values:
1. 1.25 times the gap flashover setting.
2. 1.25 times the maximum thru current for an external three-phase fault, with the line
compensated.
For Example:
Consider a long line with maximum thru current (line compensated) equal to 8A, and the gap
flashover setting equal to 12A. Set the phase IPH unit at 15A.
Next, consider a short line application with maximum thru current (line compensated) equal to
14A and the gap flashover setting equal to 12A. In this case, set the phase IPH equal to 17.5A.
These high set overcurrent units are only directional when the distance back-up function is included in the REL 356 system. IPH is supervised by FDOP for all phase subsystems.
5.5.3.4
Low Set Ground Unit (IGL)
The ground unit supervises the phase comparison logic for the ground subsystem. Since the
effect of charging current is minimum for the ground subsystem, the setting should only allow
for inherent unbalance under normal operation. A minimum setting of 0.5 A is recommended.
5.5.3.5
High Set Ground Overcurrent Unit (IGH)
The high set ground unit should follow the same guidelines as the high set phase units.
The IGH unit is directional only when the optional distance back-up is included. IGH is supervised by FDOG.
65
I.L. 40-226
5.5.4
CHAPTER 5
5.5.4.1
Version 1.00
Channel - Modem settings
Automatic Use of the Channel Delay Measurement
The relay logic continuously performs the communication Channel Delay measurement. To
use this feature set ALDT to YES. If fixed Channel Delay value is to be used set ALDT to NO.
5.5.4.2
Lead/Follow Mode (LDFL)
One terminal should be set to LDFL = LEAD and the other to LDFL = FOLO.
NOTE:
5.5.4.3
Never set both terminals the same. I.e., both to LDFL = LEAD nor both to
LDFL = FOLO.
Local Delay Timer (LDT)
REL 356 uses the LDT setting when no automatic channel delay measurement is being used
(ALDT = NO).
LDT should be equal to the total channel delay displayed in MLDT function of Monitoring Functions.
For Example:
MLDT
Set LDT
5.5.4.4
=
=
11.8 msec
11.8 msec
Transmitter level (XMTR)
(9600 bps Audio Tone option)
This setting defines the output power from the unit’s transmitter in [-dBm].
5.5.4.5
Receiver Level Signal Detector (RLSD)
(9600 bps Audio Tone option)
This setting defines the minimum threshold for declaring channel trouble (CHTB) in [-dBm].
5.5.4.6
Unit Identification (UNID)
This setting eliminates the possibility of connecting two wrong units to each other due to cross
connection in the communication channel matrix.
• The UNID numbers in both units should be adjacent.
For Example:
0 in one
2 “
10 “
and
1 in the other
3 “
11 “
• The lower number of the pair should be an even number
66
Version 1.00
I.L. 40-226
For Example:
5.5.4.7
and
1 and 2 is illegal
Communication Speed Selection (KBPS) (56/64 kbps option)
This setting allows 56 kbps or 64 kbps communication speed selection.
This speed should be coordinated with the external communication multiplexer used in the system.
A vast majority of applications are 64 kbps.
5.5.4.8
Transfer Trip (TTRP)
Transfer Trip function as initiated by a contact closure (TB5 9 to 10) can be enabled or disabled
(IN or OUT).
If enabled (TTRP = IN) contact closure, as described above will result in transmission of TTRIP
code to the remote unit, the reception for at least 10 msec will result in 3-pole tripping at the
remote unit.
5.5.4.9
Transmit Clock Source (XCLK) (56/64 kbps option)
This setting establishes source of the transmit Data clock.
If XCLK = EXT is set, the transmit data clock is extracted from the received data stream. XCLK
set to INT causes transmit clock origination from the internal crystal oscillator.
NOTE:
For systems utilizing External Communication Multiplexers (T1 or E1 type) this
setting should be EXT.
For Systems where REL 356 units are connected directly (no multiplexers) this
setting should be INT.
5.5.4.10 Loopback (LPBK)
For Loopback configuration used in test when transmitter to receiver connection is made set
LPBK = YES.
NOTE:
This setting is set to NO for normal system operation.
5.6
FAULT LOCATOR, BLINDERS AND DISTANCE PROTECTION COMMON
SETTINGS
5.6.1
Ohms per Unit Distance (XPUD)
This setting is used by the fault locator algorithm to estimate a calculated distance to the fault.
The units of XPUD will be in primary ohms per mile or ohms per kilometer, depending on the
setting of DTYP.
67
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0 and 1 is legal
I.L. 40-226
Version 1.00
For Example:
CHAPTER 5
Set XPUD = 0.8 if DTYP = miles and the line reactance is 0.8 Primary Ohms/mile.
5.6.2
Distance Unit Type for XPUD (DTYP)
Either miles (MI) or kilometers (km) should be selected. This setting should match the units
used in XPUD.
5.6.3
Line Positive sequence impedance setting angle (PANG)
This setting relates directly to the assumed positive sequence impedance angle of the line. It
defines the Zone 2 and Zone 3 phase impedance unit maximum torque angle in degrees. This
setting is also the complement of ZP (Phase reach) and is also used for defining the slope of
the blinders for OST and OSB and for the fault locator algorithm.
For example, if the assumed positive sequence impedance of the line is Z1 = 3.0 ohms at 75°,
then set PANG = 5.
5.6.4
Line zero sequence impedance angle setting (GANG)
This setting defines the assumed impedance angle of the zero sequence (Zl0) impedance of
the transmission line. Zone 2 and Zone 3 ground impedance units use this parameter for their
operation.
For Example:
If the assumed zero sequence impedance of the line is Zl0 = 15 ohms at 80° then set
GANG = 80.
5.6.5
Zero sequence impedance to Positive sequence impedance ratio (ZR)
This setting is used for all ground fault measurements. It reflects the magnitude ratio of the assumed zero sequence impedance to the positive sequence impedance of the line.
For Example:
If Zl0 = 65 ohms at 60°, and Zl1 = 19 ohms at 75°, then set ZR = 65/19 = 3.42.
5.7
BACK - UP SYSTEM SETTINGS
5.7.1
Loss of Potential Block enable (LOPB)
This setting enables the loss of potential logic (Vo and not Io) to block all Zone 2 and Zone 3
impedance units if the logic is satisfied.
68
Version 1.00
I.L. 40-226
For Example:
5.7.2
= YES to enable the logic.
Forward Directional Phase Unit (FDOP)
If the system has voltage inputs, then the high set overcurrent units (IPH) can be made directional if FDOP is in. Set FDOP
= IN to make the IPH units directional.
NOTE:
5.7.3
In a series capacitor environment the directional units are not reliable. Set
FDOP = OUT when using IPH in a series capacitor environment. This makes
the IPH units non-directional.
Forward directional ground unit (FDOG)
If the system has voltage inputs, then the high set overcurrent unit (IGH) and the time delayed
ground back-up unit (TOG) can be made directional if FDOG is in. Set FDOG = N to the make
the IGH and TOG units directional.
NOTE:
5.7.4
In a series capacitor environment the directional unit is not reliable. Set
FDOG = OUT when using IGH and TOG in a series capacitor environment. This
makes the IGH and TOG units non-directional.
Ground directional unit polarization
options (DIRU)
The ground directional unit can be zero sequence or negative sequence polarized. When zero
sequence polarized it uses all zero sequence quantities to determine the power flow direction
and it is very sensitive to zero sequence mutuals between parallel lines. When negative sequence polarized it uses all negative sequence quantities to determine the power flow direction
and its operation is negligibly affected by the presence of mutual effects. Set DIR = ZSEQ if mutuals are not a consideration and DIR = NSEQ if strong zero sequence mutuals are present in
the neighborhood of the transmission line.
5.7.5
Medium set zero sequence overcurrent unit (IOM)
This overcurrent unit supervises the ground trips of the ground units in the impedance back-up
system. If TOG is being used it is also used for tripping after a time delay, TOG. It is measuring
the ground return current or 3I0. It should be set above the maximum expected unbalance in
the normal load current flow in the line.
The recommended setting is IOM = 0.5 amps.
5.7.6
Time Overcurrent Ground back - up timer (TOG)
This timer starts timing after IOM has operated. The relay system will trip if this TOG timer has
operated. It is used for back-up to the ground distance units for high ground fault resistance
faults that do not cause system instability and may not be detected otherwise. This unit needs
to be coordinated with down stream devices.
69
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Set LOPB
I.L. 40-226
5.8
Version 1.00
ZONE 2 AND ZONE 3 SETTINGS
CHAPTER 5
Settings for Zone 2 and Zone 3 protective systems are similar. Application of the distance units
follow the standard application for a conventional step distance, non-pilot relaying system.
When REL 356 is applied in a series capacitor environment, the impedance units provided to it
are always to be used as time delayed Zone 2 and Zone 3 protective zones, with the series capacitor shorted.
Following the traditional step distance, Zone 2 is set to under-reach any Zone 1 covering the
adjacent lines coming out of the remote terminal, if possible. It is also expected that Zone 2 will
always cover at least 100 percent of the protected line plus 10 percent of the shortest adjacent
line under all operating conditions. The maximum apparent impedance that the line can have is
when the protective gaps and/or MOV’s are shorting the series capacitors totally and effectively
removing the series capacitors from the apparent impedance to the relay. Therefore, this condition should be the basis for calculating the reach of Zone 2.
Zone 2 timers, for phase and ground, should be set to coordinate with the forward and reverse
adjacent high speed trips. Moreover, the timer should include the breaking time of the slowest
adjacent breaker and a tolerance of two to three cycles. Typical Zone 2 timers range between
0.2 to 0.3 seconds.
For Zone 3, it is recommended to be set under-reaching any Zone 2 from the remote terminal,
if possible. Zone 3 should include at least 100 percent of the protected line plus 100 percent
of the adjacent shortest line plus 10 percent of the next shortest line.
Zone 3 timers, for phase and ground, should be set to coordinate with the forward and reverse
adjacent Zone 2 trips. Generally two times the Zone 2 timer may be chosen for the Zone 3 timer
setting. Zone 3 timer ranges between 0.4 and 0.6 seconds.
Applicable parameters and settings for the characteristics of the zones have been discussed
already. These are the PANG, GANG and ZR settings discussed in previous paragraphs since
they are commonly used in other parts of the relay algorithms, for example the fault locator.
Ground units in both zones are self-polarized and have a forward (ZGf) and a reverse (ZGr)
reach. Therefore, phase to ground has a forward and reverse reach in order to have better performance when applied to resistance grounded system. The FDOG is used to supervise the forward direction while the “reverse” reach is used primarily to define the overall size of the
characteristic and the amount of reach along the R-axis.
The phase-to-phase and three-phase units in REL 356 have only a forward reach (ZP). These
units are inherently directional. This implies that all phase -to-phase and some phase-to-phaseto-ground and three-phase faults have a forward reach only.
5.8.1
Zone 2 phase unit reach (Z2P)
This setting controls the Zone 2 reach for phase to phase faults in secondary ohms. It is always
forward looking.
70
Version 1.00
I.L. 40-226
For Example:
5.8.2
ZONE-2 PHASE TIMER (T2P)
Selects the time delay for Zone 2 Phase fault detection in seconds. Set T2P = 0.15 if the minimum time delay for step distance coordination is 150 milliseconds.
5.8.3
Forward Zone 2 ground unit reach (Z2GF)
This setting is equivalent to the phase unit setting since it defines the forward reach of the Zone
2 ground unit in secondary ohms.
For Example:
Set Z2GF = 30 if the Zone 2 reach is 30 ohms at 75°.
5.8.4
Reverse Zone 2 ground unit reach (Z2GR)
Phase to ground units in REL 356 have been designed to have three self-polarized phaseground units (ph-A, ph-B, ph-C). The Z2GR setting is determined by the amount of reach along
the R-axis as shown in figure 3-6, on page 27.
For Example:
If the reverse reach has been determined to be 15 ohms at 75°, set Z2GR = 15.
5.8.5
Zone 2 ground unit timer (T2G)
Selects the time delay for Zone 2 Ground fault detection in seconds. Set T2G = 0.15 if the minimum time delay for step distance coordination is 150 milliseconds.
5.8.6
Zone 3 phase unit reach (Z3P)
This setting controls the Zone 3 reach for phase to phase faults in secondary ohms. It is always
forward looking.
For Example:
If Z3 reach is 45 ohms at 75°, set Z3P = 45.
5.8.7
ZONE-3 PHASE TIMER (T3P)
Selects the time delay for Zone 3 Phase fault detection in seconds. Set T3P = 0.30 if the minimum time delay for step distance coordination is 300 milliseconds.
71
CHAPTER 5
If Z2 reach is 30 ohms at 75°, set Z2P = 30.
I.L. 40-226
5.8.8
Version 1.00
Forward Zone 3 ground unit reach (Z3GF)
CHAPTER 5
This setting is equivalent to the phase unit setting since it defines the forward reach of the
Zone 3 ground unit in secondary ohms.
For Example:
Set Z3GF = 45 if the Zone 3 reach is 45 ohms at 75°.
5.8.9
Reverse Zone 3 ground unit reach (Z3GR)
Phase to ground units in REL 356 have been designed to have three- self-polarized phaseground units (ph-A, ph-B, ph-C). The Z3GR setting is determined by the amount of reach along
the R-axis as shown in figure 3-6, on page 27.
For Example:
If the reverse reach has been determined to be 15 ohms at 75°, set Z3GR = 15.
5.8.10 Zone 3 ground unit timer (T3G)
Selects the time delay for Zone 3 Ground fault detection in seconds. Set T3G = 0.30 if the minimum time delay for step distance coordination is 300 milliseconds.
5.9
OUT-OF-STEP LOGIC SETTINGS
Segregated phase comparison is immune to system swings. When voltage inputs are part of
the REL 356, blinders are provided for power swing detection. The Out of Step Trip (OST) logic
is executed all the time regardless of the status of the channel. This means that OST is possible
when the system is operating the segregated phase comparison algorithm only. The Out of
Step Block (OSB) logic is only applicable to the back-up system, i.e., Zone 2 and Zone 3.
5.9.1
Out of Step Trip (0ST)
This setting enables the Out of Step Trip logic. Set the relay to:
5.9.2
OUT:
If there is no need for an Out of Step Trip.
WAYI:
If the controlled Out of Step Trip is in the Way in to the operating characteristics of
the relay.
WAYO:
If the controlled Out of Step Trip is in the Way out of the operating characteristics
of the relay.
Out of Step Block (OSB)
This setting enables the Out of Step Block logic that blocks the Zone 2 and/or Zone 3 distance
units under Out of Step Conditions.
Chose:
72
5.9.3
I.L. 40-226
OUT:
If no OSB is required
Z2:
If only Zone 2 units are to be blocked by the OSB logic on Out of Step conditions.
Z3:
If only Zone 3 units are to be blocked by the OSB logic on Out of Step conditions.
BOTH:
If both Zone 2 and Zone 3 are to be blocked by the OSB logic on Out of Step conditions.
Inner blinder, 21 BI, setting. (RT)
This setting is the offset in the perpendicular direction to the line impedance on the R-X diagram
in Ohms.
For Example:
Set RT = 4.0 ohms for an inner blinder 4 ohms away from the line impedance.
NOTE:
5.9.4
RT restricts tripping inside its operating characteristics. It may be used for
load restriction purposes to avoid tripping under load.
Outer blinder, 21 B0, setting (RU)
Similar to RT. It does not restrict tripping. Used mainly to detect out of step conditions.
For Example:
Set RU = 8.0 ohms for a blinder 8.0 ohms away from the line impedance.
5.9.5
Out of Step detection timer. (OST1)
This timer is started when the outer blinder, 21 B0, has operated but the inner blinder, 21 BI,
has not operated. If the timer times out, an out of step condition has been detected and OSB is
active.
For Example:
Set OST1 = 1.5 cycles.
5.9.6
Out of Step Trip on the Way in timer (OST2)
This timer is started when an Out of Step condition has been detected and the two blinders have
operated. Once it times out, a trip signal is issued for OST.
For Example:
Set OST2 = 2 cycle.
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Version 1.00
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CHAPTER 5
5.9.7
Version 1.00
Out of Step Trip on the Way out timer (OST3)
This timer is started when an Out of Step condition has been detected and the OST2 timer
has timed out and both 21 BI are NOT operated. This permits controlling the time that the
breaker opens.
OST3 = 0.5 cycles
5.9.8
Out of Step Over-ride timer. (OSOT)
This timer is started once an Out of Step condition is identified (output of OST1). An OST signal
is generated if OSOT times out and the apparent impedance seen by the relay is inside Zone
2 or Zone 3 reach plus the RT blinde
For Example:
OSOT = 1600 msec
5.10
TIME SETTINGS
REL 350 has an internal clock for event time tagging purposes. Even if the unit has lost its power supply the internal clock will continue running.
5.10.1 Setting the clock
To set the clock in the relay, set TIME = YES.
The next fields are self explanatory:
-
Year
Month
Day
Day of the week
Hour
Minutes
YEAR
MNTH
DAY
WDAY
HOUR
MIN
Enter the correct values as appropriate.
74
Version 1.00
REL 356(L)
REL 356(R)
Z3P
Z3G
Gaps flashed
Gaps flashed
Z2G
Normal
Normal
R
Phase-to-Ground units
Phase-to-Phase units
75
Figure 5-1:
CHAPTER 5
I.L. 40-226
Sub 2
ESK000253
CHAPTER 5
I.L. 40-226
76
REL 356(L)
REL 356(R)
Z3G
Gaps Flashed
Z3P
Gaps Flashed
Normal
Z3G
Z3P
Normal
Phase to Phase Unit
Phase to Ground Units
Sub 2
ESK000254
Version 1.00
Figure 5-2:
Version 1.00
REL 356(R)
REL 356(L)
77
Figure 5-3:
CHAPTER 5
I.L. 40-226
Sub 2
ESK00347
Version 1.00
CHAPTER 5
I.L. 40-226
a) Gaps not conducting
b) All gaps conducting
ESK00348
Figure 5-4:
78
I.L. 40-226
CHAPTER 5
Version 1.00
Maximum stable
Angular Separation
a) Gaps not conducting
Maximum stable
Angular separation
b) All gaps conducting
ESK00349
Figure 5-5:
79
CHAPTER 5
80
NOTES
Version 1.00
I.L. 40-226
BACKPLANE MODULE
Component Location Diagrams - - - - - - - - - -1611C26, 1502B38
All external electrical connections pass thru the Backplane module (see Figure 4-1, on page
58) of the outer chassis. Seven DIN connectors (J11, J12, J13, JA1, JA2, JA3 and JA4) allow
for the removal of the outer chassis (Backplane module) from the inner chassis (Interconnect
module, Contact Input and Relay Output modules).
Electrical inputs to the Backplane module, which are routed through the FT-14 switch to the
Backplate, include:
• VA, VB, VC, and VN
• IA/IAR, IB/IBR, IC/ICR
• BP(48, 125 or 250 Vdc) and BN (common) for primary and backup power inputs.
The Backplane module, (see Figure A-1, on page 82 and Schematic) contains three voltagetype transformers, for VA/VN (VAN), VB/VN (VBN), VC/VN (VCN) inputs.
A Transformer module (see Figure A-2 and Schematic, on page 83) is piggybacked onto the
Backplane module, consisting of three current-type transformers (IA, IB, IC) with three 0.1% resistors. The primary windings of all six transformers are directly-connected to the input terminal
(TB6/1 thru 10); the secondary windings are connected thru the Interconnect module to the
Analog Input module. The current transformers (IA, IB, IC) are not gapped; dc offset attenuation
is done with a digital filtering algorithm. Surge suppression is included where the signals enter
the module.
The Backplane module also includes:
• 4 chokes (L1 thru L4) for dc power supply filter
• surge-suppressor capacitors
INCOM/PONI is supplied in two versions:
• INCOM/PONI to RS232 computer interface (supplied as standard).
• INCOM/PONI to INCOM network interface (supplied as option).
81
APPENDIX A
Schematic - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - 1612C22
APPENDIX A
I.L. 40-226
82
Figure A-1: REL 356 Backplane Module Component Location Diagram
Version 1.00
Sub 7
1611C26
I.L. 40-226
APPENDIX A
Version 1.00
Sub 1
1502B38
Figure A-2: REL 356 Backplane/Transformer Module PC Board
83
APPENDIX A
I.L. 40-226
84
Figure A-3: REL 356 Backplane/Transformer Module Schematic
Version 1.00
Sub 4
1612C22
Version 1.00
I.L. 40-260
INTERCONNECT MODULE
Component Location Diagram - - - - - - 1611C25
The Interconnect module (see Figure B-1 and Schematic, on page 86) becomes the floor of the
inner chassis and provides electrical connectors for all other modules; it connects from the
Backplane module (at the rear), to the Analog Input and Power Supply modules (at the left and
right sides, respectively), to the Relay Output and Contact Input modules, in the center, and to
the Microprocessor, Modem (CODEC) and Display modules at the front of the chassis. The
components on the Interconnect module include:
• 2 audio transformers for 9600 bps Audio Tone communication channel
• channel alarm relay
Related connections are shown below:
Connector
J11, J12, J13
J7
J9
J5
J10
JB1
JB2
JB3
JB4
Module
Destination
Backplane
Power Supply
Analog Input
Microprocessor
Modem for 9600 bps option or
CODEC for 56/64 kbps option
Relay Output (Single Pole Trip)
Relay Output (Base 1)
Relay Output (Base 2)
Contact Input
85
APPENDIX B
Schematic - - - - - - - - - - - - - - - - - - - - 1612C21
APPENDIX B
I.L. 40-260
86
Figure B-1: REL 356 Interconnect Module Component Location Diagram
Version 1.00
Sub 3
1611C25
Sheet 3 of 3
ANALOG INPUT J2
BACKPLATE
CHANNEL
INPUT
MODEM P3
CHANNEL
OUTPUT
(POWER INPUT)
POWER SUPPLY J7
(INCOM)
MICROPROCESSOR J6
Version 1.00
CONTACT
OUTPUT
J8
MICROPROCESSOR J6
CONTROL
OUTPUT
J8
CONTROL
OUTPUT
J8
CONTACT
INPUTS
J8
87
Figure B-2: REL 356 Interconnect Module Schematic
1612C21
APPENDIX B
I.L. 40-260
Sub 4
Version 1.00
I.L. 40-226
RELAY OUTPUT MODULE
Component Location Diagram - - - - - - 1611C27
There are 3 versions of the Relay Output module for each operating voltage (48, 125 and 250
Vac), as follows:
VersionFunction
• Option
Phase B and C Trip, Breaker Failure
• Base 1
Phase A (3ø) Trip, Breaker Failure, General Start, Reclose Blocking
• Base 2
Trip Alarm, Failure Alarm, Reclose Initiate
The option version provides phase B and C control functions for Single Pole Trip (SPT).
All 9 version/voltage variants share components of the same PC Board; the slight differences
are shown on 1611C27 (sheet 1, on page 91). The 3 versions are plugged-in and permanently
secured (via brackets) to the following connectors on the Interconnect module.
VersionInterconnect Module Connector
• Option
JB1
• Base 1
JB2
• Base 2
JB3
Connector JB connects (via the Interconnect module) to the Microprocessor module’s digital
I/0 interface.
Connector JA connects relay contacts through the Backplane module to the outside world.
Opto-isolators U1, U2, U3 and U4 interface logic level output signals from the Microprocessor
module to relay driver transistors (Q1 through Q4, respectively).
Output relays K1, K2, K5, K6, K9, K10 provide desired control operations. Reed relays K3, K4,
K7, K8 monitor the breaker trip control circuit current.
Connector terminals are assigned the following functions (see Table C-1 on the following page):
89
APPENDIX C
Schematic - - - - - - - - - - - - - - - - - - - - 1611C36
I.L. 40-226
Version 1.00
Table C-1:
Option
Version
Base 1
Version
Base 2
Version
JB-8A
JB-6A
JB-2A
JB-6C
JB-8C
JB-2C
JB-4A
JB-4C
Reed B2
Reed B1
Trip B
Reed C2
Reed C1
Trip C
BFIB
BFIC
Reed A2
Reed A1
Trip A (3Ø)
—
—
GS (Gen. Start)
BFIA
RB
—
—
Trip Alarm
—
—
Failure Alarm
RI1
RI2
JA-30AC/28AC
JA-26AC/24AC
JA-22AC/20AC
JA-18AC/16AC
JA-14AC/12AC
JA-10AC/8AC
JA-6AC/4AC
JA-2A/2C
Trip B1
Trip B2
Trip C1
Trip C2
BFIB-1
BFIB-2
BFIC-1
BFIC-2
Trip A(3Ø) - 1
Trip A(3Ø) - 2
—
GS
BFIA-1
BFIA-2
RB-1
RB-2
Trip Alarm -1
Trip Alarm -2
—
Failure Alarm
RI1-1
Ri1-2
RI2-1
RI2-2
APPENDIX C
Terminal
90
I.L. 40-226
APPENDIX C
Version 1.00
Sub 3
1611C27
Figure C-1: REL 356 Relay Output Module Component Location Diagram
91
Version 1.00
APPENDIX C
I.L. 40-226
OPTION
* = See Chart Below
Component
48V, G01
125V, G04
250V, G07
R3, 4, 7, 8, 11, 14
K1, 2, 5, 6
K9, 10
C1, 2, 3, 4
Q1, 2, 3, 4
750Ω, 5 W
12V Relay
12V Relay
2.0 µF
VN2410M
4, 0K 5 W
24V Relay
24V Relay
1.0 µF
VN2410M
15, 0K 5W
48V Relay
48V Relay
0.47 µF
ZVN0535R
Figure C-2a: REL 356 Relay Output Module Schematic
92
Sub 3
1611C36
Sheet 1 of 3
I.L. 40-226
APPENDIX C
Version 1.00
BASE 1
* = See Chart Below
Component
48V, G02
125V, G05
250V, G08
R3, 4, 8, 11, 14
K1, 2, 6
K9, 10
C1, 2, 4
Q1, 2, 3, 4
750Ω, 5 W
12V Relay
12V Relay
2.0 µF
VN2410M
4, 0K 5 W
24V Relay
24V Relay
1.0 µF
VN2410M
15, 0K 5W
48V Relay
48V Relay
0.47 µF
ZVN0535R
Sub 3
1611C36
Sheet 2 of 3
Figure C-2b: REL 356 Relay Output Module Schematic
93
Version 1.00
3φ
3φ
sφ
sφ
APPENDIX C
I.L. 40-226
BASE 2
* = See Chart Below
Component
48V, G03
125V, G06
250V, G09
R3, 4, 8, 11, 14
K1, 2, 6
K9, 10
C1, 2, 4
Q1, 2, 3, 4
750Ω, 5 W
12V Relay
12V Relay
2.0 µF
VN2410M
4, 0K 5 W
24V Relay
24V Relay
1.0 µF
VN2410M
15, 0K 5W
48V Relay
48V Relay
0.47 µF
ZVN0535R
Figure C-2c: REL 356 Relay Output Module Schematic
94
Sub 3
1611C36
Sheet 3 of 3
Version 1.00
I.L. 40-226
CONTACT INPUT MODULE
APPENDIX D
Schematic - - - - - - - - - - - - - - - - - - - - 1611C37
Component Location Diagram - - - - - - 1611C28
The Contact Input module provides an opto-isolated interface:
• from the external noise-contaminated contact inputs
• to logic level inputs on the Microprocessor module
This module contains 7 identical circuits; one of these circuits is described below:
• Resistors (R1, R2, R3 and R4) limit the input current to the approximate values of:
3.9 mA
2.9 mA
8.2 mA
3.7 mA
for
for
for
for
15V input
48V input
125V input
250V input
• Zener Diode (Z1) provides overvoltage and reverse voltage protection
• Zener Diode (Z2) and shunt resistor (R5) set an approximate 0.6 mA current threshold which
turns-on opto-isolator U1
• Jumper positions JMP3 to JMP9:
(1-2) are for 15/20V
(3-4) are for 48/125V
(5-6) are for 220/250V
NOTE:
Position 3-4 is the factory setting.
• Connector JA connects to the Backplane module and, via Terminal Block TB-5, to the external contacts
• Connector JB interfaces to the Microprocessor module via connector JB-4 (on the Interconnect module)
95
Version 1.00
APPENDIX D
I.L. 40-226
Sub 7
1611C28
Sheet 2 of 2
Figure D-1: REL 356 Contact Input Module Component Location Diagram
96
I.L. 40-226
APPENDIX D
Version 1.00
Sub 3
1611C37
Figure D-2: REL 356 Contact Input Module Schematic
97
Notes
98
Version 1.00
I.L. 40-226
MICROPROCESSOR MODULE
Component Location Diagram - - - - - - 1611C22
1.1
ARCHITECTURE
The block diagram of this module is shown in Figure E-1, on page 101. Each block in the figure
has a location designator with the following convention (for example, 2/U16):
Schematic Page #
2
NOTE:
IC Number
U16
For clarity, the supporting components, e.g., transparent latches, address decode PALs, buffers, drivers, etc., are not shown on the block diagram.
Each Processor (P1 and P2) contains the following elements:
• Microprocessor
–
16 bit microcontroller (Intel 80C196), operating at a clock frequency
of 12 MHz.
• EPROM
–
an ultraviolet, erasable read-only memory for program storage.
• RAM
–
a read-write, static, volatile memory for temporary data storage.
• EEPROM
–
electrically erasable, read-write memory for settings and fault-data
storage.
• I/O Interface
–
for power system control (relay outputs and contact inputs); also, interfaces with a communication Modem and analog/digital subsystem.
Additionally, Processor P1 accesses real-time clock (U16), which contains a battery for nonvolatile operation in the absence of power.
Both processor systems are interconnected via the dual port RAM 2k x 16 (U32). This device
has 2 separate ports; each port permits independent asynchronous access for reads and writes
to any memory location. The chip arbitration logic resolves any contentions for memory access.
1.2
MEMORY MAPS
Memory maps for Processors P1 and P2 are shown in Figures E-2 and E-3, begining on page
102, respectively.
The 80C196 microcontroller supports 64K bytes of address space directly. This is adequate for
Processor 2, but Processor 1 requires more than 64K of address space because of the large
RAM requirement for oscillographic data collection. The INST output of the microcontroller is
used to decode 64K of program memory and 64K of data memory separately.
99
APPENDIX E
Schematic - - - - - - - - - - - - - - - - - - - - 1612C18
I.L. 40-226
1.3
Version 1.00
TASK ASSIGNMENT
The processors perform the following major tasks:
APPENDIX E
Processor 1
• Analog input sampling and Fourier computations
• Operator interface
• INCOM communications
• Non-volatile data storage with 2-out-of-3 memory sampling (voting)
Processor 2
• Protection functions
• Contact input interface
• Control output interface
• Communication Modem interface
1.4
JUMPER SETTINGS
Jumper functions are listed below:
Jumper
Position
JM1
JM1
1-2
2-3*
Enable Relay Output Test
Disable Relay Output Test
(Normal Operation)
JM2
JM2
JM3
JM4
JM7
JM8
JM9
1-2
2-3*
2-3
2-3
2-3
2-3
2-3
Disable Display Saver
Enable Display Saver
Spare, not used at this time“
“
“
“
“
JM5
JM5
1-2
2-3*
P2 RAM 2kx8
P2 RAM 8kx8 or 32kx8
JM6
JM6
1-2*
2-3
P2RAM 32kx8
P2 RAM 8kx8 or 2kx8
* Factory Setting
100
Description
Version 1.00
I.L. 40-226
INCOM
Network
PONI Interface
J5
φ
φ
φ
J6
J1, J2
A/D SubSystem
Interface
φ
Communication
Modem Interface
APPENDIX E
Operator
Interface
J6
Processor
Processor
P1
P2
1/U2
Relay Outputs
φ
J6
Reed Relay Inputs
φ
3/U41
J6
Dual Port
RAM
2k x 16
4/U32
Contact
Input
Interface
φ
J6
EPROM
32k x 16
1/U1,U14
EPROM
32k x 16
3/U31, U46
RAM
32k x 16
2/U7, U23
RAM
8k x 16
4/U39, U47
EEPROM
8k x 8
2/U26
Real-Time
Clock
2/U16
5 V Regulator
U36
Power Supply
φ
J3 +8.5V
ESK00052
Figure E-1: Microprocessor Module Block Diagram
101
I.L. 40-226
Version 1.00
FFFFH
APPENDIX E
4k Dual Port RAM
(2k x 16)
E000H
8k DB2
(4k x 16)
8k DB5
(4k x 16)
C000H
8k DB1
(4k x 16)
8k DB4
(4k x 16)
8k DB0
(4k x 16)
8k DB3
(4k x 16)
A000H
8000H
8k Permanent RAM (4k x 16)
6000H
8k EEPROM (8k x 8)
DATA MEMORY
4k Memory Mapped I/0
F000H
4000H
64k EPROM Program Memory
(32k x 16)
100H
80C196 special Function Registers
0H
ESK00053
Figure E-2: REL 356 Processor 1 Memory Map
FFFFH
4k
Memory Mapped I/0
F000H
E000H
4k
Dual Port RAM
(2k x 16)
RAM
C000H
8k
48k
(4k x 16)
Program Memory (EPROM)
100H
80C196 Internal
Register File
0H
ESK00054
Figure E-3: REL 356 Processor 2 Memory Map
102
Version 1.00
Sub 6
1611C22
Sheet 3 of 3
I.L. 40-226
Figure E-4: REL 356 Microprocessor Module Component Location Diagram
103
APPENDIX E
Version 1.00
APPENDIX E
I.L. 40-226
Sub 1
1612C18
Sheet 1 of 7
Figure E-5a: REL 356 Microprocessor Module Schematic
104
Version 1.00
Sub 1
1612C18
Sheet 2 of 7
I.L. 40-226
Figure E-5b: REL 356 Microprocessor Module Schematic
105
APPENDIX E
Version 1.00
APPENDIX E
I.L. 40-226
Sub 1
1612C18
Sheet 3 of 7
Figure E-5c: REL 356 Microprocessor Module Schematic
106
Version 1.00
107
Figure E-5d: REL 356 Microprocessor Module Schematic
APPENDIX E
I.L. 40-226
Sub 1
1612C18
Sheet 4 of 7
APPENDIX E
I.L. 40-226
108
Figure E-5e: REL 356 Microprocessor Module Schematic
Version 1.00
Sub 1
1612C18
Sheet 5 of 7
Version 1.00
Sub 1
1612C18
Sheet 6 of 7
I.L. 40-226
Figure E-5f: REL 356 Microprocessor Module Schematic
109
APPENDIX E
APPENDIX E
I.L. 40-226
110
Figure E-5g: REL 356 Microprocessor Module Schematic
Version 1.00
Sub 1
1612C18
Sheet 7 of 7
Version 1.00
I.L. 40-226
DISPLAY MODULE
Component Location Diagram - - - - - - 1498B40
The Display module contains a blue vacuum fluorescent alphanumeric display, with 4 characters in the function field and 4 characters in the value field; it also includes 7 LEDs, 7 push-button switches and 5 test points (See Figures F-1, on page 112, and Schematic). The 7 push-button
switches (SW1 thru SW7) are used to activate the following functions on the front panel:
• Display Select (the LEDs, to the right of this push-button, indicate the selected function)
• Reset (the targets selected)
• Function Raise (move to the following function)
• Function Lower (move to the previous function)
• Value Raise (move to the next higher value)
• Value Lower (move to the next lower value)
• Enter (the value that has been selected for upper contact testing)
The Microprocessor module scans these switches once every cycle while in the “background”
mode, where it looks for phase current or phase voltage disturbances. When a phase disturbance is detected, the relay enters the “fault” mode. While scanning, the Microprocessor module updates the Display module via the ICs (U1, U2, U3 and U4). The display will be blocked
momentarily once every minute due to the self-check function. This is for readout check and
will not interrupt the relay protection function. The Microprocessor also illuminates some LEDs
when the Display Select Switch is depressed. IC (U5) controls the LEDs, which are as follows
(See Section 1.3.6 , on page 3):
• Relay In Service (DS2)
• Settings (DS3)
• V/I/Angle (DS4)
• Last Fault (DS5)
• Previous Fault (DS6)
• Value Accepted (DS7)
• Test (DS8)
Test points (TP1 thru TP5) are used to monitor dc voltages:
• -24V
(TP1)
• + 5V
(TP2)
• -12V
(TP3)
• +12V
(TP4)
• Common
(TP5)
111
APPENDIX F
Schematic - - - - - - - - - - - - - - - - - - - - 1608C93
APPENDIX F
I.L. 40-226
112
Figure F-1: REL350 Display Module Component Location Diagram
Version 1.00
Sub 4
1498B40
Sheet 7 of 7
Version 1.00
1608C93
113
Figure F-2: REL350 Display Module Schematic
APPENDIX F
I.L. 40-226
Sub 3
Notes
114
Version 1.00
I.L. 40-226
POWER SUPPLY MODULE
Component Location Diagram - - - - - - 1611C24
The Power Supply Module consists of two identical power supplies whose outputs are auctioneered through diodes to provide an uninterrupted power source, in the event one of the supplies
fails. The following description is provided for one supply (both supplies are identical).
The input power from terminals J7/26AC and 28AC is applied to fuses F1 and F2, rectifier
bridge BR1 and filter network R1, C1. Therefore, both dc and ac operation are possible.
Switching transistor Q2 is turned on and off to provide current for the flywheel inductors L1 and
L2 which feed the charge capacitor C11. When transistor Q2 is turned off, the flywheel current
continues through diode D5.
The dc voltage, developed across C11, is applied through resistor divider R7, R17 and R14 to
the pulse width modulator U1, pin 1. In U1, this voltage is compared with the voltage on pin 2,
which is derived from an internal Zener reference voltage on pin 16. The voltage difference between pins 1 and 2 controls the high or low duty cycle (or pulse width) of the ac waveform on
pins 12 and 13. The frequency of this ac signal is determined by R13 and C7. This ac signal is
amplified by transistor Q4 which controls the gate of switching transistor Q2 thru driver Q3; thus
completing the feedback loop which controls the voltage on capacitor C11.
Chip U1 is powered from internal element VC1 (12 volt). On powerup, VC1, is initially generated
from voltage across Zener diode Z2, driving the emitter follower Q1. VC1 also initially powers
transistors Q3 and Q4 thru diode D1. When the voltage across C11 gradually builds up, and
overtakes VC1, transistors Q3 and Q4 will be powered through R16 and D2. When the voltage
across C11 reaches about 75% of its final value, the current through R3 will back bias Q1
through diode D4, turning off Q1 and supplying VC1 through R3 from the voltage across C11.
This arrangement minimizes the power dissipation on Q1. For the same reason, it is extremely
important to limit the current from P12V (Terminal J7 14AC) to 10mA. Otherwise, the turn off of
Q1 may be hampered, and serious overheating will result. The gradual buildup of voltage
across C11 is controlled by capacitor C3.
Overload protection is provided by sense resistors R18, R19 and R20 through filter R5 and C6
to control input (pin 5) of chip, U1.
The primary dc voltage (PRDC 1) across C11 is converted to a regulated ac voltage, with the
aid of U2 and U3 devices that alternately control switching transistors Q5 and Q6, thereby providing power to the primary winding of transformer T1. Protection against accidental shorts is
provided by sensing resistors R28, R29 and R30, through filter R27 and C12, to control pin 4
of U2.
115
APPENDIX G
Schematic - - - - - - - - - - - - - - - - - - - - 1356D56
I.L. 40-226
Version 1.00
The secondary winding of transformer T1, on terminals 6, 7 and 10 provides:
APPENDIX G
• +12 Vdc thru full wave rectifier D17 and D18 and auctioneering diode D21 (to terminal J2/
28A, 28C)
• -12 Vdc thru full wave rectifier D15 and D11 and auctioneering diode D14 (to terminal J2/
30A, 30C)
• +24 Vdc thru voltage doubler circuit C16, C19, D23, C18 and auctioneering diode D24 (to
terminal J7/8A, 8C)
• -24 Vdc thru voltage doubler circuit C17, D20, D25, C19 and auctioneering diode D22 (to terminal J7/6A, 6C)
The secondary winding of transformer T1, on terminals 8 and 9 provides:
• +8.5 Vdc thru full wave bridge rectifier D10, D11, D12, D13 and auctioneering diode D9 (to
terminal J2/20A, 20C, 22A and 22C) (also to terminal J7/10A, 10C)
The secondary winding of transformer T1, on terminals 4 and 5 provides:
• 6.5 VacREL 356 for the electroluminescent display (to terminals J2/4A, 4C and 6A, 6C)
The 6.5 Vac is switched by relay K1, since it is impossible to auctioneer two nonsynchronized
ac voltages. Relay K1 is controlled by status monitor U7. The 6.5 Vac output is biased at -20
Vdc to satisfy the requirements of the electroluminescent display.
The status monitor U7 checks the health of each power supply by monitoring the +8.5 Vdc outputs of each supply. The status outputs are normally low, thus, a high output means a failed
power supply (Terminal J2/12A, 12C).
Each power supply is capable of delivering a total output of 35 W power, distributed among its
six load outputs.
Due to the maximum diode rating of 1A, no individual load should exceed a current drain of 1A.
ADJUSTMENTS
To achieve optimum performance, the following adjustments are required
Adjust
Power Supply
To Achieve
On
Comments
R17
1
26.00Vdc
PRDC1 (Term. J7/16AC)
G01
R17
1
70.00Vdc
PRDC1 (Term. J7/16AC)
G02 and G03
R50
2
26.00Vdc
PRDC2 (Term. J7/18AC)
G01
R50
2
70.00Vdc
PRDC2 (Term. J7/18AC)
G02 and G03
NOTE:
116
For proper operation of the auctioneered outputs, PRDC1 and PRDC2 shoud
have identical vaues.
Version 1.00
117
Figure G-1: REL 356 Power Supply PC Board
APPENDIX G
I.L. 40-226
Sub 1
1612C63
Sheet 12
APPENDIX G
I.L. 40-226
118
Figure G-2: REL 356 Power Supply Schematic
Version 1.00
Sub 5
1356D56
Version 1.00
I.L. 40-226
ANALOG INPUT MODULE
Component Location diagram - - - - - - 1611C23
The block diagram of this module is shown in Figure H-1, on page 120. The module interfaces
with the voltage and current transformers that are mounted on the Backplane module. These
transformers provide the following ac values: VA, VB, VC, IA, IB, IC. The values are applied to
active third-order Butterworth antialiasing filters (U8 thru U13), with a cut-off frequency determined by the Nyquist criterion and the system sampling rate. Values IA, IB, IC are summed to
produce 3I0 in U5. All seven values (VA, VB, VC, IA, IB, IC, 3I0) are applied to the multiplexer
(U5), whose output connects to the A/D converter (U15) via autoranging circuitry.
The A/D converter is a 12 bit plus sign with an internal sample-and-hold amplifier. Additionally,
on request, the A/D converter executes a self-calibrating routine that corrects zero errors and,
also, full-scale and linearity errors. Device U16 provides stable, precision 5.000 V reference to
the A/D converter. The autoranging circuitry provides 16 bits of dynamic range needed to measure high current values during power system faults.
The 13 bit output is available from the A/D converter (12 bit plus sign). To achieve a 16-bit range
requires a multiplication of the A/D converter output (or gain) by eight.
If the input value satisfies the expression:
+ 0.5 V < VIN < - 0.5 V
then the comparators (U3.1 and U3.2) select the Y0 - Y) switch of U4, and multiplication by 8
takes place in the Microprocessor software.
For the range:
- 0.5 V < IIN < + 0.5 V
the (Y1 - Y) path of U4 is selected (by U3.1 and U3.2), connecting the output of U2 (analog input
with a gain of 8) to the A/D converter, performing a multiplication by 8 in the analog domain.
NOTE:
Adjust potentiometer (R59) for 5.000V at the test point (TP2) to ground.
119
APPENDIX H
Schematic - - - - - - - - - - - - - - - - - - - - 1612C20
I.L. 40-226
Version 1.00
MUX.
Select
APPENDIX H
J2
VA
J1
F
1/U13
F
VC
F
1/U12
1/U11
MUX
F
2/U10
To
IA
Control
Yo 3/U4
Y
A/D
IB
F
IC
Y1
4/U15
X8
2/U8
Antialiasing
Filters
Data
2/U9
F
3/U2
- 3I0
REF
2/U7
To Voltage and Current
Transformers via
Interconnect Module
> + .5 V
4/U16
Range Select
Comp
3/U3.2
3/U5
< - .5 V
Comp
3/U3.1
Autoranging Circuits
ESK00055
Figure H-1: Analog Input Module Block Diagram
120
µP Module
VB
Version 1.00
121
Figure H-2: Analog Input Module Component Location Diagram
APPENDIX H
I.L. 40-226
Sub 4
1611C23
Sheet 3 of 3
Version 1.00
APPENDIX H
I.L. 40-226
Sub 2
1612C20
Sheet 1 of 4
Figure H-3a: Analog Input Module Schematic
122
I.L. 40-226
APPENDIX H
Version 1.00
Sub 2
1612C20
Sheet 2 of 4
Figure H-3b: Analog Input Module Schematic
123
Version 1.00
APPENDIX H
I.L. 40-226
Sub 2
1612C20
Sheet 3 of 4
Figure H-3c: Analog Input Module Schematic
124
I.L. 40-226
APPENDIX H
Version 1.00
Sub 2
1612C20
Sheet 4 of 4
Figure H-3d: Analog Input Module Schematic
125
Notes
126
Version 1.00
I.L. 40-226
MODEM MODULE
APPENDIX I
Schematic - - - - - - - - - - - - - - - - - - - - 1612C73
Component Location Drawing - - - - - - 1612C01
1.1
ARCHITECTURE
The block diagram of this module is shown in Figure I-1, page 132.
1.2
CPU, I/O AND PROGRAM MEMORY
The CPU is a TMS320C25 Digital Signal Processor (U24). It functions as a high speed control
microprocessor. Its purpose is to control all functions of the Modem module via software instructions. The clock is a crystal (Y1) which operates at 18 MHz, but the CPU internally divides this
by four, so its instruction cycle clock is 4.5 MHz (single cycle instructions execute in 222 nanoseconds).
U1 and U2 are high-speed EPROMS that contain the program for the CPU. Each EPROM is 8
bits wide, but the two together supply 16 bit instructions, which are needed by the 16 bit CPU.
U1 supplies the least significant 8 bits (D0 thru D7); U2 supplies the most significant 8 bits (D8
thru D15). These EPROMS are addressed by CPU A0 through A11, which map program code
into the first 4K of CPU program memory.
When the CPU fetches an instruction from the EPROMS, it drives PS* and STRB* low and it
drives R/W* high; OR gates then enable the EPROM CE* inputs, and EPROM drive the CPU
data bus.
The CPU has three address mapping modes. All RAM is within the CPU IC and this RAM has
its own address map separate from program and I/O memory maps. As mentioned above, program memory is in external EPROMS which are mapped to the lowest 4K addresses. I/O and
program memory share the lowest eight address lines.
The CPU communicates with the Modem, the inputs and outputs from/to the Microprocessor
module, and various on-card functions via I/O operations. An I/O bus operation takes place
when IS* goes low; R/W* controls the direction of data flow and the STRB* strobes the data at
the appropriate time of the I/O instruction cycle. Some I/O devices (that the CPU communicates
with) are too slow to operate at full CPU speed. Therefore, one wait state is generated during
each I/O operation. This is done by ORing IS* and MISC* to the READY input.
The 24 line-programmable peripheral interface I/O devices need a separate RD* and WR* line;
U20.1 thru U20.4 and U21.1 decode the CPU IS*, STRB* and R/W* lines so that an RD* will be
asserted when the CPU wants to strobe input data. WR* will be asserted when the CPU wants
to strobe output data.
I/O port addressing is accomplished by decoder U19. When IS* is low, then the CPU address
lines (A0 thru A2) are decoded to one out of eight I/O device select lines. I/O ports 0 and 7 are
used to strobe the watchdog timer (covered later). I/O port 1 communicates with 24 line-
127
I.L. 40-226
Version 1.00
programmable peripheral interface U6; I / 0 port 0 communicates with 24 line-programmable peripheral interface U5, and I/O ports 2,3 and 4 communicate with the 9600 bps Modem.
APPENDIX I
NOTE: * This is a “Low True Signal”
1.3
WATCHDOG TIMER
The purpose of the watchdog timer is to reset the CPU and the 9600 bps Modem if the microprocessor program crashes. It does this within 1 millisecond of a program crash. At least once
each 500 microseconds, a properly running program will first access I/O port 0 then port 7.The
port 0 access will clock dual D flip-flop U16.1 thru U18.1. This will cause Q of U16.1 and D of
U16.2 to go high. A port 7 access will clock U16.2 through U18.2; Q of U16.2 will then go high.
After a non-critical couple of microseconds, controlled by R1 and C1, the output of U17.1 will
go low, which will reset both flip-flops of U16; Q of U16.2 will go low; then, after a couple of microseconds, the output of U17.1 will return to the normal high state.
When 17.1 goes low, it resets counter U22 thru U17.4; U22 is a 14 stage ripple counter driven
from the CPU at 4.5 MHz clock output. If the port 0/port 7 access sequence takes place frequently enough, then U22 will be reset before its Q output can go high. If the program crashes
and the port access sequence stops, then Q12 will go high in 455 microseconds, Q13 in 910
microseconds and Q14 in 1820 microseconds. P4 is factory set to one of these Q outputs.
A Q output from U22 will cause inverter U18.3 to rapidly discharge C2. Prior to that, one input
of U17.2 was low, so U17.2 was not resetting the CPU or resetting U22. Also, one input of
U17.2 is low when the U22Q output is high, which allows enough time for full discharge of C2.
When the Q output of U22 returns low, the output of U17.2 will go low. This will reset the CPU,
the Modem and U22 through U17. It will also apply a MRESET* to pin 22C of P3 to notify the
Microprocessor module of a reset.
1.4
ADDRESSING THE I/O DEVICES
CPU data busses are buffered from I/O data and address busses, by U23 and U15, respectively. The lower 8 data bits are bi-directionally buffered by U23 (U23 is only active during an I/O
operation). Its OE* line is driven by CPU IS*. The CPU R/W* line connects to U23 DIR to control
the direction in which I/O data moves.
The CPU communicates with three I/O devices:
• Modem (Rockwell R96DP)
• Programmable Peripheral Interface U5 (82C55) that controls the Rockwell Modem
• PIP U6 (82C55) that sends/receives data to/from the Microprocessor
The CPU must first set the address lines of the I/O device that it will access. U15 latches data
on CPU data lines D8 through D11 when CPU output is sent to I/O port 5. This sets 82C55 address lines A0 and A1 as well as Modem module address lines RS0 thru RS3. The I/O device
address remains at the Q outputs of U15 until changed by another port 5 output instruction.
Therefore, to communicate with one of the three I/O devices, the CPU must first set an address
via an output port 5 instruction (D8 thru D11 is the address), then do a port input or port output
operation to the device (D0 thru D7) to transfer the data.
128
Version 1.00
MODEM INTERFACE
A detailed description of the Modem (Rockwell R96DP) may be found in the following documents:
APPENDIX I
1.5
I.L. 40-226
• “Communications Products Data Book”
• “Quality of Received Data for Signal Processor-Based Modems”
• “Modem Interface Specifications”
• “Interface Guide, R96 DP Modem Functional Characteristics”
The Modem operates in the 9600 bps, ITU V.29 mode, summarized as follows:
• Carrier Frequency is 1700 Hz
• The data stream to be transmitted, in 6 bit frames (as shown in 8. Serial Data Protocol) at
9600 bps, is divided into groups of four consecutive data bits (quadbits). The first bit (Q1) is
used to determine the signal element amplitude to be transmitted. The second (Q2), third
(Q3) and fourth (Q4) bits are encoded as a phase change relative to the phase of the immediately preceding element (see Table I-1, page 131). The relative amplitude of the transmitted signal is determined by the first bit (Q1) of the quad bit, and by the absolute phase of the
signal element (see Table I-2, page 131). The absolute phase diagram of transmitted signal
elements, at 9600 bps, is shown in Figure I-2, page 133. The quad bits are decoded, at the
receiver, and the data bits are reassembled in the correct order.
The Modem is controlled and read through a number of addressable registers. The CPU sends
data to the Modem registers to execute commands from the Microprocessor module. The CPU
also monitors Modem registers to determine the quality of the received signal.
In order to communicate with the Modem registers, the CPU first sets the RS0 thru RS3 addresses by doing an output to port 5. The CPU then does an input or an output to port 2, 3 or
4 to activate Modem chip select line CS0*, CS1* or CS2*, respectively. An RD* at the output
of U20.3 is inverted by U3.2 to be compatible with the Modem READ line.
The Modem’s request RTS* input is controlled by U5 PB3. This turns the transmitted signal on/
off. The Modem RLSD* output is active if the received signal is detected. It is monitored by U5
PA3. The Modem is supplied by +5V, +12V and -12V.
A small test socket (PO2) on the PC board will accept a cable from the eye pattern generator
board. The eye pattern generator is only needed for factory testing.
Modem TXA and RXA are transmitter tone output and receiver tone input lines, respectively.
TXA is 600 ohms, but RXA is high impedance and is terminated by R6. These lines appear at
the REL 356 interface connector.
The R96DP serial input and output lines (RXD and TXD) transfer data from/to the CPU via U5.
Port A of U5 is configured for input to the CPU and port B is output from the CPU. Port A reads
Modem RXD, transmit and receive bit and baud clocks, CTS* and RLSD*. Port B drives Modem
TXD, RTS* and POR (Modem reset line). Port B also resets the Modem interrupt flip-flops and
forces a MRESET* to the REL 356 through U18.4.
129
APPENDIX I
I.L. 40-226
Version 1.00
The Modem transmit clock (TDCLK) interrupts the CPU when it is time to load a new bit to TXD.
It does this by clocking D flip-flop U26.1 through inverter U3.4. The Q* output of U26.1 then interrupts CPU INT1*. The transmit clock interrupt handler (software) will then reset U26.1. The
Modem receive clock (RDCLK) interrupts the CPU when it is time to read a new bit at RXD. It
does this by clocking D flip-flop U26.2. The Q* output of U26.2 then interrupts CPU INTO*. The
receive clock interrupt handler (software) will then reset U26.2.
1.6
DIGITAL INTERFACE TO MICROPROCESSOR MODULE
The Digital Interface (82C55, U6) feeds data to the Microprocessor module and receives data
from the Microprocessor module. The device is programmed for output on port A and input on
port B. The lower nibble of port C is input and the upper nibble of port C is output. Data OD0
through OD7, coming from the microprocessor, drives port B of U6. The CPU can read the data
anytime by inputting from that port. However, the microprocessor can force a read by pulsing
the DATAVAL line. This clocks D flip-flop U9.1. The Q* output goes low and activates CPU interrupt INT2*. After the CPU recognizes the interrupt, it will pulse U6, PC4 low which will reset
U9.1 and remove the interrupt.
OC0 and OC1 are control lines from the microprocessor. They are read by the CPU when it
inputs from the lower four bits of U13, port C. OC0 indicates if OD0 through OD7 is relay data
or setting up information. OC0 will be checked by the CPU whenever a DATAVAL strobe is detected. OC1 controls the output latch (U7 or U8) that will drive data lines ID0 through ID7 going
to the microprocessor. The eight output bits come from U6, port A. This octet can either be relay
data or can be signal-to-noise ratio. Relay data is latched into U8 by pulsing U6, PC7. S / N
data is latched into U7 by pulsing U6, PC6. If OC1 is low, then U8 outputs are enabled. If OC1
is high, then U7 outputs are instead enabled. In this way, the microprocessor can select which
type of data to read without interrupting the DSP CPU.
PINT will be pulsed high when appropriate (controlled by software). This is done by the CPU
pulsing U6, PC5 high. MRESET* is pulled low when the CPU reset line is forced low or when
software drives U5 port B5 high.
1.7
TONE SIGNAL LEVEL DETECTORS
The Modem transmitter output is amplified by U10.1 and rectified by the linear operational rectifier consisting of U10.2, U10.3 and associated components. This amplifier/rectifier will output
+5.0 Vdc at TXCHL for a 0 dBm Modem output. The dc output is approximately proportional to
Modem tone output voltage level below 0 dBm. The rectified output is filtered by C37.
Modem receive input is amplified by U11.2 and rectified by the linear operational rectifier, consisting of U11.1, U10.4 and associated components. This amplifier/rectifier will output +5.0 Vdc
at RXCHL for a 0 dBm Modem input. The dc output is approximately proportional to Modem
tone input voltage level below 0 dBm.
130
Version 1.00
I.L. 40-226
Q2
Q3
Q4
Phase Change *
(Degrees)
0
0
0
0
1
1
1
1
0
0
1
1
1
1
0
0
1
0
0
1
1
0
0
1
0
45
90
135
180
225
270
315
*
Table I-2
FIRST DATA BIT DETERMINES AMPLITUDE
Absolute Phase
(Degrees)
0, 90, 180, 270
45, 135, 225, 315
Q1
Relative Signal
Element Amplitude
0
3
1
5
0
√2
1
3√2
APPENDIX I
Table I-1
SECOND, THIRD AND FOURTH DATA BITS
DETERMINE PHASE CHANGE
The phase change is the actual on-line
phase shift in the transition region from
the center of one signaling element to the
center of the following signalling element.
131
Version 1.00
APPENDIX I
I.L. 40-226
EPROM
U1, 2
80C55
PPI
U24
80C55
PPI
R96D
Modem
U5
U25
Watchdog Timer
U16, 17, 18, 22
U10.1, 10.2, 10.3
0-5V
TX Level
U11.1, U11.2, U10.4
0-5V
RX Level
TX
RX
To Microprocessor Module
U6
To Communication Channel
via
Interconnect Module
DSP
CPU
I/O
ADDR
&
DATA
BUFFER
U15,23
ESK00056
Figure I-1: REL 356 Modem Block Diagram
132
I.L. 40-226
APPENDIX I
Version 1.00
90°
5
135°
45°
3
3√ 2
√2
1
0° Absolute
180°
1
3
5
315°
225°
270°
ESK00057
Figure I-2: Modulation Diagram at 9600 bps
133
APPENDIX I
I.L. 40-226
134
Figure I-3: REL 356 Modem Component Location Diagram
Version 1.00
Sub 5
1612C01
Version 1.00
Sub 2
1612C73
Page 1 of 3
I.L. 40-226
135
Figure I-4a: REL 356 Modem Schematic
APPENDIX I
APPENDIX I
I.L. 40-226
136
Figure I-4b: REL 356 Modem Schematic
Version 1.00
Sub 2
1612C73
Page 2 of 3
Version 1.00
Figure I-4c: REL 356 Modem Schematic
APPENDIX I
I.L. 40-226
137
Sub 2
1612C73
Page 3 of 3
Notes
138
Version 1.00
I.L. 40-226
CODEC MODULE
APPENDIX J
Schematic - - - - - - - - - - - - - - - - - - - - 1615C34
Component Location diagram - - - - - - 1615C33
1.8
Architecture
The block diagram is shown in Figure J-1 below.
1.9
Circuit Description
1.9.1
CPU, Program Memory and I/O
U2 is the TMS320C25 DSP CPU. It functions as a high speed control microprocessor. Clock is
crystal Y1 which operates at 20 MHz, but the CPU internally divides this by four so its instruction
cycle clock is 5.0 MHz (single cycle instructions execute in 200 nanoseconds).
U3 and U4 are high-speed EPROMS that contain the program for the CPU. Each EPROM is 8
bits wide, but the two together supply 16 bit instructions which are needed by the 16 bit CPU.
U4 supplies the least significant 8 bits of an instruction (D0 through D7) and U3 the most significant 8 bits (D8 through D15). These EPROMS are addressed by CPU A0 through A11 which
map program code into the first 4K of CPU program memory.
The CPU has three address mapping modes. All RAM is within the CPU IC and this RAM has
its own address map separate from program and I/O memory maps. I/O and program memory
share the lowest sixteen addresses.
DSP
CPU
EPROM
U3,4
COUNTER/
TIMER
U6



Parallel
Interface
to
Microprocessor
Module
80C55
PPI
U7
U2
WATCHDOG
TIMER
U5
EPLD
TX
U1
RX



Serial
Data
To/From
DCI Module
Figure J-1: Block Diagram
139
I.L. 40-226
Version 1.00
APPENDIX J
The CPU uses I/O operations to communicate data from/to the REL 356, EPDL functions and
a programmable counter/timer. an I/O bus operation takes place when IS* goes low. R/W* controls direction of data flow and STRB* strobes the data at the appropriate time of the I/O instruction cycle. Some I/O devices that the CPU communicates with are too slow to operate
at full CPU speed. Therefore, one wait state is generated during each I/O operation. This is
done by the EPLD ORing IS* and REL 356* to the READY input.
The 24 line programmable peripheral interface I/O device U7 and Programmable counter/timer
U6 provide parallel interface to microprocessor module.
1.9.2
Watchdog Timer
Purpose of the watchdog timer is to reset the CPU if the microprocessor program crashes. It
does this within 1 millisecond. At least once each 500 microseconds, a properly running program will first activate I/O address 0 then I/O address 12. This order will be decoded in the
EPLD which will in turn apply a reset pulse to ripple counter U5. If after approximately 1 ms the
reset pulse is not applied (program has crashed), then Q13 output of U5 will go high which will
reset the CPU and also apply MRESET* to the REL 356 via the EPLD (U1).
1.9.3
Interface to Microprocessor Module
82C55, U7 feeds data and receives data from the µP module.
1.9.4
56/64 kbps Serial Data Section
Parallel to serial data conversion, serial data encoding and decoding, clock recovery from the
received serial data and all other aspects of serial data transmission and reception are handled
in U1.
U1 is a programmable logic device (EPLD).
The two signals TX (Transmit Data) and RX (Receive Data) interface to Digital Communication
Interface module (DCI).
1.10
Serial Data Protocol
1.10.1 Data Rate
64 or 56 kb/sec (64,000 or 56,000 bits per second) selectable via REL 356 relay setting.
1.10.2 Data Encoding
Non-return to ZERO Inverted (NRZI). Binary “I” is encoded as a transition on the beginning of
a bit frame,. Binary “0” is encoded as no transition.
140
Version 1.00
Figure J-2: CODEC Module Schematic
APPENDIX J
I.L. 40-226
141
Sub 3
1615C34
Sheet 1 of 2
APPENDIX J
I.L. 40-226
142
Version 1.00
Figure J-2: CODEC Module Schematic
Sub 3
1615C34
Sheet 2 of 2
Version 1.00
Sub 2
1615C33
I.L. 40-226
Figure J-3: REL 356 CODEC Module
143
APPENDIX J
APPENDIX J
144
NOTES
Version 1.00
I.L. 40-226
DIGITAL COMMUNICATION INTERFACE MODULE
APPENDIX K
Schematic - - - - - - - - - - - 1615C44, 1618C52, 1618C55
Component Location - - - - 1615C43, 1615C53, 1618C56
1.1
CIRCUIT DESCRIPTION
There are several options of the REL 356 Digital Communications interface.
• DCI Assy. 1614C98G01 - Fiber Optic option, 820 nm, ST connector, multi-mode cable*
• DCI Module assembly- - - - - - - - - - - - - - - - - - - - - - - - - - - - -1615C43G01
• DCI Module schematic diagram - - - - - - - - - - - - - - - - - - - - - - - - -1615C44
• DCI Assy. 1614C98G02 - 56/64 Kbps Direct Digital Option, Electrical STD RS422/RS485
Mechanical STD RS530. Connector J1 is a male DB-25 plug as required for Data Terminal
Equipment (DTE).
• DCI Module assembly- - - - - - - - - - - - - - - - - - - - - - - - - - - - -1615C43G02
• DCI Module schematic diagram - - - - - - - - - - - - - - - - - - - - - - - - -1615C44
• DCI Assy. 1614C98G06 - fiber Optic option, 1300nm, ST connector, single-mode cable,
short reach*
• Single-mode module assembly - - - - - - - - - - - - - - - - - - - - - -1618C53G01
• Single-mode module schematic diagram - - - - - - - - - - - - - - - - - -1618C52
• Optical module assembly - - - - - - - - - - - - - - - - - - - - - - - - - - 1618C5G01
• Optical module schematic diagram - - - - - - - - - - - - - - - - - - - - - 16118C55
• DCI Assy. 1614C98G07 - Fiber Optic option, 1300nm, ST connector, single-mode cable, medium reach*
• Single-mode module assembly - - - - - - - - - - - - - - - - - - - - - -1618C53G02
• Single-mode module schematic diagram - - - - - - - - - - - - - - - - - -1618C52
• Optical module assembly - - - - - - - - - - - - - - - - - - - - - - - - - - 1618C5G02
• Optical module schematic diagram - - - - - - - - - - - - - - - - - - - - - 16118C55
• DCI Assy. 1614C98G08 - Fiber Optic option, 1300nm, ST connector, single-mode cable, medium reach*
• Single-mode module assembly - - - - - - - - - - - - - - - - - - - - - -1618C53G03
• Single-mode module schematic diagram - - - - - - - - - - - - - - - - - -1618C52
• Optical module assembly - - - - - - - - - - - - - - - - - - - - - - - - - - 1618C5G03
• Optical module schematic diagram - - - - - - - - - - - - - - - - - - - - - 16118C55
These DCI Assemblies connect to the rear of the REL 356 relay system via 4 pin header P1.
The TX (P1.3) & RX (P1.4) signals, routed to the Codec module are TTL level output & input
signals respectively.
* See section 2.5, on page 10 for details
145
Version 1.00
APPENDIX K
I.L. 40-226
Figure K-1: Internal Schematic
(Direct Digital, Fiber Optic Multi-mode, 820 nm)
146
Sub 2
1615C44
I.L. 40-226
APPENDIX K
Version 1.00
Sub 2
1615C43
Figure K-2: Component Location
147
APPENDIX K
I.L. 40-226
148
Figure K-3: Internal Schematic
(Direct Digital, Fiber Optic, Single-mode)
Version 1.00
Sub 1
1618C52
I.L. 40-226
APPENDIX K
Version 1.00
P2
P3
L3
R2
R3
R15
R14
U1
C1
L2
+
P1
C5
B
C
R1
E
C10
D1
R16
Q4
C9
Sub 1
1615C53
Figure K-4: Component Location
149
APPENDIX K
I.L. 40-226
150
Figure K-5: Internal Schematic
(Direct Digital, Fiber Optic, Single-mode)
Version 1.00
Sub 1
1615C55
I.L. 40-226
APPENDIX K
Version 1.00
LE1
C2
L2
C1
C3
C4
LE2
C5
+
+
P2
L1
P3
Sub 1
1615C56
Figure K-6: Component Location
151
Notes
152
Version 1.00
I.L. 40-226
ACCEPTANCE TESTS
INTRODUCTION
APPENDIX L
1.2
The acceptance test of the relay verifies the operation of four subsystems.
• Analog Input
• Contact Input
• Relay Output
• Communication
Additionally, Phase Comparison functional tests (simulating internal faults) are performed.
1.3
EQUIPMENT NEEDED
Qty.
Description
1
REL 356 Relay
1
Doble, Multi-amp or equivalent 3-Phase Test System
1.4
TEST SETUP
1.4.1
Current and voltage Inputs
Connect the Relay Test System to REL 356 Relay, per application diagram (Figure 1-4).
Do not leave fault currents with trip relays energized for long periods of time.
1.4.2
Power
Connect the primary and secondary dc power as shown on Figure 1-4. Consult the relay nameplate for rated voltage.
NOTE:
1.5
Before turning on dc power check jumper positions on the Contact Input and
Microprocessor modules. (See page 95 and page 99)
ANALOG INPUT AND FRONT PANEL METERING TEST
STEP 1
Turn on the primary and optional secondary dc input power if used. Make sure that the FREQ
setting matches the line frequency, and the RP setting is set to “NO” (Readout in secondary
values). The “Relay in Service” LED on the front panel should be lit.
STEP 2
NOTE:
All ac voltage & current phase angles in this document are referenced to
VA-G voltage (0 degrees). Positive angles LEAD VA-G, negative angles
LAG VA-G.
153
I.L. 40-226
Version 1.00
Fault impedance angles (FANG) are displayed as positive for inductive faults
and negative for capacitive.
APPENDIX L
Apply the following ac quantities to the relay:
V (volts)
Va =
Vb =
Vc =
/
Angle
I (amps) /
70 ∠0°
70 ∠-120°
70 ∠+120°
Ia
Ib
Ic
=
=
=
Angle
10 ∠-45°
10 ∠-165°
10 ∠+75°
Using the procedure described in Section 4.5.2, on page 40, read the following parameters:
VAG
∠VAG
VBG
∠VBG
VCG
∠VCG
IA
∠IA
IB
∠IB
IC
∠IC
=
=
=
=
=
=
=
=
=
=
=
=
70
0
70
-120
70
+120
10.0
-45
10.0
-165
10.0
+75
(VOLTS)
(DEG.)
(VOLTS)
(DEG.)
(VOLTS)
(DEG.)
(AMPS)
(DEG.)
(AMPS)
(DEG.)
(AMPS)
(DEG.)
Verify all metered values to be ± 5% on magnitude and ± 2 degrees on phase angle.
1.6
CONTACT INPUT SUBSYSTEM TEST
Make sure that the input voltage selection jumpers on the contact input module 1611C28 (See
Figure 1-2, on page 7 in Section 1, for Module Placement and Figure D-1, on page 96, in Appendix D for jumper location) correspond to the desired contact “wetting” voltage.
Apply the rated voltage across the terminals shown in the table below:
Description
DTT Key
STUB BUS
Diff Protection Disable
Target RESET
52b
Terminal
Terminal
Block
+
-
HEX
Digit
TB5
TB5
TB5
TB5
TB5
TB5
TB5
9
11
13
7
1
3
5
10
12
14
8
2
4
6
1
2
4
8
10
20
40
Using procedure described in Section 4.5.4.1, on page 41, verify proper response of the front
panel display to contact input status changes.
154
Version 1.00
RELAY OUTPUT SUBSYSTEM TEST
Using the procedure described in Section 4.5.4.2, on page 42, verify operation of relay output
subsystem. The relay contact wiring is shown on Block Diagram (Figure 1-4). Please note that
the Failure Alarm Relay (TB4, 5-6) has a normally closed contact.
1.7
COMMUNICATION SUBSYSTEM TEST
1.7.1
9600 bps Audio Tone Option
Make the following test connection on the rear of the relay:
TB4-11
TB4-12
to
to
TB4-13
TB4-14
This connects the Communication XMT pair to RCV pair.
STEP 1
Make sure that 52b contact input (TB-5 terminals 1-2) is de-energized.
Change the “OPBR” setting to “52B” to disable the open breaker code transmission. Change
the “ALDT” setting to “NO” since automatic delay time measurement is not possible with communication channel in a “Loopback” configuration. Turn the dc supply connected to the
REL 350’s dc (Battery) inputs “off” for 1 second & then back “on” again to re-initialize the modem’s “ALDT” setting on power-up sequence.
Change the “XMTR” setting to “-1” dBm. Press the “DISPLAY SELECT” key on REL 350 front
panel several times to select the “VOLTS/AMPS/ANGLE” mode. Use the FUNCTION RAISE/
LOWER keys to display the “XMTR” monitoring function. The transmitter output level is measured via the “XMTR” monitoring function should read between +2 an -5 dBm.
Change the “XMTR” setting to “-11” dBm. The transmitter output level as measured via the
“XMTR” monitoring function should read between -8 and -15 dBm.
Change the “XMTR” setting back to “-1” dBm. Use the “CHRX” monitoring function for indication
of the Channel receiver line status, “CHRX” should read “NORM”.
STEP 2
Temporarily disconnect the XMT to RCV jumper TB4-11 to TB4-13. The display CHRX should
change to CHTB (Channel Trouble).
STEP 3
Reconnect TB4-11 to TB4-13. The display CHRX should return to NORM after a short time delay.
1.7.2
56/64 KPBS Digital Communication Option
Make following Loopback connections on digital Communication Interface on the rear of the relay.
155
APPENDIX L
1.7
I.L. 40-226
I.L. 40-226
Version 1.00
• Fiber Optic Version (820 nm)
Using 50/100 µm or larger Multi Mode Cable with ST connectors at each end, connect Fiber
Optic Transmitter to Fiber Optic Receiver.
APPENDIX L
• Fiber Optic Version (1300 nm)
Using 9/125 µm, Single Mode Cable with ST connectors at each end, connect Fiber Optic
Transmitter to Fiber Optic Receiver.
NOTE:
For Medium and Long Reach Options (DCI assemblies G07 and G08) the Optical Power Attenuator must be used to limit the Receiver Input Power to maximum of -11 dBm to prevent receiver saturation.
• Direct Digital Version (RS422/RS530)
Connect Pin 2 to Pin 3 (TXA to RXA)
Connect Pin 14 to Pin 16 (TXB to RXB)
Pin placement on DB-25 connector used is as follows:
14
15
16
1
2
3
4
25
13
Step 1
Set:
UNID
KBPS
XCLK
LPBK
=
=
=
=
0
64
INT
YES
Make sure that 52b contact input (TB-5 terminals 1-2) is de-energized.
Change the “OPBR” setting to “52B” to disable the open breaker code transmission. Change
the “ALDT” setting to “NO” since automatic delay time measurement is not possible with communication channel in a “Loopback” configuration. Turn the dc supply connected to the
REL 350’s dc (Battery) inputs “off” for 1 second & then back “on” again to re-initialize the modem’s “ALDT” setting on power-up sequence.
The Monitoring Function CHRX (Received Line Status) should read NORM.
STEP 2.
Disconnect above described Loopback Connections. The display CHRX should read
CHTB (Channel Trouble).
156
Version 1.00
I.L. 40-226
1.8
FUNCTIONAL TESTS – CURRENT DIFFERENTIAL SYSTEM
1.8.1
9600 bps Audio Tone Option
The purpose of these tests is to verify the proper operation of the current differential. Having
followed all the steps in section 1. 7.1, on page 155, make sure that the following test connections on the rear of the relay are made:
TB4-11 to TB4-13
TB4-12 to TB4-14
The REL 356 modem interface has nominal time delay of approximately 10.8 milliseconds. The
LDT can be set to 10.8 msec to simulate internal faults (local and remote currents in phase).
Make sure that NORM is the received signal and the following settings are made in addition to
settings specified in section 1.7.1:
1.8.1.1
1
FDAT = TRIP
6
C2 = 0.25
2
IPH = OUT
7
OTH = 0.5
3
IGH = OUT
8
LPBK = YES
4
C0 = 1.15
9
ALDT = NO
5
C1 = 0.1
10
LDT = 10.8
Internal Faults
Apply all types of faults with currents greater than 4.0 amps to be sure the system trips. The
system should trip for all currents applied. For example, to simulate an AG fault, apply:
Ia
Ib
Ic
= 4.0 amps
= 0.0 amps
= 0.0 amps.
WARNING
The user should verify that Standing Relay Trip SRT = NO in the Test Mode Function (see
4.5.4) prior to putting the REL 356 in service.
157
APPENDIX L
STEP 3.
Reconnect the Loopback Connection. The display CHRX should return to NORM after
a short time delay.
I.L. 40-226
1.8.2
Version 1.00
56/64 kbs Digital Comm Option
APPENDIX L
The purpose of these tests is to verify the proper operation of the current differential. Having
followed all the steps in section 1. 7.2, on page 155, make sure that the Loopback Connections
are made.
The REL 356 CODEC interface has nominal time delay of approximately 1.3 milliseconds. The
LDT can be set to 1.3 msec to simulate internal faults (local and remote currents in phase).
Make sure that NORM is the received signal and the following settings are made in addition to
settings specified in section 1.7.2.
1.8.2.1
1
FDAT = TRIP
6
C2 = 0.25
2
IPH = OUT
7
OTH = 0.5
3
IGH = OUT
8
LPBK = YES
4
C0 = 1.15
9
ALDT = NO
5
C1 = 0.1
10
LDT = 1.3
Internal Faults
Apply all types of faults with currents greater than 4.0 amps to be sure the system trips. The
system should trip for all currents applied. For example, to simulate an AG fault, apply:
Ia
Ib
Ic
=
=
=
4.0 amps
0.0 amps
0.0 amps
WARNING
The user should verify that Standing Relay Trip SRT = NO in the Test Mode Function (see
section 4.5.4, on page 41) prior to putting the REL 356 in service.
1.9
FUNCTIONAL TESTS – OPTIONAL BACKUP SYSTEM
For units that include the stepped distance backup system the following tests will functionally
test all the distance units provided.
Be sure that the connections recommended in section 8 are not in and the display shows CHTB
as the signal received. A channel trouble enables the backup system.
158
Version 1.00
I.L. 40-226
1.9.1
PANG =
75
Z2P
=
4.5
GANG =
75
T2P
=
0.1
ZR
3.0
Z2GF =
4.5
BKUP =
IN
Z2GR =
0.01
LOPB =
NO
T2G
=
0.1
FDOP =
IN
Z3P
=
7.0
FDOG =
IN
T3P
=
1.0
DIRU
=
ZSEQ
Z3GF =
7.0
IOM
=
0.5
Z3GR =
0.01
TOG
=
BLK
T3G
1.0
=
=
APPENDIX L
The following settings should be used:
Phase-to-ground Units
To calculate the apparent impedance seen by the relay the following formula applies:
Vxg
Zapp = -----------------------------------------------------------------+ ZR ∠GANG-PANG
I X 2-------------------------------------------------------3
where x is either phase a, b or c.
The above formula is rigorous and general. However, if a quick approximation of the current
required at different angles (Ø) is desired, the following formula applies:
V XG
I = -------------------------------------------------------------------------------------ZR – 1
Z 2GF cos ( PANG – φ ) 1 + ---------------3
For forward Zone 2 trips follow the following table for currents and voltages applied and compare the calculated impedance in the relay target data to the provided impedance in the table.
The displayed value should fall within ±5%. Also make sure that the trip times are within 100 to
132 milliseconds.
159
I.L. 40-226
Version 1.00
APPENDIX L
V
I
AG
Va = 30 ∠0˚
Vb = 69 ∠-120˚
Vc = 69 ∠+120˚
Ia = 4 ∠-75˚
Ib = 0˚
Ic = 0˚
BG
Va = 69 ∠0˚
Vb = 30 ∠-120˚
Vc = 69 ∠+120˚
Ia = 0˚
Ib = 4∠+165˚
Ic = 0˚
CG
Va = 69 ∠0˚
Vb = 69 ∠-120˚
Vc = 30 ∠+120˚
Ia = 0˚
Ib = 0˚
Ic = 4∠+45˚
Z
I
4.5
4.5
4.5
OR
Ia = 5.65 ∠-30˚
or 5.65 ∠-120˚
OR
Ib = 5.65 ∠+120˚
or 5.65 ∠+210˚
OR
Ic = 5.65 ∠0˚
or 5.65 ∠90˚
Zone 2 ground (Z2G) should operate in all of the above.
For reverse Zone 2 trips follow the next table:
V
I
AG
Va = 30 ∠0
Vb = 69 ∠-120
Vc = 69 ∠+120
Ia = 8 ∠+105
Ib = 0
Ic = 0
BG
Va = 69 ∠0
Vb = 30 ∠-120
Vc = 69 ∠+120
Ia = 0
Ib = 8∠-15
Ic = 0
CG
Va = 69 ∠0
Vb = 69 ∠-120
Vc = 30 ∠+120
Ia = 0
Ib = 0
Ic = 8∠-135
Z
No Trip
No Trip
No Trip
Change the setting Z2GR = 4.5 and repeat the Zone 2 Test.
V
AG
Va = 30 ∠0
Vb = 69 ∠-120
Vc = 69 ∠+120
BG
Va = 69 ∠0
Vb = 30 ∠-120
Vc = 69 ∠+120
CG
Va = 69 ∠0
Vb = 69 ∠-120
Vc = 30 ∠+120
160
I
Z
Ia = 4 ∠-30
or 4.0 ∠-75
or 4.0 ∠-100
Ib = Ic = 0
4.5
Ib = 4 ∠+120
or 4.0 ∠+165
or 4.0 ∠+210
Ia = Ic = 0
4.5
Ia = 4 ∠0
or 4.0 ∠+45
or 4.0 ∠+90
Ib = Ia = 0
4.5
Z
3.18
3.18
3.18
Version 1.00
I.L. 40-226
Zone 2 (Z2G) should operate for all of the above faults.
V
I
APPENDIX L
For forward Zone 3 trips outside of Zone 2 trips, apply the following quantities. Check the
apparent impedance as well as the trip time. The trip time should be 1.0 ±5% seconds.
Z app
AG
Va = 25 ∠0
Vb = 69 ∠-120
Vc = 69 ∠+120
Ia = 3 ∠-75
Ib = 0
Ic = 0
5.0 ∠75
BG
Va = 69 ∠0
Vb = 25 ∠-120
Vc = 69 ∠+120
Ia = 0
Ib = 3∠+165
Ic = 0
5.0 ∠75
CG
Va = 69 ∠0
Vb = 69 ∠-120
Vc = 25 ∠+120
Ia = 0
Ib = 0
Ic = 3∠+45
5.0 ∠75
The following table tests external forward faults outside Zone 3 reach.
V
I
AG
Va = 25 ∠0
Vb = 69 ∠-120
Vc = 69 ∠+120
Ia = 2 ∠-75
Ib = 0
Ic = 0
BG
Va = 69 ∠0
Vb = 25 ∠-120
Vc = 69 ∠+120
Ia = 0
Ib = 2∠+165
Ic = 0
CG
Va = 69 ∠0
Vb = 69 ∠-120
Vc = 25 ∠+120
Ia = 0
Ib = 0
Ic = 2∠+45
The system should not trip.
161
I.L. 40-226
Version 1.00
The following are external reverse faults.
APPENDIX L
V
I
AG
Va = 25 ∠0
Vb = 69 ∠-120
Vc = 69 ∠+120
Ia = 3.75 ∠+105
Ib = 0
Ic = 0
BG
Va = 69 ∠0
Vb = 25 ∠-120
Vc = 69 ∠+120
Ia = 0
Ib = 3.75∠-15
Ic = 0
CG
Va = 69 ∠0
Vb = 69 ∠-120
Vc = 25 ∠+120
Ia = 0
Ib = 0
Ic = 3.75∠-135
The system should not trip.
1.9.2
Phase-to-phase Unit
To calculate the apparent impedance seen by the relay for phase-to-phase faults the following
formula applies:
Zapp =
Vxy
-------------Ix – Iy
where x is phase a, b or c and y is the next lagging phase.
The above formula is rigorous and general. However, if a quick approximation of the current
required at different angles (Ø) is desired, the following formula applies:
V XY
I = ---------------------------------------------------------2 Z 2P ( cos ( Pang – φ ) )
162
Version 1.00
I.L. 40-226
The phase-to-phase unit is totally directional. For forward Zone 2 trips the following quantities
should be applied:.
I
AB
Va = 17.3 ∠0
Vb = 17.3 ∠-120
Vc = 69 ∠+120
Ia = 3.7 ∠-45
Ib = 3.7∠+135
Ic = 0
BC
Va = 69 ∠0
Vb = 17.3 ∠-120
Vc = 17.3 ∠+120
Ia = 0
Ib = 3.7∠-165
Ic = 3.7∠+15
CA
Va = 17.3 ∠0
Vb = 69 ∠-120
Vc = 17.3 ∠+120
Ia = 3.7∠-105
Ib = 0
Ic = 3.7∠+75
Z app
APPENDIX L
V
4.05∠75
4.05∠75
4.05∠75
Zone 2 Phase (Z2P) unit should operate for all of the above tests. The trip times should be
greater than 100 milliseconds.
For Zone 3 trips outside Zone 2 reach, the following quantities should be applied:
V
I
AB
Va = 35 ∠0
Vb = 35 ∠-120
Vc = 69 ∠+120
Ia = 5 ∠-45
Ib = 5∠+135
Ic = 0
BC
Va = 69 ∠0
Vb = 35 ∠-120
Vc = 35 ∠+120
Ia = 0
Ib = 5∠-165
Ic = 5∠+15
CA
Va = 35 ∠0
Vb = 69 ∠-120
Vc = 35 ∠+120
Ia = 5 ∠-105
Ib = 0
Ic = 5∠+75
Z app
6.12∠75
6.12∠75
6.16∠75
The REL 356 should trip and the tripping time should be 1.0 ±5% seconds. Zone 3 phase (Z3P)
unit should operate for all of the above tests.
163
I.L. 40-226
Version 1.00
For forward external faults apply the following quantities:
APPENDIX L
V
I
AB
Va = 35 ∠0
Vb = 35 ∠-120
Vc = 69 ∠+120
Ia = 4 ∠-45
Ib = 4∠+135
Ic = 0
BC
Va = 69 ∠0
Vb = 35 ∠-120
Vc = 35 ∠+120
Ia = 0
Ib = 4∠-165
Ic = 4∠+15
CA
Va = 35 ∠0
Vb = 69 ∠-120
Vc = 35 ∠+120
Ia = 4∠-105
Ib = 0
Ic = 4∠+75
The REL 356 should not trip.
The following quantities simulate reverse phase-to-phase faults:
V
I
AB
Va = 35 ∠0
Vb = 35 ∠-120
Vc = 69 ∠+120
Ia = 4 ∠+135
Ib = 4∠-45
Ic = 0
BC
Va = 69 ∠0
Vb = 35 ∠-120
Vc = 35 ∠+120
Ia = 0
Ib = 4∠+15
Ic = 4∠-165
CA
Va = 35 ∠0
Vb = 69 ∠-120
Vc = 35 ∠+120
Ia = 4 ∠+75
Ib = 0
Ic = 4∠-105
The REL 356 should not trip.
WARNING
The user should verify that Standing Relay Trip SRT = NO in the Test Mode Function (See
Section 4.5.4, on page 41) prior to putting the REL 356 in service.
164
Version 1.00
OUT OF STEP SYSTEM FUNCTIONAL TESTS
For systems equipped with OST logic the following settings may be used to check the OST logic
in REL 356:
PANG
GANG
ZR
BKUP
LOPB
FDOP
FDOG
DIRU
IOM
TOG
Z2P
T2P
Z2GF
Z2GR
=
=
=
=
=
=
=
=
=
=
=
=
=
=
65
65
3.0
OUT
NO
IN
IN
ZSEQ
0.5
BLK
8.5
0.1
6.5
0.01
T2G
Z3P
T3P
Z3GF
Z3GR
T3G
OST
OSB
RT
RU
OST1
OST2
OST3
OSOT
=
=
=
=
=
=
=
=
=
=
=
=
=
=
APPENDIX L
1.10
I.L. 40-226
0.1
11.0
.2
11.0
0.01
.2
WAYO
BOTH
2.0
4.0
2
3
3
100
The situation is described more accurately in the sketch of Figure 3-4, on page 27.
NOTE:
These tests are optional and require programing Computer Aided, Multiamp or Doble test equipment.
In the R-X diagram, the positions shown in Figure 3-5, on page 28, correspond to the following quantities:
V (Volts)
I (Amps)
1
Va = 69 ∠0
Vb = 69 ∠-120
Vc = 69 ∠+120
Ia = 5 ∠-5
Ib = 5∠-125
Ic = 5∠+115
2
Va = 20 ∠0
Vb = 20 ∠-120
Vc = 20 ∠+120
Ia = 4.5 ∠-25
Ib = 4.5∠-145
Ic = 4.5∠+95
3
Va = 20 ∠0
Vb = 20 ∠-120
Vc = 20 ∠+120
Ia = 6 ∠-65
Ib = 6∠+175
Ic = 6∠+55
4
Va = 20 ∠0
Vb = 20 ∠-120
Vc = 20 ∠+120
Ia = 4 ∠-100
Ib = 4∠+140
Ic = 4∠+20
5
Va = 69 ∠0
Vb = 69 ∠-120
Vc = 69 ∠+120
Ia = 6.5 ∠-105
Ib = 6.5∠+135
Ic = 6.5∠+15
165
NOTES
The apparent impedances seen by the relay in each of the above positions and the expected
operation of the inner (21 BI) and outer (21 BO) blinders are the following:
POS
Z app
21 BI
41 BO
1
13.8 ∠5
No
No
2
4.47 ∠25
No
Yes
3
3.33 ∠65
Yes
Yes
4
5.00 ∠100
No
Yes
5
10.6 ∠105
No
No
The following tests make sure that the transmitter and receiver are connected in the unit.
NOTE:
166
Make sure that the loopback connections described in 1.7.1, page 155 and 1.7.2
on page 155 are made. Also, the metered value CHRX displayed should be
NORM.
Version 1.00
I.L. 40-226
1.1
COMMUNICATION PORT(S) USE
1.1.1
Introduction
REL 356 can be communicated with for target data, settings, etc., through the man-machine
interface (MMI), The relay can also be communicated with via the communication (comm.)
ports. Comm port communications, provides the user with more information than is available
with the MMI. For example, all 16 targets are available and a more friendly user interface for
settings can be accessed (all settings are displayed on a single screen on the user’s PC). This
section will provide the details of the comm port options, personal computer requirements, connecting cables and all information necessary to communicate with and extract data from the
relay. Additional communications details are contained in IL 40-603, (RCP) Remote Communication Program.
NOTE:
1.1.2
Earlier versions of RCP program refer to REL 356 as MSPC.
Communication Port Options
REL 356 is supplied with a rear communications port. If the network interface is not specified,
a RS-232C (hardware standard) communications port is supplied. Network interface comm.
port option allows the connection of the relay with many other devices to a 2-wire network. A
detailed discussion of networking capabilities can be found in AD 40-600, Substation Control
and Communications Application Guide.
RS-232C, rear comm. port is of the removable, Product Operated Network Interface (PONI)
type and is available in two styles. One is identified by a 25 pin (DB-25S) female connector, it
is usually black and has a single data comm. rate of 1200 bps. The second style is identified
by a 9 pin (DB-9P) male connector and externally accessible dip switches (next to the connector) for setting the communication data rate. This port option is always black in color, can be
set for speeds of 300, 1200, 2400, 4800, or 9600 bps (see Table M-2, on page 170) and offers an
option for IRIG-B time clock, synchronization input.
1.1.3
Personal Computer Requirements
Communication with the relay requires the use of Remote Communication Program (RCP) regardless of the comm. port option. RCP is supplied by ABB Relay Division and is run on a personal computer (PC).
To run the program requires an IBM AT, PC/2 PC or true compatible with a minimum of 640
kilobytes of RAM, 1 hard disk drive, a RS-232C comm. port and a video graphics adapter card.
The PC must be running Version 3.3, or higher, MS-DOS.
1.1.4
Connecting Cables
With each comm. port option the connecting cable requirement can be different. Also, connecting directly to a PC or connecting to a modem, for remote communication, affects the connecting cable requirements. Table M-1, on page 170, provides a summary of a plug pin
assignments, pins required and cable connectors.
167
APPENDIX M
COMPUTER COMMUNICATIONS
I.L. 40-226
Version 1.00
APPENDIX M
Some terminology will be defined to aid the user in understanding cable requirements in Table
M-1 (page 170). Reference, is often made to the “RS-232C” standard, for data communication.
The RS-232C standard describes mechanical, electrical, and functional characteristics. This
standard is published by the Electronics Industry Association (EIA) and use of the standard is
voluntary but widely accepted for electronic data transfer. ABB relay communications follows
the RS-232C standard for non-network data communication.
Although the RS-232C standard does not specify a connector shape, the most commonly used
is the “D” shape connector. As stated in Section 1.1.2 , on page 167, all ABB relay communication connectors are of the “D” shape (such as DB-25S).
Data communication devices are categorized as either Data Terminal Equipment (DTE) or Data
Communication Equipment (DCE). A DTE is any digital device that transmits and/or receives
data and uses communications equipment for the data transfer. DCE’s are connected to a communication line (usually a telephone line) for the purpose of transferring data from one point to
another. In addition to transferring the data, DCE devices are designed to establish, maintain,
and terminate the connection. As examples, a computer is a DTE device and a modem is a
DCE device.
By definition the connector of a DCE is always female (usually DB-9S or 25S). Similarly, DTEs
are always male (usually DB-9P or 25P). These definitions apply to the equipment being connected and to the connectors on the interconnecting cables.
One additional piece of hardware that is required, in some applications, is a “null” modem. Null
modem’s function is to connect the transmit line (TXD), pin 2 by RS-232C standard, to the receive line (RXD), pin 3. A null modem is required when connecting like devices. That is DTE to
DTE or DCE to DCE. A DCE to DCE, example, where a null modem is required, is the connection of a 25 pin, PONI to a modem.
A null modem function can be accomplished in the connecting cable or by separate null modem
package. That is, by using a conventional RS-232C cable plus a null modem. One type of null
modem, available from electronics suppliers, is B & B Electronics Type 232MFNM.
1.1.5
Setting Change Permission and Relay Password
To gain access to certain communication port functions, the REL 356 must have the remote
setting capability permission SETR set to YES and knowledge of the relay password is required. All communications port functions listed below require SETR set to YES before the actions can be performed:
Update/Change Settings
Enable Local Settings (capability)
Disable Local Settings (capability)
Activate Output Relays (contact testing function)
Access control, both setting permission and password knowledge is required for all communication port options.
168
Version 1.00
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Using comm. port communications, the ability to change settings from the MMI can be disabled.The RCP, Password Menu Choice “Disable Local Settings” when selected, will block setting changes via the MMI. Blocking the front panel setting changes, may be useful for situations
in which the access to the relay cannot be secured from tampering by unauthorized persons.
Password:
When the REL 356 is received from the factory or if the user loses the relay password, a new
password can be assigned with the following procedure:
Turn off the relay dc supply voltage for a few seconds,
Restore the dc supply voltage and wait for the relay to complete the self check/start-up
routine, Using RCP, perform the Password Menu choice “Set Relay Password”,
Use the word “password” when prompted for the “current relay password” and
Then enter a new password.
Password setting change procedure must be completed within 15 minutes of energizing relay
or “password” will not be accepted as the “current” password.
1.1.6
Troubleshooting
In the event the communication remains unsuccessful, first make sure that the relay is powered,
proper communication cable is used (Table M-1, on page 170), and the connection is good.
For further testing, check that the bit rate (Baud) on the RS-PONI (Table M-2, on page 170) is set
to correspond to the one displayed at the bottom right of the RCP display.
If after these verifications the problem remains, try to remove the power from the relay and apply it again. If the communication still fails (several attempts), the communication equipment
needs to be serviced.
1.1.7
SIXTEEN FAULT TARGET DATA
The REL 356 saves the latest 16 fault records, but only the latest two fault records can be accessed from the front panel. For complete 16 fault data, the computer communication is necessary.
1.1.8
OSCILLOGRAPHIC DATA
Three sets of oscillographic data are stored in REL 356. Each set includes seven analog traces
(Va, Vb, Vc, Ia, Ib, Ic and In), with one cycle pre-fault and 7-cycle fault information, and 20 sets
of digital data based on 12 samples per cycle. Refer to Section 1.2, on page 1, for detailed information.
169
APPENDIX M
Before attempting any of the above functions, the setting of SETR must be verified via the
front panel MMI. Using the setting change procedure in Section 4.5, on page 40, verify or
change SETR such that it is set to YES.
I.L. 40-226
Version 1.00
NOTE:
IF POWER IS INTERRUPTED TO RELAY ALL “OSCILLOGRAPHIC DATA” WILL
BE LOST.
APPENDIX M
Table M-1
Communications Cable Requirements
Cable
(Straight = no
null modem)
Pins Req’d.
(All pins
not required)
Cable Connectors
Data Rate
Straight
2, 3, 7
To port: 25 pin DTE
To PC: 9 or 25 pin DCE
1200 bps only
DB-25S, RS-232C connected to modem
Null Modem
2, 3, 7
To port: 25 pin DTE
to Modem: 25 pin DTE
1200 bps only
DB-9P, RS-232C connected to PC*
Null Modem
2, 3, 5
To port: 9 pin DCE
To PC: 9 or 25 pin DCE
See Table M-2
For settings
2, 3, 5
To port: 9 pin DCE
To Modem: 25 pin DTE
See Table M-2
For settings
Connection Type
DB-25S, RS-232C connected to PC*
DB-9P, RS-232C connected to modem*
* Note:
Straight
A communications cable kit (item identification number 1504B78G01) that will
accommodate most connection combinations is available through your local
ABB representative.
Table M-2
RS-PONI Dip Switch Settings
Port Data
Rate
Dip Switch Pole
1
2
3
bps
0
0
0
300
0
0
1
1200
0
1
0
2400
0
1
1
4800
1
0
0
9600
1
0
1
19200
1
1
0
1200
1
1
1
1200
4
Dip Switch Pole
5
Auto Answer
Rings
0
0
none
0
1
4
1
0
8
1
12
1
NOTE:
170
Turn the power OFF and ON, anytime
Dip Switch changes are made.
Version 1.00
1.2
I.L. 40-226
OSCILLOGRAPHIC DATA DEFINITIONS
CURRDIFF.MSP
BKUPMSP.MSP
Current diff. comparison
Distance Backup Subsystem
APPENDIX M
The Oscillographic and Recording Program (OSCAR) under selection: “Load Screen Layout
File” of the main menu offers the following display files for REL 356.
Phases A, B, C, GND
Phases A, B, C, GND
The signals associated with the above files are described in the following section.
1.2.1
CURRDIFF.MSP
In CURRDIFF.MSP the following signals are shown:
Ia, Ib, Ic, -3I0, Vag, Vbg, Vcg and 3V0: Self explanatory.
1.2.2
IT
VFLi
VFRi
OPw
RESw
PT
Compound “current” waveform
Local Phasor
Remote Phasor
Operate value
Restraint value
Pilot Trip
IL:
IH:
52b:
IE:
CDIV:
CT:
Low set overcurrent supervision
High set overcurrent supervision
Auxillary Breaker contact for phase A
Very low set current for open breaker detection
Change detector of current and/or voltage
Channel trouble signal
SCTB
RDTT
TDDT
ROBR:
TNRM:
RNRM:
TDSB
RDSB
CARM:
TRSL:
Soft channel trouble. If no delay time measurement
Direct transfer trip received
Transmit direct transfer trip
Remote Open breaker signal received
Transmit in normal mode
Receive in normal mode
Transmit diff. protection disable
Receive diff. protection disable
Channel OK
Trip seal (breaker trip current detected)
BKUPMSP.MSP
For BKUPMSP.MSP the following signals are defined:
171
I.L. 40-226
Version 1.00
Ia, Ib, Ic, -3I0, Vag, Vbg, Vcg and 3V0: Self explanatory.
APPENDIX M
RIFT:
3RI:
RB:
21B0:
21BI:
OSB:
OST:
Z2P:
Z2G:
Z3P:
Z3G:
Z2T:
Z3T:
TOG:
IOM:
LOP:
172
Reclose into a fault trip
Reclose initiate for multiphase faults
Reclose block
Outer blinder for OST
Inner blinder for OST
Out-of-step block signal (disables Z2 and Z3 three-phase fault detection)
Out-of-step trip
Zone 2 phase unit operated
Zone 2 ground unit operated
Zone 3 phase unit operated
Zone 3 ground unit operated
Zone 2 trip (phase or ground after T2)
Zone 3 trip (phase or ground after T3)
Ground overcurrent trip
Medium set ground overcurrent unit operated
Loss of potential detected (v0 and not I0)
Version 1.00
I.L. 40-226
Figure No.
S-1
S-2
S-3
S-4
S-5
S-6
S-7
Description
Block Diagram - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - Logic Diagram - - - - - - - - - - - - - - - - - - - - - - - - sheet 1 of 3 - - - - - - - - - - - - - - - - - - Logic Diagram - - - - - - - - - - - - - - - - - - - - - - - - sheet 2 of 3 - - - - - - - - - - - - - - - - - - Logic Diagram - - - - - - - - - - - - - - - - - - - - - - - - sheet 3 of 3 - - - - - - - - - - - - - - - - - - Zone 2 and Zone 3 Backup System - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - Optional Directional Overcurrent Units - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - OST and OSB Logic Diagram - - - - - - - - - - - - - (2420F06 in part) - - - - - - - - - - - - - - -
page 175
page 177
page 179
page 181
page 183
page 185
page 187
173
SYSTEM DIAGRAMS
SYSTEM DIAGRAMS
Version 1.00
OPTIONAL
SPARE
SPARE
175
I.L. 40-226
DIFFERENTIAL
PROTECTION
DISABLE
Figure S-1. Block Diagram
SYSTEM DIAGRAMS
DISABLE
ITL
CHOK
STUB BUS/OPEN BKR.
TRIP
CH ALARM
SBP
DTT-SEND(1)
OPBK(1)
CD
OPBKR
IL
TRIP
PT
SBOBT
PILOT TRIP
40
0
DC POWER OK
µP SELFCHECK OK
PLT
TRIP
IL
RCV -DISABLE
52b
CHANNEL
ALARM
TA
TRIP
ALARM
FA
FAILURE
ALARM
BK1
BK2
RY1
RY2
BFI-1
BFI-2
BFI-3
BFI-4
BFI-5
BFI-6
BFI
ITR
DTT
RCV-DISABLE
PSE
CHOK
L
L
BK1
BK2
TRIP
CHOK
CA
CHOK
IAE
IBE
ICE
OPBKR
COMM
RECV
PSE
DISABLE
52b
GENERAL
START
LDT + 8
0
SBP
OPBR IE
BOTH
GS
Version 1.00
COMM
XMTR
XMT-DISABLE (1)
150
150
OUT
BKUP IN
SIGNAL TO ACTIVATE
BACKUP SYSTEM
SEBR
BK3
BK4
RY1
RY2
BFI
CH ALARM
PSE
L
L
BK3
BK4
TRIP
BK5
BK6
RY1
RY2
RECL INTO FAULT
PT
52b
RIFT
250
500
BTRP
3PT
BFI
OST
1H
10
0
1. DTT-SEND
2. XMT - DISABLE
3. OPBK
BTRP – BACKUP (DISTANCE) TRIP
ALRB
NOTE:
Bold characters denote system settings
RB
OST – OUT-OF-STEP TRIP
0
200
RI1
177
RI2
Figure S-2. Logic Diagram (1 of 3)
L
BK6
* Denotes change
SYSTEM DIAGRAMS
I.L. 40-226
0
300
RBEN
NORB
L
BK5
RECL BLOCK
DTT
RECL INITIATE
NOTE (1)
Signals to be applied to COMM XMTR
one at a time in order of descending priority:
CO C1 C2
Im
Symm.
IB
Transmit only the Imaginary
part of the phasor.
DFT
IT
Cosine
Filter
Comp.
Version 1.00
Re
IA
ITL
Filter
IC
Communication Delay Compensation
“Sampling”
LDT
OP = /ITL + ITR/
RES = /ITL/ + /ITR/
Im
Receive only the Imaginary
part of the phasor
Re
Protective
Algorithm
Trip Command
ITR
PLT
IF [OP - 0.7 RES] > OTH
CHOK
Then Trip
NOTE:
Bold characters denote system settings
I.L. 40-226
OTH
179
Figure S-3. Logic Diagram (2 of 3)
SYSTEM DIAGRAMS
OPTO
ISOL
Opto
Isolator
Hardware Inputs
52b
Stub
Bus
Protection
Opto
Isolator
DISABLE
Primary
Input
Power
52b
Backup
Input
Power
SBP
P
Power
Supply
1
N
P
PSE
Power
Supply
2
N
OUT
Opto
Isolator
PHASE A
IAL
IAE
IAH
IACD
VACD
PHASE B
IBL
IBE
IBH
IBCD
VBCD
PHASE C
Target
Reset
ICL
ICE
ICH
ICCD
VCCD
GROUND
Version 1.00
Disable
Pilot
Protection
FDOP OUT
Target Reset
NONDIRECTIONAL
TTRP
OPTO
ISOL
DTTSend
DTT - SEND
IN
OUT
IPH
IN
NOTE:
Bold characters denote system settings
IAHT
IN
FDOP A
DIRECTIONAL
FDOP OUT
OUT
IPH
IN
IBHT
IN
FDOP B
IH
FDOP OUT
HIGH SET
OVERCURRENT
TRIP
OUT
IPH
IN
ICHT
IN
FDOP C
IGL
IGH
IGCD
FDOG OUT
OUT
IGH
IN
FDOG
LOW LEVEL
SUPERVISION
CHANGE DETECTOR
IL
IACD
IBCD
ICCD
IGCD
0
250
VACD
VBCD
VCCD
CD
181
I.L. 40-226
IAL
IBL
ICL
IGL
IGHT
IN
∆V ∆I
CD
∆I
Figure S-4. Logic Diagram (3 of 3)
SYSTEM DIAGRAMS
Version 1.00
IL3φ
FDOP
16
OSB
(Z2, BOTH)
OSB
LOPB
(YES)
Load Restriction
3φ
Zone 2
3φ
A
N
D
O
R
T2P
(BLK)
φφ
FDOG
FDOG
φG
OSB
(Z3, BOTH)
T2P
(BLK)
FDOP
IL3φ
3φ
ZONE 3
A
N
D
O
R
T3P
(BLK)
φφ
FDOG
FDOG
φG
T3P
(BLK)
183
Figure S-5. Zone 2 and Zone 3 Back-up System
SYSTEM DIAGRAMS
I.L. 40-226
Sub 2
2420F06
Sheet 2 (in part)
Version 1.00
A
N
FDOP
D
LOW LEVEL CURREN
SUPERVISION
FROM
SHEET 1
IAL
A
IBL
N
ICL
D
O
FDOG
IL3φ
IL
R
FDOG
OUT
TOG
BLK
O
φG
R
φA
φφ
3φ
OPERATING
ELEMENTS
Sub 2
2420F06
Sheet 2 (in part)
I.L. 40-226
Figure S-6. Optional Directional Overcurrent Units
185
SYSTEM DIAGRAMS
Version 1.00
φ
φ
φ
Sub 2
2420F06
Sheet 2 (in part)
I.L. 40-226
Figure S-7. OST and OSB Logic Diagram
187
SYSTEM DIAGRAMS