Volume 3, Issue 4 SEP 2015
A NOVEL THREE-PHASE BUCK–BOOST AC–DC
CONVERTER
ANANDAPU NAGAVENI
M.Tech PE
SRI VENKATESWARA COLLEGE OF
ENGINEERING, Suryapet, Nalgonda
District, Telangana, India.
SURESH REGATTI
Assistant Professor
SRI VENKATESWARA COLLEGE OF
ENGINEERING, Suryapet, Nalgonda
District, Telangana, India.
Abstract- A simple, low-cost, reduced-switch,
three-phase ac–dc buck–boost converter is proposed in
this paper. The converter can operate with input power
factor correction and is suitable for applications where
a converter needs to operate over a wide range of input
ac voltages and/or produce a wide range of output dc
voltages. The paper will examine how a reduced
switched converter with capacitive input filter operates
in the boost mode and how a reduced switch converter
operates in buck and boost modes. In this paper, the
converter’s operation is explained and analyzed in
detail and its design is discussed. The feasibility of the
converter is confirmed by experimental results obtained
from a prototype.
Index Terms – AC-DC power conversion,
power conversion harmonics, power converter, pulse
width modulated power converters.
converters that perform PFC with a reduced number
of switches are variations of the converter proposed
in [7] and their output voltage is always higher than
their input voltage because they are boost-type
converters. This is a drawback if there is a need for a
converter that needs to
I. INTRODUCTION
Power electronic converters operating from the
utility mains can generate current harmonics that are
injected into the mains. The dramatic growth in the use of
electrical equipment in recent years has resulted in a greater
need to limit these harmonics to meet regulatory standards.
This can be done by some form of power factor correction
(PFC) to shape the input phase currents so that they are
sinusoidal and in phase with the phase voltages. Threephase PFC is typically done by using a six-switch converter
either to process the bulk of the power fed to the load or to
be an active filter that processes only a portion of the power
fed to the load. Using a six-switch converter, however, is
costly and complicated given the number of active switches
that must be used and the sophisticated control needed to
ensure a good power factor. Cheaper and simpler methods
of performing three-phase active input PFC have been
developed using converters with less than six
switches. One such converter, first proposed in, is a
single-switch boost converter that can be designed to
operate so that its line currents operate in the
discontinuous conduction mode and are bounded by a
sinusoidal envelope. Many three-phase ac–dc
Fig. 1. Three-phase, single-switch ac–dc buck–boost
converter
Operate for a wide range of input ac voltages and/or
produce a wide range of output dc voltages such as a
front-end rectifier for a commercial product that must
work with several ranges of acvoltages. Relatively
few reduced switch three-phase ac–dc buck–boost
rectifiers have been proposed in the power electronics
literature [9]–[15] mainly due to topological
constraints. One such converter is the three-phase ac–
dc single-switch buck–boost converter shown in Fig.
1 [8], which will henceforth be referred to as the
conventional converter in this paper. The converter is
operated with a constant duty cycle throughout the
line cycle and is designed so that its input capacitors
operate in the discontinuous voltage mode (DVM),
which results in naturally sinusoidal input currents.
Like a boost converter, inrush and short-circuit
currents can be limited by the presence of an
inductor, L ,in Fig. 1. This converter, however, has a
drawback that has restricted its use: the switch has a
very large peak voltage stress >1 kV for buck
mode,>1.5 kV for boost mode) regardless of whether
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215
its output voltage is made to be lower or higher than
its input voltage. This is especially the case when the
output voltage is higher than its input voltage. Such a
high peak voltage stress has made the converter in
Fig. 1 impractical so that it is rarely used in industry.
In this paper, a new three-phase reduced switch
buck–boost converter is described. The paper will
examine how a reduced switched converter with
capacitive input filter operates in the boost mode and
how a reduced switch converter operates in buck and
boost modes. Such an examination has not been
performed in the literature to the best of the authors’
knowledge. In this paper, the operation of the new
ac–dc buck–boost converter, which is an advance on
the work performed in [16], is explained in detail; its
steady-state characteristics are determined by
analysis and are then presented for both buck and
boost operating modes. Based on the results of the
analysis, a procedure that can be used in the design of
the converter\s key components is developed and
then demonstrated with an example. The feasibility
of the proposed converter is confirmed with results
obtained from an experimental prototype.
II. CONVERTER OPERATION
Fig.2. Proposed ac-dc reduced switch buck-boost
converter
The three-phase ac–dc buck–boost converter
examined is shown in Fig. 2. The converter is similar
to the conventional converter shown in Fig. 1 as the
input section is the same and input PFC is performed
by the charging and discharging of the input
capacitors. The main difference between the new
converter and the conventional converter is that each
of the switches in the converter under test sees a lineto-neutral voltage (the voltage across one of the three
input capacitors) across it rather than a line-to-line
voltage (the voltage across two input capacitors),
which is the case for the switch in the conventional
converter. Since a switch in Fig. 2 sees a line-to- that
of the switch in Fig. 1. As a result of reducing the
peak voltage stress, lower rated devices can be used
instead of what can be used in the conventional
converter for the same operating conditions and the
use of devices with the same rating will allow for a
larger operational range. It should be noted that if
IJOEET
Volume 3, Issue 4 SEP 2015
output capacitor Co is completely discharged, the
inrush current can be limited by the presence of
buck–boost inductor Lo just like it can be limited by
the boost inductor in a boost converter. Moreover,
short-circuiting current is also limited by the presence
of inductor Lo. It is possible for both switches to be
on at the same time during regular steady-state
operation, as will be shown below, so that the
inadvertent short-circuiting of switches does not
result in converter destruction. Similar to a PWM dc–
dc single-switch buck–boost converter, the proposed
converter operates as a buck converter when its duty
cycle, D<0.5 and as a boost converter whenD>0.5. In
this section, the operation of the proposed converter
when D<0.5 and D>0.5 is explained.
The equivalent circuit diagrams for the proposed
converter steady-state operation when D<0.5 and
D>0.5 are given in Figs. 3 and 4 and the typical
waveforms of the two operations are given in Figs. 5
and
6, respectively. It should be noted that the
switch status is shown in the modal circuit diagrams.
If a component is conducting current, it is shown in
the figure; if not, then it is not. The following
assumptions are made to simplify the modal
equations for the steady-state operation of the
converter:
A1: The line frequencyfl is small with respect to the
switching frequencyfs; thus, the input side voltages,
currents, and resistances during a switching period
(Ts= ) are constants.
A2: The input filter capacitors are considered to have
equal values C = C = C = C. Similarly, all three
input inductors are of equal value such that L =L =
L =L.
A3:It is assumed that C is small and there is
sufficient current in the dc side to discharge it
Completely throughout the line cycle so that
cooperates in the DVM.
A4: The output capacitor Co and the load resistor
Rare combined and considered as a dc voltage
sourceV2.
A5: Due to the symmetry of a three-phase system, it
is sufficient to consider only π/6 of the line cycle
[12]. The equations derived below are found for a
switching cycle in the line cycle for the interval
ω t ε[π/3,π/2], where V , =V , V , =V , = - and V1
being the peak phase voltage. It should be noted that
the equations can be generated by starting from any
switching cycle; this particular cycle was selected to
reduce the redundant equations.
A. D<0.5 [Buck Mode of Operation]
216
Volume 3, Issue 4 SEP 2015
Prior to t=t , both S1 andS2 are OFF and the input
capacitors are charged by the input line currents.
While this is happening, the current through output
inductor Lo is freewheeling in the dc side of the
converter.
1) Mode 1(t0 ≤t≤t ) [see Fig. 3(a)]: At t=t , S1 is
turned ON and the line current I , , and the
discharging current of C I ( , ) flow through rectifier
diode D1 and enter the dc side. Currents I , and
I ( , ) flow through S , L , D and return to the ac
side. At the common point of the input capacitors (x),
the returning current splits as I , and I ( , ) . The
voltage of the C at t=t can be expressed as follows
by considering its discharge:
v
, ( )
=V
, ( )
−
,
,
(
)
(1)
Where V , ,( )the initial voltage or the peak is value
of V for the K switching cycle, and I , is the line
current for phase A in K cycle. At the input side,
I , and I , , respectively, charge C and C ( I , =
−I , −I , ). C begins to charge from −V and reach
voltage V , ( ) at t=t when the mode ends, and its
voltage can be expressed as follows:
V
, ( )
= −V +
, (
)
(2)
Mode 1 ends when Ca is fully discharged
( V , ( ) =0); thus, t can be calculated as follows by
rearranging (1)
t =t +
(
( ,
, ( ))
, )
(3)
2) Mode 2 (t1 ≤t≤t2)[see Fig. 3(b)]: Ca becomes fully
discharged at t=t1. During this mode, Ca remains
discharged, line current I ,
flows through
D , S , L , andD . I , returns to the input side and
continues to charge C and C . I , freewheels
throughL ,D ,D , and the load.
3) Mode 3(t2 ≤t≤t3)[see Fig. 3(c)]: This mode begins
a t=t2 when S1 is turned OFF. During this mode,
both S1and S2are OFF and the ac input side is
separated from the dc output side. In the ac input
side, the phase currents continue to charge C and C ,
and Ca will begin to be charged by I , . Mode 3 ends
T
when S is turned ON at t= t (t =t + 2) due to the
180 phase shift between the two switches. The
value of V , at the end of the mode is
Fig.3. Modes of the converter when D<0.5 (a)Mode 1
(t <t<t ).(b)Mode2(t <t<t ).(c) Mode 3(t <t<t ).(d)
Mode 4( t <t< t ).(e) Mode 5( t <t< t ).(f) Mode
6(t <t<t ).
V
, ( )
, (
=
)
(4)
4) Mode 4 (t3 ≤t≤t4)[see Fig. 3(d)]: During Mode 4,
Ca continues to be charged byIa,k, while C and C ,
are discharged by giving I , and I , respectively.
The sum of the above currents flows through D ,L ,
and S . ( I , +I , ) and(I , +I , ) return to the input
side via D6 and D2,respectively. Mode 4 ends
when C and C , are discharged to a voltage level
of−V2 (these capacitors charge opposite to the
reference directions shown in Fig. 2) at t=t as given
below:
t =t +
(
(
(
))
(5)
, )
,
5) Mode 5(t4 ≤t≤t5)[see Fig. 3(e)]: During this mode,
Ca continues to be charged by line current, while the
voltage across C and the voltage across C remain at
− V . I , flows through D , while I , freewheels
through L ,D , and the load.
6) Mode 6 (t5 ≤t≤t6)[see Fig. 3(f)]: This mode begins
when S is turned OFF at t=t5. Since both S and S are
OFF, this mode is similar to Mode 3. During this
mode, C reaches its peak voltage for k cycle, while
C and C begin to charge as given below
, (
, (
)
, (
)
, (
)
, (
)/
)
/
(6)
Mode 6 ends when S is turned ON at t=t and the
next switching cycle (k+1) begins.
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217
B.D>0.5 [Boost Mode of Operation]
It should be noted that unlike in the buck mode in
the boostmode, the input capacitor discharging
currents and the current of L are not constant during
the K switching cycle; thus, those variables are
represented by lowercase letters below. Before t=t ,
S is OFF and S is ON. C is charged by line current,
while Cb andCc discharge, giving currents I ,
andI , , respectively.
1) Mode 1 (t0 ≤t≤t1) [see Fig. 4(a)]: At t=t , S is
turned ON and C begins to discharge; therefore,
I , and the discharging current of C ( I , )flow
through switch S1 and chargeLo, before returning to
the ac side through switch S , D , and D . The
discharging current of C is i , . The current in
D equals (I , +I , ). The current in D consists of
I , and discharging current of C (I , ). Both diodes
D and D are OFF. This mode ends when C and
C are charged in the opposite direction to a voltage
level that equals the output voltage −V . The voltage
of C at the end of Mode 1 is
V
, ( )
=V
, (
Volume 3, Issue 4 SEP 2015
(7)
∫ (i , − I , )dt
)−
V , ( ) in (7) is the initial voltage of C and(i
I , ) is C ’s discharging current
V
, ( )
=V
.( )
−
∫
i
,
−I
,
−
dt = −V (8)
,
The value oft1 can be found by solving (8), which
indicates the voltage of
at t= t . As explained
above, V , ( ) in (8) equal − V . The following
equation gives the current of Lo at t=t
I
, ( )
=I
, ( )
+
∫ (v
,
−v
,
)dt
(9)
where the voltage acrossLo is the dc bus voltage and
equals the line-to-line input capacitor voltage
v , −v ,
2) Mode 2(t1 ≤t≤t2)[see Fig. 4(b)]: During Mode 2,
Ca continues to discharge as in Mode 1 and I ,
flows through S , L , and D . Line current flows
through D ,S ,L , and S before it divides into I ,
and I , . Currents flow through D and D ,
respectively. The voltages across C and C remain at
a voltage level of− V . The charging of L can be
expressed as
I
, ( )
=I
, ( )
+
∫ (V
,
− V )dt
(10)
During Mode 2, the voltage across L is the difference
between V , and V because the voltage of C and
C remains at−V .
3) Mode 3(t2 ≤t≤t3)[see Fig. 4(c)]: S is turned OFF
at the start of this mode.Cacontinues to discharge
and( I , + I , ) flows through L ,R, and D and
returns to the input side.C can be charged according
to (11) and that C can be charged in a similar manner
by current since I , =I , = ,
Fig.4. Modes of the converter when D>0.5 (a)Mode 1
(t <t<t ).(b)Mode2(t <t<t ).(c) Mode 3(t <t<t ).(d)
Mode 4( t <t< t ).(e) Mode 5( t <t< t ).(f) Mode
6(t <t<t ).(g) Mode 7(t <t<t ).
V
, ( )
= −V +
,
(t − t )
(11)
The following equation can be used to find the
current of L at t=t :
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218
V
, ( )
=V
I
, ( )
=I
Volume 3, Issue 4 SEP 2015
,
(16)
∫ (i , − I , )dt
)−
, (
, ( )
−
∫ vc , dt
(17)
Fig.5. Typical waveforms when D<0.5.
I
. ( )
=I
, ( )
+
∫ (vc
− vc, )dt
,
(12)
This mode ends whenCa is fully discharged and (7) is
equated to zero to find t=t as follows:
V
, ( )
=V
, ( )
−
∫
i
,
−I
,
dt = 0 (13)
4) Mode 4(t3 ≤t≤t4)[see Fig. 4(d)]: During Mode 4,
Ca remains completely discharged. Throughout this
mode, both output diodes D and D conduct
current and the line current I , flows through
D ,S ,L , and D and returns to the input side. Ib,k
charges C and I , chargesC . The charging of C can
be expressed as
V
, ( )
=V
, ( )
+
,
(t − t )
(14)
Where t = t +
. i , freewheels through
D D and R and has a final value of
V
, ( )
=I
, ( )
−
(t − t )
(15)
5) Mode 5(t4 ≤t≤t5)[see Fig. 4(e)]: S is turned ON at
t=t . Current I , flows out of C and I , flows out
of C so that current flows through D and L , C
remains discharged. The relevant equations for Mode
5 are as follows:
Fig.6. Typical waveforms when D>0.5.
6) Mode 6(t5 ≤t≤t6)[see Fig. 4(f)]: This mode begins
when voltages of C and C . are zero. All the input
capacitors remain fully discharged as dc bus is short
circuited.
7) Mode 7(t6 ≤t≤t7) [see Fig. 4(g)]: At t=t , S1 is
turned OFF and I , starts to charge C . The
difference in current betweeniLo,kandIa,kis the total
discharge of C and C . This mode ends at t= t
whenS1is turned ON. This is the start of the next
switching cycle k+1. The charging of C can be
expressed as
V
. ( )
=
,
(1 − D)T (18)
The discharging ofCc can be expressed as follows by
considering the discharging current as I , − I , :
V
, ( )
=−
∫ (i
,
− I , )dt (19)
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219
The current of Lo at the end of Mode 7 can be
expressed as
I
, ( )
=I
, ( )
+
∫ vc , dt (20)
Fig. 7. DC-DC single-switch LC filter buck-boost
converter.
III. CONVERTER ANALYSIS
When D<0.5, the input capacitors are most
likely to be discontinuous during all the switching
cycles in a line cycle due to high circulating currents
in the dc side of the ac–dc buck–boost converter.
That is the input capacitors operate in DVM; hence,
the input line currents are bounded by a sinusoidal
envelope and as a result the input line currents are
perfectly sinusoidal and the input power factor is
excellent. The input capacitors, however, can be
semicontinuous when D>0.5, especially if the
converter maximum power is low due to less current
in the dc side. As a result, the input current will not
be bounded by a sinusoidal envelope and the
presence of harmonics will complicate the analysis.
Analysis for Buck Mode of Operation (D≤0.5):The
objective of the mathematical analysis is to find a
relationship between the output-to-input voltage
conversion ratioM, input capacitor value C, switching
period Ts, and the switch duty cycle D as they are the
main parameters of the proposed converter. This
relationship is found by considering the energy
balance of the converter—the total input
energyW from all three phases over a π/6 of the line
cycle must be equal to the dc energy output to the
load for the same duration, provided the converter is
lossless. The procedure to determine the output
energyW involves the multiplication of output dc
voltage V2, output dc current, and the time duration
for π/6 of the line cycle. The procedure to determine
Wi considers the sum of the energy in each phase,
with the energy per phase dependent on the
integration
of
the
instantaneous
energy
(multiplication of instantaneous voltage and current)
over aπ/6 portion of the line cycle. Based on
assumption A in Section II, input phase voltage and
current are considered as constants during a
IJOEET
Volume 3, Issue 4 SEP 2015
switching period so that they can be considered as dc
parameters V and I for any particular switching
cycle. As a result, an equivalent dc–dc buck–boost
converter circuit with an LCfilter can be used as a
first step to find the instantaneous values that are
required to find the desired relationship between M,
input capacitor valueC, switching period Ts, and the
switch duty cycle D. The step-by-step process for the
analysis of the converter operating in buck mode is as
follows.
Step 1: The analysis will begin by considering a dc–
dc buck– boost converter with anLCfilter shown in
Fig. 7. An expression for the instantaneous input
resistance will be determined in terms of input dc
voltageV , output voltage V (it should be noted that
this output voltage is the same as the output voltage
of the full three-phase converter), andD. The reason
for finding the instantaneous input resistance R1 is
because the instantaneous input current I = and
can be found using R for any V value for any
switching cycle during the line cycle.
Step 2: In this step, the dc source of the equivalent
converter (which represents an instantaneous input
voltage for any switching cycle during a line cycle) is
replaced with a three-phase ac source. The singlephaseLCfilter is replaced by a three-phase LC filter
and a diode bridge rectifier. Doing so results in a
three-phase
ac–dc
single-switch
buck–boost
converter. The expression for R found in Step 1 is
used to find the instantaneous input line current for
any switching cycle for any phase of the three-phase
system, for example,I , =V , /R .
Step 3: The input energy that is associated with each
phase can be determined by multiplying the
instantaneous input current determined in Step 2 with
the input voltage and then integrating the result over
an interval ofπ/6of the line cycle (assumption A ).
The summation of the threephase input energy gives
the converter’s the total input energy.
Step 4: Assuming that the converter is ideal, the
converter’s total input energy can be equated with its
output energy to determine the converter’s output-toinput voltage conversion ratio for the buck mode of
operation. This ratio is dependent on C ,T , andD. It
should be noted that this ratio is for a single-switch
version of the proposed converter that is derived by
replacing the dc input source of the instantaneous
single-switch dc–dc buck–boost converter used in
Step 1 with a three-phase input. This ratio, however,
is valid for the proposed converter, as will be
explained in detail below after Step 4. With this
summary in mind, the analysis can proceed as
follows:
A. Step 1: Calculating the Instantaneous Input
Resistance Using DC–DC Buck–Boost Converter
220
Volume 3, Issue 4 SEP 2015
Fig. 7 shows the equivalent single-switch buck–boost
converter with a dc source. A single-phase LC filter
is placed between the dc source(V )and the converter.
The converter goes through three significant modes
during steady-state operation and equivalent circuits
for these modes and typical waveforms that are
required for the analysis are given in Figs. 8 and 9.
The three significant modes are as follows:
1) Mode 1 (0≤t≤t1) [see Fig. 8(a)]: At t =0, S is
turned ON and input capacitor Cstarts to discharge,
giving a constant current I − I , where I is the
output current and I1 is the instantaneous input
current. The diode D is OFF and the voltage of the
diode v =V + V . The switch current isI . During
Mode 1,v becomes zero at t=D T and continue to
charge in the opposite direction to its reference
direction shownin Fig. 8.
2) Mode 2(t1 ≤t≤t2) [see Fig. 8(b)]: Mode 2 begins
when v =−V ., where V is the output voltage but
negative asthe direction is opposite to the reference
direction. During this mode,V remains at this voltage
while the line current flows throughSandLo.Dois
forward biased and the current throughit is I − I .
Fig.8. Modes of the converter when D<0.5 (a)Mode 1
(0<t<t ).(b)Mode 2(t <t<t ).(c) Mode 3(t <t<t ).
3) Mode 3(t2 ≤t≤Ts) [see Fig. 8(c)]: Att =DT , S is
turned OFF. Cwill start to be charged byI and I will
flow through D . During this mode,vCcrosses the
time axis at t=D V and continues to rise. At t=T , C
reaches its peak voltage,V .
The average voltage of input inductor L is zero at
steady state; therefore, when the loop that consists of
V , L,and C in Fig. 7 is considered, the average
voltage ofCmust equal V 1, the instantaneous input
voltage. The average voltage across C (V , )for a
switching period can be found from its voltage
waveformvCshown in Fig. 9. When V , is equated
to V , the following equation can be obtained.
IJOEET
Fig.9. Typical waveforms for dc-dc buck boost
converter when D<0.5
V,
V D T + V (1 − V )T
T
= 0.5
(
)
…
= V (21)
Equation (21) consists of terms D ,D , and D , where
D is the normalized time at which v becomes zero
first (during discharging of C), D is the normalized
when v becomes −V , and D is the normalized time
when v becomes zero for the second time (during
charging ofC), as shown in Fig. 9. Equations (22) and
(23) can be used to reduce the variables D and D ,
respectively, from (21). Equations (22) and (23) are
derived by considering the tangent ofv Curve shown
in Fig. 9 and are as follows:
D =D +
(22)
D =D +
(23)
Substituting (22) and (23) into (21) results in
D V (V + V ) + V (1 − D)
…
V (V + V )
(
)(
)
(
)
= V (24)
which gives the relationship between input voltageV ,
duty ratio D, the normalized time point at which
V crosses zero axis D , and the peak capacitor
voltage V . In order to find the instantaneous
resistance R
after obtaining (24), input
currentI must be found next.I can be calculated by
considering the charging ofCfrom minimum voltage
V to its peak voltage V in Mode 3. During Mode 3,
the entire source currentI1is used to chargeCfor the
221
duration of dt=(1 –D)Ts until S is turned ON again;
this can be expressed by
I =C
(25)
or by (26) where dv = V
I = C(
(
)
+V , according to Fig. 9
(
)
(27)
In order to further reduce variables from (27), D1
needs to be removed; thus, the steady-state operation
of the loop L , D , and V of Fig. 8 was considered.
The average voltage across output inductor L is also
zero at steady state; as a result, the average voltage
across diodeD (V , ) should equal V ,the output
dc voltage. The instantaneous voltage of D (V )has
a triangle shape (see Fig. 9). V = V + V . At C
t=0,V starts from peak voltage and becomes zero at
t=D T ; therefore, V , can be expressed as
V
,
=
(
)
=V
)(
)
R =
−
(
=
(
)[
(
)
)
(1 − D)(1 − D +
) (31)
v (ω t) = V sin(ω t)
(32)
v (ω t) = V sin(ωlt − 2π/3) (33)
v (ω t) = V sin(ω t − 4π/3)
]
(35)
C. Step 3: Calculation of the Three-Phase Input
Energy This step of the analysis is to calculate the
total input energy for the three-phase system by
summing the integrals of the instantaneous energy
over π/6 of the line cycle for each of the three phases.
The input energy of phase A for π/3 ≤ωl ≤π/2 can be
derived as follows:
/
W = ∫ / v (ω t)i (ω t)d(ω t)(36)
whereva(ωlt) andia(ωlt)are the instantaneous phase A
voltage and current obtained in Step 2. Substituting
the values from (32) and (35) into (36) gives
(
)[
(
)
∗ (V sin(ω t)) )d(ω t)
]
(37)
W =
/
(
)[
(
)
∗ ∫ / (1 −
]
and solving (38) yields
W =
(
)[
(
)
( +
]
√
)(39)
Similarly, the input energy for phases B and C can be
given also be obtained by replacing the voltage and
current in (36) by the relevant values
(30)
B. Step 2: Calculation of the Instantaneous Line
Currents for a Three-Phase Single-Switch Buck–
Boost Converter This step of the analysis uses the
input resistance equation to find the input currents
during each switching cycle for the threephase
system. The instantaneous input voltages for a
balanced three-phase system are
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)
cos(2ω t)d(ω t)(38)
= V (29)
Equation (29) can be rearranged to find D in order to
remove it from (27) to reduce the number of variables
in the R expression to obtain (31)
D =
(
Currents for phases B and C are analogous to (35) but
phase shifted by 2π/3
W =
/
∫/
(28)
When D is removed from (28) using (22), the result
is
(
i (ω t) =
) (26)
R can now be calculated by dividing (24) by (26) and
can be expressed as
R =
Volume 3, Issue 4 SEP 2015
whereV1 is the peak phase voltage and ωl is the
angular line frequency. The instantaneous input line
currents can be obtained by the ratio of input voltage
to the input resistance corresponding to each phase.
For example, the current in phase A is
W =
W =
(
)[
(
)
]
(
)[
(
)
]
( −
( +
√
√
) (40)
) (41)
The total input energy Wi is
W = W + W + W (42)
which results in
W =
(
)[
(
)
]
( )(43)
(34)
222
D. Step 4: Derivation of the Mathematical
Relationship Between M,C T , and D For the energy
equilibrium of the converter, W = W . W over the
interval ofπ/6 of fundamental period can be expressed
as
W =
(44)
whereV2 is the output dc voltage and Ris the load
resistance. Substituting for W and W using (44) and
(43), and rearranging the results leads to the
following relationship:
=
(
)[
(
)
]
(45)
If the output-to-input voltage conversion ratio M is
defined as the ratio of output voltage
to line–line
peak input voltage, then M can be expressed as a
function of C, Ts, and D as follows:
=√
=
(
)[
(
)
]
(46)
Equation (46) givesMas a function ofCandDfor a
threephase ac–dc single-switch version of the
proposed buck–boost converter and was derived by
considering the input capacitor voltage waveform and
the energy equilibrium of this singleswitch converter.
Although (46) was derived for the singleswitch
version of the proposed converter, it is valid for the
proposed converter because the input capacitor
voltages have comparable shapes and the peak input
capacitor voltages for any switching cycle are the
same. Graphs of curves ofMversusDfor different
input capacitors when the converter operates in the
buck mode can be plotted based on (46) using
MATLAB. Such graphs can be used as part of a
design procedure, as shown in Section IV. Analysis
for Boost Mode Operation (D>0.5):The analysis for
boost mode operation differs from that of buck mode
operation because the input capacitor voltages (and
thus the input currents) are less likely to be sinusoidal
and more likely to be distorted. The fact that the input
currents are probably not sinusoidal complicates the
analysis of the boost mode operation,and thus, an
approach that is different from the one used for buck
mode analysis is needed. Given the interdependence
of the components and key variables such as input
capacitor voltage v , output inductor voltage V ,k,
etc., the analysis of the converter in the boost mode
cannot be performed using equations with closedform solutions and some sort of a computer program
must be used to solve the aforementioned modal
equations. The objective of the boost mode analysis
Volume 3, Issue 4 SEP 2015
is to confirm that a chosen value of Ca obtained from
an analysis of the buck mode is satisfactory for boost
mode operation as well. In order to do this, it must
first be determined that the converter is operating at
steady state for the chosen value of Ca and a
randomly selected D. If it is determined that the
selected Ddoes not result in converter steady-state
operation, then it must be changed until it does so.
Once it has been determined that the converter is in
steady-state operation, instantaneous input capacitor
voltage waveforms can be determined for a line cycle
and used to determine the input current waveforms to
see if they meet the appropriate harmonic standard,
without undue stress placed on the converter
components. If these criteria are not met, then a
different value of Ca must be selected. A flowchart of
the computer program described in this section is
shown in the Appendix (see Fig. 18)
IV. DESIGN PROCEDURE AND EXAMPLE
In this section, a procedure that can be used to
determine the key parameters of the proposed
converter (the input capacitors, inductors and the
duty ratio) is presented and demonstrated with an
example. The output filter components can be
determined in the same manner as those of a
conventional buck–boost converter [17] and a
procedure for their design is not given here. For the
example, the converter specifications will be an input
line–line rms voltage Vin =220 V, an output
voltage V =150 V(D<0.5) and 500 V (D>0.5), a
maximum output powerPo,max=2 kW, and a
switching frequencyfs=25 kHz.
Fig.10. Voltage conversion ratio M versus duty ratio
D for the proposed converter when D<0.5
A. Selecting the Input Capacitors (C = C =C ) In
order to select an input capacitor valueC , either the
buck or the boost mode of operation should be
considered first and converter operation should be
confirmed for the other mode.C is more likely to be
fully discontinuous throughout the input line cycle
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223
when the converter is in buck mode as mentioned in
Section III. Therefore, based on (46) derived by
mathematical analysis, a suitable C for the required
output-to-input voltage conversion ratioMand duty
ratio D for buck mode operation can be selected
using appropriate design curves shown in Fig. 10.
Although a particular value ofC may be satisfactory
for buck mode converter operation, it may be
unsuitable for the converter operating in boost mode
because that input current harmonics standard may
not be satisfied as the voltage across C may not be
fully discontinuous throughout the line cycle. Some
sort of compromise, therefore, must be considered as
increasing the value ofC to reduce switch stresses in
the buck mode may result in a too largeC in the boost
mode to ensure an input current that is compliant
with IEC standard. As a result of this compromise, it
is necessary to confirm that the converter designed
for buck mode can meet the IEC standard when it is
operated in the boost mode; the design procedure is,
therefore, iterative. In this section, only the final
iteration of the design example is shown. M can be
calculated asM=
. If D is closer to 0.5, then C that
√
will be in DVM for all the switching cycles can be
obtained using the characteristic curves shown in Fig.
10, which shows a set of curves ofMversusDfor a
range of C values.M<1 and 0≤D≤0.5 for buck
operation. Each curve with markers refers to a
different C value [20 nF< C <250 nF]. The solid
straight line which goes through the origin indicates
M versus D during the boundary DVM. That is, if the
operating point lies on the straight line without
markers, then when D<0.5,C ’s voltage will touch
zero axis exactly when t=DTs, in the critical
switching cycle where phase voltage is at its peak.
Therefore, any operating point that is in the area
below the straight line will ensure DVM operation
of C . The higher the value of C , the lower will be
the peak switch voltageV , , so that it is important to
select the highest capacitance that will ensure the
DVM operation of C . According to Fig. 10,
whenCa=220 nF and theDis approximately 0.5, the
proposed converter operates in DVM; therefore, for
this iteration,Cawas chosen as 220 nF.
Once C forD<0.5 is selected, the next step is to
perform the “check” in order to find out if the
converter meets the IEC standard in the boost mode
or not.
B. Selecting the Input Inductor(La =Lb =Lc):
The design of the converter in the previous
steps is based on the assumption that the input
currents are perfectly sinusoidal. However, in reality,
these currents will have high-frequency ripple.
Volume 3, Issue 4 SEP 2015
WhenD<0.5, there is more current available to
discharge the input capacitors. This makes it more
likely that the input capacitor voltages will be fully
discontinuous and thus more likely that the input
currents will be sinusoidal. As a result, it is the highfrequency ripple that is more dominant when the
converter is operatingD<0.5.
Fig. 11. Single-phase equivalentLCfilter circuit
Fig. 11 shows a per-phase equivalentLCfilter section
of circuit that can be used to find the relationship
between C ,L , and fr (fr is the dominant harmonic
frequency (sidebands) related to f ). Equation (47)
gives the allowed high-frequency input ripple current
in to the utility side ( I )as a function of total
generated harmonics(I ), f , and C −L
I
/
=I (
If I
L C =(
)(47)
/
)
= 20%I
, then(47)
1+
(48)
.
becomes
Where C =220 nF and f =25060 Hz or 24940 Hz. La
=1.1 mH
C. Selecting the Duty Ratio D and Checking IEC
Standard Compliance in the Boost Mode With value
ofCa chosen above and D that allows the converter
boost operation to reach the steady state, the next step
of the design procedure is to confirm that the input
current harmonic standard is satisfied for boost
operation. This done by finding the fast Fourier
transform of the input inductor currenti , as shown
as the last step in Fig. 18. For this example, such a
check was performed and the harmonic content was
found to be satisfactory with respect to IEC 61000-32 Class A. If this had not been the case, then a
newCaneeded to have been found.
D. Peak Switch Voltage The peak switch voltage in
the buck mode of operation occurs when the
converter is at the full load and at the switching cycle
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Volume 3, Issue 4 SEP 2015
where the phase voltage is at its peak. Due to the
placement of the switches,v (pk) is limited to the
maximum phase voltage of theCaso that the switch
stress is about half of the peak switch voltage stress
of a switch in the conventional single-switch
threephase buck–boost converter (see Fig. 1). This
switch stress can be found as
V,
=
,
(1 − D)T .
I (pk) = 7.5A(= (√2P ,
)/( 3V ))
(49)
the selected Ca=220 nF andD=0.5 (which was
determined from Fig. 13) and the switching period Ts
=40μs. The resultant switch voltage stress at this
operating point is approximately 700 V. For boost
operation:For the selected operating point, v is
semicontinuous for boost mode. This was found by
the instantaneous input capacitor voltage(v )found
by using Fig. 18. As a result, the maximum switch
stress can occur during any switching cycle and this
value will be dependent on the minimum value
ofv , or the voltage value when switch is turned
OFF and the line current I , for that switching
cycle.To find these values in order to calculate
V ( , ) , a sweep mustbe performed using Fig. 18
V(
)
=V
, ( )
+ I , (1 − D)T /C
(50)
Fig. 13.(a) Phase current and voltage when V = 500
V for loads: (b) 500 W [V : 100 V/div, I: 10 A/div, t:
10 ms/div].
Fig. 13. (b) Phase current and voltage when V = 500
V for loads: 500 W [V: 100 V/div, I: 10 A/div, t: 10
ms/div].
The values obtained from the sweep were I , =6 A
and V , ( ) =450 V, and they resulted in a V , of
approximately 800 V.
IV. CONCLUSION
Fig. 12. (a) Input current and voltage when V = 150
V and P = (a) 2000 W
Fig. 12. (b). Input current and voltage when V = 150
V (b) 500 W [V : 100 V/div, I: 10 A/div, t: 10ms/div].
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Three-phase ac–dc buck–boost converters
can step up input voltage and step down input
voltage. As such, they can be used in applications
that require a converter that can operate over a wide
range of conditions. The size and cost of these
converters can be reduced if they are implemented
with reduced switch topologies, but few such
topologies have been proposed in the power
electronics literature due to topological constraints. It
has been shown in the literature that it is possible to
implement a three-phase ac–dc buck–boost converter
with a capacitive input filter using just a single
switch, but although this converter is very attractive,
it is also impractical because of its very high peak
switch voltage stress. As a result, a new three-phase
reduced switch buck–boost converter with
significantly reduced peak switch voltage stresses
that is based on the single-switch converter was
discussed in this paper. This paper examined how a
225
Volume 3, Issue 4 SEP 2015
reduced switched converter with capacitive input
filter operates in the boost mode (as opposed to the
conventional approach of operating a reduced switch
converter with inductive input filter in the boost
mode), which has not been previously addressed. It
also examined how a reduced switch converter can
operate in both buck and boost modes, which also has
not been previously addressed. In this paper, the
operation of the new ac–dc buck–boost converter was
explained in detail; its steady-state characteristics
were determined by analysis and were then presented
for both buck and boost operating modes. Based on
the results of the analysis, a procedure that can be
used in the design of the converter’s key components
was developed and then demonstrated with an
example. The feasibility of the proposed converter is
confirmed with results obtained from an experimental
prototype. It was found that operating a reduced
switch converter with capacitive input filter in the
boost mode means that there is less current available
to fully discharge the input capacitors during
switching cycles, which results in distorted input line
currents, thus the need for smaller input capacitors.
The use of smaller input capacitors results in
increased switch stress so that a compromise must be
considered in the design of the converter that works
satisfactorily in both modes. Other properties that
were determined are as follows: the converter has a
better efficiency when working in boost mode than in
buck mode, nearly sinusoidal input currents with
minimal input filtering can be obtained naturally if
there is sufficient current flowing in the converter to
discharge the input capacitors, the input and output
currents of the converter are continuous, and the
input capacitors voltages have a dc component due to
the nature of the two-switch buck– boost topology
that does not affect the input PFC. It should be noted
that most of the properties and characteristics
discussed in this paper have not been mentioned
anywhere in the power electronics literature that is
related to reduced switch buck–boost converters.
Fig. 18. Flow chart analysis of boost mode operation
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