Proposal of Three-phase Two-level Unidirectional
SEPIC PWM Rectifiers with High Power Factor
Flabio Alberto Bardemaker Batista
Carlos Henrique Illa Font
Dept. of Electronics, Campus Florianópolis
Federal Institute of Santa Catarina (IFSC)
Florianópolis, Brazil
flabio@ifsc.edu.br
Dept. of Electronics, Campus Ponta Grossa
Federal University of Technology – Paraná (UTFPR)
Ponta Grossa, Brazil
illafont@utfpr.edu.br
Abstract—This paper presents the initial theoretical analysis of
three-phase two-level unidirectional SEPIC PWM rectifiers. The
rectifiers operate in CCM (continuous conduction mode) with
high power factor and output voltage control. Converter
switching stages are analyzed for single-phase structure and the
three-phase Y-connected and the Δ-connected rectifiers are
derived from it. These rectifiers have the advantages of
providing high power factor with low input filtering effort, as
Boost rectifiers, and lower output voltage level, as Buck
rectifiers. The disadvantage is the increase of component count,
due the need for additional capacitors and inductor per phase.
The control strategy is presented with a description of the
objectives of the mains current control loop and the output
voltage control loop. Simulation results from a rectifier with
380V input voltage, 400V output voltage, 20kHz switching
frequency and 6kW output power are also presented.
I.
INTRODUCTION
PFC Boost AC-DC converter topologies are widely used
as front-end stages both in single-phase and three-phase
applications. The main advantages of Boost PFC rectifiers are
low input filtering effort, high efficiency, sinusoidal mains
current and controllability of output voltage [1-3].
Therefore, for three-phase 380V or 440V AC mains
voltage, Boost PFC rectifiers produce an output voltage too
high to directly feed many types of loads in applications as
Electric Vehicle (EV) battery charging [4], UPS systems and
telecom power supplies [5].
In the applications named before, a DC-DC step-down
stage is required after the PFC Boost rectifier. Thus, this
increases component count and decreases the efficiency.
Moreover, the blocking voltage stress on the power
semiconductors of the DC-DC converter stage is defined by
the Boost converter output voltage and not by the lower load
voltage level.
Buck-type AC-DC rectifiers are solutions for front-end
stage with lower output voltage level. Therefore, even in CCM
(continuous conduction mode), the input current of Buck
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converter is discontinuous. Then, for high power factor
operation, a large and bulk LC filter is needed at the input [67].
This paper proposes the use of three-phase SEPIC
rectifiers for feed loads that require low DC voltage level in
systems that require high power factor. This solution has the
advantages of providing high power factor with low input
filtering effort, as Boost rectifiers, and lower output voltage
level, as Buck rectifiers. The disadvantage is the increase of
component count, due the need for additional capacitors and
inductor per phase.
In the literature, some topologies of three-phase SEPIC
rectifiers were presented in [8-14]. The topology presented in
[8] is a three-level unidirectional SEPIC-type rectifier,
operating in continuous conduction mode and suitable for
medium power applications. This topology employs only three
active switches, unlike the topology presented in [11], whose
employs six active switches in the two level version.
The system proposed in [9] is composed by a three-phase
diode-bridge rectifier cascaded by a SEPIC DC-DC converter
operating in CCM. The structure is simple and robust. The
input currents do not follow a sinusoidal shape leading the
system to operate with high total harmonic distortion.
The topologies presented in [10], [12-14] use three singlephase modules and provide galvanic isolation between AC
mains and DC load. The proposed rectifiers presented in [10],
[12-13] operate in CCM and they are intended for use in low
power applications.
The topology presented in [14] operates in discontinuous
conduction mode (DCM). This proposal has the advantage of
providing unity power factor, without the use of any current
sensor and currents control loop because in DCM the system
has a resistive-load behavior.
First, the Y-connected rectifier topology is presented in
Section II. Section III of this paper presents the theoretical
analysis of a single-phase leg and the behavior of the threephase system. Section IV shows the control scheme.
Simulation results are presented in Section V. Finally, the
discussions for the Δ-connected rectifier topology are
presented in Section VI.
II.
THE PROPOSED Y-CONNECTED THREE-PHASE SEPIC
PWM RECTIFIER
The proposed Y-connected three-phase SEPIC rectifier is
presented in Fig. 1. This unidirectional topology is the twolevel version of the three-level one presented in [8]. It has
three switches and each single-phase leg is connected in a Y
configuration.
The proposed Y-connected three-phase SEPIC rectifier is
capable of providing high power factor with low filtering
effort. The output voltage can be controlled to be lower, equal
or higher than the mains input voltage.
III.
THEORETICAL ANALYSIS
A. Single-phase Analysis
The operating modes for a single-phase leg are presented
in Fig. 2, considering that all semiconductors are ideal and the
system operating in steady state. In continuous conduction
mode (CCM), there are four operating modes, where two are
for input current greater than zero and two for the input
current lower than zero.
In the first operating mode, S1 is turned on and the input
voltage v1 is greater than zero. The energy from input source
v1 is transferred to the inductor L1. Capacitors C1 and C2
transfer its energy for inductor L2 through S1. The output
capacitor Co supplies the load. This operating mode ends when
S1 is turned off.
Figure 2. Operating modes for a single-phase leg: a) first, b) second, c)
third and d) fourth.
The analysis for the first operating mode yields to (1), (2),
(3) and (4):
In the second operating mode, S1 is off and the input
voltage v1 is greater than zero. Input source v1, inductors L1
and L2 transfer the energy to the output, charging output
capacitor Co and supplying the load, and charging capacitors
C1 and C2. This operating mode ends when S1 is turned on
again.
v L1 ( t ) = v1 ( t )
(1)
v L2 ( t ) = v C1 ( t ) + v C2 ( t )
(2)
iCo ( t ) = −
Third and fourth operating modes are similar to first and
second operating modes, respectively. But in these last two
operating modes the input voltage v1 is lower than zero.
Vo
Ro
iC1 ( t ) = iC2 ( t ) = −iL2 ( t )
where:
- v1(t): mains voltage;
- vL1(t): voltage across inductor L1;
- vL2(t): voltage across inductor L2;
- vC1(t): voltage across capacitor C1;
- vC2(t): voltage across capacitor C2;
- Vo: output voltage;
- Ro: load resistance;
- iCo(t): current in capacitor Co;
- iC1(t): current in capacitor C1;
Figure 1. The proposed Y-connected three-phase SEPIC PWM rectifier.
- iC2(t): current in capacitor C2;
(3)
(4)
(
For the second operating mode, the analysis conducts to
(5), (6), (7) and (8):
v L1 ( t ) = v1 ( t ) − v C1 ( t ) − v C2 ( t ) − Vo
= − v1 ( t ) + Vo
(5)
v L2 ( t ) = −Vo
(6)
(
)
v D5 ( t ) + v D6 ( t ) = − v C1 ( t ) + v C2 ( t ) + Vo =
- iL2(t): current in inductor L2.
)
VD5max = VD6 max =
V1pk + Vo
2
(13)
(14)
where:
- vD5(t): voltage across rectifier diode D5;
- vD6(t): voltage across rectifier diode D6;
V
iCo ( t ) = iL1 ( t ) + iL2 ( t ) − o
Ro
(7)
iC1 ( t ) = iC2 ( t ) = iL1 ( t )
(8)
- VD6max: maximum voltage across rectifier diode D6;
Considering the volt-second balance in inductors L1 and
L2, from (1), (2), (5) and (6), results in (9) and (10).
v L1 ( t )
Ts
(
)
= 0 ⇒ d ( t ) . v C1 ( t ) + v C2 ( t ) + Vo =
= −v1 ( t ) + v C1 ( t ) + v C2 ( t ) + Vo
v L2 ( t )
Ts
(
- VD5max: maximum voltage across rectifier diode D5;
- V1pk: mains peak voltage.
During second operating mode, S1 is turned off. The
voltage across switch S1 is given by (16), through (15).
(9)
)
= 0 ⇒ d ( t ) . v C1 ( t ) + v C2 ( t ) + Vo = Vo (10)
v S1 ( t ) = v C1 ( t ) + v C2 ( t ) + Vo = v1 ( t ) + Vo
(15)
VS1max = V1pk + Vo
(16)
where:
- vS1(t): voltage across switch S1;
- VS1max: maximum voltage across switch S1.
where:
B. Three-phase Analysis
For three-phase analysis, it is considered the rectifier’s
behavior in 60 degrees of the mains period. Assuming the
analysis in the sector where 60o ≤ ω.t ≤ 120o, the mains
currents have the behavior presented in (17).
- d(t): duty cycle;
- Ts: switching period;
- < >Ts: average value in the switching period.
Substituting (10) in (9), it yields to (11).
v C1 ( t ) + v C2 ( t ) = v1 ( t )
(11)
Assuming that capacitors C1 and C2 have the same
capacitance, it yields to (12).
⎧i1 ( t ) ≥ 0
⎪⎪
⎨i2 ( t ) ≤ 0
⎪
⎪⎩i3 ( t ) ≤ 0
(17)
(12)
Considering that, in the three-phase system, each phase
will have the same operating modes as single-phase leg, the
operating modes for three-phase rectifier is presented in Fig. 3.
Therefore, the capacitors C1 and C2 are charged with a half
of input voltage level. The voltage across capacitors C1 and C2
are important parameters for describing the maximum voltage
across semiconductors.
Since the three-phase rectifier has three active switches
and each switch can assume two states, it results in eight
different operating modes for the selected sector. As notation,
0 means that the switch is off and 1 means that the switch is
on.
During the first operation mode, the switch S1 is turned on
and the rectifiers diodes D5 and D6 are blocked. The voltage
across rectifier diodes is given by (14), through (13).
Therefore, in the operating mode 000 the three active
switches are off while in the operating mode 111 all switches
are on.
v C1 ( t ) = v C2 ( t ) =
v1 ( t )
2
First operating
mode (000)
Second operating
mode (001)
Third operating
mode (010)
Fourth operating
mode (011)
Fifth operating
mode (100)
Sixth operating
mode (101)
Seventh operating
mode (110)
Eighth operating
mode (111)
Figure 3. Operating modes for the sector where 60o ≤ ω.t ≤ 120o.
Fig. 4 shows the equivalent circuit for operating modes 1
(000) and 5 (100). In these operating modes, the capacitors
among different phases are placed in parallel. So, it means that
the capacitors cannot be charged with the mains input voltage
level.
Since the capacitors among different phases are placed in
parallel, it imposes a restriction for defining appropriate
vectors in a space vector modulation. Even if the operating
modes where the capacitors are placed in parallel are avoided,
the available vectors from the others operating modes are
dependent on the input voltage. Thus, the synthesized vector
cannot be obtained adequately, as in the space vector
modulation strategy proposed for Boost rectifiers [2-3].
This behavior is different from the single-phase case and a
proper modulation strategy should be searched for three-phase
rectifier.
C. Start-up Operation
The SEPIC rectifier presents an advantage during the startup when compared with Boost rectifiers. At the initial start-up
all capacitors, including the large output capacitor Co, are
discharged. When the three-phase rectifier is turned on, an
inrush current surge charges all capacitors.
The inrush current produces little consequence because the
capacitances C1, C2, C3, C4, C5 and C6 are small and charge
rapidly. Then, the output bulk capacitor is charged slowly to
the output voltage level, under an inherent current limit
control. This behavior is completely different of a Boost
rectifier, whose inrush surge has great magnitude because it
charges the output capacitor directly. Boost rectifiers need an
inrush current circuit with additional inrush resistors and an
AC contactor.
IV. CONTROL STRATEGY
The control scheme of the SEPIC rectifier is showed in
Fig. 5. It is composed by three current control loops and a
voltage control loop. The voltage control loop provides DC
output voltage regulation and the references for the current
control loops. The current control loops impose sinusoidal
shapes for the input currents without displacement factor.
The gains and the variables presented in Fig. 5 are
described as follow:
• kIi: current sensors gains;
• kVi: mains voltage gains;
Figure 4. Equivalents circuits for a) first operanting mode (000) and b) fifth
operating mode (100).
The control strategy is based on the multiplier approach
for imposing the current references. This concept is the same
traditional scheme used for three-phase Boost rectifiers. The
modeling and control design will be omitted here for the sake
of brevity.
A sinusoidal PWM modulation is used for generating the
command signals. A sawtooth carrier signal is used for the
three signal comparators.
V. SIMULATION RESULTS
A numeric simulation was performed with the
specifications presented in Table I, using software PSIM 9.0.4.
• kVo: output voltage gain;
• km: multiplier gains;
• VoRef: system reference voltage;
• I1Ref, I2Ref and I3Ref: current reference voltages;
• Hi1(s), Hi2(s) and Hi3(s): current controllers;
• Hv(s): output voltage controller;
• PWM1, PWM2 and PWM3: PWM modulators.
TABLE I.
SIMULATION PARAMETERS
Parameters
Input mains line voltage
Output voltage
Mains frequency
Switching frequency
Output power
Inductors L1, L2 and L3
Inductors L4, L5 and L6
Capacitors C1, C2, C3, C4, C5 and C6
Capacitor Co
Values
380 V
400 V
60 Hz
20 kHz
6000 W
4 mH
900 µH
330 nF
1500 µF
Figure 5. Control scheme of three-phase SEPIC rectifier.
The three-phase input currents waveforms are shown in
Fig. 6. The currents present sinusoidal shape, allowing high
power factor.
Figure 7 presents the waveforms of input voltage and input
current for phase 1 and the output voltage. The output voltage
level is 400V for 220V input phase voltage (380V input line
voltage). In that case, SEPIC rectifier is operating as stepdown converter.
Figure 8 presents the waveforms of input currents and
output voltage during the start-up. One can observe that there
are no several spikes in the input currents and the output
capacitor is charged slowly, without any auxiliary circuitry for
start-up.
Figure 6. Input currents waveforms.
Figure 9 shows the voltage across capacitor C1 and C2. It is
observed that, for the sinusoidal PWM modulation adopted,
the capacitor voltage is asymmetrical and with 900V peak
voltage.
Figure 7. Output voltage, input voltage v1 and input current i1 (multiplied
by 10) waveforms.
Figure 11. Input currents waveforms for the Δ-connected three-phase SEPIC
PWM rectifier.
Figure 8. Output voltage and input currents waveforms during start-up.
VII. CONCLUSIONS
Three-phase unidirectional Y-connected SEPIC rectifier
and Δ-connected SEPIC rectifier are presented as power factor
correctors. The switching stages are analyzed for the singlephase leg and the behavior for the three-phase system is
presented.
The simulation results show that the proposed
unidirectional rectifiers are operating with high power factor
and that the output voltage is in the desired value. Also, the
start-up behavior of SEPIC rectifier is verified by simulation.
Figure 9. Capacitors C1 and C2 voltage waveforms.
VI.
DISCUSSION FOR THE Δ-CONNECTED THREE-PHASE
SEPIC PWM RECTIFIER
Fig. 10 shows the Δ-connected three-phase SEPIC PWM
rectifier topology, where each single-phase leg is connected in
a Δ configuration. Possible advantages of this topology are
lower input current total harmonic distortions and increase of
efficiency, as observed in [3] for Boost rectifiers.
In the case of a Boost rectifier, with a proper modulation
strategy, for the active switches, conduction losses and
switching losses are smaller in Δ-connected topology.
The three-phase input currents waveforms for the Δconnected three-phase SEPIC PWM rectifier topology are
shown in Fig. 11.
The theoretical analysis shows that the three-phase SEPIC
rectifier cannot operate as three single-phase converters, since
the capacitors will not be charged with the input voltage level.
Capacitors among different phases are placed in parallel
and it imposes a restriction for defining appropriate vectors in
a space vector modulation. Even if the operating modes where
the capacitors are placed in parallel are avoided, the available
vectors from the others operating modes are dependent on the
input voltage. Thus, the synthesized vector cannot be obtained
adequately, as in the space vector modulation strategy
proposed for Boost rectifiers [2-3].
The challenge is to find a space vector modulation, which
improves the capacitor’s charging process, lowering the
voltage level across them. Thus, this will result in lower
voltage levels of stress in semiconductors.
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