IEEE TRANSACTIONS ON POWER ELECTRONICS, VOL. 12, NO. 2, MARCH 1997
319
Three-Phase Step-Down Reversible
AC–DC Power Converter
Tim C. Green, Member, IEEE, Mohamed H. Taha, Nasrudin Abd. Rahim, Member, IEEE, and Barry W. Williams
Abstract—Bidirectional dc current flow is not a natural feature
of the buck (step-down) switch-mode rectifier, which leaves it
at a disadvantage to boost (step-up) designs. A circuit topology
is presented that allows bidirectional flow and which, by dual
use of components, uses fewer devices than anti-parallel bridges.
Sinusoidal current, controlled displacement factor, and variable
voltage transfer ratio are demonstrated in a 1.5-kVA prototype.
Dynamic performance is investigated through simulation and
experiment. A P I plus velocity controller is shown to be adequate
provided care is taken over changing between rectification and
inversion.
Index Terms—Bidirectional conversion, control, distortion factor, rectification, sinusoidal current, switch mode.
I. INTRODUCTION
T
HE boost switch-mode rectifier is the dominant design
for both single- and three-phase rectifiers where there is
a requirement to draw near-sinewave currents from the mains.
This requirement is likely to follow from the need to comply
with a standard such as IEC 555-2 [1]. In the three-phase case,
the principle advantage of the boost topology is that it is able
to operate in all four quadrants of the
plane without
the need for additional power components. The step-up from
the three-phase voltage to a dc voltage above the line voltage
peak is also a benefit in induction motor drives. The higher dc
link voltage allows a larger constant torque operating region.
Not all loads, however, suit a stepped-up mains voltage.
Battery chargers and dc motor drives would require a further (dc–dc) power conversion stage to operate with a boost
rectifier. A further disadvantage of a boost rectifier is that it
needs special protection during start-up because the converter
is uncontrolled while the dc link voltage remains below the
line voltage peaks.
The buck switch-mode rectifier would suit low and medium
voltage dc loads, especially those that require a controlled
variable voltage between 0 and the 1.5 times the phase voltage
peak.
The disadvantage of the buck rectifier is that there is
no path for reverse current flow [2]. Thus, regeneration is
limited to loads that can reverse their voltage. There is also a
small transient regeneration capability while the dc current is
forward and the ac currents are phase inverted. Under these
circumstance, the dc current is rapidly driven to zero.
Manuscript received September 7, 1995; revised August 7, 1996.
The authors are with the Department of Electrical and Electronic Engineering, Imperial College of Science, Technology and Medicine, London SW7
2BT, U.K.
Publisher Item Identifier S 0885-8993(97)01841-3.
Fig. 1. Anti-parallel connected buck converters.
A buck converter with regenerative capability through reversal of the dc current flow would be a useful addition to
the present family of power converters. This paper addresses
that need.
II. THE BIDIRECTIONAL BUCK RECTIFIER
Traditional phase-angle controlled rectifiers have the same
restriction to unidirectional current flow as the buck rectifier.
This is overcome by operating two thyristor bridges in antiparallel [3]. Applying this idea to the buck converter gives the
circuit shown in Fig. 1. The proposal is to take advantage of
the simplification of the buck rectifier in [4] and [5], which
changes the single bridge from 6 switches and 6 diodes to
3 switches and 12 diodes. The reverse connected bridge in
Fig. 1 cannot be simplified in the same manner because the
current paths cannot be enforced as necessary. However, the
two bridges (one simplified and one not) can be consolidated
so that they share diodes and save on components overall. The
result is the circuit of Fig. 2. This circuit is able to deliver
positive or negative dc current to a normally positive voltage
link. In this sense it is two quadrant. On the ac side, it is able
to operate in all four quadrants of the
plane.
A. Operation in Rectifier Mode
In rectifying mode (positive dc current), switches SR1–SR3
are used and SI1–SI6 are held off. Assuming for the moment
that the dc-side inductor current,
is constant, the switches
0885–8993/97$10.00  1997 IEEE
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IEEE TRANSACTIONS ON POWER ELECTRONICS, VOL. 12, NO. 2, MARCH 1997
TABLE I
Fig. 2. A simplified and consolidated anti-parallel buck converter.
(3)
(4)
Fig. 3. The sextants of a mains cycle defined by the zero-crossings of the
phase currents in rectifying mode and the relationship to phase voltage.
can be used to provide current pulses, of amplitude , with
sinusoidally modulated pulse-widths in the three phases of
the ac supply. The circuit is a current source converter in
contrast to the voltage source boost converter. Consequently,
it is essential to ensure that there is always a current path
available for
. Overlapping of turning-on and turning-off
switches is normally employed.
The mains cycle is divided into sextants defined by the zerocrossings of the desired phase currents, as shown in Fig. 3. The
corresponding phase voltage definitions are given by (1). The
rectifier switch corresponding to the largest magnitude phase
current is held on for that sextant while the other two switches
are pulse-width modulated (PWM) according to a sinewave
pattern. The switch duty cycles for the first sextant are defined
by (2). The phase angle can be set by the modulator reference
generator. The current flows and the bridge voltage for the
switch combinations for this sextant are given by Table I:
(1)
Using the phase voltage definitions of (1), the average bridge
voltage simplifies to (5) [6]
(5)
is a dc value controlled by the depth of modulaThus,
tion with superimposed switching frequency components. The
inductor current
can be kept constant by suitable choice
of . For the rectification mode,
is set just greater than
so that the resistance of the inductor is overcome and the
inductance has a zero voltage-time integral.
B. Operation in Inverter Mode
In inverting mode, energy is removed from the dc side
by decreasing
to below
so that
reverses. When
this occurs switches SR1–SR3 will no longer conduct and are
turned off. Switches SI1–SI6 are used instead. Again,
is
held constant and the switches used to provide sinusoidally
PWM pulses of currents in the three phases.
The flow of positive and negative phase currents for each
phase are through separate switches for inverter mode, e.g.,
SI1 and SI2 for . For the first sextant, in which
is the
largest magnitude phase current and is positive (for inversion
are negated versions of those shown in Fig. 3 and
is also negative) the duty cycles of the switches are defined
as in (6). The analysis proceeds as for the rectifier case and
the bridge voltage is again defined by (5)
(2)
The inductor current is therefore chopped between the
phases to give phase currents defined by (3) and an average
bridge voltage defined by (4)
(6)
GREEN et al.: THREE-PHASE STEP-DOWN REVERSIBLE AC–DC POWER CONVERTER
321
C. The Pulse-Width Modulator
The modulator was implemented in a field-programmable
gate-array (FPGA). The sextant symmetry was exploited by
using a 60 sinewave look-up table to form the reference
waveform which is then multiplied by a depth of modulation. A standard pulse-width generator creates pulses that are
then de-multiplexed to appropriate switches depending on the
sextant and the state of the rectifier/inverter mode.
The modulator block diagram is given in Fig. 4. It can be
seen that the look-up table is phase-locked to the ac supply for
synchronization. The address counter for the look-up table can
be made to run ahead or fall behind the mains waveform in
order to change the displacement factor (
) of the current.
A synchronous implementation of the PWM was chosen.
This gives the advantage of using every look-up table sample
every cycle. An asynchronous PWM will use an uneven pattern
of increments between samples if the carrier does not happen
to be an exact multiple of the mains frequency. This is almost
always the case since the mains frequency changes through the
day. The disadvantage of synchronous PWM associated with
motor control, that is, wide variation of switching frequency, is
not encountered because the deviation of the mains frequency
is not large. Two different synchronization ratios can be
provided for 50- and 60-Hz operation. To achieve the correct
synchronization ratio, the carrier is also phase-locked to the
mains. Sixty-four samples per sextant were used giving a
switching frequency of 19.2 kHz for a nominal 50-Hz mains.
With 8-b resolution of the pulse edges, this gives a nominal
clock frequency of 9.83 MHz.
The modulator is provided with an 8-b interface for
;
phase advance and retard inputs and a signal to set rectifying
or inverting mode.
Fig. 4. Block diagram of the synchronous pulse-width modulator.
D. The Power Circuit
A 3-kVA prototype power converter was built in order to
verify correct operation of the converter and to allow its dynamic properties to be studied. The semiconductors used were
IXSH40N60 (SR1–3) and IRGPC50KD2 (SI1–6) IGBT’s and
STTA6006TV2 diodes. These have voltage ratings sufficient
for operation from 415-V ac supplies. The current rating was
dictated by the inductors rather than the semiconductors. RC
snubbers of 47 and 1 nF were added across each device.
The dc-side network was composed of a 1470- F capacitor
and an inductor of 40 mH and 2.7 . The ac-side filters were
composed of three inductors of 0.2 mH and 1.4 with deltaconnected 10- F capacitors. The equivalent star capacitance
is 3.3 F giving a filter with a double pole at 6.2 kHz. The
filter gives reasonable attenuation of the 19.2-kHz switching
frequency. The PWM currents are three-level and so only the
sidebands, and not the carrier itself, appear at the first multiple
of 19.2 kHz.
Fig. 5. Phase current (top) and phase voltage (bottom) during rectifier mode.
5 A/div; 100 V/div and 5 ms/div.
current is dominated by the mains frequency sinusoid and the
switching frequency components are greatly attenuated.
The inversion mode was tested with a dc supply of 150
V and a resistive three-phase load. Fig. 6 shows the results.
Again, it can be seen that sinusoidal currents were achieved.
In normal operation, inversion would be of dc power into
the ac mains. Testing of this required an outer loop controller
to set an appropriate value of .
E. Steady-State Operation
The circuit was tested in the rectification mode with a simple
resistive load and a phase voltage of 90 V. Testing could be
completed in open loop with
being set manually. A phase
current and phase voltage are shown in Fig. 5. The phase
III. CONTROL SYSTEM DESIGN
The system to be controlled is the LC circuit on the dc-side
of the converter and the converter itself. The target variable
is the capacitor voltage, which is normally to be controlled
322
Fig. 6. Phase voltage (top) and phase current (bottom) during inverter mode.
100 V/div; 5 A/div and 5 ms/div.
IEEE TRANSACTIONS ON POWER ELECTRONICS, VOL. 12, NO. 2, MARCH 1997
Fig. 8. Simulated open loop response of VO (center) and IL to a step change
in M (top) from 0.3 to 0.8. 50 V/div; 5 A/div and 10 ms/div.
Fig. 7. Schematic diagram of the coded loop system.
to be equal to a reference value This voltage is subject to
disturbances caused by the flow of load current. The LC circuit
is a simple second-order system with little inherent damping,
but when it is combined with the bridge a nonlinear system
results. There are two nonlinearities. The input has a saturation
nonlinearity because the depth of modulation is limited to
. There is also a zero-crossing dead-band for
introduced because of the need to change between rectifier
and inverter mode to allow the zero-crossing.
The control system design was based on a linear secondorder plant and was later assessed in a Simulink simulation to
ascertain the effects of the known nonlinearities. Several approaches to the controller design are possible. For the rectifier,
both
and state feedback approaches have been used [2], [7].
control has the disadvantage of poor output disturbance
rejection in this application. That rejection property can be
incorporated through state feedback or by adding a derivative
or velocity term. The velocity term is readily available in a
measurable form because the derivative of
is set by the
capacitor current.
The layout of the control system is shown in Fig. 7 including
the placement of the phase-locked loop and the feedback of
and
(the velocity term). Also shown is the feedback of
, the zero points of which must be checked before changing
between use of SR1–3 and SI1–6.
Fig. 9. Experimental open loop response of VO (center) and IL to a step
change in M (top) from 0.3 to 0.8. 50 V/div; 5 A/div and 10 ms/div.
The state-space model of the linear system including the
disturbance term is given by (7) with
given by (5)
(7)
The open loop response of the system to a step change in
was tested and simulated to check the model (Figs. 8 and
9). The open loop poles are at
s with a
natural frequency of 130 rad/s and a damping factor of 0.26.
The
plus
controller will give two open loop zeros
and a further pole. The
and
terms were then chosen
as
and
to give a dominant
pair of closed loop poles that are slightly slower but more
highly damped (natural frequency of 110 rad/s and damping
factor of 0.55) than the open loop case. Their locations are
s with the third pole at
s .
GREEN et al.: THREE-PHASE STEP-DOWN REVERSIBLE AC–DC POWER CONVERTER
323
(a)
(a)
(b)
(b)
(c)
Fig. 10. Simulated response to step decrease in VOref from (120 to 40 V): (a)
M and mode signal 0.2/div and 10 ms/div. (b) IL 2 A/div. (c) VO 20 V/div.
(c)
Choosing a fast and lightly damped system gives a step
response that is fast, but with the consequence that a large
Fig. 11. Experimental response to step decrease in VOref (120 to 40 V): (a)
M and mode signal 0.2/div and 10 ms/div. (b) IL 2 A/div. (c) VO 20 V/div.
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IEEE TRANSACTIONS ON POWER ELECTRONICS, VOL. 12, NO. 2, MARCH 1997
amplitude capacitor charging current flows. A design using
damping factors close to unity may be preferred to reduce the
current stress of the semiconductors during transients.
The step-decrease version of the step response is, in this
case, a more difficult test than the step increase because it is
likely to exercise the zero-crossing nonlinearity. In order to
reduce the capacitor voltage quickly, charge must be removed
by reversing
and entering inverting mode. The sign of the
voltage error can be used to indicate the desired direction of
and hence the desired mode. However, a mode change
cannot be immediately undertaken if
is presently nonzero.
It must be allowed to reach zero and then the mode changed.
A window comparator is used to detect when
is close to
zero and a delay allowed to ensure zero is reached. This
procedure is most easily expressed in software and so the
mode selection and
controller were implemented on
an 80C196 micro-controller.
Figs. 10 and 11 show a comparison of the experimental
results with the Simulink simulation. The phase voltage was
90 V and the voltage reference was stepped from 120 to 40
V. The step causes a negative voltage error, which signals the
desire to change mode and also causes
to fall. This, in
turn, causes
to decrease rapidly. A short period after
reaches zero the mode signal changes to inversion mode and
turns negative, thereby removing charge from the capacitor.
The dc output voltage reduces and
returns to zero as the
voltage reference value is approached. The voltage needs to
fall slightly below the reference in order to initiate a return to
rectifying mode.
remains at zero until this happens.
The step decrease test has established that inversion into the
mains is operational and that with suitable mode control a brief
period of inversion can be used to provide a fast step down
response, a function unavailable in the unidirectional buck
converter. Continuous inverting action is also possible with
a regenerative dc system as was demonstrated in steady state.
Alternative methods of setting the mode based on an explicit
current reference have been explored through simulation [8].
[3] K. Thorborg, Power Electronics—In Theory and Practice. U.K.:
Chartwell-Brat, 1993, sec. 4.4.
[4] L. Malesani and P. Tenti, “Three-phase AC/DC PWM converter with
sinusoidal AC currents and minimum filter requirements,” IEEE Trans.
Ind. Appl., vol. IA-23, no. 1, pp. 71–77, 1987.
[5] D. Ciscato et al., “PWM rectifier with low DC voltage ripple for magnet
supply,” IEEE Trans. Ind. Appl., vol. IA-28, pp. 414–420, 1992.
[6] A.-M. Majed, T. C. Green, and B. W. Williams, “Low EMI 3-phase
AC/DC converter with controllable displacement factor,” in Conf. Rec.
Power Quality ‘92, Munich, Germany, Oct. 1992.
, “Dynamic properties of a step-down sinusoidal current AC/DC
[7]
converter under state-feedback control,” in Conf. Rec. APEC ‘93, 1993,
pp. 161–167.
[8] T. C. Green, M. H. Taha, N. A. Rahim, and B. W. Williams, “Control
of a three-phase step-down reversible AC–DC power converter,” in 6th
Euro. Conf. Power Elec. and Appl. (EPE ‘95), Sevilla, Spain, Sept.
19–21, 1995, pp. 2.695–2.700.
Tim C. Green (M’89) received the B.Sc. (Eng.)
degree from Imperial College, University of London, in 1986 and the Ph.D. degree from Heriot-Watt
University, Edinburgh, in 1990.
He has been a Lecturer in Power Electronics
and drives at Heriot-Watt University and, since
1994, at Imperial College, London. His research
covers sinewave current ac–dc converters, induction
and reluctance motor drives, FACTS, and signal
processing in vibration test systems and drives.
Dr. Green is an associate member of the Institute
of Electrical Engineers.
Mohamed H. Taha was born in Lebanon on April
7, 1961. He received the B.Sc. (electrical engineering) degree from Grayounis University in Libya in
1985, the M.Sc. (power electronics) degree from
Bradford University in 1987, and the Ph.D. degree
from Aston University, Birmingham, AL, in 1992.
He has been a Lecturer in Electrical Engineering
at the Lebanese University in Beruit and, since 1995,
has been a Research Assistant at Imperial College,
London. His research covers solid-state tap changers
and bidirectional ac–dc power conversion.
Dr. Taha is an associate member of the Institute of Electrical Engineers and
a member of the Institute of Engineers in Lebanon.
IV. CONCLUSIONS
It has been shown that a consolidation of two anti-parallel
ac/dc buck converters comprising only nine switches provides
inversions and rectification through bidirectional dc current.
The buck converter’s advantage of variable low voltage dc is
maintained. A
plus velocity controller was shown to give
adequate performance in step response tests and will provide
disturbance rejection. The bidirectional buck converter can
provide a fast response to step decreases in demand voltage
because it can employ inversion to remove energy from the
dc side. However, this is only feasible if changes between
the inversion and rectification modes can be arranged quickly
while maintaining integrity of the current paths.
REFERENCES
[1] T. Green, “The impact of EMC regulations on mains-connected power
converters,” IEE Power Eng. J., vol. 8, pp. 35–43, 1993.
[2] R. Itoh, “Steady-state and transient characteristics of a single-way
step-down PWM GTO voltage-source converter with sinusoidal supply
currents,” Proc. Inst. Elect. Eng., Pt. B, vol. 136, no. 4, pp. 168–175,
1989.
Nasrudin Abd. Rahim was born in Johore,
Malaysia, on November 17, 1960. He received the
B.Sc. (Hons) and M.Sc. degrees from University of
Strathclyde in 1984 and 1987 and the Ph.D. degree
from Heriot-Watt University in 1995.
He is presently a Lecturer with the Department
of Electrical Engineering, Universiti Malaya,
Malaysia. His research interests include power
electronics, real-time control system, and electrical
drives.
Barry W. Williams received the M.Eng.Sc. degree from University of
Adelaide, Australia, in 1978 and the Ph.D. degree from Cambridge University,
U.K., in 1980.
After seven years as a Lecturer at Imperial College, London, he was
appointed to the Chair of Electrical Engineering at Heriot-Watt University,
Edinburgh, in 1986. His research interests include power semiconductor
modeling and protection, converter topologies, and application of ASIC’s and
microprocessors to industrial electronics.