National Conference
on
INFORMATION AND COMMUNICATION
“NCIC-2013”
12TH April 2013
Proceedings
Organized By
Department of Electronics and Communication Engineering
VELAMMAL INSTITUTE OF TECHNOLOGY
(Approved by AICTE New Delhi, Affiliated to Anna University-Chennai)
(An ISO 9001:2008 Certified Institution)
Velammal Knowledge Park, Panchetti-601 204
COMMITTEE MEMBERS
CHIEF PATRON
Dr. M. V. Muthuramalingam,
Chairman, VET
PATRON
Thiru. M. V. M. Sasikumar,
Director, VET
ADMINISTRATOR
Thiru. M. V. Nagamuthu
ADVISOR
Prof. K. Razak
PRINCIPAL
Dr. T. Chandrashekar
VICE PRINCIPAL
Dr. N. Durai Pandian
CONVENOR
Dr. A. Viswanatham Head/ ECE
CO-CONVENOR
Dr. R. Karthikeyan Asso. Prof./ ECE
ORGANIZING SECRETARIES
Mr. Sanjay Kumar Suman Asso. Prof./ ECE
Mr. B. V. Santhosh Krishna AP/ ECE
============================================================================
CONFERENCE CHAIR
Dr. K. M. M. Prabhu IIT, Chennai
ADVISORY COMMITTEE
ORGANIZING COMMITTEE
Dr. P. Hanumantha Rao
Mr.G.Shanmugaraj, AP/ECE
Sameer, Chennai
Mrs.N.Revathy, AP/ECE
Mr.B.V.Srikanth, Scientist E
Mrs.J.Megala, AP/ECE
ISRO, Sriharikota
Mr.L.Balaji, AP/ECE
Dr. S. Bose,
Mr.C.Raja , AP/ECE
Anna University, Chennai
Mr.G.Sethuram Rao, AP/ECE
Dr. Dhananjay Kumar
PROGRAM COMMITTEE
MIT, Anna University, Chennai
Mrs. Bharathi AP/ECE
Dr. N. K. Mohanthy
Mrs. Janci Rani AP/ECE
Velammal IT, Chennai
Mrs. S. Manju AP/ECE
Dr. M. Devaraju
Ms. G. Gnana Priya AP/ECE
RMKEC, Chennai
Mr. Karthikeyan AP/ECE
Dr. G. R. Suresh
Mrs. Gayathri Devi AP/ECE
SRM-Easwari, Chennai
Mr. Jeeva Bharathi AP/ECE
Dr. R. Mariappan
Mrs. Porselvi AP/ECE
Velammal IT, Chennai
Ms. H. Mehanaz AP/ECE
Preface and Acknowledgement
While it was a large and tough task, editing the conference proceeding has been a privilege for
us. Many people have been involved in the production of this proceeding which started with the
planning and large discussion and launching of a call for papers. Preliminary papers were
received and reviewed by the external/internal experts and finally authors are intimated for
selected papers for presentation. We are pleased that the papers selected cover a variety of
different topics of Electronics and Communication Engineering and come from all over India.
We are most grateful to the dedication, expertise and professionalism of referees.
The conference provided a setting of discussing recent developments, in a wide variety of topics
including, Data communication, Digital and wireless communication, ubiquitous computing,
Embedded system and VLSI, signal processing, Antenna and wave propagation, wireless
network etc. The conference has been a good opportunity for the participants to present and
discuss the topic in their respective research area.
We would like to thank all the authors as well as the conference committee members and
reviewer for their enthusiasm, their time and expertise which helped to make this conference a
successful event.
Our sincere gratitude to Prof. K.M.M Prabhu, IIT Chennai, Dr. Dhanajay Kumar, Anna
University Chennai, Dr. S. Bose, Anna University Chennai, Dr. G. R. Suresh, SRM Eswari
Engineering College, Chennai, Dr. M. Devaraju, RMK Engineering College, Chennai,
Mr.B.V.Srikanth, Scientist ISRO, Dr. Hanumantha Rao, Sameer Chennai and Mr. Visweswaran,
National Instruments Bangalore for their advice, motivation and support.
We are obliged to our Management, Principal and Vice Principal for their continuous
encouragement and guidance.
We are thankful to our reviewer Dr. N. K. Mohanty and Dr. R. Mariappan for their constructive
comments to enrich this conference.
We must acknowledge our colleagues and supporting staff members and students for their help at
various phases of conference.
We must thank to our sponsors IJCAES, Advantech Instruments and Services Chennai, Trident
Tech Chennai and National Instruments Bangalore
Sanjay Kumar Suman
B.V. Santhosh Krishna
Velammal Institute of Technology
(Approved by AICTE New Delhi, Affiliated to Anna University Chennai)
(An ISO 9001-2008 Certified Institution)
Velammal Knowledge Park, Chennai- Kolkatta Highway
Panchetti-601204
Ph: 044 30446300-306, 27994065/66 Fax: 044 30446309
Email: info@velammalitech.edu.in
Website: www.velammalitech.edu.in
Message from Chairman
Dr. M. V. Muthuramalingam
I am really happy to know that the Department of Electronics and Communication
Engineering is organizing a National Conference on “Information and Communication” on 12th
April 2013.
I hope that this conference would surely induce modern ideas among the participants
paving way for new inventions in the IT and Communication Industries.
Signature
Velammal Institute of Technology
(Approved by AICTE New Delhi, Affiliated to Anna University Chennai)
(An ISO 9001-2008 Certified Institution)
Velammal Knowledge Park, Chennai- Kolkatta Highway
Panchetti-601204
Ph: 044 30446300-306, 27994065/66 Fax: 044 30446309
Email: info@velammalitech.edu.in
Website: www.velammalitech.edu.in
Message from Director
Thiru. M. V. M. Sasikumar
I am extremely happy to know that the Department of Electronics and Communication
Engineering is organizing a National Conference on “Information and Communication” on 12th
April 2013. The applications of any advanced science and engineering is to help the nation for its
development. Information and Communication Technology in the present day scenario have a
challenge to provide reliable and secure voice and data communication. It is essential for those
professionals of Communication Engineers to get latest updates of Information technology and its
advanced applications to meet the challenges.
I hope that this conference would certainly induce innovative ideas among the participants
paving way for new inventions and new technologies in the field of Information and
Communication.
“Two things help success in life. The way you manage when you have
nothing , the way you manage when you have everything”
Wishing all a Happy and prosperous Tamil New Year
Signature
Velammal Institute of Technology
(Approved by AICTE New Delhi, Affiliated to Anna University Chennai)
(An ISO 9001-2008 Certified Institution)
Velammal Knowledge Park, Chennai- Kolkatta Highway
Panchetti-601204
Ph: 044 30446300-306, 27994065/66 Fax: 044 30446309
Email: info@velammalitech.edu.in
Website: www.velammalitech.edu.in
Message from Principal
Dr.T.Chandrashekar
I am very glad to hear that the Department of Electronics and Communication Engineering
is organizing a National Conference on “Information and Communication” on 12th April 2013. IT
& Electronics industry especially data communication and internet utilization in infrastructure and
ad hoc mode is playing a greater role in the progress of our nation. It is essential for professional
Engineers engaged in research and development of IT sector to understand the updates that are
coming up from time to time. Creating a platform for the Electronics and communication
Engineering professionals to share and express their views in the advancement of IT and
Electronics applications gives a great opportunity to know about the progress achieved by this
today.
I hope the Conference on “Information and Communication” would certainly help
everyone to have the latest updates to have a better understanding to contribute more in the field
of Electronics and Communication Engineering. I wish all the best to the participants, HOD of
Electronics and Communication Engineering & the faculty members.
On behalf of the management, I thank the sponsors IJCAES, Advantech Instrument and
services, National Instruments and Trident Tech for their sponsorship.
Wish you all a Happy and Prosperous Tamil New Year
Signature
Velammal Institute of Technology
(Approved by AICTE New Delhi, Affiliated to Anna University Chennai)
(An ISO 9001-2008 Certified Institution)
Velammal Knowledge Park, Chennai- Kolkatta Highway
Panchetti-601204
Ph: 044 30446300-306, 27994065/66 Fax: 044 30446309
Email: info@velammalitech.edu.in
Website: www.velammalitech.edu.in
Message from HOD
Dr. A. Viswanatham
Dear Participants, miscellaneous
It is a great pleasure for me to announce that our department is conducting a national
conference on “Information and Communication” (NCIC-2013) on 12th April’ 13.
The conference is a point of convergence for exchange of views, techniques and latest
trends between the end user, the development and the research communities. The purpose of this
conference is to bring together researchers, experts from industry, academia, and other interested
organizations to meet, exchange information and ideas in developments in the field of Information
and Communication Engineering. It enriches the latest developments in IT and ECE related
technologies; engineering solutions, and academic research. The conference program has been
designed to provide ample opportunities to researchers to network and to share ideas and
information about the theme of the conference.
I hope this conference NCIC-2013 will be enjoyable, memorable, and productive for
participants and looking forward to the technological innovations that result from your networking
and discussions.
Wishes Happy and Prosperous Tamil New Year.
Thanking you
Dr. Viswanatham. A
NATIONAL CONFERENCE ON INFORMATION AND
COMMUNICATION (NCIC 2013)
12th April 2013
contents
Sl
1
2
PAPER
ID
NCIC 01
NCIC 02
TITLE OF THE PAPER AND AUTHORS
PAGE
NO
Area efficient sad architecture for block based video compression
standards
S.Archana, D.Rukmani Devi
1
Bit Loading of OFDM with High Spectral Efficiency for MIMO
C.V.Umamaheswari,R.Loganathan
7
NCIC 03
Implementation of high speed architecture of arithmetic coder in
FPGA using SPIHT
M. Naveenkumar,V.Meenakshi
14
NCIC 04
Biometric Monitoring System for Multi Sensor Multi-modal Node
Architecture
J. Mohana
20
5
NCIC 05
Energy Consumption in Sensor Network using Continuous
Neighbor Discovery
A.Maria Nancy ,G Senthil Kumar
25
6
NCIC 06 Double edge triggered flip flop design using conditional pulse
3
4
enhancement scheme
A.Saisudheer, V. Muralipraveen
DA-Based DCT with Error-Compensated Adder Tree
Chinababu Panduru, P. Mahesh Kumar
7
NCIC 07
8
NCIC 08 GPS based railway track survey system
9
NCIC 09
33
38
V.Mahalakshmi,K.O.Joseph
45
Effect of Power Integrity on Analog Circuits over L-Band
Frequency
Jagan.N, Umma Habiba.H, Prasad.S
50
NATIONAL CONFERENCE ON INFORMATION AND
COMMUNICATION (NCIC 2013)
12th April 2013
10
11
12
NCIC 10
Opportunistic Transmission of Information in Cooperation Systems
Using Distributed Space Time Codes
S.Yogesh Chinnaraja, A.Sumathi
55
NCIC 11
Design of Cost Efficient Memory Using Advanced Error Correction
Method
M.Poornima, P.Rajendiran
60
NCIC 12
Implementation of Word Matching Stage of BLASTN Using
Modified Bloom Filter
A.Jenifer, S.Karthick
65
A novel witricity for wireless charging
13
14
15
16
17
18
19
70
NCIC13
Kannan S, N.Sasirekha.
NCIC 14
Low-Power and Area-Efficient Carry Select Adder Using Modified
BEC-1 Converter
L.Mugilvannan , S.Ramasamy
75
NCIC 15
Key distribution scheme for hierarchical cluster wireless sensor
network
S. Jenifer Ruby ,T. Kavitha
79
NCIC16
Accumulator Based Pseudorandom BIST
S.Naveen Pitchumani ,K.L.Hemalatha
83
NCIC 17
An efficient logic test structure for low power testing
P.Anand Selvakumar ,K.L.Hemalatha
87
NCIC18
LUT optimization using combined apc-oms technique for memorybased computation
R.Ramya, S.Sudha
92
NCIC 19
VLSI implemention of robust secure scan based design for
differential cryptanalysis
G.Agalya,S.Sudha
98
NATIONAL CONFERENCE ON INFORMATION AND
COMMUNICATION (NCIC 2013)
12th April 2013
20
21
NCIC 20
NCIC 21
22
NCIC 22
23
NCIC 23
24
25
26
NCIC 24
NCIC 25
NCIC 26
Design of Wireless Home automation and security system using
PIC Microcontroller
V. Sathya Narayanan, S. Gayathri
Hardware Implementation of Scalable Encryption Algorithm
Sharon Preethi G ,T.Blesslin Sheeba
A symmetric load balancing for distributed hash table using virtual
server
M.Raja
Energy Efficient Data Transmission with Mobile Sink in Clustering
Protocol
Sathish.G.P, B.R.Shyamala Devi
103
108
113
117
Component analysis based facial expression recognition
G.Sethuram Rao, M.Jeeva Bharathi
124
Low cost non recursive digital filter structures
G.Shanmugaraj, N.Kalaiarasi
131
A Cross layer framework design for transport of video over wireless
networks
A.Dhanalakshmi ,L.Balaji
135
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NATIONAL CONFERENCE ON INFORMATION AND
COMMUNICATION (NCIC 2013)
12th April 2013
ABSTRACTS
NCIC01 AREA EFFICIENT SAD ARCHITECTURE FOR BLOCK BASED
VIDEO COMPRESSION STANDARDS
S.Archana, D.Rukmani Devi
Abstract- Block based motion estimation is one of the critical task in video compression
standards such as MPEG-4, H.263, H.264. The key element of the block based motion
estimation algorithms is the matching criteria. SAD(Sum of Absolute Difference) is the
most common matching criteria chosen in video coding because of its low complexity,
good performance and ease of hardware implementation. By utilizing the concept of
reversibility a novel compression array unit using reversible 4:2 compressor has been
proposed. Experimental results indicate that the proposed compression unit will impose
effectiveness on the SAD architecture in calculating the motion vectors with reasonable
area overhead and power penalty.
NCIC 02 BIT LOADING OF OFDM WITH HIGH SPECTRAL EFFICIENCY
FOR MIMO
C.V. Umamaheswari, R.Loganathan
Abstract— The demand for high speed data services have been increasing day by day, a
very promising approach is to use Multiple-Input Multiple-Output Orthogonal Frequency
Division Multiplexing (MIMO-OFDM). In this paper adaptive bit loading is applied to
MIMO-OFDM, to obtain a bit and power allocation for each subcarrier assuming
instantaneous channel knowledge. Relying on the available partial CSI at the transmitter,
considerably improved communication is possible. Adaptive Bit Loading in MIMOOFDM is used to maximize the transmission rate, along with desired Bit Error Rate
(BER) performance in wireless systems under the constraint of fixed transmit power.
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Proceedings of National Conference on Information and Communication (NCIC’13)
NCIC 03 IMPLEMENTATION OF HIGH SPEED ARCHITECTURE OF
ARITHMETIC CODER IN FPGA USING SPIHT
M. Naveenkumar, V.Meenakshi
Abstract— -In this paper an implementation of the image compression standard, SPIHT
based on reconfigurable logic design. Several Discrete Wavelet Transform architectures
are introduced for discrete wavelets applications. For higher order compression ratio, we
use SPIHT for our lossy image compression technique. A major objective of our
progressive compression scheme is to select the most important information which yields
the largest resolution reduction to be transmitted first. To reduce design complexity, The
implementation of reconfigurable FIFO based on image size that reduces area and power.
In addition we provide a study on what storage elements are required for each wavelet
coefficient. Our design is simulated through Modelsim and synthesized through Quartus
II IDE.
NCIC 04 BIOMETRIC MONITORING SYSTEM FOR MULTI SENSOR MULTIMODAL NODE ARCHITECTURE
J. Mohana
Abstract – Biometric monitoring and healthcare using wireless sensor networks is an
active area of applied research. The general network topology used for wireless body
area networks is the star topology with the sensor nodes sending their data to a central
processing node for data fusion. Reliability of these networks is very important since
they deal with human life. Reported applications have had performance and reliability
problems. In the paper, several reported applications of wireless body area networks are
reviewed and the reliability of a sample WBAN is computed.
NCIC 05 ENERGY CONSUMPTION IN SENSOR NETWORK USING
CONTINUOUS NEIGHBOR DISCOVERY
G Senthil Kumar ,A MariaNancy
Abstract:In wireless sensor network to make reliable path connectivity and packet
exchange will take more time and also need more power.
Two techniques are
analysed here to reduce time and maintain power consumption. One of the
technique is Continuous Neighbor Discovery, It will find neighbor node and also
continuously maintain a immediate neighbour node view. Another one is Link
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Proceedings of National Conference on Information and Communication (NCIC’13)
Assessment Method, It allows f o r probabilistic guarantee of collision-free packet
exchange. Each sensor using a simple protocol in a coordinate effort to reduce power
consumption without increasing the time required to detect hidden sensors.
NCIC 06 DOUBLE EDGE TRIGGERED FLIP FLOP DESIGN USING
CONDITIONAL PULSE ENHANCEMENT SCHEME
A.Saisudheer, V. Muralipraveen
Abstract: In this paper, a novel low-power pulse-triggered flip-flop (FF) design is
presented. First, the pulse generation control logic, an AND function, is removed from
the critical path to facilitate a faster discharge operation. A simple two-transistor AND
gate design is used to reduce the circuit complexity. Second, a conditional pulseenhancement technique is devised to speed up the discharge along the critical path only
when needed. As a result, transistor sizes in delay inverter and pulse-generation circuit
can be reduced for power saving. Various post layout simulation results based on UMC
CMOS 50-nm technology reveal that the proposed design features the best power-delayproduct performance in seven FF designs under comparison. Its maximum power saving
against rival designs is up to 0.013µm. Compared with the conventional transmission
gate-based FF design, the average leakage power consumption is also reduced by a factor
of 1.52
NCIC 07 DA-BASED DCT WITH ERROR-COMPENSATED ADDER
TREE
Chinababu Panduru, P. Mahesh Kumar
Abstract: Here we are operating the shifting and addition in parallel, an errorcompensated adder-tree (ECAT) is proposed to deal with the truncation errors and to
achieve low-error and high-throughput discrete cosine transform (DCT) design. Instead
of the 12 bits used in previous works, 9-bit distributed arithmetic-precision is chosen for
this work for peak-signal-to-noise-ratio (PSNR) requirements. Thus, an area-efficient
DCT core is implemented to achieve 1 Gpels/s throughput rate with gate counts of 22.2 K
for the PSNR requirements outlined in the previous works.
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Proceedings of National Conference on Information and Communication (NCIC’13)
NCIC 08 GPS BASED RAILWAY TRACK SURVEY SYSTEM
V.Mahalakshmi, Dr.K.O.Joseph
Abstract— Now a days due to natural disaster like floods, earthquake, cyclone, etc.
there are many accidents are occurring in Railways due to cracks in the rails. System
have some limitations and delay in delivering the signals, if the bridges or track got
damaged, the information goes to railway authority people takes prolonged time and
there by notifying and informing to the corresponding trains takes more time. So to
avoid delays, our proposed system will immediately notifies and informs the current
train comes on the track through wireless medium. Project discusses the technical and
design aspects in detail and also provides the proposed multi sensor railway track
geometry surveying system. This paper also presents the details of the implementation
results of utilizing simple components inclusive of a GPS module, GSM Modem and
Displacement based track detector assembly. Surveying system describes in this project
is operational on both ballast and slab tracks. The system can be also operated in the
tunnels without any interruptions.
NCIC 09 EFFECT OF POWER INTEGRITY ON ANALOG CIRCUITS OVER
L-BAND FREQUENCY
Jagan.N, Umma Habiba.H, Prasad.S
Abstract –In mixed signal board with common power supply, the digital circuits
operating at high frequency produce switching noise affect the performance of the
sensitive RF circuits present at another end of the board. In this paper the power integrity
is discussed using solid power plane, power plane with AI-EBG, power plane with
double slit EBG and power transmission line techniques.
NCIC 10 OPPORTUNISTIC TRANSMISSION OF INFORMATION IN
COOPERATION SYSTEMS USING DISTRIBUTED SPACE TIME CODES
S.Yogesh Chinnaraja, A.Sumathi
Abstract—Distributed space-time coding (DSTC) is used in cooperation system
consisting of two cooperative users in sending their information to a common destination,
DSTC is applied in an opportunistic manner, called opportunistic DSTC (O-DSTC),
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Proceedings of National Conference on Information and Communication (NCIC’13)
depending on whether the two users succeed in decoding each other’s information or not.
An O-DSTC scheme is applied for full-duplex relaying scenarios, which is, referred to as
the full-duplex-based O-DSTC. Space Time codes (STC) were developed for frequency
non selective (flat) fading channels. In case of broadband wireless communication
systems, the channel exhibits frequency selectivity (delay spread), resulting in inter
symbol interference (ISI) that can cause serious performance degradation. Among the
various ISI mitigating approaches, orthogonal frequency division multiplexing (OFDM)
is one of the most promising techniques as it eliminates the need for high complexity
equalization and offers high spectral efficiency. In order to combine the advantages of
both the MISO systems and the OFDM, space-frequency (SF) coded MISO OFDM
systems have been proposed, where two-dimensional coding is applied to distribute
channel symbols across space (transmit antennas) and frequency (OFDM tones).BER
analysis of both O-DSTC and SFC are done
NCIC 11 DESIGN OF COST EFFICIENT MEMORY USING ADVANCED
ERROR CORRECTION METHOD
M.Poornima, P.Rajendiran
Abstract -- Faults in the memory generally tested by comparing faulty circuits with test
circuits. Due to this testing process cost of memory is increasing. To reduce testing cost
prefect error correcting method is required. A methodology existing here is called a
matrix code, combines hamming and parity code to assure the improvement of reliability
and yield of the memory chip in the presence of high defects. The method is evaluated
using fault injection experiments. The result are compared to well-known technique such
as reed-muller and hamming code. LDPC (Low Density Parity Code) codes are find in
increasing use in application requiring reliable and highly efficient information transfer
over bandwidth or return channel-constrained links in the presence of data corrupting
noise LDPC which will detect and correct multiple errors in memory.
NCIC 12 IMPLEMENTATION OF WORD MATCHING STAGE OF BLASTN
USING MODIFIED BLOOM FILTER
A.Jenifer, S.Karthick
Abstract — Basic Local Alignment Search Tool (BLAST) is a standard computer
application that molecular biologists use to search for sequence similarity in genomic
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Proceedings of National Conference on Information and Communication (NCIC’13)
databases. BLASTN, a version of BLAST specifically designed for DNA sequence
searches i.e., it will find the similarities between the query sequence and the subject
sequence. This similarity is to understand the function and evolutionary history of an
organism. In this BLAST process, word matching stage is the most time consuming part.
While the database increases, the speed of the BLAST process gets decreased. In order to
derive an efficient structure for BLASTN, a reconfigurable architecture is proposed to
accelerate the computation of the word matching stage. This paper describes an FPGA
based hardware implementation designed to accelerate the BLAST algorithm. The main
objective is to explore the feasibility of using bloom filter to realize a portable FPGA
based accelerator. Finally, the results are compared with the NCBI BLASTN software
running on a general purpose computer.
NCIC 13 A NOVEL WITRICITY FOR WIRELESS CHARGING
Kannan S, N.Sasirekha.,M.E.,(Ph.D)
Abstract— The main objective of this project is to develop a device for wireless power
transfer. Wireless power transfer can make a remarkable change in the field of the
electrical engineering which eliminates the use conventional copper cables and current
carrying wires. Based on this concept, the project is developed to transfer power within a
small range. This project can be used for charging batteries those are physically not
possible to connect electrically such as pace makers implanted in the body that runs on a
battery. Moreover this technique can be used in number of applications, like charging a
mobile phone, iPod, laptop battery, propeller clock wirelessly. This concept is an
Emerging Technology, and in future the distance of power transfer can be enhanced as
the research across the world.
NCIC 14 LOW-POWER AND AREA-EFFICIENT CARRY SELECT ADDER
USING MODIFIED BEC-1 CONVERTER
L.Mugilvannan, S.Ramasamy
Abstract -Carry Select Adder (CSLA) is one of the fastest adders used in many dataprocessing processors to perform fast arithmetic functions. From the structure of the
CSLA, it is clear that there is scope for reducing the area and power consumption in the
CSLA. This work uses a simple and efficient transistor-level modification in BEC-1
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Proceedings of National Conference on Information and Communication (NCIC’13)
converter to significantly reduce the area and power of the CSLA. Based on this
modification 16-b square-root CSLA (SQRT CSLA) architecture have been developed
and compared with the SQRT CSLA architecture using ordinary BEC-1 converter. The
proposed design has reduced area and power as compared with the SQRT CSLA using
ordinary BEC-1 converter with only a slight increase in the delay. This work evaluates
the performance of the proposed designs in terms of delay, area, and power by hand with
logical effort and through Cadence Virtuoso. The results analysis shows that the proposed
CSLA structure is better than the SQRT CSLA with ordinary BEC-1 converter.
NCIC 15 KEY DISTRIBUTION SCHEME FOR HIERARCHICAL CLUSTER
WIRELESS SENSOR NETWORK
S. Jenifer Ruby,T. Kavitha
Abstract— In wireless sensor networks (WSNs), key management is one of the vital
aspects of security. Since sensor networks suffer from the resource constraints like
inadequate memory space, connectivity, resiliency, communication overhead, key pre
distribution scheme be supposed to need a smaller amount memory space as likely as
supporting strong security power, i.e., high resilience against node capture. a random-key
pre distribution scheme has professional explanation for distribution keys between sensor
nodes. In this paper propose new key distribution which is based on stated based, signal
range and clustering heterogeneous sensor nodes. Uses deployment knowledge to divide
deployment regions into overlap clusters, every of which has its own distinct key space.
The signal ranges of the sensor nodes might considerably develop the performance of the
key-sharing method, if two sensor nodes directly located within communication range
and also to be in active-state at the similar time. Key pre distribution scheme that
guarantees a higher probability of sharing keys between nodes that are within the signal
range. As an outcome, the planned approach provides enough security and is expected to
minimize the key ring, decrease the communication overhead, and provide high
connectivity. Through careful assembly of these clusters, network resilience is enhanced,
without compromise connectivity or communications overhead.
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Proceedings of National Conference on Information and Communication (NCIC’13)
NCIC 16 ACCUMULATOR BASED PSEUDORANDOM BIST
S.Naveen Pitchumani,,K.L.Hemalatha
Abstract-- In a BIST design, the generation and application of the test vectors and the
analysis of the resulting response are part of the circuit (or system) under test. Weighted
pseudorandom built-in self-test (BIST) schemes have been used to reduce the number of
test vectors for achieving complete fault coverage in BIST applications. 3-weight pattern
generation uses only three weights, 0, 0.5 and 1. An accumulator-based 3-weight test
pattern generation scheme is presented that tests the MAC unit with different multiplier
such as Vedic Multiplier, Booth multiplier, Array multiplier and different adders such as
Carry look ahead adder, Ripple carry adder; the proposed scheme generates set of
patterns with weights 0, 0.5, and 1. Comparison is done based on the speed of operation
of MAC with all these three types of multipliers and finally we carried out BIST with
proposed Accumulator Based 3-Weight Pattern Generation by changing the adders used
in the MAC.
NCIC 17 AN EFFICIENT LOGIC TEST STRUCTURE FOR LOW POWER
TESTING
P.Anand Selvakumar,K.L.Hemalatha
Abstract- In this paper proposes a new single cycle access test structure for logic test. It
will eliminates the unnecessary dynamic power consumption problem of conventional
shift-based scan chains during switching transition in the scan FF and also reduces the
accessing time into one clock cycles. This leads to more realistic circuit behavior during
stuck-at and at-speed tests. It enables the complete test to run at much higher frequencies
equal or close to the one in functional mode. It will be shown, within one clock cycle
testing can be achieved compared to other published solutions we carried out testing with
some published solutions on ISCAS’89 net lists. And finally we developed BIST in
steganography design where initially we developed new algorithm with high embedding
capacity and also undetectable by statistical analysis methods such as Regular-Singular
(RS) and Chi-square analyses. Here we use LFSR as key module to overcome the
security holes in the existing systems. In functional mode this LFSR module will be used
for steganography application and in testing mode this will act as a random generator
.The structure allows an additional on-chip debugging signal visibility for each register.
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Proceedings of National Conference on Information and Communication (NCIC’13)
NCIC 18 LUT OPTIMIZATION USING COMBINED APC-OMS TECHNIQUE
FOR MEMORY-BASED COMPUTATION
R.Ramya,S.Sudha
Abstract-The efficient memory computing system alternative to conventional logic
computing is required in DSP applications. The LUT designed using combined APCOMS technique can be used for these applications. APC-OMS technique reduces the
LUT size to one-fourth of its original. In this paper, FIR filter is designed using
conventional LUT. If conventional LUT is used, the on-chip memory size is getting
larger. The memory size can be reduced by decomposing the LUT. FIR filter is designed
using multiplexer which is used to select the filter co-efficients. With LUT, area and
delay efficiency cannot be achieved. This design has less number of memory accesses
and area than LUT based FIR design. By the proposed method, 50% area efficiency and
20%throughput is achieved. The filter designs are simulated using Modelsim6.4a and are
synthesized using Quartus II 9.0.
NCIC 19 VLSI IMPLEMENTION OF ROBUST SECURE SCAN BASED DESIGN
FOR DIFFERENTIAL CRYPTANALAYSIS
G.Agalya, S.Sudha
Abstract— Cryptography plays a key role in ensuring the privacy and integrity of data.
Cryptanalysis is the study of how to crack encryption algorithms and their
implementations. Differential cryptanalysis is a plain text attack which occurs in the
cryptographic system. Testing can control and observe the internal states of the system.
While testing in the cryptographic system, by observing the input and output bit changes,
the third persons may shift out key. To reduce the observability and to increase the
security, Robust secure scan design(RSS) is proposed. RSS design encrypts the content
during scan chain operation..By adding pipelining process in the S Box and transforming
the S Box transformation into combinational design,50% high throughput is achieved
over the standard Encryption algorithm. By this method the security is much improved as
it incorporates RSS design, which involves double encryption process
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Proceedings of National Conference on Information and Communication (NCIC’13)
NCIC 20 DESIGN OF WIRELESS HOME AUTOMATION AND SECURITY
SYSTEM USING PIC MICROCONTROLLER
V. Sathya Narayanan, S. Gayathri
Abstract—The development of the new technologies in the field of electronics has
brought tremendous changes in the day to day life of every human being. They have
entered the fields like industry, medicine, telecommunication and also home automation.
This paper introduces the intelligent home automation system (IHAM) which is
developed using PIC microcontroller with the ZigBee wireless communication
technology, speech recognition technique and GSM network technology that control
the home appliance. The automation centres on recognition of voice commands and uses
low-power RF ZigBee wireless communication modules which are relatively cheap. The
home automation system is used to control all lights and electrical appliances in a home
or office using voice commands with help of HM2007 chip that is widely used for such
appliances. The proposed system gives the overall framework of hardware and
software design, and describes ways to implement the system. The paper also explains
the security system for fire hazards that may occur through smoke sensor and GSM
Module that is controlled by the same controller that sends the SMS to the user if the
smoke is detected.
NCIC 21 HARDWARE IMPLEMENTATION OF SCALABLE ENCRYPTION
ALGORITHM
Sharon Preethi G , T.Blesslin Sheeba
Abstract-The advent of new low-power Field Programmable Gate Arrays (FPGA) for
battery powered devices opens a host of new applications to FPGAs. In order to provide
security on resource constrained devices lightweight cryptographic algorithms have been
developed. SEA is a scalable encryption algorithm targeted for small embedded
applications. It is a lightweight cryptographic algorithm. It was initially designed for
software implementations in controllers, smart cards, or processors. In this Paper we
proposed a system that investigates its performances in recent field-programmable gate
array (FPGA) devices. The proposed system is applicable where there are limited
processing resources and throughput requirements. For this purpose, we propose low-cost
encryption routines with small code size and memory targeted for processors with a
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Proceedings of National Conference on Information and Communication (NCIC’13)
limited instruction set. Further we are carrying out ASIC implementation of Scalable
encryption algorithm to reduce area and improve efficiency.
NCIC 22 A SYMMETRIC LOAD BALANCING FOR DISTRIBUTED HASH
TABLE USING VIRTUAL SERVER
M.raja
Abstract- Peers participating in a distributed hash table (DHT) may host different
numbers of virtual servers and are enabled to balance their loads in the reallocation of
virtual servers. Most decentralized load balance algorithms designed for DHTs based on
virtual servers require the participating peers to be asymmetric, where some serve as the
rendezvous nodes to pair virtual servers and participating peers, thereby introducing
another load imbalance problem. While state-of-the-art studies intend to present
symmetric load balancing algorithms, they introduce significant algorithmic overheads
and guarantee no rigorous performance metrics. In this paper, a novel symmetric load
balancing algorithm for DHTs is presented by having the participating peers approximate
the system state with histograms and cooperatively implement a global index. Each peer
independently reallocates in our proposal its locally hosted virtual servers by publishing
and inquiring the global index based on their histograms. Unlike competitive algorithms,
our proposal exhibits analytical performance guarantees in terms of the load balance
factor and the algorithmic convergence rate, and introduces no load imbalance problem
due to the algorithmic workload. Through computer simulations, we show that our
proposal clearly outperforms existing distributed algorithms in terms of load balance
factor with a comparable movement cost
NCIC 23 ENERGY EFFICIENT DATA TRANSMISSION WITH MOBILE SINK
IN CLUSTERING PROTOCOL
Sathish.G.P, B.R.Shyamala Devi
Abstract— Designing an Energy Efficient Data Transmission Protocol has a
significant influence on the energy performance of Wireless Sensor Network (WSN). A
set of isolated urban areas (e.g. urban parks or building blocks) covered by sensor nodes
(SNs) monitoring environmental parameters (e.g., pollution, fire detection, light intensity,
temperature, moisture, surveillance etc..). Mobile sinks (MSs) are fixed upon the public
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Proceedings of National Conference on Information and Communication (NCIC’13)
vehicles with fixed trajectories (e.g. buses) to collect the sensory data from WSN fields.
Within the MS’s range the existing system involve either single-hop transfer of data from
SNs involving in data retrieval, processing, buffering and delivering tasks. These nodes
run the risk of rapid energy consumption causing decreased network lifetime and loss of
network connectivity. Our proposed protocol aims at minimizing the overall network
overhead and energy expenditure associated with the multihop data retrieval process
while also ensuring balanced energy consumption among SNs and prolonged network
lifetime. This can be achieved through building cluster structures consisted of member
nodes that route their measured data to their assigned cluster head (CH) and a mobile sink
deployed in sensor area collects the sensory data from cluster heads through random path.
CHs performs data filtering upon raw data exploiting potential spatial-temporal data
redundancy and pass the filtered data to appropriate end nodes with sufficient residual
energy, located in proximity to the MS’s trajectory. Simulation results confirm the
effectiveness of our approach against as well as its performance gain over alternative
methods.
NCIC 24 COMPONENT ANALYSIS BASED FACIAL EXPRESSION
RECOGNITION
G.Sethuram Rao, M.Jeeva Bharathi and Sanjay Kumar Suman
Abstract The Intelligence of Human-Computer Interaction is one of the hot researching
areas. Facial expression recognition is an important part of human-computer interaction.
At present, the research of facial expression recognition has entered an era of a new
climax. In real-time facial expression recognition system, the paper presents an
expression feature extraction method that combined canny operator edge detection with
the AAM (active appearance model) algorithm. During the Canny edge detection, the
adaptively generated high and low thresholds, increased the capability of noise
suppression, and the time complexity of the algorithm is less than the traditional canny
operator. Finally, by using leas squares method, we can classify and identify the feature
information.
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Proceedings of National Conference on Information and Communication (NCIC’13)
NCIC 25 LOW COST NONRECURSIVE DIGITAL FILTER STRUCTURES
G. Shanmugaraj, N. Kalaiarasi
Abstract—This paper presents a novel method of hardware reduced fast FIR filter
structure for parallel data processing. In general, arithmetic operation modules such as
adder and multiplier modules, consume much power, energy, and circuit area. The power
consumed by the adder structure is also very significant while designing a low power
filter. The proposed low power multipliers and low power adders are used to reduce
dynamic power consumption of digital FIR filter. Supported by a review of literature, the
proposed methodology is superior and economical. The results show improved
performance in terms of cost reduction, which has practical implications in terms of
applications.
NCIC 26 A CROSS LAYER DESIGN FOR TRANSPORT
OF VIDEO OVER WIRELESS NETWORKS
A. Dhanalakshmi, L. Balaji
Abstract-To maximize end user satisfaction, Wireless
multimedia
applications
needs the communication network to allocate resources dynamically. Cross layer
framework design offers a solution to this problem. In this paper a cross layer framework
design strategy optimizes the application, physical, and MAC layers jointly for
video streaming. An efficient FEC mechanism to combat channel errors is chosen
based on the channel condition. The optimization is done to maximize the average
PNSR of the received video signal.
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Proceedings of National Conference on Information and Communication (NCIC’13)
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