Leonardo Electronic Journal of Practices and Technologies
Issue 24, January-June 2014
ISSN 1583-1078
p. 83-96
Improved Switching Performance Analysis of Space Vector Pulse width
Modulation on Field Programmable Gate Array
Nagalingam RAJESWARAN1*, Tenneti MADHU2 and Munagala SURYAKALAVATHI3
1
Dept.of ECE, SNS College of Technology, Coimbatore, Tamilnadu, India.
Swarnandhra Inst. of Engg. and Tech., Narasapur, Andhrapradesh, India.
3
Dept. of EEE, Jawaharlal Nehru Technological University, Hyderabad, Andhrapradesh,
India.
E-mails: rajeswarann@gmail.com; tennetimadhu@gmail.com; mungala12@yahoo.co.in
2
*
Corresponding author: +91-422-2666264
Abstract
Nowadays VLSI (Very Large Scale Integration) technology is being
successfully implemented by using Pulse Width Modulation (PWM) in
applications like power electronics and drives. The main problems in PWM
viz. harmonic distortion and switching speed are overcome by implementing
the Space-Vector PWM (SVPWM) technique by using the Xilinx tool VHDL
(Verilog High Speed Integrated Circuit (VHSIC) Hardware Description
Language) and tested in programmable Integrated Circuits of Field
Programmable Gate Array (FPGA). The results are provided along with
simulation analysis in terms of hardware utilization and schematic, power
report, computing time and usage of memory.
Keywords
Field Programmable Gate Array; Pulse Width Modulation; Space Vector
Pulse Width Modulation; Hardware Description Language
83
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Improved Switching Performance Analysis of Space Vector Pulse width Modulation on Field Programmable…
Nagalingam RAJESWARAN, Tenneti MADHU, and Munagala SURYAKALAVATHI
Introduction
In many new industrial applications the usage of switching power converters
especially the PWM inverter controllers have lead to improvements in power electronic
systems and modern motor drives [1]. The output voltage of inverter fed to the induction
motor system is mainly determined by PWM strategy. When a PWM signal is applied to the
gate of a power transistor, it causes the turns ON and OFF intervals of the transistor to change
from one PWM period to another [2]. The major issue with PWM is the presence of
harmonics. In many industrial applications, Sinusoidal PWM (SPWM), also called Sine coded
PWM, is used to control the inverter output voltage [3]. The output frequency of SPWM is 50
Hz and the design is limited to two levels of modulation index viz. 0.5 and 0.75 [4]. SPWM
reaches only up to 78% of square-wave operation, but the amplitude of maximum possible
voltage is 90% of square-wave in the case of SVPWM. Vmax = Vdc/2 for Sinusoidal PWM and
Vmax = Vdc/√3, where, Vdc is DC-Link voltage for Space Vector PWM [5].This means that
SVPWM can produce about 15% higher than SPWM in output voltage and offers great
flexibility to optimize switching waveforms [6 -9].
In Figure.1, the Root Mean Square (RMS) voltage is called the effective voltage, as
opposed to the peak voltage which corresponds to the maximum amplitude of the voltage
Maximu
m
variations.
Peak
Average
Effective or RMS
Voltag
Time
Maximum
negative
Figure 1. Sine Waveform with RMS
Total Harmonic Distortion (THD) is defined as the ratio of the rms value of the
waveform not including the fundamental, to the rms fundamental magnitude [10]. When no
DC is present, this can be written as,
α
THD
=
∑ I
I
n=2
2
n
(1)
1
The amplitude of the odd harmonics produced depends only upon the ratio of the dead
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Leonardo Electronic Journal of Practices and Technologies
Issue 24, January-June 2014
ISSN 1583-1078
p. 83-96
time to the period of switching frequency. Accordingly, it has been possible to present
generalized curves which allow the design engineer to estimate the amplitudes of these
harmonics for any combination of fundamental and modulating frequencies [11].
PWM strategies implemented by microprocessor-based hardware and software have
the advantages of flexibility, precise control and less components leading to compactness and
lower cost. Space -Vector PWM provides a better technique compared to the more commonly
used PWM or sinusoidal PWM (SPWM) techniques because of their easier digital realization
and better DC bus utilization [12].
FPGA implementation of SVPWM provides advantages such as rapid prototyping,
simpler hardware and software design, high speed computation and hence fast switching
frequency [13-15]. The proposed design methodology is used for the improvement of overall
performance of the SVPWM in terms of total hardware utilization in Integrated Circuits(IC).
Material and Method
Space Vector PWM in Figure 2, uses space-vectors to generate the gate signals and is
implemented by averaging the time spent in adjacent switching states.
S2
[0 1 0] V3
[1 1 0] V2
1/√3Vdc
S3
S1
[1 0 0] V1
[0 1 1] V4
2/3Vdc
S4
S6
[0 0 1] V5
S5
[1 0 1] V6
Figure 2. Space Vector Diagram
Totally six switches are used i.e, S1 to S6.The values of switching vectors are assigned in
Table 1 and there are eight possible combinations of ON and OFF patterns for the three upper
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Improved Switching Performance Analysis of Space Vector Pulse width Modulation on Field Programmable…
Nagalingam RAJESWARAN, Tenneti MADHU, and Munagala SURYAKALAVATHI
electronic switches from the value of 000 to 111 related with V0 to V7. Here the ON and OFF
states of the lower power switches are opposite to the upper ones and are completely
determined once the states of the upper power electronic switches are known. Generally, the
SVPWM implementation involves sector identification, switching time calculation, switching
vector determination and optimum-switching-sequence selection for the inverter voltage
vectors [16].
Table 1. Illustrating Switching Vectors and Line Voltages
Line to neutral Line to
Voltage
Switching Vectors
Voltage
line voltage
Vectors
A
B
C Van Vbn Vcn Vab Vbc Vca
V0
0
0
0
0
0
0 0 0 0
V1
1
0
0 2/3 -1/3 -1/3 1 0 -1
V2
1
1
0 1/3 1/3 -2/3 0 1 -1
V3
0
1
0 -1/3 2/3 -1/3 -1 1 0
V4
0
1
1 -2/3 1/3 1/3 -1 0 1
V5
0
0
1 -1/3 -1/3 2/3 0 -1 1
V6
1
0
1 1/3 -2/3 1/3 1 -1 0
V7
1
1
1
0
0
0 0 0 0
V0, V1 ..... V7 are the voltage vectors;
A,B,C are the switching vectors of SVPWM
Van,Vbn,Vcn are the Line to neutral voltage
Vab,Vbc,Vca are the Line to line voltage
Space vector representation of three-phase quantities xa(t), xb(t) and xc(t) with space
distribution of 120o apart is given by:
x=
2
2
( (t ) + a b (t ) + a x c (t ))
3 xa
(2)
where, a = ej2π/3 = cos (2π/3) + jsin(2π/3); a2 = ej4π/3 = cos (4π/3) + jsin(4π/3); x – can be a
voltage, current or flux and does not necessarily has to be sinusoidal
The waveform of SVPWM is shown in Figure.3 with the phase voltages and the total
time period ‘T’. The voltages Va,Vb and Vc represent the three phase voltages of the power
supply. T1, T2, T0 and T7 are calculated based on volt-second integral of vref .
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Leonardo Electronic Journal of Practices and Technologies
Issue 24, January-June 2014
ISSN 1583-1078
p. 83-96
V1
V0
V2
V7
Va
Vb
Vc
T0/2
T1
T2
T
T
Figure 3. Waveform of SVPWM
T
T7
T1
T2
T
⎤
1
1⎡0
v
v
dt
v
dt
v
dt
v 7 dt ⎥
=
+
+
+
⎢
0
1
2
ref
∫
∫
∫
∫
∫
T 0
T ⎢⎣ 0
⎥⎦
0
0
0
v ref .T = T 0 . 0 +
2
2
o
o
.
+ V d (cos 60 + j sin 60 ) T 2 + T 7 . 0
V
d T1
3
3
v ref .T = v 0 .T 0 + v1 .T 1 + v 2 .T 2 + v 7 .T 7
v ref .T =
2
2
o
o
.
+ v d (cos 60 + j sin 60 ) T 2
v
d T1
3
3
(3)
(4)
(5)
(6)
T v ref cos α =
2
1
.
+
3 vd T 1 3 vd T 2
(7)
T v ref sin α =
1
vT
3 d 2
(8)
Solving for T1, T2 and T0,7 gives:
⎤
3 ⎡ T
1
m
cos α − T sin α ⎥
2 ⎢⎣ 3
3
⎦
T
1
=
T
2
= mT sin α
(9)
(10)
where,
m =
v
ref
(2)
vd
3
The switching table and states are given in Table 2. To make the oscillation between
the high and low states, the clock signal is applied. In Table 3, two clock signals namely clock
and clk1 are used. They will be assigned as different set of offset values and make them as the
rising edge. The Clock to setup on destination clock CLK1 and Clock are 10.267ns and
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Improved Switching Performance Analysis of Space Vector Pulse width Modulation on Field Programmable…
Nagalingam RAJESWARAN, Tenneti MADHU, and Munagala SURYAKALAVATHI
5.991ns respectively. Two different reset signals are used in the design. First reset signal is set
as low and second reset signal rst is set high for the simulation of the assigned input.
Table 2. Switching table Table 3. Simulation parameters
Parameters Value Assigned
State Switch Number
clock
40 offset
A B
C
000 OFF OFF OFF
reset
0
100 ON OFF OFF
Enable
1
110 ON ON OFF
Value
01
010 OFF ON OFF
clk1
50 offset
011 OFF ON ON
rst
1
001 OFF OFF ON
clk_out
Analog set
101 ON OFF ON
waveout
Analog set
111 ON ON ON
FPGA Implementation
The selected FPGA device is xc3s500e-4-pq208. The total available pin of the selected
FPGA device is P208.The total allotted pins for the input and output is 23. The Input and
Output (IOB) properties of the device are given in the Table 4. The static timing report and
clock reports simulation outputs (screen shots) are shown in Figures 4-6. All the values are
given in nanoseconds (ns). The four clock regions X0Y0, X1Y0, X0Y1 and X1Y1 are used in
the design. The summary of the components used in these regions are given in Table 5.
In digital implementation, this algorithm is simplified in the hardware design (Shown
in Figures 7-8). The RTL and technological view of SVPWM in FPGA are shown in Figures
9 and 10. The Number of External Input IOBs are 7, Number of External Input IBUFs are 7,
Number of External Output IOBs are 16, and Number of External Bidir IOBs are 0. Overall
effort level (-ol): Standard, Placer effort level (-pl): High, Placer cost table entry (-t): 1 and
Router effort level (-rl): Standard. The synchronization of different modules is one of the
important tasks in IC. The timing reports have clearly proved that there is an overall
improvement in the performance of the design. It will reduce the complexity of the IC and
make it becomes more fast.
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Leonardo Electronic Journal of Practices and Technologies
Issue 24, January-June 2014
ISSN 1583-1078
p. 83-96
Table 4. IOB Properties
IOB Name Type Direction IO Standard Drive Strength PIN Number
CLK1
IBUF INPUT LVCMOS25
P184
CLK_out<0> IOB OUTPUT LVCMOS25
12
P112
CLK_out<1> IOB OUTPUT LVCMOS25
12
P116
CLK_out<2> IOB OUTPUT LVCMOS25
12
P115
CLK_out<3> IOB OUTPUT LVCMOS25
12
P109
CLK_out<4> IOB OUTPUT LVCMOS25
12
P119
CLK_out<5> IOB OUTPUT LVCMOS25
12
P120
CLK_out<6> IOB OUTPUT LVCMOS25
12
P113
CLK_out<7> IOB OUTPUT LVCMOS25
12
P123
RST
IBUF INPUT LVCMOS25
P106
VALUE<0> IBUF INPUT LVCMOS25
P110
VALUE<1> IBUF INPUT LVCMOS25
P108
clock
IBUF INPUT LVCMOS25
P183
enable
IBUF INPUT LVCMOS25
P107
reset
IBUF INPUT LVCMOS25
P130
wave_out<0> IOB OUTPUT LVCMOS25
12
P132
wave_out<1> IOB OUTPUT LVCMOS25
12
P133
wave_out<2> IOB OUTPUT LVCMOS25
12
P128
wave_out<3> IOB OUTPUT LVCMOS25
12
P129
wave_out<4> IOB OUTPUT LVCMOS25
12
P134
wave_out<5> IOB OUTPUT LVCMOS25
12
P135
wave_out<6> IOB OUTPUT LVCMOS25
12
P137
wave_out<7> IOB OUTPUT LVCMOS25
12
P140
Figure 4. Simulation output of Clock Clock to Figure 5. Simulation output of Clock CLK1 to
PAD
PAD
Figure 6. Simulation output of Clock Report
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Improved Switching Performance Analysis of Space Vector Pulse width Modulation on Field Programmable…
Nagalingam RAJESWARAN, Tenneti MADHU, and Munagala SURYAKALAVATHI
Table 5. Summary of Components used in the clock
Module Used Available Percentage(%)
DIFFM
6
29
20
Clock
DIFFS
7
29
24
Region X1Y0
IBUF
2
11
18
SLICEL
20
582
3
SLICEM 20
582
4
Clock
DIFFMI
1
11
9
Region X0Y1 DIFFSI
1
11
9
BUFGMUX 2
6
33
DIFFM
3
29
10
Clock
DIFFS
3
29
10
Region X1Y1
SLICEL
23
582
3
SLICEM 25
582
4
Figure 7. RTL Internal block view of SVPWM
Figure 8. Gate level schematic view
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Leonardo Electronic Journal of Practices and Technologies
Issue 24, January-June 2014
ISSN 1583-1078
p. 83-96
Figure 9. RTL View of SVPWM
Figure 10. Technological view
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Improved Switching Performance Analysis of Space Vector Pulse width Modulation on Field Programmable…
Nagalingam RAJESWARAN, Tenneti MADHU, and Munagala SURYAKALAVATHI
Results and Discussions
The design and FPGA implementation of programmable Space Vector Pulse width
Modulation (SVPWM) control circuit is presented. The Total simulation time is 11.854ns
(8.042ns logic, 3.812ns route) (67.8% logic, 32.2% route), Total memory usage is 164308
kilobytes. Total REAL time to Xst completion is 6.00 secs and Total CPU time to Xst
completion is 5.92 secs. The data flow schematic, shown in Figure 11, with the signals are
represented as clock, reset, enable, state, next_state, table_index, clk1, rst, value wave_out.
The signals clk_out, and wave_out are assigned values as height 50, offset value 5.0 and scale
of 0.777. The total length is 8 bits.
Figure 11 Data flow model of SVPWM
Once the inputs are assigned, the program runs and the outputs are displayed as a
waveform. The simulated output for the SVPWM using Xilinx tool is shown in Figure 12.
The timing summary is tabulated in Table 6. In Table 7, the maximum utilization of hardware
is only 2-3 percentage compared with the available units. The requirement of power to
produce the output is 0.081W.
Table 6. Timing Summary
Parameters
Frequency
Minimum period
10.857 ns
Maximum Frequency
92.108 MHz
Minimum input arrival time before clock
6.647 ns
Maximum output required time after clock 11.854 ns
Maximum combinational path delay
No path found
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Leonardo Electronic Journal of Practices and Technologies
Issue 24, January-June 2014
ISSN 1583-1078
p. 83-96
Table 7. Device Utilization Summary
Parameters
Used Available Utilization
Logic Utilization
53
Number of Slice Flip Flops
Number of 4 input LUTs
153
Logic Distribution
96
Number of occupied Slices
Number of Slices containing only related logic 96
Number of Slices containing unrelated logic 0
Total Number of 4 input LUTs
185
Number used as logic
153
Number used as a route-thru
32
Number of Bonded IOBs
23
Number of BUFGMUXs
2
9312
9312
1%
1%
4656
96
96
9312
2%
100%
0%
2%
158
24
14%
8%
Figure 12. Switching waveform
The screen shot of power analysis report and thermal information are shown in Figure.
13 a and 13 b. The obtained ambient and junction temperature values are less. All the analysis
reports have clearly proved that the SVPWM technique is efficiently programmed and
implemented in IC.
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Improved Switching Performance Analysis of Space Vector Pulse width Modulation on Field Programmable…
Nagalingam RAJESWARAN, Tenneti MADHU, and Munagala SURYAKALAVATHI
Figure 13a and 13b. Screen shot of Power Analysis and Thermal Information report
Conclusions
The performance of SVPWM improves with increased switching frequency. This
technique when implemented in real time will reduce the hardware complexity and hence can
be used for the testing of three phase induction motor and other power electronic devices.
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Nagalingam RAJESWARAN, Tenneti MADHU, and Munagala SURYAKALAVATHI
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