2
We describe an application of stepwise charging for driving off-chip signals. Our driver, designed for a chip built in a
0.8
µ m bulk CMOS process, dissipates significantly less than CV 2 per cycle while driving a 100 pF load to a 5 V swing with transition times as low as 10 ns. The transition time is adjustable; dissipation measured on a test chip ranges from 53% of CV 2 at 16 ns to 70% at 10 ns. The target chip is approximately 6% larger with our driver than with a conventional one.
Low-power drivers for off-chip loads (pad drivers) present special challenges to the silicon-chip designer. The driving energies for external signals are typically orders of magnitude larger than for internal signals. Consequently, off-chip loads often dominate the total dissipation of a chip, even though there are likely many more internal than external nodes, and despite higher internal switching frequencies.
Pad-driver dissipation is difficult or expensive to reduce significantly by the conventional methods of voltage and capacitance reduction. The voltage swing is typically set by the interface level specifications of the surrounding chips.
The capacitance is largely determined by packaging. A reduction of either may incur a prohibitive cost or be infeasible for other reasons. Thus, the design space for a pad driver is severely restricted by system-level constraints. It is possible, when designing a tapered-inverter-chain driver, to trade dissipation for delay to some extent [1], but the total dissipation per charge-discharge cycle never goes below CV 2 .
In this paper, we present a pad driver designed to drive a load capacitance of 100 pF with a 5 V swing, with transition time less than 15 ns, and with total dissipation well below
CV 2 . The target chip uses 5 V external signalling with a
3.3 V core supply voltage. As a result, 80% of the dissipation is due to off-chip signalling. Significant further reduction of the total dissipation required a subCV 2 driver.
The driver described here uses stepwise charging to accomplish the dissipation goal. The principles of stepwise charging and a proof-of-concept driver have been described previously [2]; related ideas have also been published [3,4].
The driver presented here is capable of edge rates 50 times faster than those of the proof-of-concept driver, while still dissipating well under CV 2 per cycle. The increased level of performance required the implementation to be quite different from the proof-of-concept driver: here, the control pulses for the switches are generated asynchronously.
The remainder of this paper is organized as follows. In
Section 2, we give a brief background on the theory of stepwise charging. In Section 3, we describe the design of the pad driver, based on our mathematical modelling and on the application specifications. In Section 4, we describe a test chip, present performance data measured from that chip, and compare theory with simulation and measurements.
Section 5 contains our conclusions.
Switches
V
N
C
T
C
T
V
2
V
1
2
1
0
C
L
Figure 1. Simplified schematic of a stepwise-charging driver for a capacitive load switches
, , ,
C
N
L
. To charge the load from 0 to V , the
are pulsed in succession. Thus, the load is charged in N steps. To discharge the load, the switches are pulsed in the reverse order: N – 1
,
N – 2
…
0 .
ISLPED 1996 Monterey CA USA
0-7803-3571-8/96/$5.00

1996

V dd
V in
N opt
=
3 t
-----------
4m
ρ
C
T
C
T
C
L
Figure 2. Block diagram of stepwise pad driver. A transition on the input causes the controller to generate control pulses to turn on and off the switches (cf. Figure 1) in succession. The buffers match the drive capabilities of the controller outputs to the rather large gate capacitances of the switches.
The idea behind stepwise charging is to charge and discharge a capacitive load successively, in several steps, by moving charge from and to intermediate potentials. A conventional
CMOS inverter is a one-step charger: it delivers all charge directly to the load at potential V dd
and returns all charge from the load directly to ground at potential 0.
Figure 1 depicts a simplified schematic of a stepwise driver with N steps. Tank capacitors, mediate potentials V
1
…
V
N – 1
C
T
, provide the inter-
, given by V i
≈ iV
⁄
N
With these potential values, the average voltage drop across
.
each switch when the tanks are successively connected to the load is limited to V
⁄ (
2N
)
. Dissipation per cycle is therefore reduced by a factor of N compared to the conventional, one-step case. The tanks need not be preset to V i
; under weak conditions, the potentials provably converge to the ideal values when the driver repeatedly cycles the load
A complete pad driver requires a number of blocks in addition to the switches. Figure 2 shows a high-level block diagram of the driver described in this paper. The tank capacitors are shared by several drivers. Each tank must then be larger than the sum of all load capacitances; tanks are therefore placed off-chip, as they would be in most cases.
The first decision in the design of a stepwise driver is how many charging steps to use. For low-power purposes, we wish to find the number that gives the lowest overall dissipation. The best number of steps (based on a simple linear model of the switch) is given by the following equation [2]:
(1)
1.2
1
0.8
0.6
0.4
0.2
N = 2
N = 3
N = 4
N = 5
0
0 5 10
Transition time (ns)
15 20
Figure 3. Theoretical dissipation of the stepwise pad driver as function of transition time and number of charging steps, normalized to CV 2 . Note that dissipation exceeds CV 2 at sufficiently short transition times: the supplementary energy needed to drive several very large switch gate capacitances outweighs the gains in output energy.
Here,
ρ
models the intrinsic speed of the process; for the 0.8
µ m process used for this design,
ρ
= 15 ps. The parameter m is selected by the designer. It quantifies the exponential nature of the charging process: it is the number of RC time constants used for each charging step. Suitable values range from 2 to 4. We used m = 3 in this design.
Figure 3 shows the theoretical dissipation as a function of transition time for different numbers of charging steps. With the circuit and process parameters listed above, N opt
= 4
The minimum is shallow: only a few percent is gained by
.
going from three to four steps. Moreover, the total gate area of the switches increases as the square of the number of steps [2]: thus, a four-step design would require almost twice as much gate area as a three-step design. For these reasons, we chose three steps for this design.
Figure 1 shows each switch represented as a single nFET.
The present design is different in two important ways. First, each tank capacitor is connected to the load with two switches in parallel: one for charging and the other for discharging. This arrangement allows each switch to be optimally sized for its unique voltage range. In contrast, with single switches, each switch must be sized for the worse of the two transitions, and thus an unnecessarily large gate capacitance is driven during the other transition. Single switches suffice for the ground and V dd
connections, which each take part in only one transition. The second difference from Figure 1 is that two switches (the V dd
switch and the discharge switch for the top tank capacitor) are pFETs. These have a lower on-resistance per gate capacitance for the upper third of the voltage swing, where these switches operate.
The switch sizes were chosen to meet a target transition time of 10 ns as a safety margin against a slower-than-usual run. Switch device widths range from 250
µ m to 1000
µ m.

A
C
B
A
B
C
~d
D
~d
D’
Figure 4. The delay line has a tunable delay D. The intrinsic delay through the gate is constant and similar for both paths
(A
→
C and B
→
C), so the output pulse width D’ is close to D.
The controller of Figure 2 generates the gate pulses for the switches. With a transition time of 15 ns and three charging steps, the gate pulses should have a duration of 5 ns. No
200 MHz clock is available on the target chip, so we designed an asynchronous controller, whose core building block is outlined in Figure 4. The input signal is routed to a voltage-controlled delay line. The original and delayed versions of the signal are combined to yield a pulse of duration close to the delay when a positive-going edge appears on the input. Identical delay blocks are appended for more steps, and mirror-image logic generates pulses on negative-going edges. This arrangement also allows precise adjustment of the transition time during testing, which would not have been possible with a simpler feedback scheme [5].
0.8
0.7
0.6
0.5
0.4
0.3
0.2
0.1
measurements
Hspice simulation (no L)
Hspice simulation (with L)
0
10 12 14 16
Transition time (ns)
18 20
Figure 5. Measured and simulated dissipation for pad driver as a function of transition time. The simulated waveforms with added inductance exhibit ringing not present in the lab setup.
Since this ringing introduces a quasi-random element in the measurements, the curve is not as smooth for this case.
ate the detailed behavior of the test setup in simulation. It should be noted that lumped inductances are an overly simplified model of the actual current loops involved.
Figure 6 shows oscilloscope traces of the output signal of the test chip. Two traces with different transition times are shown. The edges appear smooth in the faster case because of test setup inductances and finite transition times of the gate pulses controlling the switches.
A photomicrograph of the test chip pad driver is shown in
Figure 7. As can be seen in the figure, the switches occupy a large part of the area. They would be less prominent if a smaller load and/or a longer transition time were specified.
The buffer section contains tapered inverter chains matching the drive capabilities of the controller outputs to the large gate capacitances of the switches. The input stage handles level conversion from the core voltage swing (3.3 V) to the
5 V used in the rest of the driver.
We have compared circuit simulations with measurements from a test-chip implementation of the driver. Before fabrication, the dissipation of the complete driver, including the controller, was estimated with HSPICE to be 60% of CV 2 at a transition time of 10 ns. This is worse than the theoretical estimate of 41% of CV 2 (Figure 3). Note, however, that the theory is based on an idealized device model. It also assumes that the output is allowed to fully reach each intermediate voltage before the next charging step commences. Both of these assumptions affect prediction accuracy. Furthermore, controller dissipation is not included in the theoretical figure.
Figure 5 shows lab measurements of the test chip driver dissipation as a function of transition time. The results of
HSPICE simulations using device parameters from the actual fabrication run are also shown (at around 65% of
CV 2 , these values are somewhat higher than for the pre-fabrication simulations). Intriguingly, the measured dissipation is lower than the simulated values. This effect appears to be due to parasitic inductance in the test setup. Figure 5 includes simulated figures with a 30 nH inductance added in each bonding wire. The resulting figures are closer to the measured ones, although we have not yet been able to recre-
Figure 6. Scope traces of output waveforms for two different transition times. Rise and fall time values are also shown.

Input Controller Buffers Switches Pad
Figure 7. Pad driver (test chip photo). Four pad rings run across the switches; in addition to the supply voltage and ground, they carry the two intermediate voltages. The tank capacitances are connected to the rings via dedicated pads (not shown). For size reference, the bonding area is 90
µ m square.
Pad drivers based on stepwise charging offer the unique combination of moderately fast transition times and sub-
CV 2 dissipation. The design described here reaches transition times as low as 10 ns while dissipating only 70% of
CV 2 . This is in the same range as that of typical slewratelimited pads. We believe that performance could be improved somewhat by fine-tuning the design and by exploiting better packaging.
The RC -based design procedure [2] for stepwise-charging buffers is adequate for determining starting points for circuit simulation iterations, even for drivers with relatively fast transition times such as this one. It should be realized, however, that Equation (1) is based on a highly simplified model of the MOS device, where gate capacitance and onresistance are linearly related. Neither short-channel effects such as velocity saturation nor packaging inductance are taken into account. Refinements of the theory would be useful, but detailed simulations would probably still be necessary to determine the actual performance of the driver, particularly for short-channel devices.
Stepwise pad drivers incur a penalty in terms of silicon area and I/O pins. Figure 7 indicates that the total area of driver and pad is approximately twice that of a conventional design. The overall area of the target chip, which is approximately 6 mm square, is about 6% larger with stepwise pad drivers than with conventional ones. The target chip is not I/
O-limited, and the extra pads needed to connect the drivers to the off-chip tank capacitors do not further increase the pad frame. The number of tank capacitor pins required per intermediate voltage depends largely on package and bond wire inductance. The inductance improves the dissipation figures somewhat, but it also degrades the transition time. We currently rely on circuit simulations to estimate its influence.
In summary, we have applied our theory and practice of stepwise charging to the specific design problem of a lowpower pad driver for a target chip specification. The resulting prototype has demonstrated the viability of stepwise charging as a practical means to reduce power dissipation when conventional techniques cannot be leveraged, as is the case for pad drivers, where voltage swing and transition time requirements severely constrain the design space.
This research was supported by ARPA under contracts number MDA903-92-D-0020, DABT63-19-C0052, and
DAAL01-95-K3528. We thank Sanjaya Dharmasena for helping out with simulations, and Erlend Olson for valuable comments.
[1] Brian S. Cherkauer and Eby G. Friedman. A unified design methodology for CMOS tapered buffers. IEEE Transactions on
VLSI Systems, vol. 3, no. 1, pages 99–111, March 1995.
[2] L.“J.” Svensson and J.G. Koller. Driving a capacitive load without dissipating fCV
2
. In Proceedings of IEEE Symposium on Low
Power Design, 1994, pages 100–101.
[3] Mark Hahm. Modest power savings for applications dominated by switching of large capacitive loads. In Proceedings of IEEE
Symposium on Low Power Design, 1994, pages 60–61.
[4] Kei-Yong Khoo and Alan N. Willson, Jr. Charge recovery on a databus. In Proceedings of ISLPD ‘95, Dana Point, 1995, pages
185–189.
[5] Mircea R. Stan and Wayne P. Burleson. Low-power CMOS clock drivers. In Proceedings of TAU ‘95, pages 149–156.