Rédha.
CHIBANI 1
ElMadjid.
BERKOUK 1
Mohamed
Seghir.
BOUCHERIT1
J. Electrical Systems 7-2 (2011): 131-148
Regular paper
Study of a new DC voltage equalising
circuit for Five-Level Neutral Point
Clamped-Voltage Source Inverter
This paper presents a new clamping bridge to solve capacitor balancing problems in Five-Level
Neutral-Point-Clamped Voltage Source Inverter (NPC VSI) and realise the equalisation in the
DC capacitor voltage. The voltage balancing circuit consists of four bidirectional switches and
two inductances. This solution avoids capacitor unbalancing problem, leads to a simpler
implementation and presents high equalization efficiency and increases the reliability of the
drive system. Simulation results show the effectiveness of our method. The cascade studied is a
two two-level PWM rectifier- five-level NPC VSI- Permanent Magnet Synchronous Machine.
Keywords: Multilevel inverter, Neutral Point Clamped, Voltage Source Inverter, Sliding mode, DC
capacitor voltage unbalance, Clamping bridge.
1. Introduction
The general trend in power electronic devices has been to switch power semiconductors at
increasingly high frequency in order to minimize harmonics and reduce passive
components sizes. However, the increase in switching frequency increases the switching
losses, which become especially significant at high power levels. One of the several
methods for decreasing switching losses is the multilevel inverter.
This kind of converter offers a high number of switching state so that the inverter output
voltage can be stepped in smaller increment. The multilevel inverters are considered today
as the most suitable power converters for high voltage capability and high power quality
demanding applications with voltage operation above classic semiconductor limits, lower
common-mode voltages, near-sinusoidal outputs, together with small dv/dt’s.
The multilevel converter has found widespread applications in industry. They can be used
for pipeline pumps in the petrochemical industry, fans in the cement industry, pumps in
water pumping stations, traction applications in the transportation industry, steel rolling
mills in the metals industry, grid integration of renewable energy sources, reactive power
compensation and other applications.
Multilevel inverter systems are generally classified as diode-clamping inverters, cascade
inverters, and flying-capacitor inverters. Among multilevel inverters, the three-level diodeclamped inverter, which is called the neutral-point clamped (NPC) inverter, has been
commonly used [1]. But the NPC inverter has a major disadvantage that there will be
voltage unbalance in DC capacitors (expense of the divergence of DC capacitor voltages
resulting in the collapse of one and rise of the other). This may result in poor quality
voltage outputs, affecting the control performance and causing a violation in the safe
operating limits leading to inverter malfunctioning.
However, it is difficult to control real power flow for balancing the neutral-point (NP)
potential. The causes of NP potential drift can be non uniform switching device or DC link
*
Corresponding author: R. Chibani, E-mail: redha29@yahoo.fr
Laboratoire de commande des processus ECOLE NATIONALE POLYTECHNIQUE. 10, Rue Hassen BADI.
ELHarrach BP182. ALGER. ALGERIE
1
emberkouk@yahoo.fr ; ms_Boucherit@yahoo.fr
Copyright © JES 2011 on-line : journals/esrgroups.org/jes
R. CHIBANI et al: Study of a new DC voltage equalising circuit for ...
capacitor characteristics or fluctuation due to the irregular and unpredictable charging and
discharging in each capacitor [2] [3] [4]. The voltage across the capacitor may grow or
decay so that the NP voltage fails to keep the half of the DC link voltage. Therefore, an
excessive high voltage may be applied to the switching devices of DC link capacitors and
this affects the converter performance due to the generation of uncharacteristic harmonics
and the presence of overvoltages across the semiconductor switches.
Therefore, the choice of appropriate modulation techniques and the development of
advanced neutral point potential control techniques are necessary to overcome the NP
potential problems. Some solutions have been proposed, which are based on redundant
switching configurations [1] [5-14] or on the addition of zero-sequence voltage components
to the output voltage [6]. However, all these methods seem to be not always useful in noload or low-load operations, when the supplied current tends to zero. In real systems, noload conditions determine almost always the loss of DC-link capacitors voltages balance,
owing to converter non ideality. Unfortunately, these methods modify the output voltage
waveform. As the number of inverter-level increases, the problem of capacitor balancing
becomes more complex and the solution very drastic.
The unbalance DC voltage problem can also be solved by separate DC sources [3] or by
adding electronic circuitry. In [15-17], clamping bridges based on transistors and resistors
are proposed as a solution to this problem. Disadvantages of this method are the
requirement for large power dissipating resistors, high current switches, and thermal
management requirements. This method is best suited for systems that are charged often
with small currents.
This paper deals with a new clamping bridge for the DC capacitor voltage equalisation. It
has been proposed to compensate DC-link capacitor voltages fluctuations in a NPC VSI
that permits to achieve a correct capacitors voltages sharing, when conventional balancing
methods fail.
In order to stabilize these DC voltages, we propose in this paper to study the cascade
constituted by two three- phase two-level PWM rectifier-clamping bridge - five-level NPC
VSI - Permanent Magnet Synchronous Machine.
2. Five-level cascade
The global scheme of the cascade is given on the figure 1.
Figure 1. Structure of the cascade proposed
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J. Electrical Systems 7-2 (2011): 131-148
2.1. Five-level NPC-VSI modelling
The general structure of the three-phase five-level NPC voltage source inverter is shown on
the figure 2. It is composed by 24 pairs transistor-diode.
Every leg of this inverter includes eight pairs, four on the upper half leg and four on the
lower one.
The optimal control law is given below:
Bk1 = Bk 5
Bk 2 = Bk 4
(1)
Bk3 = Bk6
B k 7 = B k 1 .B k 2 .B k 3
B k 8 = B k 4 .B k 5 .B k 6
Bks is the control signal of TDks . TDks represents every pair transistor-diode by one bidirectional switch.
The voltage of the three-phase A, B, C relatively to the middle point M and using the half
b
leg connection functions FkM are given by VXM with x = point A, B or C.
V kM = [ F kb1 .( U c 1 + U c 2 ) + F k 7 .( U c 1 )] − [ F kb0 .( U c 3 + U c 4 ) + F k 8 .( U c 3 )] (2)
The input currents of the three-phase five-level inverter using the load currents are given by
the following relations:
i d 1 = F11b .i1 + F 21b .i 2 + F 31b .i 3
′
′
′
i d 2 = F 11b .i 1 + F 21b .i 2 + F 31b .i 3
′
′
′
i d 3 = F 10b .i 1 + F 20b .i 2 + F 30b .i 3
i d 4 = F 10b .i 1 + F 20b .i 2 + F 30b .i 3
(3)
i d 0 = i1 + i 2 + i3 − i d 1 − i d 2 − i d 3 − i d 4
Figure 2. General structure of the three-phase five-level NPC VSI
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2.2. Control strategy of the inverter
This strategy uses four bipolar carriers ( U p1 , U p 2 , U p3 , U p 4 ). It is characterised by two
parameters m the index modulation and r the modulation rate. The algorithm of this
strategy can be summarised as follows:
Step 1: Determination of the intermediate voltages
If
V refk > U
If
V refk < U
If
V refk > U
If
V refk < U
If
V refk > U
p3
If
V refk
< U
p3
If
V refk > U
p4
If
V refk < U
p1
then
p1
p4
then
V
= 0
kM 1
then
V kM 2 = + 2U c
then
V kM 2 = +U c
p2
p2
V kM 1 = + U c
= 0
then
V kM
then
V kM 3 = −U c
then
V kM 4 = −U c
then
3
(4)
V kM 4 = − 2U c
Step 2: Determination of the output voltage
V kM = V kM 1 + V kM 2 + V kM 3 + V kM 4
(5)
3. Permanent Magnet Synchronous Machine modelling
The model of PMSM without damper winding has been developed on rotor reference
frame as follows [15][16][17][18]:
U d Rs + Ld s − ω .Lq id
0
=
.
+
Uq
ω .Ld
Rs + Lq s iq ω .Kt
(6)
The electric torque is stated as:
Cem = K t .iq + ( Ld − Lq ).id .iq
(7)
J .( sω ) = Cem − Cr − K .ω
(8)
Control of PM motors is performed using field oriented control for the operation of
synchronous motor as a DC motor. For the PM synchronous machine used, we develop the
algorithm i d =0 (Fig3). When the d axis current is equal to zero, the block diagram of the q
axis becomes similar to that of a DC machine and the speed can be controlled by using a
sliding mode controller which generates the q axis voltage. We use a current regulator for
the d and q axes [15][17].
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J. Electrical Systems 7-2 (2011): 131-148
Figure 3. Permanent Magnet Synchronous Machine speed control scheme based on sliding
mode
4. Two-level PWM current rectifier modelling and control
The general structure of the two-level PWM current rectifier is given on the figure 4.
Figure 4. Structure of one two-level PWM current rectifier
4.1. Modelling of the two-level PWM rectifier
The optimal control of this two-level PWM rectifier is (k=1,2,3):
B k 1r = B k 0 r
(9)
The voltage equations are given by (10) where Vres are the source voltage, ires the line
current, and V x the rectifier input voltage (x=F,G,H), respectively and R and L are
respectively the input resistance and the input inductance:
⎡ V res 1 ⎤ ⎡ R + Lp
⎢V
⎥ ⎢
⎢ res 2 ⎥ = ⎢ 0
⎣⎢V res 3 ⎦⎥ ⎢⎣ 0
0
R + Lp
0
0 ⎤ ⎡ i res 1 ⎤ ⎡ V F
0 ⎥⎥ ⎢⎢ i res 2 ⎥⎥ + ⎢⎢ V G
R + Lp ⎦⎥ ⎣⎢ i res 3 ⎦⎥ ⎢⎣V H
⎤
⎥
⎥
⎦⎥
(10)
The input voltages of the two-level PWM rectifier are defined as follows:
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VF =
1
( 2 F11 r − F 21 r − F 31 r ).U red
3
1
( 2 F 21 r − F11 r − F 31 r ).U red
3
1
V H = ( 2 F 31 r − F 21 r − F11 r ).U red
3
VG =
(11)
The rectifier output current is given as follows:
I red = F11 r i res 1 + F 21 r i res 2 + F 31 r i res 3
(12)
4.2. Control of the two-level PWM current rectifiers
4.2.1. Voltage feedback control
Each phase k (k=1,2 or 3) of the three-phase network feeding the rectifiers considered can
be represented by a R,L circuit. Vresk is the voltage of one phase k of the three-phase
network and Vk is the voltage of the leg k of the rectifier.
The voltage loop imposes the effective value of the network reference current
corresponding to the power exchanged between the network and the continue load (fig5).
Figure 5. Control algorithm of the output DC voltage of the two-level PWM current
rectifier.
For the voltage loop modelling, we use the instantaneous power conservation principle.
In this principle, Pin is the input power of the rectifier and Pout the output one.
Pin =
3
2
−
∑ (V resk .I resk − R.I resk
k =1
2
1 dI resk
L.
)
2
dt
Pout = U c1 .(i ch1 + i c1 ) + U c 2 .(i ch 2 + i c 2 )
(13)
(14)
If we suppose the sinusoidal currents of the network in phase with the corresponding
voltages Vresk and we neglect the rectifier losses and the Joule effect in the network
resistors
R , we can write:
P = 3.Vr .I e = 2.U c .I red
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(15)
J. Electrical Systems 7-2 (2011): 131-148
Vr and I e are the amplitude of the phase voltage and current respectively
3.V r .I e
2.U c
We define the next values as follows:
Then I red =
(16)
U c1 + U c 2
2
ic1 + i c 2
ic =
2
i +i
i ch = ch1 ch 2
2
(17)
Uc =
I red = ich + ic
We want to regulate the voltage U c of the rectifier. For that, we choose for sliding surface:
S = U c − U cref
(18)
Its derivative is:
•
S = U
•
U
c
•
Uc
•
(19)
c
I red − i ch
C
3 .V r . I e
= (
− ich ) / C
2 .U c
(20)
=
(21)
•
The condition S . S < 0 insures the attractibility of the trajectory towards the sliding
surface. For that, we choose:
•
(22)
S = − k 1 . sign ( S ) − k 2 . S
The output of the sliding mode controller gave:
Rectifier n°1
I ea = − [ C .( k1 .sign (U ca − U cref ) + k 2 .(U ca − U cref )) − ich ].
2 .U ca
3 .V r
(23)
2 .U cb
3 .V r
(24)
Rectifier n°2
I eb = −[ C .( k 1 .sign (U cb − U cref ) + k 2 .(U cb − U cref )) − i ch ].
4.2.2. Current feedback control
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We control the network current of the phase 1 and 2 by a sliding mode regulator. The
algorithm of this current loop is given on the figure 6. In this scheme, the transfer function
H ( p) is expressed as follows:
I resk
1
=
V
R + L. p
H ( p) =
(25)
Figure 6. Control algorithm of the network current iresk of the two-level PWM rectifier.
From the network equations we have:
•
V res 1 − V
V res
2
= R . I res 1 + L . I
A
− V B = R . I res
VA = N
VB = N
g1
g2
.U
.U
res 1
•
2
+ L. I
(26)
res 2
c
(27)
c
We choose the following sliding surfaces
S 1 = I res 1 − I ref 1
S 2 = I res 2 − I ref
(28)
2
To satisfy the attractibility condition, we choose:
•
S 1 = − k 11 . sign ( S 1 ) − k 21 . S 1
•
S 2 = − k 12 . sign ( S 2 ) − k 22 . S 2
•
S
•
k
= I
resk
−
2 .ω . I e . cos( ω .t −
(29)
2 .( k − 1).π
)
3
with k = 1 , 2 , 3
We obtain:
Rectifier n°1:
N g 1 = [V res 1 − R . I res 1 + L .k 11 . sign ( I res 1 − I ref 1 ) +
L .k 21 ( I res 1 − I ref 1 ) −
2 . L .ω . I e . cos( ω .t )] / 2 .U c
(30)
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N g 2 = [V res 2 − R . I res 2 + L .k 12 .sign ( I res 2 − I ref 2 ) +
L .k 22 ( I res 2 − I ref 2 ) −
2 . L .ω . I e . cos( ω .t )] / 2 .U c
Rectifier n°2:
M g 1 = [U res 1 − R . J res 1 + L .k 11 .sign ( J res 1 − J ref 1 ) +
L .k 21 ( J res 1 − J ref 1 ) −
M
g2
2 . L .ω . J e . cos( ω .t )] / 2 .U c
= [U res 2 − R . J res 2 + L .k 12 .sign ( J res 2 − J ref 2 ) +
L .k 22 ( J res 2 − J ref 2 ) −
(31)
2 . L .ω . J e . cos( ω .t )] / 2 .U c
5. Clamping bridge
In this section, a clamping bridge control is introduced to balance the four DC input
voltages, avoid NP potential drift and improve the performances of the speed control of the
permanent magnet synchronous machine.
Several publications have discussed ways to solve this balancing problem in three-level
NPC-VSI [5-14]. The multitude of proposals (selection of appropriate voltage vectors)
implemented to ensure DC voltage balancing can be broadly divided into two categories. In
the first category based on space vector realization, redundant switching states of the
converter are used while in the second category using carrier-based pulse width modulation
(PWM) scheme, a zero sequence voltage signal is added to the modulation signals. In some
schemes using zero sequence voltage to balance DC capacitor voltages, knowledge of load
power factor (or direction of instantaneous power flow) is required which is difficult to
implement under transient conditions, and in others, measurements of both capacitor
voltages and load currents (magnitudes or polarities) are required. Unfortunately, these
methods modify the output voltage waveform. Also, as the number of inverter-level
increases, the problem of capacitor balancing becomes more complex and the solution very
drastic.
By using a separate supply for each DC-link level, the balancing issues are solved [3].
However, this solution is expensive especially for more then three-level. Another solution
consists of adding electronic circuitry. In [13] and [14], clamping bridges based on
transistors and resistors (dissipative method) are proposed as a solution to this problem.
Advantages are low cost and low complexity. Disadvantages are high energy losses, high
current switches and costly design thermal management requirements for large values. This
method is best suited for systems that are charged often with small currents.
In order to remedy to the unbalance problem, we suggest a solution which consists in
establishing a bridge balancing between the rectifier and the intermediate filter (fig 7). The
aim of this use is to limit and stabilise variations of the input DC voltages of the inverter.
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R. CHIBANI et al: Study of a new DC voltage equalising circuit for ...
Figure 7. Structure of the clamping bridge
The capacitor voltage equalization clamping bridge scheme has many advantages such as
higher equalization efficiency and a modular design approach.
As shown in Figure 7, switches T1 , T2 , T3 and T4 are MOSFET; diodes D1 , D2 , D3 , D4 are
continued flow diodes; L1 and L2 is the energy storage inductors; C1 , C2 , C3 , C4 are four
adjacent series cells, respectively.
The basic operational principle is as follows:
* When Uc1>Uc2, a drive signal is given to the switches, and switch T2 is turned off and
T1 is turned on. While T1 is on, capacitor C1, switch T1 and inductor L1 forms a loop
circuit, whose current is Ic1 . The part of energy of capacitor C1 transfers to inductor L1 .
While T1 is off, capacitor C2 , inductor L1 and the diode D2 forms a loop circuit, whose
current is Ic2 .
The energy of inductor L1 transfers to capacitor C2 .
* When Uc1 <Uc2 , switch T1 is turned off and T2 is turned on. The energy transfers from
C2 to C1 until the voltages of the two capacitors are same.
* When Uc3>Uc4, a drive signal is given to the switches, and switch T4 is turned off and
T3 is turned on. While T3 is on, capacitor C3, switch T3 and inductor L2 forms a loop
circuit, whose current is Ic3. The part of energy of capacitor C3 transfers to inductor L2 .
While T3 is off, capacitor C4 , inductor L2 and the diode D3 forms a loop circuit, whose
current is Ic2 . The energy of inductor L2 transfers to capacitor C3 .
* When Uc3 <Uc4 , switch T3 is turned off and T4 is turned on. The energy transfers from
C3 to C4 until the voltages of the two capacitors are same.
The balancing algorithm searches to efficiently remove energy from a strong capacitor and
transfer that energy into a weak one until the capacitor voltage is equalized across all
capacitors.
A. Switch control strategy of the clamping bridge
Step 1: Deduction of the sign of the differences.
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J. Electrical Systems 7-2 (2011): 131-148
We use the following equations:
− U c2 )
= ( i L 1 + i c 2 − i d 2 − i c1)
dt
d (U c 3 − U c 4 )
C.
= (i L 2 + ic 3 − ic 4 − id 3)
dt
Step 2: Deduction of the command of the transistors
C.
d (U
c1
(32)
(33)
U c 2 > U c1 ⇒ T2 = 1; T1 = 0
U c1 < U c 2 ⇒ T2 = 0; T1 = 1
(34)
U c 3 > U c 4 ⇒ T3 = 1; T4 = 0
U c 4 < U c 3 ⇒ T3 = 0; T4 = 1
6. Simulation results
Figure 8. Reference voltages and bipolar carriers
Figure 9. Output voltage VA for m=6, r=0.8 and f=50Hz
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R. CHIBANI et al: Study of a new DC voltage equalising circuit for ...
Figure 10. Harmonic spectrum of the voltage VA for m=9 and r=0.8.
Figure 11. Harmonic spectrum of the voltage VA for m=12 and r=0.8
Figure 12. Harmonic spectrum of the voltage VA for m=15 and r=0.8
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Figure 13. Characteristics of the voltage VA for m=6
Voltage Uca and its reference
Voltage Ucb and its reference
Vres1 , ires1 and its reference
Ures1 , jres1 and its reference
Figure 14. Output DC voltage, Network voltage and current of the two-level PWM current
rectifier
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Voltages Uc1 and Uc3
Voltages Uc2 and Uc4
Figure 15. DC input voltages of the five-level NPC-VSI without using the clamping bridge
Speed
Current id
Electromagnetic torque
Current iq
Figure 16. Performances of the Permanent Magnet Synchronous Machine without using
the Clamping bridge
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J. Electrical Systems 7-2 (2011): 131-148
Voltages Uc1 and Uc2
Voltages Uc3 and Uc4
Figure 17. DC input voltages of the five-level NPC-VSI by using the clamping bridge
Speed and its reference
d axis current (id)
Electromagnetic torque
q axis current (iq)
Figure 18. Input DC voltages and PMSM performances obtained by using Clamping bridge
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6.1. Results interpretation
The figure 8 shows the reference voltages and the four bipolar carriers used for this
strategy. The figures 9 to 12 give the output voltage VA and its harmonic spectrum for a
modulation index m=6 (fig9), m=9 (fig10), m=12 (fig11) and m=15 (fig12) and a
modulation rate r=0.8. The frequency is 50 Hz. We notice that in the four cases, the
harmonics gather by families centred around frequencies multiple of 4.m.f. Because of the
symmetry to the quarter of the period presented by the voltage VA, we obtain only odd
harmonics. The most important harmonics gather around the first family.
The modulation rate r lets linear adjusting of fundamental magnitude from r=0 to r=1 and
the harmonics rate decreases when r increases (Figure13).
For evaluating the performances of the Clamping bridge proposed, two simulations are
presented. The first one propose to study a two two-level PWM current rectifier – Fivelevel NPC VSI – Permanent Magnet Synchronous Machine. This study shows particularly
the problem of the instability of the input DC voltages of the five-level NPC VSI and its
consequence on the performances of the PMSM speed control.
The figure 14 shows the voltage Uca and Ucb and their references obtained by controlling the
two-level PWM rectifiers by sliding mode control function. Those voltages follow perfectly
their references (200V). The network currents ires1 of the upper rectifier is in phase with the
network voltage Vres1. The network current jres1 of the lower rectifier is in phase with the
network voltage Ures1. The parameters of the net are: R=0.25Ω ; L=10mH.
On the figure 15, we show perfectly the problem of the unbalance of the four DC voltages
of the intermediate capacitors bridge. The voltages Uc2 and Uc4 are decreasing and the
voltages Uc1 and Uc3 are increasing. The parameters of the capacitors are: C1=C2=C3=C4=
20µF
The figure 16 shows the consequences of the DC voltages drift on the characteristics of the
Permanent Magnet Synchronous Machine. The speed follows its reference (400rad/s) but
the undulations on the electromagnetic torque and different currents (id, iq) are very
important due to the unbalance problem of the four input DC voltages. The parameters of
the PM synchronous machine are: Ld=Lq=3.2mH; Rs=1Ω; p=3; Φf=0.13N.m/A; J=6.10-4
kg.m²; Fc=9,5.10-5 N.m.s/rad.
Those results show the importance of the stability of the input DC voltages of the inverter
to have good performances for the speed control of the PM synchronous machine.
On the second simulation we introduce the clamping bridge proposed in the precedent
cascade on the Figure 1 in order to show the different input DC capacitor voltage
equalization performances. We can see on the figure 17 that the four voltages (Uc1, Uc2, Uc3
and Uc4) stabilise around the desired value (200V) and the DC link capacitor voltages are
equalized. By using this technique of stabilisation, we can remark on the figure 18 that the
undulations on the performances (Torque and currents id and iq) of the PMSM disappear
and those performances are improved by using the inductive Clamping bridge. The
parameters of the Clamping bridge are: L1= 1mH L2=1mH.
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J. Electrical Systems 7-2 (2011): 131-148
The afore-presented results confirm that the clamping bridge is able to equalize DC link
capacitor voltages and stabilize the different DC voltages around the desired value. The
performances of speed control of the PMSM are then ameliorating.
7. Conclusion
The present contribution intends to demonstrate that permanent magnet synchronous
machine control based on sliding mode control when applied with a two-level PWM current
rectifier – Five-level PWM NPC-VSI may contribute both for functional performances
improvement and attenuation of some technological limitations. With a high number of
semi-conducting devices, current and voltage quality are improved and weight reduced by
avoiding heavy filters.
The input DC voltages are generated by a five-level PWM current rectifier controlled by
sliding mode function control. By this study, we have particularly shown the problem of the
stability and its effect on the speed control of PMSM and the input DC voltages sources of
the inverter.
In the last part of this paper, we propose a simple solution to stabilise the four DC voltages
by using a new clamping bridge composed by four switches (pair transistor-diode) and two
inductances.
This technique permit an economic and simple electronic implementation, whereas in the
space vector modulation control the computational burden, the complexity of the
algorithms and the number of instructions are drastic especially when the number of levels
of the inverter is greater than three.
This nondissipative equalization design has many advantages such as high equalization
efficiency due to the nondissipative current diverter, bidirectional energy transferring
capability, and a modular design. Another advantage of this system is that no closed-loop
control is needed and the process is self-limiting: when voltage equalization is complete,
the switching of the capacitors consumes minimal energy.
This method compares with the dissipative method and it is characterized by the low energy
loss and the high equalizing speed in the process of charging and discharging.
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