ISSCC 2002 / SESSION 25 / PROCESSOR BUILDING BLOCKS / 25.7
25.7 Adaptive Body Bias for Reducing Impacts of Die-to-Die and Within-Die Parameter Variations on Microprocessor
Frequency and Leakage
James Tschanz, James Kao', Siva Narendra, Raj Nair, Dimitri Antoniadis', Anantha Chandrakasan', Vivek De
Microprocessor Research Labs, Intel Corporation, Hillsboro, OR, 'Massachusetts Institute of Technology, Cambridge, MA
Measurements on a 150nm CMOS test chip show that on-chip bidirectional adaptive body biasing compensates effectively for die-to-die parameter variation to meet both frequency and leakage requirements. An enhancement of this technique to correct for within-die variations triples the accepted die count in the highest frequency bin.
See Digest page 422
J. Tschanz
Block Diagram
Outline
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Process parameter variations
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1
- Die-to-die (D2D)
- Within-die (WID)
Adaptive body bias (ABB) test chip
Effectiveness of ABB
Impact of within-die variations
Compensation of WID variations (WID-ABB) 1ll;
,5
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4 L
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ob
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-
;
Phase detector
& counter
Cntzal path
,
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Parameter Variation
Phase Detector and Counter
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150nm CMOS technology
PD
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Critical Dath
-
,
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0.925
1
1.075
1.15
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out
1.225
Technology
(one subsitel
Dimensions
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150nm CMOS
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1.6X0.2 mm2
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-0.5V to 0.5V
Body bias
resolution
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344
-- -
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32mV
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ISSCC 2002 VISUALS SUPPLEMENT / 0 IEEE
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code
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PD=I: F>
,
F,
PD=O: ,F
, < F,
4.5X6.7 mm2
+
Bias range
5-bit
digital
"B"t
"ss
Adaptive Body Bias (ABB)
U1
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RBB
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Body Bias Modes
-
I .
NBB + FBB
1
'CCA
'REF
FBB + RBB
NBB 4 RBB
'=
vCCA
vCC
'CCA
= 'CC
'CCA
VREF< VCCA
Count: PD=O
Accounts for WID
RBB
< 'CC
VREF< VCCA
Count: PD=I
Count: PD=I
Area overhead: 4 5 3 %
ABB Test Chip Operation
1.2
, 1.8
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Frequency target
1.5
1.2
U
-8
.-
s
0.9
0.8
al
-p
c
0.6
0.7
L
I
0.5
0
20
9
0.3
' 0
0.6
40
80
60
Time (ms)
lj/i
Body bias adapts to meet frequency target
with minimum leakage
Neglects WID variation
I
bias (miniyize P),
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100%
E 80%
60%
40%
6 20%
0%
nl
115
1225
IIN:RBB,
N:FBB
N: FBB
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t
1 die
1
Effectiveness of S-ABB
B
1075
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Area overhead: -2%
[paper 16.41
r
0.4
-04 H'
______
and critical path
1
Normalized frequency
s
Measure Pleak
of circuit block
p~= Phase detector
0925
10 dies
13dies
36 dies
Frequency vs. Critical Path Count (NCP)
11oc
Accepted
dies
Frequency
Variation
$ 5
%
-
4
- 3
=8 2
09
1.I
1.5
13
Normalized die frequency
E
z
2
1
/
Z
i
0925
-
1
1075
115
1225
Normalized frequency
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==r-*
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=
-
_
c
l
_=__-
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.____--_-
=-
Jl-
I
Frequency p and CJ reduce as N,, increases
Frequency distribution unchanged for N
, > 14
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0 IEEE / ISSCC 2002 VISUALS SUPPLEMENT
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ISSCC 2002 / PAPER 25.7
ISSCC 2002 / PAPER 25.6
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Continued from page 345 _ _ _ _
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ontinued from page 343
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h
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Middle Bwass
-
__-
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l
_
_
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_
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WID Delav Variation vs. Logic Depth
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40%
OS olp = 5.6%
E 20%
(0
os olp = 3.0 Y o
E
I
RFread.ebp,
-16%
-8%
0%
8%
16%
Variation (%)
-
Active low inputs and
static receivers reduce
impact of noise
4.27%
Device olp
need fnr a lntrh
--
__ - -
_
I
Path Depth
dynamic nodes to allow
phase 1 (CK)inputs to be
"caught" removing the
[
Late Bypass
pseudo-NMOS
Mux selects enable
pullup
and latch reducing power
and enabling stall
recovery
Within-Die Adaptive Body Bias (WID-ABB)
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Compensates for
WID variation
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:
N
__________
e
_*_____=-I
,
_
_
- -__-
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_
_^-
Results Datapath
?
$
g
a
*
Functional units (FU) are
pre-enabled saving power
and removing the need for
a result mux
Effectiveness of WID-ABB -
/;
Z
100%
80%
60%
40%
20%
0%
;
FU outputs flow
transparently through the
middle and late bypasses
stopping only for the CK
clock boundry at the input
to the FU
Accepted
97% in
ahighest
WID-ABB
I 1 FEEKyI
% 5
x
m
-
bin
4
I= 23
Antimillers are used to
enable long precharge
pulldown results busses
E
z
1
I
I
0
0925
1
1075
115
1225
Normalized frequency
Summary
Ii
Within-Die Bias Distributions
_--
A 7.48mm2 integer datapath i s constructed with 128
general registers,6 fully bypassed ALUs a n d 4
cache address ports
- Double-pumped decoders/wordlinesin register file
delivered high performance/bandwidthin a small foot print
96 GB/s read bandwidth, 64 GB/s write bandwidth in 2mm2
- Antimiller circuits reduce area by allowing long minimally
spaced precharge-pulldownnets
- Register file write bitlines are reused to accomplish first
stage of bypass
- Pre-enabledfunctional units reduce power consumption
15% while removing logic stages from bypass network
-
NMOS zody
0.5
RBB
Bias(V) WFBB
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a
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ISSCC 2002 VISUALS SUPPLEMENT / 0 IEEE
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ISSCC 2002 / PAPER 26.1
1
Bias Resolution
4'
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dies,
100%
100 %
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1'
1
i
It
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B
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1'
!
1
WID -ABB
dies,
F 1.075
2 Yo
1.89 %
0.50%1
1.47%1
66%
0.69 Yo
97 %
0.21 %
Distribution of White Noise ('ds)
packaged parts measured on an automatic handler
n
1
hlwi: 0.035
SD: 0.00s
T(C): -40
i
300mV bias resolution sufficient for ABB
WID-ABB requires 1OOmV bias resolution
Conclusion
D2D and WID variations impact
microprocessor frequency and leakage
ABB improves die acceptance rate from
50% to 100%
ABB is most effective when WID variations
are considered
Compensating for WID variations by WIDABB increases number of high frequency
dies from 32% to 97%
f
1
1
F
6.02
4
d.04
d.06
Theorbtical
BrownianNoise
Conclusion
The measured angular rate white noise is 0.05
deg/rt.s with an ultimate resolution of 50 deg/h.
'I
The gyros operate accurately -4OC to +85C
during applied shocks over 1000 gees and
survive shocks of 30,000 gees unimpaired.
i
1
Complete angular rate to voltage transducer in
7mm x 7mm x 3mm package weighing 0.35 grams.
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