Topics Chapter 4
Combinational Logic Networks
Standard cells (already discussed in
Chapter 2).
■ Managing the delay of combinational
networks (“logical effort”, “buffer
insertion” and “crosstalk minimization”
skipped).
■ Power optimization.
■ Testing of combinational logic (postponed).
■
Revised by SG: January 10, 2004
Modern VLSI Design 3e: Chapter 4
Page 1
Copyright  1998, 2002 Prentice Hall PTR
Fanout
■
Fanout adds capacitance.
sink
source
sink
sink
Revised by SG: January 10, 2004
Modern VLSI Design 3e: Chapter 4
Page 2
Ways to drive large fanout
Copyright  1998, 2002 Prentice Hall PTR
Buffers
Increase sizes of driver transistors. Must
take into account rules for driving large
loads.
■ Add intermediate buffers. This may
require/allow restructuring of the logic.
■
Revised by SG: January 10, 2004
Modern VLSI Design 3e: Chapter 4
Page 3
Copyright  1998, 2002 Prentice Hall PTR
Revised by SG: January 10, 2004
Modern VLSI Design 3e: Chapter 4
Page 4
Copyright  1998, 2002 Prentice Hall PTR
Wire capacitance
Use layers with lower capacitance.
■ Redesign layout to reduce length of wires
with excessive delay.
Placement and wire capacitance
■
g1
g3
g2
g4
dvr
unbalanced load
g1
g3
g2
g4
dvr
more balanced
Revised by SG: January 10, 2004
Modern VLSI Design 3e: Chapter 4
Page 5
Copyright  1998, 2002 Prentice Hall PTR
Revised by SG: January 10, 2004
Modern VLSI Design 3e: Chapter 4
Path delay
Combinational network delay is measured
over paths through network.
■ Can trace a causality chain from inputs to
worst-case output.
Page 6
Copyright  1998, 2002 Prentice Hall PTR
Path delay example
■
network
graph model: nodes and edges modeling
network; however, only the delays of nodes
matter, not their function.
Revised by SG: January 10, 2004
Modern VLSI Design 3e: Chapter 4
Page 7
Copyright  1998, 2002 Prentice Hall PTR
Revised by SG: January 10, 2004
Modern VLSI Design 3e: Chapter 4
Page 8
Copyright  1998, 2002 Prentice Hall PTR
Delay model
Nodes represent gates.
■ Assign delays to edges—signal may have
different delay to different sinks.
■ Lump gate and wire delay into a single
value.
■
Revised by SG: January 10, 2004
Modern VLSI Design 3e: Chapter 4
Page 9
Copyright  1998, 2002 Prentice Hall PTR
Critical path
Critical path = path which creates longest
delay.
■ Can trace transitions which cause delays
that are elements of the critical delay path.
■
Revised by SG: January 10, 2004
Modern VLSI Design 3e: Chapter 4
Critical path through delay graph
Page 10
Copyright  1998, 2002 Prentice Hall PTR
Reducing critical path length
To reduce circuit delay, must speed up the
critical path—reducing delay off the path
doesn’t help.
■ There may be more than one path of the
same delay. Must speed up all equivalent
paths to speed up circuit.
■ Must speed up cutset through critical path.
■
Revised by SG: January 10, 2004
Modern VLSI Design 3e: Chapter 4
Page 11
Copyright  1998, 2002 Prentice Hall PTR
Revised by SG: January 10, 2004
Modern VLSI Design 3e: Chapter 4
Page 12
Copyright  1998, 2002 Prentice Hall PTR
Logic rewrites
deep logic
Logic transformations
Can rewrite by using subexpressions.
■ Flattening logic increases gate fanin.
■ Logic rewrites may affect gate placement.
■
a
b
shallow
logic
c
d
e
Revised by SG: January 10, 2004
Modern VLSI Design 3e: Chapter 4
f
Page 13
Copyright  1998, 2002 Prentice Hall PTR
Revised by SG: January 10, 2004
Modern VLSI Design 3e: Chapter 4
False paths
Logic gates are not simple nodes—some
input changes don’t cause output changes.
■ A false path is a path which cannot be
exercised due to Boolean gate conditions.
■ False paths cause pessimistic delay
estimates.
■
Revised by SG: January 10, 2004
Modern VLSI Design 3e: Chapter 4
Page 15
Copyright  1998, 2002 Prentice Hall PTR
Page 14
Copyright  1998, 2002 Prentice Hall PTR
Logic optimization
Logic synthesis programs transform
Boolean expressions into logic gate
networks in a particular library.
■ Optimization goals: minimize area, meet
delay constraint.
■
Revised by SG: January 10, 2004
Modern VLSI Design 3e: Chapter 4
Page 16
Copyright  1998, 2002 Prentice Hall PTR
Technology-independent
optimizations
Works on Boolean expression equivalent.
■ Estimates size based on number of literals.
■ Uses factorization, resubstitution,
minimization, etc. to optimize logic.
■ Technology-independent phase uses simple
delay models.
■
Revised by SG: January 10, 2004
Modern VLSI Design 3e: Chapter 4
Page 17
Copyright  1998, 2002 Prentice Hall PTR
Technology-dependent
optimizations
Maps Boolean expressions into a particular
cell library.
■ Mapping may take into account area, delay.
■ May perform some optimizations on
addition to simple mapping.
■ Allows more accurate delay models.
■
Revised by SG: January 10, 2004
Modern VLSI Design 3e: Chapter 4
Power consumption (Chapter 3)
A single cycle requires one charge and one
discharge of capacitor: E = CL(VDD - VSS)2 .
■ Clock frequency f = 1/t.
■ Power = E f = f CL(VDD - VSS)2.
■
Page 18
Copyright  1998, 2002 Prentice Hall PTR
Power optimization
Glitches cause unnecessary power
consumption.
■ Logic network design helps control power
consumption:
■
– minimizing capacitance;
– eliminating unnecessary glitches.
Revised by SG: January 10, 2004
Modern VLSI Design 3e: Chapter 4
Page 19
Copyright  1998, 2002 Prentice Hall PTR
Revised by SG: January 10, 2004
Modern VLSI Design 3e: Chapter 4
Page 20
Copyright  1998, 2002 Prentice Hall PTR
Glitching example
■
Gate network:
Glitching example behavior
■
1-0-0-0
– beginning: bottom input is 1;
– end: NAND output is 1;
0-0-1-1
■
1-0-0-0
0-0-1-0
Revised by SG: January 10, 2004
Modern VLSI Design 3e: Chapter 4
Page 21
NOR gate produces 0 output at beginning
and end:
Copyright  1998, 2002 Prentice Hall PTR
Difference in delay between application of
primary inputs and generation of new
NAND output causes glitch.
Revised by SG: January 10, 2004
Modern VLSI Design 3e: Chapter 4
Page 22
Adder chain glitching
Copyright  1998, 2002 Prentice Hall PTR
Explanation
Unbalanced chain has signals arriving at
different times at each adder.
■ A glitch downstream propagates all the way
upstream.
■ Balanced tree introduces multiple glitches
simultaneously, reducing total glitch
activity.
■
bad
Revised by SG: January 10, 2004
Modern VLSI Design 3e: Chapter 4
good
Page 23
Copyright  1998, 2002 Prentice Hall PTR
Revised by SG: January 10, 2004
Modern VLSI Design 3e: Chapter 4
Page 24
Copyright  1998, 2002 Prentice Hall PTR
Signal probabilities
Glitching behavior can be characterized by
signal probabilities.
■ Transition probabilities can be computed
from signal probabilities if clock cycles are
assumed to be independent.
■ Some primary inputs may have nonstandard signal probabilities—control signal
may be activated only occasionally.
■
Revised by SG: January 10, 2004
Modern VLSI Design 3e: Chapter 4
Page 25
Copyright  1998, 2002 Prentice Hall PTR
Transition Probability
Ps: probability that signal s is 1.
■ Transition probability of this signal:
Ptr,s = 2 Ps(1 - Ps).
■
Revised by SG: January 10, 2004
Modern VLSI Design 3e: Chapter 4
Delay-independent probabilities
■
Compute output probabilities of primitive
functions:
– PNOT = 1 - Pin
– POR = 1 - Π(1− Pi)
– PAND = Π Pi
■
Can compute output probabilities of
reconvergent fanout-free networks by
traversing tree.
Revised by SG: January 10, 2004
Modern VLSI Design 3e: Chapter 4
Page 27
Copyright  1998, 2002 Prentice Hall PTR
Page 26
Copyright  1998, 2002 Prentice Hall PTR
Delay-dependent probabilities
More accurate estimation of glitching.
Glitch accuracy depends on accuracy of
delay model.
■ Can use simulation-style algorithms to
propagate glitches.
■ Can use statistical models coupled with
delay models.
■
Revised by SG: January 10, 2004
Modern VLSI Design 3e: Chapter 4
Page 28
Copyright  1998, 2002 Prentice Hall PTR
Power estimation tools
■
Power estimator approximates power
consumption from:
– gate network;
– primary input transition probabilities;
– capacitive loading.
■
Factorization for low power
■
Proper factorization reduces glitching; a has
the highest transition probability.
f = ab + bc + cd
bad
May be switch/logic simulation based or
use statistical models.
g1
a
Revised by SG: January 10, 2004
Modern VLSI Design 3e: Chapter 4
Page 29
Copyright  1998, 2002 Prentice Hall PTR
b
Revised by SG: January 10, 2004
Modern VLSI Design 3e: Chapter 4
Factorization techniques
In example, a has high transition
probability, b and c low probabilities.
■ Reduce number of logic levels through
which high-probability signals must travel
in order to reduce propagation of glitches.
■
Revised by SG: January 10, 2004
Modern VLSI Design 3e: Chapter 4
Page 31
Copyright  1998, 2002 Prentice Hall PTR
good
g2
c
Page 30
Copyright  1998, 2002 Prentice Hall PTR
Layout for low power
Place and route to minimize capacitance of
nodes with high glitching activity.
■ Feed back wiring capacitance values to
power analysis for better estimates.
■
Revised by SG: January 10, 2004
Modern VLSI Design 3e: Chapter 4
Page 32
Copyright  1998, 2002 Prentice Hall PTR