A 22dB PSRR Enhancement in a
Two-Stage CMOS Opamp Using Tail Compensation
Paul M. Furth, Sri Harsh Pakala, Annajirao Garimella and Chaitanya Mohan
VLSI Laboratory, Klipsch School of Electrical and Computer Engineering,
New Mexico State University, Las Cruces, NM 88003, USA
Email: pfurth@nmsu.edu, sriharsh@nmsu.edu, garimella@ieee.org
Abstract— A new compensation technique known as tail compensation is applied to a two-stage CMOS operational amplifier.
The compensation is established by a capacitor connected between the output node and the source node of the differential
amplifier. For the selected opamp topology, tail compensation
allows better performance in terms of bandwidth and power
supply rejection ratio (PSRR) when compared to Miller and cascode compensation. Operational amplifiers using Miller, cascode
and tail compensation were fabricated in a 0.5-µm 2P3M CMOS
process. The circuits operate at a total quiescent current of 90 µA
with ±1.5V power supplies. Experimental results show that tail
compensation increases the unity-gain frequency by 60% and
25% and improves PSRR from the positive rail by 22 dB and
26 dB over a frequency range from 23 kHz to 3.0 MHz compared
to Miller and cascode compensation, respectively.
nearly zero; hence the main motivation for selecting node VX
in the compensation path. From node V1 to node VOU T power
supply noise is injected through the parasitic capacitance Cgd
in the tail compensation technique. As such, PSRR begins to
degrade at moderate rather than low frequencies.
Index Terms—Tail compensation, Miller compensation, power
supply rejection ratio, two-stage opamps.
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Fig. 1. Primary VDD signal path created in (a) Miller (b) cascode and (c)
proposed tail compensation schemes.
I. I NTRODUCTION
Power supply rejection ratio (PSRR) often determines the
performance limit of sensitive analog circuitry such as ADCs,
PLLs, VCOs and LDOs [1], [2]. Indeed, whenever the supply
voltage is generated by a switched-mode power supply, ripple
noise is unavoidable. In portable communications devices,
which utilize transceiver circuits operating at high frequencies,
supply ripple may even cause stability degradation at the
frequency of transmission [3].
While many existing techniques, such as Miller and cascode compensation [4]–[19], ensure stability of a closed-loop
amplifier, in some circumstances they lead to poor PSRR.
Referring to Fig. 1, let V1 be the output of the first stage
and VOU T be the output of the second stage of a two stage
CMOS opamp. Miller compensation is placed between nodes
V1 and VOU T and cascode compensation between nodes VY
and VOU T , where node VY is the source of the cascoding
transistor. The gain from VDD to nodes V1 [8] and VY is very
nearly unity, as will be demonstrated later. In this way, power
supply noise is easily induced through the large compensation
capacitors to the output node, resulting in the degradation of
PSRR at low frequencies.
To this end, we introduce a new compensation technique
called “tail” compensation which does not create a path from a
node contaminated by VDD noise. In this technique, as shown
in Fig. 1(c), the compensating capacitor CT is connected to
the low impedance tail current node VX of the amplifier. As
will be demonstrated later, the gain from VDD to VX is very
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II. CMOS T WO -S TAGE A MPLIFIER
The circuit implementation of a two-stage operational amplifier with Miller, cascode and the proposed tail compensation
schemes is shown in Fig. 2. The circuit consists of two
stages, a differential pair with single-ended load (M1 -M8 )
and a common-source output stage (M12 -M13 ). Generally the
effective transconductance of a differential amplifier equals the
transconductance of differential input transistors M1 , M2 . In
this case, the load of the first stage is cascode current source
M3 -M4 . The current through M1 is not mirrored to node V1 ;
hence, the effective transconductance of the first stage reduces
to 0.5gm1 = 0.5gm2 .
The current through transistor M1 is utilized to create a
feed-forward path to node VOU T through mirror M5 -M6 and
transistors M9 -M12 . The mirror formed by transistors M11 M12 has a dimension ratio of 1:K, thus giving rise to a
feed-forward transconductance of 0.5Kgm1 . In this way, the
current generated through the M1 branch is utilized for two
purposes: (i) enhancing the negative going slew-rate and (ii)
biasing the output stage of the amplifier. The common-source
transistor M13 in the second stage is similarly sized K times
the unit-sized PMOS transistor. Bias voltages and currents are
generated by transistors M14 -M19 and resistors Rb .
A. Op-amp Gain
Let the output resistance and equivalent capacitance to
ground of the first and second stages be denoted by R1 and
VDD
M19
M6
M9
VBP
M13
Ib
Ib
VCP
M18
M10
VY
M5
VCN
Rb
Ib
V IN-­
M1
Ib
CC
VCN
M14
M7 m=2
Bias Circuit
Tail
M8 m=2
M11
m=K
M12
Output Stage
First Stage
Feed-­forward Path
CL
RL
CT
VBN
M17
M16
VOUT
VIN+
2Ib
VBN
Miller
CM RM
M2
VX
M15
Fig. 2.
Cascode
M3
V1
Rb
V SS
m=K
M4
VBP
Schematic of two-stage operational amplifier illustrating Miller, cascode, and tail compensation techniques.
C1 , and ROU T and COU T , respectively. Also, let the transconductance, output resistance, gate-to-source, and gate-to-drain
capacitances of an individual transistor Mi be represented by
gmi , roM i , Cgsi and Cgdi , respectively. Referring to Fig. 2,
the gains of the first and second stages are
AV 1 = −0.5gm2 R1 ,
AV 2 = −g m13 ROU T
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where R1 = roM 2 ||(gm3 roM 3 roM 4 ) ≈ roM 2 and ROU T =
(roM 12 ||roM 13 ||RL ). The overall gain of the two-stage amplifier, including the feed-forward path is
AV = AV 1 AV 2 + 0.5Kgm1 ROU T .
The amplifier of Fig. 2 is implemented using all three
compensation techniques – Miller, cascode, and tail – in order
to clearly differentiate the performance of the proposed tail
compensation technique. The tail compensation capacitor CT
is introduced between node VOU T and node VX , a node with
a low input resistance of (1/gm1 )||(1/gm2 ). The output of the
first stage is isolated from the feedback network by the current
buffer [12], [13] formed by transistor M2 . Current fed back
through� M2 establishes the� dominant low-frequency pole at
−1
ωp1 = R1 ( C2T )gm13 ROU T
.
III. S MALL S IGNAL A NALYSIS
Small-signal models of the three compensation topologies
are shown in Fig. 3. Three LHP poles and two LHP zeros
were derived for each topology. A summary of the equations of
poles and zeros and their unity-gain frequencies (ωU GF ) along
with their approximate frequencies for each compensation
network are given in Table I. These theoretical values are
computed with values from a SPICE operating point analysis
using 0.5-µm transistor models.
As one can observe, the dominant pole ωp1 in each
configuration-Miller, cascode and tail-is established by compensating capacitances CM , CC and CT , respectively. The
effect of the first non-dominant pole ωp2 is approximately
nullified through careful placement of the first LHP zero
ωz1 . The second zero ωz2 is at very high frequencies (f >
150 MHz); hence, it has negligible effect on opamp stability.
The non-dominant poles ωp2 and ωp3 depend on output
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B. Tail Compensation
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Fig. 3. Small signal model of opamps in Fig. 2 using (a) Miller and cascode
compensation and (b) proposed tail compensation.
capacitor COU T . Zero ωz1 depends only on the compensation
capacitors. The non-dominant poles in Miller and cascode are
real, whereas those in tail compensation are a complex pole
pair with a theoretically computed damping factor Q = 0.76.
IV. P OWER S UPPLY R EJECTION R ATIO A NALYSIS
The PSRR small signal models of the three different
compensation schemes are shown in Fig. 4. The opamp is
connected in a unity-gain configuration and an AC signal in
series with the DC power supply voltage is placed at the VDD
terminal. The ratio VDD /VOU T defines PSRR.
There are several differences in the PSRR small-signal
models of Fig. 4 compared to the small-signal models of
Fig. 3. Since PSRR is measured in unity-gain configuration,
input VIN + is now at ground and VOU T is connected to
VIN − . Looking at the first stage of Fig. 4, the effect of
transistor M2 on node V1 is seen in resistance roM 2 and the
effect of the unity-gain feedback is through transconductance
−0.5g m2 VOU T . Node V1 is also loaded by Cgs13 to VDD . For
common-mode voltage signals, in particular VDD , node VX is
TABLE I
E QUATIONS FOR AC S MALL - SIGNAL MODELS AND THEIR THEORETICALLY COMPUTED LOCATIONS
Pole/Zero
Miller (Fig. 3(a))
ωp1
1
f (Hz)
Cascode (Fig. 3(a))
5k
1
R1 CM gm13 ROU T
gm13 CM
C1 CM +COU T (C1 +CM )
ωp2
1
RM
ωp3
ωz1
�
1
C1
+
1
CM
+
1
COU T
1
RM C M
�
ωU GF
Pole
ωp1,P SRR
�C
OU T CC
gm3 R1
g�m13 CC
+C1 (CC +COU T )
1
+gm3
R1 C 1
170M
gm2 gm13
2COU T CM
�
1
CC
+
1
COU T
gm3
CC
8M
gm13
KC1
ωz2
Tail (Fig. 3(b))
f (Hz)
4k
1
R1 (CT /2)gm13 ROU T
4.5k
complex pole pair ωp2,3
15M
R1 CC gm13 ROU T
3M
�
f (Hz)
16M
�
66M
14M
�
gm1 gm13
C1 Cgd13 +Cgd13 COU T +C1 COU T
gm2
CT
10.4M
250M
gm13
KC1
250M
gm13
C1
156M
6.2M
gm2
2CC
8.3M
gm2
CT
10.4M
TABLE II
E QUATIONS FOR THE LOCATION OF PSRR DOMINANT POLES
Miller (Fig. 4(a))
f (Hz)
(roM 2 CM gm13 roM 13
)−1
Cascode (Fig. 4(a))
1.5k
(roM 2 CC gm13 roM 13
f (Hz)
)−1
1.2k
Tail (Fig. 4(b))
(roM 2 Cgd13 gm13 roM 13
f (Hz)
)−1
23k
open, since it is loaded by cascode current source M7 -M8 (see
Fig. 2). Therefore, whatever current enters node VX through
transistor M1 must circulate back through transistor M2 onto
node V1 . The current entering node VX through transistor M1 ,
VDD /roM 1 , appears at node V1 as a dependent current source,
as shown in Fig. 4. A final difference between the two models
in the first stage is that the impedance of the cascode buffer
1/gm3 in Fig. 4(a) is now attached to VDD .
Differences in the second stage of the PSRR small-signal
model are that transconductance gm13 in parallel with re�
sistance roM 13 now go to VDD , rather than ground. ROU
T
is the equivalent resistance to ground at node VOU T , where
�
ROU T = ROU
T ||roM 13 . All other differences in the second
stage are due to measuring PSRR in unity-gain configuration,
wherein VIN + is tied to ground and VOU T to VIN − .
As mentioned earlier, the reason for degraded PSRR performance in Miller and cascode compensation techniques is that
noise from VDD appears unattenuated at nodes V1 and VY .
Small-signal analysis of the PSRR models in Fig. 4 yield the
following gain equations from VDD to nodes V1 , VY , and VX .
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The dominant pole determines the shape of the PSRR
frequency response, which is a single-pole system for frequencies below the unity-gain frequency fU GF . A summary
of the dominant pole equations are shown in Table II. In
Miller and cascode compensation, the dominant poles are
created by capacitors CM and CC , with theoretically computed
values of 1.5 kHz and 1.2 kHz, respectively. However, in
tail compensation the dominant pole is caused by the small
parasitic capacitance Cgd13 of transistor M13 and not the large
compensation capacitor CT . This leads to the dominant pole
occurring at the moderate frequency of 23 kHz, leading to a
higher PSRR for moderate-to-high frequencies.
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≈
1
VY
≈ 1,
≈1
gm13 roM 13
VDD
1
gm2 roM 13 (K + roM 2 gm13 )
1+
(3)
Using small-signal parameters, the gain VX /VDD ≈ 2.5 ×
10−4 , which is close to 0.
The PSRR at low frequencies, P SRRDC , is the same for
Miller, cascode and tail compensation, and is given by
P SRRDC = 0.5gm2 roM 2 gm13 roM 13 .
(4)
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V. E XPERIMENTAL R ESULTS AND C ONCLUSIONS
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The three designs were implemented in a 0.5-µm 2P3M
CMOS process. A chip micrograph is shown Fig. 5. Measurements were performed using power supplies ±1.5V and a total
bias current of 90 µA. The output load consisted of a 40 kΩ
resistor in parallel with a 20 pF capacitor. Simulated openloop gain for all three schemes was 69 dB. To achieve a phase
margin of 63o , the required compensation capacitors-CM , CC
and CT -were 1.25 pF, 1.55 pF and 2.75 pF, respectively.
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VDD
VX
VDD
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Fig. 4. PSRR Small signal model of opamps in Fig. 2 showing (a) Miller
and cascode compensation and (b) proposed tail compensation.
Measured transient waveforms of the amplifiers in an inverting
configuration with a gain of −1V /V are shown in Fig. 6.
While the Miller and cascode compensated designs achieved
a measured fU GF of 6.4 MHz and 8.2 MHz, respectively,
fU GF for the tail compensated design was 10.3 MHz, an
improvement of 60% over Miller and 25% over cascode.
(a)
(c)
Fig. 5.
Chip micrograph showing (a) Miller (b) cascode and (c) tail
compensated designs. Dimensions in Table III.
1
0.5
Input
Miller
Cascode
Tail
Vout (V)
0
−0.5
−1
−1.5
−2
−2.5
0
0.5
1
1.5
2
2.5
3
3.5
4
4.5
Time (µs)
Fig. 6. Measured transient responses with input VIN = 1.6 Vpk−pk at
200 kHz. Amplifiers are in a unity-gain inverting configuration. (Offset added
for visibility).
PSRR was experimentally verified by configuring the amplifier as a voltage follower and adding a 100 mVpk−pk
sinusoid to the VDD rail. Fig. 7 shows the measured PSRR
responses. The tail compensated design outperforms the Miller
and cascode compensated designs by approximately 22 dB
for frequencies in the range of 23 kHz to 3 MHz. Dominant
poles for PSRR for the three compensation networks closely
correlate with the analytical values computed in Table II.
80
70
22 dB
PSRR (dB)
60
50
40
30
20
10
0
1
10
Fig. 7.
Miller Compensation
Cascode Compensation
Tail Compensation
2
10
3
10
4
10
Frequency (Hz)
TABLE III
S UMMARY OF M EASURED R ESULTS
Parameter/Design
Miller
Cascode
Tail
UGF (MHz)
6.4
8.2
10.3
SR+/SR- (V/µs) (10%-90%)
6.3/2.9
5.8/3.0
3.4/5.1
PSRR @ 100 kHz (dB)
44
40
66
PSRR @ 3 MHz (dB)
14
8
36
Circuit area (µm x µm)
177 x 74
181 x 74
200 x 74
R EFERENCES
(b)
−3
supply noise sensitive analog applications, tail compensation
may prove beneficial, due to its increased fU GF and enhanced
PSRR performance.
5
10
6
10
Measured PSRR of the three different compensation schemes.
All hardware measurement results are summarized in Table III. The measured slew-rate performance is similar for all
three designs. On the other hand, tail compensation proved
best for sustained high values of PSRR over a wide range
of frequencies. The PSRR of the two-stage opamp with tail
compensation is 22 dB and 26 dB higher, compared to that
of Miller and cascode compensation designs, respectively. In
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