Vol. 35, No. 6
Journal of Semiconductors
June 2014
A capacitor-free high PSR CMOS low dropout voltage regulator
Li Zhichao(李志超)1; Ž , Liu Yuntao(刘云涛)1 , Kuang Zhangqu(旷章曲)2 , and Chen Jie(陈杰)1
1 Institute
of Microelectronics, Chinese Academy of Sciences, Beijing 100029, China
Micro Technology Co. Ltd, Beijing 100085, China
2 Superpix
Abstract: This paper presents a capacitor-free CMOS low dropout voltage regulator which has high PSR performance and low chip area. Pole splitting and gm boosting techniques are employed to achieve good stability. The
capacitor-free chip LDO was fabricated in commercial 0.18 m CMOS technology provided by GSMC (Shanghai,
China). Measured results show that the capacitor-free LDO has a stable output voltage 1.79 V, when supply voltage
changes from 2.5 to 5 V, and the LDO is capable of driving maximum 100 mA load current. The LDO has high
power supply rejection about 79 dB at low frequency and 40 dB at 1 MHz frequency, while sacrifice of the
LDO’s active chip-area is only smaller than 0.02 mm2 .
Key words: CMOS; low dropout regulator; power supply rejection; capacitor-free
DOI: 10.1088/1674-4926/35/6/065004
EEACC: 2570
1. Introduction
Power management is a vital block for system-on-chip
(SoC) applications, especially in portable products such as
cellular phones, video cameras, and laptops. Consequently,
low dropout regulators (LDO), which have advantages of low
power consumption, low noise, low production cost, high PSR,
and easy integration, have obtained considerable attention in
the mobile battery-operated design. LDO is usually used to provide a precise power supply voltage, eliminate the effects of
input supply ripples and suddenly changed current of the load.
To enhance the closed-loop stability, traditional low
dropout regulators are usually realized with an off-chip capacitor equivalent series resistance (ESR), which generates an ESR
zero to realize pole-zero cancellation. However, the stability
in this method, which relies on the value of the ESR, will become a drawback when the load condition is changed. In order to eliminate the ESR and implement a full on-chip LDO,
and to maintain the closed-loop stability, several methods have
been developed. Rincon-Mora et al. proposed the efficient current buffer methodŒ1 , and pole-zero doublet methodŒ2 . Leung
et al. proposed a regulator with damping factor control frequency compensationŒ3 . The regulator costs a large chip area
due to three compensating capacitors. Gao et al. in Ref. [4] created a zero by frequency dependent voltage controlled current
sources(VCCS) instead of ESR, but still needed a low ESR capacitor as co-existence of VCCS generated zero. Other methods such as employing a differentiator formed by a current amplifier and a capacitor in Ref. [5], using three folded-cascode
current operational amplifier in Ref. [6], and applying ACboosting and active-feedback frequency compensation (ACBAFFC) in Ref. [7], have been reported recently. Nevertheless,
these methods have intrinsic drawbacks due to more than one
capacitor or complicated circuits.
Moreover, another research focus, power supply rejection
(PSR) should be high enough to eliminate the effect of power
supply spurs. Weak transconductance of the pass transistor, low
DC gain and finite bandwidth are the main reasons for poor
PSRŒ9 . Several approaches have been proposed with the purpose of improving PSR: feed-forward ripple cancellation technique in Ref. [8], using cascade structures for pass transistor in
Ref. [9], and adaptive bias to extend the bandwidth in Ref. [10].
By using these techniques, PSR can reach 50 to 60 dB,
which has a good performance on filtering the power supply
ripples.
In this paper, brief analyses about the stability of classical LDOs are described first. Then, a high PSR capacitor-free
low dropout regulator, based on Miller capacitor compensation and gm boosting technique, is proposed. The experimental
measurement results are given in the next section and the conclusion is summarized in the last section.
2. Analysis of Classical LDOs
A traditional LDO is composed of an error amplifier, a pass
element, a feedback network (FN), a reference voltage generator, and loading ESR, as shown in Fig. 1.
The topology creates obviously two poles at the pass MOSFET (MP) output node and the error amplifier output node. The
MP output pole P1 is given by:
P1 D
1
;
RO COUT
RO D RDS ==.RF1 C RF2 /==RL ;
(1)
where RDS is the resistance between MP’s drain and source. P1
is the dominated pole because both COUT and RL have considerable values in most applications. The error amplifier output
pole P2 at the gate of MP is another pole that affects the stability of the LDO. Usually, the size of MP is very large to get
high current through the load, so the parasitic capacitors in MP
should be considered for their contributions to P2 . The value
of P2 has to be defined by:
* Project supported by the National Natural Science Foundation of China (Nos. 61036004, 61234003, 61221004).
† Corresponding author. Email: lizhichao@ime.ac.cn
Received 7 November 2013, revised manuscript received 13 January 2014
© 2014 Chinese Institute of Electronics
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J. Semicond. 2014, 35(6)
Li Zhichao et al.
Fig. 1. Traditional LDO topology.
Fig. 3. Proposed LDO topology.
output and the error amplifier output. It makes the pole at the
output of the first stage error amplifier become the dominant
pole and the pole at the output of the MP become the second
pole. The Miller capacitor has a very important “pole splitting” propertyŒ11 . We can view the second stage buffer and
MP as one circuit block which has transconductance denoted
0
with gm2
. Then, the small signal model can be illustrated in
Fig. 4 as same as a classical two-stage operational amplifier.
The transfer function is given in Eq. (3).
Vo .s/
Cc
0
D gm1 gm2
R1 R2 1
s
0
Vin .s/
gm2
˚
1 C sŒR1 .C1 C Cc /
Fig. 2. Pole-zero for traditional LDOs.
P2 D
1
;
Ro1 ŒCo1 C CGS C .1 C gMP RO /CGD 
0
C R2 .C2 C Cc / C gm2
R1 R2 Cc 
(2)
where gMP denotes MP’s transconductance.
From Eqs. (1) and (2), we can get two poles both located
in the GBW at low frequencies, which influence the stability
of the closed-loop.
Fortunately, a zero Z1 is generated by the off-chip capacitor equivalent series resistance (ESR), which can compensate
the influence of the second pole P2 and enhance the stability
of the classical LDO.
As illustrated in Fig. 2, the LDO will become unstable
when the zero Z1 move to the location at high frequency or
beyond the unity gain frequency denoted as Z10 .
To achieve reliable closed-loop stability, either P1 or P2
should be pushed to higher frequency in circuit design. However it is difficult to effectively move both P1 and P2 because
of the large off-chip capacitor COUT and the large size of MP
in common applications. Sacrificing the gain of error amplifier
or power consumption to push poles to higher frequency are
unsatisfactory approaches for analog circuit designers.
3. Proposed LDO structure
3.1. Stability analysis of proposed LDO
A second stage buffer with gm boosting technique and a
Miller capacitor are applied in proposed LDO as shown in
Fig. 3. The Miller capacitor Cc is utilized to connect the MP
C s 2 R1 R2 ŒC1 C2 C Cc C1 C Cc C2 
1
:
(3)
Two poles can be obtained as follows:
P1 D
P2 D
1
;
0
gm2
R1 R2 Cc0
(4)
0
Cc
gm2
:
C1 C2 C C2 Cc C C1 Cc
(5)
0
gm2
:
C2
(6)
Because the output capacitor of the first stage error amplifier C1 is reduced by adopting a buffer as second stage, C2 is
much larger than C1 . Usually Cc is also designed to be much
larger than C1 , so the P2 can be approximately derived as:
P2 D
0
By adjusting the transconductance gm2
or the Miller capacitor Cc , the pole P1 is pushed to lower frequency while the
pole P2 is pushed to higher frequency. Besides, the transconductance of the second stage is boosted to be a large value and
it is a contribution to enhance the DC gain and to get high PSR.
From the transfer function (3), an unexpected Right-HandZero (RHZ) is induced by the feed-forward path Cc :
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Z1 D
0
gm2
:
Cc
(7)
J. Semicond. 2014, 35(6)
Li Zhichao et al.
VREF D VOUT
Fig. 4. Proposed LDO topology.
The RHZ is at very high frequency because gm boosting
technique is employed in the second stage buffer. So the influence of the zero can be easily eliminated owing to the large
0
gm2
.
From Fig. 3, there is another pole P3 at the gate of the MP.
The expression of P3 can be derived referring to Eq. (2):
1
P3 D
;
Ro2 ŒCo2 C CGS C .1 C gMP RDS /CGD 
(8)
where Ro2 is the output resistance of the second stage buffer.
Compared to classical designs, where the DC gain is the product of the error amplifier’s output resistance and the MP’s parameter capacitor, and it requires that the output resistance should
be high, Ro2 is permitted to be a small value while maintaining
a considerable gain in this design, because gm2 is boosted to a
large value and has a good tradeoff with power consumption.
(9)
The second stage is using a buffer with gm boosting composed of seven transistors M20–M26. The technique of gm
boosting is realized by M25 and M26. If the voltage of the error
amplifier output VO1 fluctuates by V , which transfers to the
gate of M25, a voltage with the value of V will be added
to signal VN at the gate of M26 for the same transconductances
of M25 and M26. The size of M22 is designed by k times to
the size of the M21, similarly the M24 compared to the M23.
As we know, the transconductance gm is proportional to the
transistors’ size W=L, so we can get:
gm22 kgm21 ;
(10)
gm24 kgm23 :
(11)
Additionally, for transistor M23 in Fig. 5, variations at the
drain and gate are related as follows:
Vd23 =Vg23 D
gm23 =gm21 :
(12)
The drain to source current in transistor M22 can be derived using Eqs. (10) and (12):
Ids22 D kgm23 Vg23 ;
Ids24 D
3.2. Improvement of the proposed LDO’s PSR
PSR is defined as the transmission gain from input signal
to output signal (Avin / divided by the transmission gain from
power supply signal to output signal (Avdd /. Input signal reflecting the Avin should be added into the positive input terminal of the error amplifier (as VREF in Fig. 5), and the power
supply signal reflecting the Avdd should be added into the input
terminal of the LDO (as VIN in Fig. 5). High PSR means that
the LDO system should have a considerable Avin .
The proposed LDO as depicted in Fig. 3 has a second
buffer stage with gm boosting added in the middle of the error amplifier and the MP, which are two major contributions
to Avin of the traditional LDO as depicted in Fig. 1. The second buffer stage offers an additional transmission gain which
is proportional to the transconductance gm2 to the proposed
LDO and it will increase the Avin . According to Section 3.3,
the transconductance of the second stage buffer is boosted by
k times to that transconductance in the same circuit without gm
boosting technique and consequently the PSR of the proposed
LDO is improved efficiently.
RF2
:
RF1 C RF2
.gm25 =gm26 /gm24 Vg25 ;
Vg23 D Vg25 D V:
(13)
(14)
(15)
For the same transconductances of M25 and M26 and the
same voltages at gates of M23 and M25, with Eqs. (11), (13),
(14) and (15), the output voltage at the gate of MP (VO2 / can
be derived as:
VO2 D
2kgm23 V .rds22 ==rds24 /:
(16)
The transconductance of the second stage buffer is boosted
by k times to that transconductance in the same circuit without
gm boosting technique, the closed-loop stability of the circuit
is consequently enhanced, and the gate of MP can be driven to
cut-off the transistor much more efficiently.
The PASS MOS transistor is designed large as mentioned
before and resistances in the feedback network are formed by
small resistance with the same value in series to guarantee concordant variations caused by manufacture and application of
environmental conditions.
4. Simulation and measurement results
3.3. Transistor-level implementation
4.1. Simulation results
The transistor-level of the proposed LDO is illustrated in
Fig. 5. The left part is bias circuits with power down control
transistors. The error amplifier is formed by five transistors
M10–M14, whose one input comes from bandgap reference
voltage (VREF ), and the other input comes from feedback voltage. It makes a relation between the output voltage VOUT and
the VREF .
The proposed LDO was implemented in 0.18 m CMOS
technology, and post-layout simulations were covered by all
corners and environmental conditions. When the AC signal is
added into the error EA’s positive input terminal labelled VREF
in Fig. 5, the frequency responses are simulated as shown in
Fig. 6 to reflect the stability and location of poles and zeros of
the LDO. The open-loop gain is higher than 110 dB when the
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Li Zhichao et al.
Fig. 5. Transistor-level of the proposed LDO.
Fig. 6. Frequency response of the proposed LDO (gain and phase).
Fig. 8. Micrograph of the proposed LDO.
Fig. 7. PSR of the proposed LDO with different load currents (0, 50,
and 100 mA).
Fig. 9. Measured line regulation with load current of 30 mA.
load current varies from 0 to 50 mA, and it is also a high value
of 106 dB when the load current is up to 100 mA. The phase
margin is maintained at about 79 degrees, which can promise
good closed-loop stability. The PSR results are shown in Fig. 7
which is obtained by adding AC signal to the LDO’s input terminal labelled VIN in Fig. 5. When the load current changes
from 0 to 50 mA, the PSR values remain as at least 79 dB
and change to 75 dB when load current is 100 mA. The PSR
value can also be lower than 40 dB when frequency is 1 MHz
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The performance of the proposed regulator is summarized in
Table 1.
5. Conclusion
A high PSR full on-chip CMOS low dropout regulator is
proposed in this paper. The proposed LDO is fabricated in standard CMOS 0.18 m technology. The pole splitting and gm
boosting technique are used to get good performance of stability and PSR. The proposed LDO can drive 100 mA load and
chip area is only less than 0.02 mm2 . With these advantages,
the proposed LDO is suitable for low power system-on-chip
application.
Fig. 10. Measured output voltage versus supply voltage with load current of 30 mA.
Table 1. Performance of the proposed LDO.
Parameter
Value
Technology
0.18 m
Active area
180 100 m2
Supply voltage
2.5–5 V
Output voltage
1.79 V
Line regulation
2.5 mV/V
Maximum load
100 mA
and load current is 0 to 100 mA.
4.2. Fabrication and measurement results
The proposed LDO has been fabricated in standard 0.18
m CMOS technology provided by GSMC (Shanghai, China).
The active area is about 180 100 m2 excluding the pads and
ESD circuits, whose chip photograph is shown in Fig. 8 taken
by Olympus BX51WI-DPMC when the enlargement factor is
set to be 200. The line regulation is measured by Tektronix oscilloscope DPO4104B. When the supply voltage transforms
from 2.42 to 4.42 V as shown in channel 1, the upper half
of Fig. 8, the output voltage changes about 5 mV as shown
in channel 2, the lower half of Fig. 9. So the calculated line
regulation is 2.5 mV/V. The measured output voltage of the
LDO goes up to 1.79 V shown in Fig. 10 when the power supply varies from 1.5 to 2.5 V, then the output voltage is maintained at 1.79 V till the power supply voltage varies up to 5 V.
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