EECS 31L:
Introduction to Digital Design Lab
Lecture 3
Pooria M.Yaghini
The Henry Samueli School of Engineering
Electrical Engineering and Computer Science
University of California, Irvine
Lecture 3: Outline
•
•
•
•
FOR / GENERATE Loop
Data Types
Pre-defined Attributes
Assignment 2 Description
EECS 31L: Introduction to Digital Design Lab, Lecture 3
(c) 2015 Pooria. M. Yaghini
2
Lecture 3: Review
Logical :
--------------------------------y <= NOT a AND b; -- =a'.b
y <= NOT (a AND b); -- =(a.b)'
y <= a NAND b; -- =(a.b)'
--------------------------------Shift (given x="01001"):
------------------------------y <= x SLL 2; -- ="00100"
y <= x SLA 2; -- ="00111"
y <= x ROR -2; -- ="00101"
------------------------------Concatenation (given x="01001"):
-------------------------------------------------y <= x(2 DOWNTO 0) & "00"; -- = x SLL 2
y <= x(2 DOWNTO 0) & x(0) & x(0); -- = x SLA 2
y <= x(2 DOWNTO 0) & x(4 DOWNTO 3); -- = x ROL 2
-------------------------------------------------Concatenation with comma and OTHERS (assume y index is (1 TO 4)):
------------------------------------------------------------y <= (OTHERS=>'0'); -- ="0000" (positional mapping)
y <= (4=>'1', OTHERS=>'0'); -- ="0001" (nominal mapping)
y <= ('1', OTHERS=>'0'); -- ="1000" (positional mapping)
y <= ('0','0','1','0'); -- ="0010" (positional mapping)
EECS 31L: Introduction to Digital Design Lab, Lecture 3
(c) 2015 Pooria. M. Yaghini
3
Lecture 3: Review
VHDL
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.all;
ENTITY design IS
PORT(a, b, c: in STD_LOGIC;
y: OUT STD_LOGIC);
END;
ARCHITECTURE body OF design IS
BEGIN
y <= (not a and not b and not c) or
(a and not b and not c) or
(a and not b and c);
END;
EECS 31L: Introduction to Digital Design Lab, Lecture 3
SystemVerilog
module design(
input logic a, b, c,
output logic y);
assign y = ~a & ~b & ~c |
a & ~b & ~c |
a & ~b & c;
endmodule
(c) 2015 Pooria. M. Yaghini
4
Lecture 3: Concurrent Statements
• Purely Concurrent Statement Syntax
WHEN
assignment_expression WHEN conditions ELSE
assignment_value WHEN conditions ELSE
...;
SELECT
WITH identifier SELECT
assignment_expression WHEN value(s),
assignment_value WHEN value,
...;
GENERATE
EECS 31L: Introduction to Digital Design Lab, Lecture 3
(c) 2015 Pooria. M. Yaghini
5
Lecture 3: Concurrent Statements
• Purely Concurrent Statement Syntax
WHEN
assignment_expression WHEN conditions ELSE
assignment_value WHEN conditions ELSE
...;
SELECT
WITH identifier SELECT
assignment_expression WHEN value(s),
assignment_value WHEN value,
...;
GENERATE
What about generate?
EECS 31L: Introduction to Digital Design Lab, Lecture 3
(c) 2015 Pooria. M. Yaghini
6
Lecture 3: GENERATE
FOR / GENERATE
Similar to LOOP statement
Repeat a part of code number of times
creates several instances of the same assignments
label: FOR identifier IN range GENERATE
[declarations
BEGIN]
(concurrent assignments)
END GENERATE;
Range limits of the range must be static.
EECS 31L: Introduction to Digital Design Lab, Lecture 3
(c) 2015 Pooria. M. Yaghini
7
Lecture 3: GENERATE
FOR / GENERATE
Similar to LOOP statement
Repeat a part of code number of times
creates several instances of the same assignments
Example:
SIGNAL x: BIT_VECTOR (7 DOWNTO 0);
SIGNAL y: BIT_VECTOR (15 DOWNTO 0);
SIGNAL z: BIT_VECTOR (7 DOWNTO 0);
...
G1: FOR i IN 0 TO 7 GENERATE
z(i) <= x(i) AND y(i+8);
END GENERATE;
EECS 31L: Introduction to Digital Design Lab, Lecture 3
(c) 2015 Pooria. M. Yaghini
8
Lecture 3: GENERATE Example
• XOR Tree
EECS 31L: Introduction to Digital Design Lab, Lecture 3
(c) 2015 Pooria. M. Yaghini
9
Lecture 3: GENERATE Example
• XOR Tree
LIBRARY ieee;
USE ieee.std_logic_1164.all;
--------------------------------------ENTITY xor_tree IS
PORT ( x: IN STD_LOGIC_VECTOR (7 DOWNTO 0);
y: OUT STD_LOGIC);
END xor_tree;
-----------------------------------------------ARCHITECTURE DataFlow OF xor_tree IS
SIGNAL temp: STD_LOGIC_VECTOR (6 DOWNTO 0);
BEGIN
temp(0) <= x(0);
temp(1) <= temp(0) XOR x(1);
temp(2) <= temp(1) XOR x(2);
temp(3) <= temp(2) XOR x(3);
temp(4) <= temp(3) XOR x(4);
temp(5) <= temp(4) XOR x(5);
temp(6) <= temp(5) XOR x(6);
y
<= temp(6) XOR x(7);
END shifter;
EECS 31L: Introduction to Digital Design Lab, Lecture 3
(c) 2015 Pooria. M. Yaghini
10
Lecture 3: GENERATE Example
• XOR Tree
Will this work?
LIBRARY ieee;
USE ieee.std_logic_1164.all;
--------------------------------------ENTITY xor_tree IS
PORT ( x: IN STD_LOGIC_VECTOR (7 DOWNTO 0);
y: OUT STD_LOGIC);
END xor_tree;
-----------------------------------------------ARCHITECTURE DataFlow OF xor_tree IS
SIGNAL temp: STD_LOGIC_VECTOR (7 DOWNTO 0);
BEGIN
gen: FOR i IN 1 TO 7 GENERATE
y <= y XOR x(i);
END GENERATE;
END shifter;
EECS 31L: Introduction to Digital Design Lab, Lecture 3
(c) 2015 Pooria. M. Yaghini
11
Lecture 3: GENERATE Example
• XOR Tree
Will this work?
NO
LIBRARY ieee;
USE ieee.std_logic_1164.all;
--------------------------------------ENTITY xor_tree IS
PORT ( x: IN STD_LOGIC_VECTOR (7 DOWNTO 0);
y: OUT STD_LOGIC);
END xor_tree;
-----------------------------------------------ARCHITECTURE DataFlow OF xor_tree IS
SIGNAL temp: STD_LOGIC_VECTOR (7 DOWNTO 0);
BEGIN
gen: FOR i IN 1 TO 7 GENERATE
y <= y XOR x(i);
END GENERATE;
END shifter;
EECS 31L: Introduction to Digital Design Lab, Lecture 3
(c) 2015 Pooria. M. Yaghini
12
Lecture 3: GENERATE Example
• XOR Tree
Will this work?
LIBRARY ieee;
USE ieee.std_logic_1164.all;
--------------------------------------ENTITY xor_tree IS
PORT ( x: IN STD_LOGIC_VECTOR (7 DOWNTO 0);
y: OUT STD_LOGIC);
END xor_tree;
-----------------------------------------------ARCHITECTURE DataFlow OF xor_tree IS
SIGNAL temp: STD_LOGIC_VECTOR (7 DOWNTO 0);
BEGIN
temp(0) <= x(0);
gen: FOR i IN 1 TO N-1 GENERATE
temp(i) <= temp(i-1) XOR x(i);
END GENERATE;
y <= temp(7);
END DataFlow ;
EECS 31L: Introduction to Digital Design Lab, Lecture 3
(c) 2015 Pooria. M. Yaghini
13
Lecture 3: GENERATE Example
• Vector Shifter
row(0): 0 0 0 0 1 1 1 1
row(1): 0 0 0 1 1 1 1 0
row(2): 0 0 1 1 1 1 0 0
row(3): 0 1 1 1 1 0 0 0
row(4): 1 1 1 1 0 0 0 0
LIBRARY ieee;
USE ieee.std_logic_1164.all;
-----------------------------------------------ENTITY shifter IS
PORT ( inp: IN STD_LOGIC_VECTOR (3 DOWNTO 0);
sel: IN INTEGER RANGE 0 TO 4;
outp: OUT STD_LOGIC_VECTOR (7 DOWNTO 0));
END shifter;
-----------------------------------------------ARCHITECTURE shifter OF shifter IS
SUBTYPE vector IS STD_LOGIC_VECTOR (7 DOWNTO 0);
TYPE matrix IS ARRAY (4 DOWNTO 0) OF vector;
SIGNAL row: matrix;
BEGIN
row(0) <= "0000" & inp;
row(1) <= row(0)(6 DOWNTO 0) & '0';
row(2) <= row(1)(6 DOWNTO 0) & '0';
row(3) <= row(2)(6 DOWNTO 0) & '0';
row(4) <= row(3)(6 DOWNTO 0) & '0';
outp <= row(sel);
END shifter;
EECS 31L: Introduction to Digital Design Lab, Lecture 3
(c) 2015 Pooria. M. Yaghini
14
Lecture 3: GENERATE Example
• Vector Shifter
row(0): 0 0 0 0 1 1 1 1
row(1): 0 0 0 1 1 1 1 0
row(2): 0 0 1 1 1 1 0 0
row(3): 0 1 1 1 1 0 0 0
row(4): 1 1 1 1 0 0 0 0
LIBRARY ieee;
USE ieee.std_logic_1164.all;
-----------------------------------------------ENTITY shifter IS
PORT ( inp: IN STD_LOGIC_VECTOR (3 DOWNTO 0);
sel: IN INTEGER RANGE 0 TO 4;
outp: OUT STD_LOGIC_VECTOR (7 DOWNTO 0));
END shifter;
-----------------------------------------------ARCHITECTURE shifter OF shifter IS
SUBTYPE vector IS STD_LOGIC_VECTOR (7 DOWNTO 0);
TYPE matrix IS ARRAY (4 DOWNTO 0) OF vector;
SIGNAL row: matrix;
BEGIN
row(0) <= "0000" & inp;
G1: FOR i IN 1 TO 4 GENERATE
row(i) <= row(i-1)(6 DOWNTO 0) & '0';
END GENERATE;
outp <= row(sel);
END shifter;
EECS 31L: Introduction to Digital Design Lab, Lecture 3
(c) 2015 Pooria. M. Yaghini
15
Lecture 3: VHDL Objects
• VHDL Objects (CONSTANT, SIGNAL, VARIABLE, FILE)
SIGNAL signal_name : type_name [:=value];
SIGNAL output : INTEGER :=2;
CONSTANT
constant_name : type_name [ := value];
CONSTANT
rise_fall_time : TIME := 2 ns;
VARIABLE variable_name : type_name [:=value];
VARIABLE vararr : BIT_VECTOR(2 DOWNTO 0):= “000”;
FILE logical_name : file_type IS mode "file_name";
FILE INFILE
: TEXT
EECS 31L: Introduction to Digital Design Lab, Lecture 3
IS
IN
"in.dat";
(c) 2015 Pooria. M. Yaghini
16
Lecture 3: Data Types
• VHDL Data Types
Predefined
User‐defined
EECS 31L: Introduction to Digital Design Lab, Lecture 3
(c) 2015 Pooria. M. Yaghini
17
Lecture 3: Predefined Data Types
• Predefined Synthesizable Data Types
Main synthesizable types:
• BIT, BIT_VECTOR
• BOOLEAN
• STD_LOGIC, STD_LOGIC_VECTOR
• INTEGER (with subtypes NATURAL, POSITIVE)
• UNSIGNED, SIGNED
• UFIXED, SFIXED (VHDL 2008)
• FLOAT (VHDL 2008)
Examples of actual type definitions:
TYPE
TYPE
TYPE
TYPE
TYPE
BIT IS ('0', '1');
BIT_VECTOR IS ARRAY (NATURAL RANGE <>) OF BIT;
BOOLEAN IS (FALSE, TRUE);
INTEGER IS RANGE -2147483647 TO 2147483647; --default
INTEGER_VECTOR IS ARRAY (NATURAL RANGE <>) OF INTEGER;
EECS 31L: Introduction to Digital Design Lab, Lecture 3
(c) 2015 Pooria. M. Yaghini
18
Lecture 3: Predefined Data Types
• Predefined Synthesizable Data Types
From the package standard:
BIT
BIT_VECTOR
BOOLEAN
BOOLEAN_VECTOR (2008)
INTEGER
NATURAL
POSITIVE
INTEGER_VECTOR (2008)
CHARACTER
STRING
EECS 31L: Introduction to Digital Design Lab, Lecture 3
x
x
x
x
x
y
x
x
fclk
x
x
x
<=
<=
<=
<=
<=
<=
<=
<=
<=
<=
<=
<=
'1';
"1111";
FALSE;
(FALSE, TRUE, FALSE);
-255;
1111;
0;
255;
5_000_000;
(0, 1, 2, 3);
'a';
"mp3";
(c) 2015 Pooria. M. Yaghini
19
Lecture 3: Predefined Data Types
• Predefined Synthesizable Data Types
From the package std_logic_1164:
STD_ULOGIC
STD_ULOGIC_VECTOR
STD_LOGIC (*)
STD_LOGIC_VECTOR (*)
(*) Industry standard
EECS 31L: Introduction to Digital Design Lab, Lecture 3
(c) 2015 Pooria. M. Yaghini
20
Lecture 3: Predefined Data Types
• Predefined Synthesizable Data Types
From the package std_logic_1164:
STD_ULOGIC
STD_ULOGIC_VECTOR
STD_LOGIC (*)
STD_LOGIC_VECTOR (*)
(*) Industry standard
‘U’
‘X’
‘0’
‘1’
‘Z’
‘W’
‘L’
‘H’
‘–’
Uninitialized
Forcing unknown
Forcing low
Forcing high
High impedance
Weak unknown
Weak low
Weak high
Don’t care
EECS 31L: Introduction to Digital Design Lab, Lecture 3
(c) 2015 Pooria. M. Yaghini
21
Lecture 3: Predefined Data Types
• Predefined Synthesizable Data Types
From the package std_logic_1164:
STD_ULOGIC
STD_ULOGIC_VECTOR
STD_LOGIC (*)
STD_LOGIC_VECTOR (*)
x
x
x
x
<=
<=
<=
<=
'Z';
"0011ZZZZ";
'1'; y <= 'Z';
(OTHERS => 'Z');
(*) Industry standard
‘U’
‘X’
‘0’
‘1’
‘Z’
‘W’
‘L’
‘H’
‘–’
Uninitialized
Forcing unknown
Forcing low
Forcing high
High impedance
Weak unknown
Weak low
Weak high
Don’t care
EECS 31L: Introduction to Digital Design Lab, Lecture 3
(c) 2015 Pooria. M. Yaghini
22
Lecture 3: Predefined Data Types
• Predefined Synthesizable Data Types
From the package std_logic_1164:
STD_ULOGIC
STD_ULOGIC_VECTOR
STD_LOGIC (*)
STD_LOGIC_VECTOR (*)
x
x
x
x
<=
<=
<=
<=
'Z';
"0011ZZZZ";
'1'; y <= 'Z';
(OTHERS => 'Z');
(*) Industry standard
‘U’
‘X’
‘0’
‘1’
‘Z’
‘W’
‘L’
‘H’
‘–’
Uninitialized
Forcing unknown
Forcing low
Forcing high
High impedance
Weak unknown
Weak low
Weak high
Don’t care
EECS 31L: Introduction to Digital Design Lab, Lecture 3
(c) 2015 Pooria. M. Yaghini
23
Lecture 3: Predefined Data Types
• Type Classification (according to the number of bits)
EECS 31L: Introduction to Digital Design Lab, Lecture 3
(c) 2015 Pooria. M. Yaghini
30
Lecture 3: Predefined Data Types
• Type Classification (according to the number of bits)
Example: What is the “dimension” of each signal below?
Assume that none is of type CHARACTER or STRING.
EECS 31L: Introduction to Digital Design Lab, Lecture 3
(c) 2015 Pooria. M. Yaghini
31
Lecture 3: Predefined Data Types
• Type Classification (according to the number of bits)
Example: What is the “dimension” of each signal below?
Assume that none is of type CHARACTER or STRING.
a
b
c
d
e
f
g
h
i
<=
<=
<=
<=
<=
<=
<=
<=
<=
'1';
'Z';
"0000";
50_000_000;
("0001", "0000", "1111 ");
(OTHERS => 'Z');
('1', '1', '0', '1', '0');
FALSE;
(("000","000"),("000","000"));
EECS 31L: Introduction to Digital Design Lab, Lecture 3
(c) 2015 Pooria. M. Yaghini
32
Lecture 3: Predefined Data Types
• Type Classification (according to the number of bits)
Example: What is the “dimension” of each signal below?
Assume that none is of type CHARACTER or STRING.
a
b
c
d
e
f
g
h
i
<=
<=
<=
<=
<=
<=
<=
<=
<=
'1';
'Z';
"0000";
50_000_000;
("0001", "0000", "1111 ");
(OTHERS => 'Z');
('1', '1', '0', '1', '0');
FALSE;
(("000","000"),("000","000"));
EECS 31L: Introduction to Digital Design Lab, Lecture 3
--scalar
--scalar
--1D
--1D (INT, NAT, or POS)
--1Dx1D or 2D
--1D
--1D
--scalar
--1Dx1Dx1D or 3D
(c) 2015 Pooria. M. Yaghini
33
Lecture 3: Predefined Data Types
Example: To which predefined data types can the signals below belong to?
a
b
c
d
e
f
g
h
i
BV
BO
SL
SLV
UNS
=
=
=
=
=
<=
<=
<=
<=
<=
<=
<=
<=
<=
'1';
FALSE;
"FALSE";
"0000000Z";
10001;
50_000_000;
(OTHERS => 'Z');
('1', '1', '0', '1', '0');
"11" & "010";
BIT_VECTOR
BOOLEAN
STD_LOGIC or STD_ULOGIC
STD_LOGIC_VECTOR/STD_ULOGIC_VECTOR
UNSIGNED
EECS 31L: Introduction to Digital Design Lab, Lecture 3
SIG
INT
NAT
POS
CHAR
STR
=
=
=
=
=
=
SIGNED
INTEGER
NATURAL
POSITIVE
CHARACTER
STRING
(c) 2015 Pooria. M. Yaghini
34
Lecture 3: Predefined Data Types
Example: To which predefined data types can the signals below belong to?
a
b
c
d
e
f
g
h
i
BV
BO
SL
SLV
UNS
=
=
=
=
=
<=
<=
<=
<=
<=
<=
<=
<=
<=
'1';
FALSE;
"FALSE";
"0000000Z";
10001;
50_000_000;
(OTHERS => 'Z');
('1', '1', '0', '1', '0');
"11" & "010";
BIT_VECTOR
BOOLEAN
STD_LOGIC or STD_ULOGIC
STD_LOGIC_VECTOR/STD_ULOGIC_VECTOR
UNSIGNED
EECS 31L: Introduction to Digital Design Lab, Lecture 3
--BIT, SL, CHAR
--BO
--STR
--SLV, UNS, SIG, STR
--INT, NAT, POS
--INT, NAT, POS
--SLV, UNS, SIG, STR
--BV, SLV, UNS, SIG, STR
--same as above
SIG
INT
NAT
POS
CHAR
STR
=
=
=
=
=
=
SIGNED
INTEGER
NATURAL
POSITIVE
CHARACTER
STRING
(c) 2015 Pooria. M. Yaghini
35
Lecture 3: Predefined Data Types Examples
• Tri‐state buffer
EECS 31L: Introduction to Digital Design Lab, Lecture 3
(c) 2015 Pooria. M. Yaghini
36
Lecture 3: Predefined Data Types Examples
• Tri‐state buffer
Question:
What data type is needed?
EECS 31L: Introduction to Digital Design Lab, Lecture 3
(c) 2015 Pooria. M. Yaghini
37
Lecture 3: Predefined Data Types Examples
• Tri‐state buffer
Question:
What data type is needed?
STD_LOGIC
EECS 31L: Introduction to Digital Design Lab, Lecture 3
(c) 2015 Pooria. M. Yaghini
38
Lecture 3: Predefined Data Types Examples
• Tri‐state buffer
Question:
What data type is needed?
STD_LOGIC
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
----------------------------------------ENTITY tri_state IS
PORT (input, ena: IN STD_LOGIC;
output
: OUT STD_LOGIC);
END ENTITY;
----------------------------------------ARCHITECTURE tri_state OF tri_state IS
BEGIN
output <= input WHEN ena='1' ELSE 'Z';
END ARCHITECTURE;
-----------------------------------------
EECS 31L: Introduction to Digital Design Lab, Lecture 3
(c) 2015 Pooria. M. Yaghini
39
Lecture 3: Predefined Data Types Examples
Exercise:
Circuit with “don’t care” outputs
Question: Why is STD_LOGIC needed here?
-
EECS 31L: Introduction to Digital Design Lab, Lecture 3
(c) 2015 Pooria. M. Yaghini
40
Lecture 3: User-Defined Data Types
• A simple classification for user‐defined types:
• Integer Types
TYPE type_name IS RANGE range_specifications;
• Enumerated Types
TYPE type_name IS
(type_values_list);
• Array Types (Integer or Enumerated)
TYPE type_name IS ARRAY (range_specs) OF element_type;
EECS 31L: Introduction to Digital Design Lab, Lecture 3
(c) 2015 Pooria. M. Yaghini
41
Lecture 3: User-Defined Data Types
• A simple classification for user‐defined types:
• Integer Types
TYPE type_name IS RANGE range_specifications;
Example
TYPE negative
IS RANGE INTEGER'LOW TO -1;
TYPE temperature IS RANGE 0
TO 273;
TYPE my_integer IS RANGE -32
TO 32;
EECS 31L: Introduction to Digital Design Lab, Lecture 3
(c) 2015 Pooria. M. Yaghini
42
Lecture 3: User-Defined Data Types
• A simple classification for user‐defined types:
• Enumerated Types
TYPE type_name IS
(type_values_list);
Example
TYPE BIT
IS ('0', '1');
TYPE STD_ULOGIC
IS ('U','X','0','1','Z','W','L','H','X');
TYPE machine_state IS (idle, transmitting, receiving);
EECS 31L: Introduction to Digital Design Lab, Lecture 3
(c) 2015 Pooria. M. Yaghini
43
Lecture 3: User-Defined Data Types
• A simple classification for user‐defined types:
• Array Types (Integer or Enumerated)
TYPE type_name IS ARRAY (range_specs) OF element_type;
Example
-----------------1D:------------------------------------TYPE typeA IS ARRAY (7 DOWNTO 0) OF BIT;
CONSTANT const: typeA := "00001111";
----------------1Dx1D:--------------------------------TYPE typeB IS ARRAY (NATURAL RANGE <>) OF BIT_VECTOR(2 DOWNTO 0);
CONSTANT const: typeB(1 DOWNTO 0) := ("000", "111");
CONSTANT const: typeB(1 DOWNTO 0) := (('0','0','0'), ('1','1','1'));
----------------1Dx1D:------------------------------TYPE typeC IS ARRAY (POSITIVE RANGE <>) OF INTEGER;
CONSTANT const: typeC(1 TO 4) := (5, -5, 3, 0);
-----------------2D:--------------------------------TYPE typeD IS ARRAY (1 TO 3, 1 TO 4) OF BIT;
CONSTANT const: typeD := (("0000","0000","0000"));
-----------------3D:-------------------------------TYPE typeE IS ARRAY (1 TO 2, 1 TO 3, 1 TO 4) OF BIT;
CONSTANT const: typeE := (("0000","0000","0000"),("0000","0000","0000"));
EECS 31L: Introduction to Digital Design Lab, Lecture 3
(c) 2015 Pooria. M. Yaghini
44
Lecture 3: User-Defined Data Types
• SUBTYPE and RECORD
SUBTYPE is a TYPE with a constraint (allows direct assignments)
TYPE INTEGER IS RANGE -2147483647 TO 2147483647; --default
SUBTYPE POSITIVE IS INTEGER RANGE 1 TO INTEGER'HIGH;
----------------------------------------------------------TYPE STD_LOGIC IS ('X', '0', '1', 'Z', 'W', 'L', 'H', '–');
SUBTYPE my_logic IS STD_LOGIC RANGE '0' TO 'Z';
RECORD is a collection whose elements can be of different types
TYPE memory_access IS RECORD
address: INTEGER RANGE 0 TO 255;
block : INTEGER RANGE 0 TO 3;
data
: BIT_VECTOR(15 DOWNTO 0);
END RECORD;
...
VARIABLE mem_inst : memory_access;
mem_inst.address = 100;
EECS 31L: Introduction to Digital Design Lab, Lecture 3
(c) 2015 Pooria. M. Yaghini
45
Lecture 3: Type Conversion
• Type Conversion
For example:
INTEGER
STD_LOGIC_VECTOR
BIT_VECTOR
STD_LOGIC_VECTOR
to
to
to
to
STD_LOGIC_VECTOR
INTEGER
STD_LOGIC_VECTOR
SIGNED
Conversion techniques:
With type casting
With type‐conversion functions
EECS 31L: Introduction to Digital Design Lab, Lecture 3
(c) 2015 Pooria. M. Yaghini
46
Lecture 3: Type Conversion
• Type Conversion
With type casting (Automatic Conversion):
Only STD_LOGIC_VECTOR or (UN)SIGNED
SIGNAL sig: SIGNED(7 DOWNTO 0);
SIGNAL slv: STD_LOGIC_VECTOR(7 DOWNTO 0);
sig
Slv
<= SIGNED(slv);
<= STD_LOGIC_VECTOR(sig);
With type‐conversion functions:
--INTEGER to SIGNED:
to_signed(arg,size)
--or
conv_signed(arg,size)
--INTEGER to STD_LOGIC_VECTOR:
conv_std_logic_vector(arg,size)
SIGNAL a,b: IN UNSIGNED (7 DOWNTO 0);
SIGNAL y: OUT STD_LOGIC_VECTOR (7 DOWNTO 0);
...
y <= CONV_STD_LOGIC_VECTOR ((a+b), 8);
EECS 31L: Introduction to Digital Design Lab, Lecture 3
(c) 2015 Pooria. M. Yaghini
47
Lecture 3: Type Conversion
EECS 31L: Introduction to Digital Design Lab, Lecture 3
(c) 2015 Pooria. M. Yaghini
48
Lecture 3: Type Conversion
• Classical Mistakes in VHDL Assignments
Error 1: Type mismatch
Example: One side is BIT, the other is BOOLEAN
Error 2: Size mismatch
Example: One side has 8 bits, the other has 4
Error 3: Invalid value or invalid representation
Examples: BIT does not accept the value ‘Z’
BIT_VECTOR requires double quotes
INTEGER cannot be represented with quotes
Error 4: Incorrect indexing
Examples: Order (ascending or descending) is reversed
Index values fall outside the actual range
Incorrect use of parentheses
Error 5: Incorrect assignment operator
Use “<=” for signals, “:=” for variables, constants, and initial/default values
EECS 31L: Introduction to Digital Design Lab, Lecture 3
(c) 2015 Pooria. M. Yaghini
49
Lecture 3: VHDL Attributes
Predefined Attributes
Predefined attributes retrieve information about named entities
Attributes of Scalar Types (numeric, enumerated, physical)
Attributes of Array Types
Attributes of Signals
Attributes of Named Entities
EECS 31L: Introduction to Digital Design Lab, Lecture 3
(c) 2015 Pooria. M. Yaghini
50
Lecture 3: VHDL Attributes
Predefined Attributes
Predefined attributes retrieve information about named entities
Attributes of Scalar Types (numeric, enumerated, physical)
Attributes of Array Types
Attributes of Signals
Attributes of Named Entities
Written with a “tick” (’)
IF clk’EVENT AND ...
IF clk’QUIET ...
FOR i IN input’RANGE ...
EECS 31L: Introduction to Digital Design Lab, Lecture 3
(c) 2015 Pooria. M. Yaghini
51
Lecture 3: VHDL Attributes
Predefined Attributes
Example: Array‐related attributes
SIGNAL x: BIT_VECTOR(m DOWNTO n);
The following is returned by the attributes below:
x’LOW
x’HIGH
x’LEFT
x’RIGHT
x’LENGTH
x’RANGE
x’REVERSE_RANGE
x’ASCENDING
EECS 31L: Introduction to Digital Design Lab, Lecture 3
(c) 2015 Pooria. M. Yaghini
52
Lecture 3: VHDL Attributes
Predefined Attributes
Example: Array‐related attributes
SIGNAL x: BIT_VECTOR(m DOWNTO n);
The following is returned by the attributes below:
x’LOW
x’HIGH
x’LEFT
x’RIGHT
x’LENGTH
x’RANGE
x’REVERSE_RANGE
x’ASCENDING
-- n
EECS 31L: Introduction to Digital Design Lab, Lecture 3
(c) 2015 Pooria. M. Yaghini
53
Lecture 3: VHDL Attributes
Predefined Attributes
Example: Array‐related attributes
SIGNAL x: BIT_VECTOR(m DOWNTO n);
The following is returned by the attributes below:
x’LOW
x’HIGH
x’LEFT
x’RIGHT
x’LENGTH
x’RANGE
x’REVERSE_RANGE
x’ASCENDING
-- n
-- m
EECS 31L: Introduction to Digital Design Lab, Lecture 3
(c) 2015 Pooria. M. Yaghini
54
Lecture 3: VHDL Attributes
Predefined Attributes
Example: Array‐related attributes
SIGNAL x: BIT_VECTOR(m DOWNTO n);
The following is returned by the attributes below:
x’LOW
x’HIGH
x’LEFT
x’RIGHT
x’LENGTH
x’RANGE
x’REVERSE_RANGE
x’ASCENDING
-- n
-- m
-- m
EECS 31L: Introduction to Digital Design Lab, Lecture 3
(c) 2015 Pooria. M. Yaghini
55
Lecture 3: VHDL Attributes
Predefined Attributes
Example: Array‐related attributes
SIGNAL x: BIT_VECTOR(m DOWNTO n);
The following is returned by the attributes below:
x’LOW
x’HIGH
x’LEFT
x’RIGHT
x’LENGTH
x’RANGE
x’REVERSE_RANGE
x’ASCENDING
-----
n
m
m
n
EECS 31L: Introduction to Digital Design Lab, Lecture 3
(c) 2015 Pooria. M. Yaghini
56
Lecture 3: VHDL Attributes
Predefined Attributes
Example: Array‐related attributes
SIGNAL x: BIT_VECTOR(m DOWNTO n);
The following is returned by the attributes below:
x’LOW
x’HIGH
x’LEFT
x’RIGHT
x’LENGTH
x’RANGE
x’REVERSE_RANGE
x’ASCENDING
------
n
m
m
n
m‐n+1
EECS 31L: Introduction to Digital Design Lab, Lecture 3
(c) 2015 Pooria. M. Yaghini
57
Lecture 3: VHDL Attributes
Predefined Attributes
Example: Array‐related attributes
SIGNAL x: BIT_VECTOR(m DOWNTO n);
The following is returned by the attributes below:
x’LOW
x’HIGH
x’LEFT
x’RIGHT
x’LENGTH
x’RANGE
x’REVERSE_RANGE
x’ASCENDING
-------
n
m
m
n
m‐n+1
m DOWNTO n
EECS 31L: Introduction to Digital Design Lab, Lecture 3
(c) 2015 Pooria. M. Yaghini
58
Lecture 3: VHDL Attributes
Predefined Attributes
Example: Array‐related attributes
SIGNAL x: BIT_VECTOR(m DOWNTO n);
The following is returned by the attributes below:
x’LOW
x’HIGH
x’LEFT
x’RIGHT
x’LENGTH
x’RANGE
x’REVERSE_RANGE
x’ASCENDING
--------
n
m
m
n
m‐n+1
m DOWNTO n
n TO m
EECS 31L: Introduction to Digital Design Lab, Lecture 3
(c) 2015 Pooria. M. Yaghini
59
Lecture 3: VHDL Attributes
Predefined Attributes
Example: Array‐related attributes
SIGNAL x: BIT_VECTOR(m DOWNTO n);
The following is returned by the attributes below:
x’LOW
x’HIGH
x’LEFT
x’RIGHT
x’LENGTH
x’RANGE
x’REVERSE_RANGE
x’ASCENDING
---------
n
m
m
n
m‐n+1
m DOWNTO n
n TO m
FALSE
EECS 31L: Introduction to Digital Design Lab, Lecture 3
(c) 2015 Pooria. M. Yaghini
60