The University of Toledo
EECS:4630/5630/7630 Physical Design of VLSI Circuits
Dr. A.D. Johnson
f00s - 1
Lecture:TR 4.15-5.30 PL-3020
Office hours W 7.15-9.00 NI-2049
SYLLABUS
Physical Design of VLSI Circuits
Week starting
Subject
1.
August
21
2.
August
28
3.
Septemb. 4
Septemb. 11
5.
Septemb. 18
6.
Septemb. 25
7.
Octob.
2
8.
Octob.
9
9.
10.
Octob.
Octob.
16
23
11.
Octob.
30
12.
13.
14.
Novemb. 6
Novemb. 13
Novemb. 20
15.
Novemb. 27
16.
Decemb.
Goals:
Textbook:
Lecture notes
Lab manual:
Grading Policy:
4
Introduction to VLSI design: component placement, routing area partitioning,
routing, verification, testing. Ch.16.Floorplanning.
Ch.16.Routing Region Partitioning: Definitions, canonical tiling, channel
intersection graph, T and X-junction partitioning.
Ch.16.Routing Region Partitioning: routing order graph, the set of channels with
a feasible routing order.VLSI Design Tools Lab environment. [Hwk#1]
Ch.17. VLSI channel routing: Horizontal and vertical constraints and their
modeling,[Hwk#3]
Ch.17. Data structures for list and graph models. Metrics for the quality of
channel routing. Data structure for the wiring[Hwk#4
17.Left Edge channel routing algorithm and its Suboptimal modification.
[Hwk#5].
Developement of Channel routing beyond Left Edge algorithm: Greedy channel
router, and other techiques.[Hwk#6]
Ch.17.Other detailed routing methods: River routing, power net routing clock net
routing. {Term project assigned}
Ch.17. Global routing techniques: maze routing, line routing. Hierarchical router.
Ch.16. Component placement: constructive, and iterative improvement
algorithms][Hwk#2]
Compaction: Basic definitions: One-dimensional mask layout compaction.
Constraint graph. Circuit extraction and design rule checking. [Hwk#7]
Compaction: One-dimensional constraint graph compaction algorithm. [Hwk#8]
Compaction: Two-dimensional compaction. [Hwk#9] Midterm Exam.
Ch.13.Simulation: logic simulation, timing analysis,formal
verification,[Hwk#10]
Ch.13.Simulation: switch, and transistor level simulation. {Term project #2
assigned}
Ch.14.Testing: the BST, faults, fault simulation, test patterns, built-in self testing.
Gaining general knowledge about electronic design automation tools for all phases of the VLSI
design cycle. Learning the specifics of the "design tools design" for selected phases of the VLSI
design cycle.
Michael S. Smith: Application Specific Integrated Circuits, Addison-Wesley,1997. (This same book
is the course textbook for EECS 6660/8660 Field Programmable Gate Arrays and Suggested reading
book for 4610/5610 Digital VLSI Design I.
Lecture notes for in-depth coverage of some topics not covered by the book will be handed out.
The VLSI Design Tools Lab manual will be handed out.
Homeworks / Midterm /Project = 20 / 40 / 40.
f00s - 2
Lecture:TR 4.15-5.30 PL-3020
Office hours W 7.15-9.00 NI-2049
The University of Toledo
EECS:4630/5630/7630 Physical Design of VLSI Circuits
Dr. A.D. Johnson
Homework schedule
Hwk#topic
week assigned
week due
1o Channel description file: no vert. constr. & LEFTEDGE
3
4
2o Preprocessing tool LRMOST, Left Edge hand routing
4
5
3o LE algorithm net-on-track placement tool LEORPL
6
7
4o LE wiring tool LEWIRE
7
8
5o Channel description file: no cyclic vert. constr. and MODLEFT
8
9
6o Vertical constraint structure representation tool VECONG
8
9
7o Geometric layout - creation and I/O
11
12
8o Feature bloating tool BLOATS, and constraint graph
12
13
9o Constr. graph edge weights - COLOWE and repl. vect. COGREV
13
14
14
15
10o Compaction to max coordinates - COGMAX
Policy on submission of homeworks and project reports
1. All homework reports (solutions) are due at the beginning of the second class of the week.
2. In order to discourage the practice of working to finish the reports during the time scheduled for
classes, the absolute deadline for handing in the reports is five minutes after the time scheduled for
the beginning of the class.
3. Homeworks handed in after the deadline, but before the beginning of the first class of the next week
are accepted for half credit.
4. This policy promotes good planning habits. The fact that something went wrong the morning of the
due day does not make a case for delaying the due time. We ought to be prepared for the day when
something unforeseen happens.