June 11-12
2005
Electrical Characterization of
MOS Devices with Advanced
Gate Stacks
Eric M. Vogel Leader, CMOS and Novel Devices Group
and Director, NIST AML Nanofab
Semiconductor Electronics Division
Gaithersburg, MD 20899
Advanced Dielectrics
Ultrathin and high-κ gate dielectrics present numerous
challenges to MOS device characterization.
Slide No. 2
Eric M. Vogel June 11-12, 2005
“Electrical Characterization of MOS Devices”
Scope
• This 2-part lecture will focus on the understanding necessary
to characterize MOS capacitors and gated diodes on bulk silicon
having advanced gate dielectrics using the most common lower
frequency (<~ 1 MHz) techniques: 1) Capacitance,
2) Conductance, 3) Charge-Pumping, 4) Tunneling.
• For FET Parameter Extraction see G. Ghibaudo lecture
• For LF Noise see C. Clayes lecture
• For SOI see S. Cristoloveanu lecture and A. Zaslavsky lecture
• For Reliability, Defect generation, and Device Instability see J.
Stathis lecture
• For High Frequency Device Characterization see G. Dambrine
lecture
Slide No. 3
Eric M. Vogel June 11-12, 2005
“Electrical Characterization of MOS Devices”
OUTLINE
• Capacitance-Voltage
• Conductance
• Tunneling
• Charge-Pumping
Slide No. 4
Eric M. Vogel June 11-12, 2005
“Electrical Characterization of MOS Devices”
CAPACITANCE-VOLTAGE
• Measurement Issues
• Theory (Without Interface States)
• Parameter Extraction
• Including Interface States
Slide No. 5
Eric M. Vogel June 11-12, 2005
“Electrical Characterization of MOS Devices”
C-V Measurement Issues
• Conditions
• Errors
• Equivalent Circuits
Slide No. 6
Eric M. Vogel June 11-12, 2005
“Electrical Characterization of MOS Devices”
Measurement Conditions
• The ac voltage should be as small as possible
to ensure small signal approximation while
still allowing accurate measurement.
• Assuming that the device capacitance is
properly extracted from the measured
capacitance, either parallel or series mode
may be used since the one can be derived from
the other (Cs=Cp*(1+D2), D=1/ωRpCp).
• Quasi-static C-V measurements generally
can not be performed (using standard q-s meters)
due to the large leakage currents.
Slide No. 7
Cm
Eric M. Vogel June 11-12, 2005
“Electrical Characterization of MOS Devices”
Gm
Measurement Errors
Relative Measurement Accuracy for HP4284A
• The relative measurement
Calculations from HP4284A Precision LCR Meter Operation Manual p. 9-7 to 9-15
accuracy of an LCR meter
This is only valid for: medium/long integration
100Hz <= F <= 1MHz
depends on the frequency
1 m cable
and the nominal capacitance
Vdc < 20 V
30mV <= Vac <= 150mV <or> Vac = 10mV,20mV,25mV
and conductance of the device
Cp-Gp measurement mode
short and open correction performed
under test.
• We have developed a
spreadsheet which calculates
the relative measurement
accuracy of the HP4284A.
Slide No. 8
Input
C (F)
G (S)
F (Hz)
Vac (Vrms)
Output
C_relacc (+/-%)
G_relacc (+/-%)
D_relacc (+/-%)
1.30E-10
1.00E-02
1.00E+03
5.00E-02
1288.996212
D too large (D>0.1)*
157833.5641
Eric M. Vogel June 11-12, 2005
“Electrical Characterization of MOS Devices”
1.05296E-05
(FYI: Cal
(FYI: Cal
(FYI: Cal
Measurement Errors
• The relative capacitance
measurement error
of an LCR meter increases
with:
→ decreasing frequency
→ increasing conductance
→ decreasing capacitance
Capacitance Error (+/- %)
105
-11
104
103
102
101
100
10-1
10-2
102
103
104
Frequency (Hz)
Slide No. 9
-3
C = 10 F, G = 10 S
-6
C = 10-11 F, G = 10 S
-10
-6
C = 10 F, G = 10 S
Eric M. Vogel June 11-12, 2005
“Electrical Characterization of MOS Devices”
105
106
Capacitor Equivalent Circuits
Gc
Cc
Rs
Lo
Slide No. 10
Eric M. Vogel June 11-12, 2005
“Electrical Characterization of MOS Devices”
Equivalent Circuits
Transistor
Equivalent Circuit†
Capacitor
LCR Measurement
Equivalent Circuit
Cm
Gm
Gc
Cc
Rs
†K.
Lo
Slide No. 11
Ahmed, E. Ibok, G. Yeap, Q. Xiang,
B. Ogle, J. J. Wortman, and J. R. Hauser,
IEEE Trans. Elec. Dev., vol. 46,
pp. 1650-1655, 1999.
Eric M. Vogel June 11-12, 2005
“Electrical Characterization of MOS Devices”
Examples of Measured Behavior
600
F = 1 MHz
Capacitance (pF)
Capacitance (pF)
140
F = 10 kHz
500
400
300
200
100
2
10 Hz
3
10 Hz
4
10 Hz
105 Hz
106 Hz
120
100
80
60
ISSG 2.1 nm
-5
2
Area = 5x10 cm
40
20
0
-3
-2
-1
0
Vg (V)
1
2
0
-3
-2
-1
0
1
2
3
Vg (V)
• For thicker dielectrics, a simple • For thinner or leakier
reduction in capacitance at
dielectrics, capacitance rollhigh frequencies due to series
over, negative capacitance, and
resistance is many times
increasing capacitance with
observed.
bias is sometimes observed.
Eric M. Vogel June 11-12, 2005
Slide No. 12
“Electrical Characterization of MOS Devices”
Modeling “Measured” Capacitance
• Series resistance alone
cannot explain an increase in
or negative measured
capacitance at high
frequency.
1000
Capacitance (pF)
800
Rs=20Ω, L=10µH
600
Rs=20Ω, L=45µH
Rs=103Ω, L=0µH
400
F=1MHz
200
0
• Inductance is necessary to
observe an increase in or
negative capacitance at high
frequency.
Gm =
Correct Capacitance
Rs=20Ω, L=0µH
-200
-3
-2
-1
1
Vg (V)
Gc (Gc Rs + 1) − ω 2Cc2 Rs
(G R
c
2
2
s − ω C c Lo + 1) + ω (C c Rs + Gc Lo )
2
(
2
)
Cc 1 − ω 2Cc Lo − Gc2 Lo
Cm =
(C R
GR
−ω C
L 11-12,
+ 1) + ω
Eric (M.
Vogel
June
2005
2
2
c
Slide No. 13
0
s
c o
2
c
2
)
+
G
L
s
c o
“Electrical Characterization of MOS Devices”
Correcting Measured Capacitance
• Previous work provided methodologies to correct
measured capacitance for leakage and series resistance1,2.
• Recent work has provided the methodology that includes a
series inductance3.
• It is unknown whether the
series inductance is due to
measurement (e.g. cabling)4
or a physical phenomenon5.
1K.
J.Yang and C. Hu, IEEE Trans. Elec. Dev., vol. 46, pp. 1500-1501, 1999.
M. Vogel, W. K. Henson, C. A. Richter, and J. S. Suehle, IEEE Trans. Elec. Dev., vol. 47, p. 601, 2000.
3H.-T. Lue, C.-Y. Liu, and T.-Y. Tseng, IEEE Elec. Dev. Lett., vol. 23, pp. 553-555, 2002.
4A. Nara, N. Yasuda, H. Satake, and A. Toriumi, IEEE Trans. Semi. Manuf., vol. 15, pp. 209-213, 2002.
5M. Matsumura, and Y. Hirose, Jap. J. Appl. Phys., vol. 39, pp. L123-L125, 2000.
2E.
Slide No. 14
Eric M. Vogel June 11-12, 2005
“Electrical Characterization of MOS Devices”
C-V Theory
• Potential and Charge Balance
• Built-in Voltage
• Total Semiconductor Charge
• Regions of Operation
• Capacitance
• Quantum Mechanical Effects
Slide No. 15
Eric M. Vogel June 11-12, 2005
“Electrical Characterization of MOS Devices”
Equations for C-V
Potential Balance:
Vg = Vsub − V poly + Vox + Vbi
Charge Balance:
Qsub (Vsub ) + Q poly (V poly ) + Qox = 0
• To calculate C-V, we need to solve the above equations.
• Vpoly is measured from the oxide-poly interface to the bulk of
the poly. Vpoly = 0 for metal gate electrodes.
• Qox is charge in the oxide that is fixed with bias.
• We will first neglect defects in the dielectric that change
occupancy with applied bias (interface states).
• Vbi is the built-in potential between the gate and substrate.
Slide No. 16
Eric M. Vogel June 11-12, 2005
“Electrical Characterization of MOS Devices”
Potential Balance
Vg = Vsub − V poly + Vox + Vbi
Vbi =
(E
vac
Potential balance
− E f , poly ) @ poly bulk
q
Q poly (V poly ) = CoxVox
−
(E
vac
− E f ,sub ) @ sub bulk
q
Using Gauss’ Law
Qsub
Vg = Vsub − V poly + V fb −
Cox
Qox
V fb = Vbi −
Cox
Slide No. 17
Eric M. Vogel June 11-12, 2005
“Electrical Characterization of MOS Devices”
More later
Charge Density in a Semiconductor
ρ = q ( p − n + N d+ − N a− )
Classical Charge Density (cm-3) in
a Semiconductor
⎛ 2Nv
⎞
⎛ − η − E gap ⎞ 2 N c
⎛η ⎞
⎟
⎜
⎟⎟ −
F1 2 ⎜⎜
F1 2 ⎜⎜ ⎟⎟ +
φt
π
⎟
⎜ π
⎝
⎠
⎝ φt ⎠
⎟
ρ = q⎜
Nd
Na
⎟
⎜
−
⎜ 1 + 2 exp⎛ η − ( Ed − Ec ) ⎞ 1 + 4 exp⎛ ( Ea − Ec ) − η ⎞ ⎟
⎟
⎜
⎜
⎟⎟
⎜
φt
φt
⎝
⎝
⎠
⎠⎠
⎝
F1/ 2 (η ) =
Slide No. 18
2
π
∫
∞
0
E
dE
1 + exp( E − η )
η ≡ E f − Ec
Eric M. Vogel June 11-12, 2005
“Electrical Characterization of MOS Devices”
φt ≡
kT
q
Calculating the Built-in Voltage
Vbi =
(E
vac
− E f , poly ) @ poly bulk
−
(E
vac
− E f ,sub ) @ sub bulk
q
q
⎛ 2Nv
⎞
⎛ − η − E gap ⎞ 2 N c
⎛η ⎞
⎟
⎜
⎟⎟ −
F1 2 ⎜⎜
F1 2 ⎜⎜ ⎟⎟ +
φt
π
⎟ η ≡ E f − Ec
⎜ π
⎝
⎠
⎝ φt ⎠
⎟
ρ = q⎜
Nd
Na
⎟
⎜
−
⎜ 1 + 2 exp⎛ η − ( Ed − Ec ) ⎞ 1 + 4 exp⎛ ( Ea − Ec ) − η ⎞ ⎟
⎟
⎜
⎜
⎟⎟
kT
⎜
φ
φ
⎝
⎝
⎠
⎠ ⎠ φt ≡
t
t
⎝
q
E
2 ∞
F1/ 2 (η ) =
dE
∫
0
π 1 + exp( E − η )
• To calculate Vbi set ρ = 0 and find Ef in the bulk of the
semiconductor.
Slide No. 19
Eric M. Vogel June 11-12, 2005
“Electrical Characterization of MOS Devices”
Calculating Total Semiconductor Charge
Qsub (Vsub ) + Q poly (V poly ) + Qox = 0
⎛ 2Nv
⎞
⎛ − η − E gap ⎞ 2 N c
⎛η ⎞
⎟
⎜
⎟⎟ −
F1 2 ⎜⎜
F1 2 ⎜⎜ ⎟⎟ +
φt
π
⎟
⎜ π
⎝
⎠
⎝ φt ⎠
⎟
ρ = q⎜
Nd
Na
⎟
⎜
−
⎜ 1 + 2 exp⎛ η − ( Ed − Ec ) ⎞ 1 + 4 exp⎛ ( Ea − Ec ) − η ⎞ ⎟
⎟
⎜
⎜
⎟⎟
⎜
φt
φt
⎝
⎝
⎠
⎠⎠
⎝
• To calculate Qsub(Vsub) or Qpoly(Vpoly), one must integrate ρ from
the oxide/semi interface to the bulk of the semiconductor.
Slide No. 20
Eric M. Vogel June 11-12, 2005
“Electrical Characterization of MOS Devices”
Calculating Total Semiconductor Charge
Qsub = −Ε surf ε
η bulk = (E f − Ec ) bulk = φb
F3 / 2 (η ) =
Slide No. 21
2
π
∫
∞
0
Ε 2surf
⎡ 4Nv ⎛
⎛ − φb − E gap ⎞
⎛ − φb − Vsub − E gap ⎞ ⎞ ⎤
⎜
⎜
⎟
⎟⎟ ⎟⎟ + ⎥
−
F
F
⎢
⎟ 3 2 ⎜⎜
⎜ 3 2⎜
π
φ
φ
3
⎝
⎠
⎝
⎠⎠ ⎥
t
t
⎝
⎢
⎢ 4N ⎛
⎥
⎛ φb ⎞
⎛ φb + Vsub ⎞ ⎞
c
⎜⎜ F3 2 ⎜⎜ ⎟⎟ − F3 2 ⎜⎜
⎢
⎥
⎟⎟ ⎟⎟ +
⎢3 π ⎝
⎥
⎝ φt ⎠ ⎠
⎝ φt ⎠
⎢
⎥
⎛
⎞
⎛
⎞
⎛
⎞
−
−
(
)
E
E
φ
d
c
⎢ ⎜
⎥
⎜ 1 + 2 exp⎜ b
⎟ ⎟⎟
⎥
2qφt ⎢ ⎜ Vsub
φt
⎟
⎜
⎟
⎝
⎠
=
+ ln
+ ⎥
N
⎜
⎟⎟
ε ⎢ d ⎜ φt
⎛
⎞
+
−
−
V
E
E
φ
(
)
sub
d
c
⎢ ⎜
⎥
⎟ ⎟ ⎟⎟
⎜ 1 + 2 exp⎜ b
⎜
⎢ ⎝
⎥
φt
⎝
⎠ ⎠⎠
⎝
⎢
⎥
⎛
⎛ ( Ea − E c ) − φb ⎞ ⎞ ⎞ ⎥
⎢ ⎛
⎜
⎜
+
1
4
exp
⎜
⎟ ⎟⎟ ⎥
⎢
φt
V
⎝
⎠ ⎟⎟ ⎥
⎢ N a ⎜ − sub + ln⎜
⎜
⎛ ( Ea − E c ) − φb − Vsub ⎞ ⎟ ⎟ ⎥
⎢ ⎜ φt
⎟ ⎟ ⎟⎟ ⎥
⎜ 1 + 4 exp⎜
⎢ ⎜⎜
φt
⎝
⎠ ⎠⎠ ⎦
⎝
dE ⎣ ⎝
E3 2
1 + exp( E − η )
Eric M. Vogel June 11-12, 2005
“Electrical Characterization of MOS Devices”
Solving Potential and Charge Balance
Potential Balance:
Charge Balance:
Qsub
Vg = Vsub − V poly + V fb −
Cox
Qsub (Vsub ) + Q poly (V poly ) + Qox = 0
• Given: Vg, Nsub, Npoly, Cox, Qox
• The above 2 equations can be solved for 2 unknowns: Vsub, Vpoly
Slide No. 22
Eric M. Vogel June 11-12, 2005
“Electrical Characterization of MOS Devices”
Regions of Operation
1.4
3e-6
Inversion
1.2
2e-6
1.0
Depletion
0.6
Qsub
Vsub
1e-6
Ef-Ec=-nkT/q
0.8
0.4
0.2
Ef-Ec=-Egap+nkT/q
0.0
-0.2
-2
-1
0
Vg
1
2
3
Inversion
-1e-6
Accumulation
-3e-6
-0.4
-3
0
-2e-6
Accumulation
-4
Depletion
4
-4e-6
-4
-3
-2
-1
0
1
2
Vg
• Accumulation occurs when the Ef is near the valence band.
• Inversion occurs when the Ef is near the conduction band.
Slide No. 23
Eric M. Vogel June 11-12, 2005
“Electrical Characterization of MOS Devices”
3
4
Common Approximations
3e-6
• Qinv = Cox (Vg-Vt)
Qacc
2e-6
Depletion
1e-6
Qsub
• Qacc = Cox (Vg-Vfb)
0
Inversion
-1e-6
Accumulation
-2e-6
-3e-6
Qinv
-4e-6
-4
-3
-2
-1
0
1
Vg
Slide No. 24
Eric M. Vogel June 11-12, 2005
“Electrical Characterization of MOS Devices”
2
3
4
Quasi-static vs. Deep Depletion
3
4
Quasi-static
Deep Depletion
1
2
Vox
Vsub
3
Quasi-static
Deep Depletion
2
1
0
-1
0
-2
-1
-4
-3
-2
-1
0
Vg
1
2
3
4
-3
-4
-3
-2
-1
0
Vg
1
2
3
• The previous analysis assumes minority carrier generation can
keep up with the dc bias (quasi-static).
• However, deep depletion is typically seen for MOS capacitors
with ultra-thin oxides.
Slide No. 25
Eric M. Vogel June 11-12, 2005
“Electrical Characterization of MOS Devices”
4
Calculating Capacitance
Total Device Capacitance:
Substrate/Poly Capacitance:
Slide No. 26
(
Ctot = (Csub ) + C
Csub ( poly ) =
−1
−1
poly
dQsub ( poly )
dVsub ( poly )
Eric M. Vogel June 11-12, 2005
“Electrical Characterization of MOS Devices”
+C
)
−1 −1
ox
1.2
1.2
1.0
1.0
Nsub = 10
0.6
cm
-3
LF
HF
DD
0.4
0.2
0.8
2
17
C (µF/cm )
0.8
2
C (µF/cm )
Typical C-V Characteristics
14
0.6
LF
HF
DD
0.4
0.2
0.0
Nsub = 6x10
-3
cm
0.0
-4
-3
-2
-1
0
Vg (V)
1
2
3
4
-4
-3
-2
-1
0
1
2
3
Vg (V)
• High frequency means that carriers can respond to the dc
signal but not the ac signal
• Low Frequency means that carriers can respond to the dc
and ac signals.
• Deep-depletion means Eric
thatM.the
carriers cannot respond to
Vogel June 11-12, 2005
the dc or ac signals.
“Electrical Characterization of MOS Devices”
Slideeither
No. 27
4
Quantum Mechanical Effects
• The previous analysis was based on a classical description
of charge in the semiconductor.
• The large band bending in the semiconductor causes the
formation of a potential well.
• This results in a quantization of the density of states and a
shifting of the carrier centroid away from the
semiconductor/insulator interface.
• The most fundamental and computationally expensive
approach to handle these quantum-mechanical effects is to
solve the Schroedinger and Poisson equations together.
Slide No. 28
Eric M. Vogel June 11-12, 2005
“Electrical Characterization of MOS Devices”
Quantum Mechanical Effects
• The splitting of energy levels and the shifting of the carriers
away from the interface leads to a decrease of the inversion
layer or accumulation layer charge density as a functio of the
surface potential as compared to classical simulation.
• van Dort et al. pursued a more computationally efficient
approach of modeling these effects via an increase in the
effective bandgap of silicon.
• Hareland et al. improved on van Dort’s work by providing a
more detailed description of the bandgap widening based on a
comparison to a rigorous self-consistent SchroedingerPoisson solution.
13
⎛ ε ⎞
23
∆E g = 5.92 × 10 −8 ⎜ si ⎟ (Ε s )
⎝ 4kTq ⎠
Slide No. 29
Eric M. Vogel June 11-12, 2005
“Electrical Characterization of MOS Devices”
Quantum Mechanical Effects
3.5
Classical
3.0
2.5
QM
2
C (µF/cm )
• Quantum Mechanical
Effects result in a drop of
the maximum capacitance
and a slight shift of the
threshold voltage.
2.0
1.5
Metal Gate
Tox = 1.0 nm
1.0
0.5
Nsub = 2x1017cm-3
0.0
-4
-3
-2
-1
0
Vg (V)
Slide No. 30
Eric M. Vogel June 11-12, 2005
“Electrical Characterization of MOS Devices”
1
2
3
4
C-V Parameter Extraction
• Methodology
• Oxide Thickness
• Substrate Doping
• Polysilicon Doping
• Flatband Voltage
• Oxide Charge and Workfunction
Slide No. 31
Eric M. Vogel June 11-12, 2005
“Electrical Characterization of MOS Devices”
Parameter Extraction using Modeling
1.6
• NCSU CVC program
fits experimental C-V
data using a model
that has the following
parameters: Vfb, Tox,
Nsub, Npoly
1.4
2
C (µF/cm )
1.2
• NCSU CVC does not
include interface
states.
1.0
0.6
Vfb = -0.987 V
Tox = 2.01 nm
0.4
Nsub = 2.97x10
0.8
Measured
Modeled
0.2
cm
20
cm
Npoly = 1.61x10
-3
0.0
-4
-3
-2
-1
0
Vg (V)
Slide No. 32
17
Eric M. Vogel June 11-12, 2005
“Electrical Characterization of MOS Devices”
1
2
3
-3
Impact of Simulation Code
Slide No. 33
1.50
1.25
1.00
2
C (µF/cm )
• Simulators show a difference of
up to 20% in the calculated
accumulation capacitance.
• This discrepancy leads to large
inaccuracies in the values of
dielectric thickness extracted
from C-V.
• Possible reasons include: the
use of approximations for
quantum effects vs. Schrödinger
equation, wave function
boundary conditions, and type of
carrier statistics.
0.75
0.50
UTQuant [30]
NIST
Schred [32]
NCSU [25]
NEMO [29]
Berkeley [31]
Tox = 2.0 nm
18
-3
Nsub = 10 cm
0.25 Npoly = 1020 cm-3
n-channel, n-poly gate
0.00
-3
-2
-1
0
Vg (V)
Eric M. Vogel June 11-12, 2005
“Electrical Characterization of MOS Devices”
1
2
3
Oxide Thickness Definitions
• The Equivalent Oxide Thickness (EOT) is obtained from the
gate dielectric capacitance alone.
• EOT must be determined from C-V measurements using a
fitting or extraction algorithm which includes QM effects,
polysilicon depletion, etc.
• The Capacitance Equivalent Thickness (CET) is determined
by simply taking the ∈SiO2xArea/Cmeas where Cmeas is the
measured capacitance in inversion or accumulation at some
defined voltage.
Slide No. 34
Eric M. Vogel June 11-12, 2005
“Electrical Characterization of MOS Devices”
Oxide Thickness Definitions
• In order to achieve a
small EOT, the interfacial
thickness must be
controlled.
2.0
1.5
EOT (nm)
• EOT is the thickness of
SiO2 which would produce
the same capacitance as
that obtained from a high-K
dielectric.
1.0
T(SiO2) = 1 nm, k(High-k) = 20
T(SiO2) = 1 nm, k(High-k) = 40
T(SiO2) = 0.5 nm, k(High-k) = 20
T(SiO2) = 0.5 nm, k(High-k) = 40
0.5
0.0
0
1
2
3
4
5
Physical Thickness of High-κ Dielectric (nm)
Slide No. 35
Eric M. Vogel June 11-12, 2005
“Electrical Characterization of MOS Devices”
Thickness Extraction
+C
)
−1 −1
ox
• The maximum capacitance in
accumulation is close to Cox.
• The minimum capacitance is
due to the substrate
capacitance.
14
2
−1
poly
C (µF/cm )
(
Ctot = (Csub ) + C
−1
12
Ctot
10
Csub
Cox
8
6
4
2
0
-4
-3
-2
-1
0
Vg (V)
Slide No. 36
Eric M. Vogel June 11-12, 2005
“Electrical Characterization of MOS Devices”
1
2
3
4
Thickness Extraction
1.75
1.70
1.65
CET (nm)
• The capacitance in
accumulation (represented here
by CET) is not strongly impacted
by the substrate or polysilicon
doping.
1.60
1.55
1.50
• The CET does depend strongly
on whether the gate is metal or
polysilicon.
Slide No. 37
19
-3
20
-3
Npoly = 10 cm
EOT = 1.0 nm
N-channel Device
Vg = -2 V
Npoly = 10 cm
Metal
1.45
1.40
1015
1016
1017
1018
-3
Nsub (cm )
Eric M. Vogel June 11-12, 2005
“Electrical Characterization of MOS Devices”
1019
Substrate Doping Extraction
1.2
1.0
0.8
2
C (µF/cm )
• The substrate doping strongly
impacts the minimum
capacitance but does not
strongly impact the maximum
capacitance in accumulation.
0.6
0.4
17
Nsub = 10
0.2
• The minimum capacitance can
be used to determine substrate
doping.
Slide No. 38
-3
cm
14
Nsub = 6x10
0.0
-4
-3
-2
-1
0
Vg (V)
Eric M. Vogel June 11-12, 2005
“Electrical Characterization of MOS Devices”
1
2
3
cm
4
-3
Polysilicon Doping Extraction
3.0
• The capacitance in
inversion can be used to
determine polysilicon
doping.
2.5
2
C (µF/cm )
• The depletion of
polysilicon results in a large
drop of the capacitance.
Metal
Poly=1020 cm-3
2.0
1.5
1.0
Poly=5x1019 cm-3
Tox = 1.0 nm
0.5 N = 2x1017cm-3
sub
0.0
-4
-3
-2
-1
0
Vg (V)
Slide No. 39
Eric M. Vogel June 11-12, 2005
“Electrical Characterization of MOS Devices”
1
2
3
4
Flatband Voltage Extraction
• There are numerous
sources of possible error
with this technique.
Slide No. 40
18
10
10-1
Cfb/Cox
• If the oxide capacitance
and substrate doping is
known, the flatband
capacitance (and hence
Vfb) can be found.
100
17
10
16
10
15
10
10-2
Na
10-3
10-1
-3
14
0
=1
cm
100
Tox (nm)
Eric M. Vogel June 11-12, 2005
“Electrical Characterization of MOS Devices”
101
Workfunction and Oxide Charge
Extraction
EOT
⎤
1 ⎡
V fb = φms −
xρ ( x )dx ⎥
⎢
∫
ε ox ⎣ 0
⎦
EOT 1
EOT
⎤
1 ⎡
V fb = φms −
xρ ( x )dx + ∫ xρ f 2bulk ( x )dx ⎥
⎢
∫
ε ox ⎣ 0
⎦
EOT 1
For a stacked dielectric
Slide No. 41
Eric M. Vogel June 11-12, 2005
“Electrical Characterization of MOS Devices”
Workfunction and Oxide Charge
Extraction
V fb = φms −
−
−
1
ε ox
1 ⎡1
2⎤
EOT
ρ
⎥⎦
ε ox ⎢⎣ 2 f 1bulk
[Q
f 1int f
R. Jha, et al., IEEE EDL 25, 420 (2004)
+ Q f 2 int f − (ρ f 1bulk − ρ f 2bulk )EOT2 ]EOT
1 ⎡1
⎤
(
)
EOT
Q
ρ
ρ
−
−
f 1bulk
f 2 bulk
2
f 1int f ⎥ EOT2
⎢
ε ox ⎣ 2
⎦
For a SiO2/high-k stack where EOT1(2) is the EOT of the highk (SiO2), Qf1(2)int are the charges at the high-k/SiO2 (SiO2/Si)
interface, ρf1(2)bulk are charges uniformly distributed within the
high-k (SiO2).
Slide No. 42
Eric M. Vogel June 11-12, 2005
“Electrical Characterization of MOS Devices”
Workfunction and Oxide Charge
Extraction
R. Jha, et al., IEEE EDL 25, 420 (2004)
If interface charges dominate bulk charges:
V fb = φms −
V fb = φms −
1
ε ox
1
ε ox
[Q
[Q
f 1int f
]EOT + [Q
1
f 1int f
1
ε ox
+ Q f 2 int f ]EOT +
f 2 int f
1
ε ox
[Q
EOT ]
f 1int f
EOT2 ]
The intercepts and slopes of Vfb vs. EOT with varying EOT1
and EOT2 can provide Φms, Qf1intf, and Qf2intf.
Slide No. 43
Eric M. Vogel June 11-12, 2005
“Electrical Characterization of MOS Devices”
Effective Workfunction
• The vacuum work
function of a metal does
not necessarily equal the
effective work function of
the metal due to charge
transfer, defects, and
dipoles.
Slide No. 44
Eric M. Vogel June 11-12, 2005
“Electrical Characterization of MOS Devices”
C-V Including Interface States
• Theory
• Interface State Capacitance
• Interface State Density “Extraction”
Slide No. 45
Eric M. Vogel June 11-12, 2005
“Electrical Characterization of MOS Devices”
Including Interface States
• Qit is charge in the oxide that changes occupancy with bias.
• Dita(d) is the density of acceptor(donor)-like interface states
Qsub (Vsub ) + Q poly (V poly ) + Qit (Vsub ) + Qox = 0
Qsub Qit (Vsub )
Vg = Vsub − V poly + V fb −
−
Cox
Cox
⎡− qDita ( Et − Ei )Fsa (( Et − Ei ) − (E f − Ei )) ⎤
Qit (Vsub ) = ∫ ⎢
⎥dEt
+ qDitd ( Et − Ei )Fsd (( Et − Ei ) − (E f − Ei ))⎦
Ev ⎣
−1
−1
⎛
⎛
⎛ − (Et − E f ) ⎞ ⎞
⎛ (Et − E f )⎞ ⎞
⎟⎟ ⎟⎟
Fsd (Et − E f ) = ⎜⎜1 + 2 exp⎜⎜
⎟⎟ ⎟⎟
Fsa (Et − E f ) = ⎜⎜1 + 0.25 exp⎜⎜
Ec
⎝
Slide No. 46
⎝
φt
⎠⎠
⎝
⎝
Eric M. Vogel June 11-12, 2005
“Electrical Characterization of MOS Devices”
φt
⎠⎠
Interface State Capacitance
• At very low frequencies
(quasi-static), interface states
respond to the ac signal over
the entire bias range resulting
in a capacitance.
(
Ctot = (Cit + Csub ) + C
Slide No. 47
−1
−1
poly
+C
)
−1 −1
ox
0.35
2
Capacitance (µF/cm )
• At very high frequencies
(infinite), interface states do not
respond to the ac signal.
0.30
0.25
0.20
Tox = 10 nm
0.15
Dit = 1012 cm-2eV-1
Ideal HF
HF with Dit
0.10
QS with Dit
0.05
-3
-2
-1
0
Vg (V)
Cit ,QS
∆Qita + ∆Qitd
=
∆Vsub
Eric M. Vogel June 11-12, 2005
“Electrical Characterization of MOS Devices”
1
2
3
Interface State Capacitance
tan (ωτ )P(V )dV
∫
ωτ
= (c p )
Cit =
qDit
−1
p
s
s
p −∞
τp
σp ≡
−1
p
cp
vth
s
= capture cross section
Capacitance (µF/cm2)
∞
2.5
Tox = 1.0 nm
2.0
Dit = 1012 cm-2eV-1
FET
Cap (102 Hz)
Cap (103 Hz)
Cap (104 Hz)
Cap (105 Hz)
Cap (106 Hz)
1.5
1.0
0.5
0.0
-2.0
-1.5
-1.0
-0.5
0.0
0.5
1.0
Vg (V)
• At intermediate frequencies, SRH theory must be used including
the effect of surface potential variation across the interfacial plane.
•P(Vs) is the probability thatEric
the
band bending is V , ps is the free
M. Vogel June 11-12, 2005 s
carrier
“Electrical Characterization of MOS Devices”
Slide No. 48 concentration.
Dit Extraction
EOT = 0.62 nm
Nsub = 4x1017 cm-3
3
Exp. Data (105 Hz)
Simulation:
105 Hz (Dit profile 1)
2
σs = 4 (kT/q)
σp = 10-14 cm2
1
Simulation:
Quasi-static (Dit profile 2)
Simulation: No Dit
0
-2.0
-1.5
-1.0
-0.5
0.0
Gate Voltage (V)
10
8
profile 1
profile 2
-1
Dit (x10 cm eV )
6
12
-2
• Proper modeling requires
including the interface state
capacitance as a function of
frequency.
2
• Some have attempted
extracting Dit from the “hump”
observed in C-V using a
quasi-static approach.
Capacitance (µF/cm )
4
4
2
0
Slide No. 49
Eric M. Vogel June-1.0
11-12, -0.5
2005 0.0
E - E (eV)
“Electrical Characterization of MOS Devices”
t
i
0.5
1.0
Dit Extraction on Thick Oxides
2) Terman: A HF CV curve is
measured and compared to a
theoretical ideal (no Dit) CV
curve to obtain the amount of
voltage stretch-out.
Slide No. 50
0.35
2
Capacitance (µF/cm )
1) Low-High Frequency: A quasistatic (QS) and a high-frequency
(HF) CV curve is measured and
interface state capacitance is
determined.
0.30
0.25
0.20
Tox = 10 nm
0.15
12
0.10
-2
Dit = 10 cm eV
Ideal HF
HF with Dit
-1
QS with Dit
0.05
-3
-2
-1
0
Vg (V)
Eric M. Vogel June 11-12, 2005
“Electrical Characterization of MOS Devices”
1
2
3
Dit Extraction on Thin Dielectrics
2) Terman: With decreasing
EOT (increasing dielectric
capacitance), the voltage
shift (Qit/Cox) due to
charging of traps
(stretch-out)
becomes smaller.
Slide No. 51
∆V (V)
1) Low-High Frequency: Quasistatic measurements cannot be
performed on advanced
dielectrics due to leakage
current
100
10
Nit = 1012 cm-2
-1
11
-2
Nit = 10 cm
10-2
10
-2
Nit = 10 cm
10-3
10-4
0
2
4
6
EOT (nm)
Eric M. Vogel June 11-12, 2005
“Electrical Characterization of MOS Devices”
8
10
12
Dit Extraction
• However the number of
parameters that can provide
a reasonable fit is large.
4
17
2
Capacitance (µF/cm )
• Dit can be extracted by
properly modeling the
frequency dependence of the
interface state capacitance.
3
5
F = 10 Hz
2
1
σs = 4 (kT/q), σp = 10-14 cm2
σs = 1 (kT/q), σp = 10-14 cm2
σs = 4 (kT/q), σp = 10
-17
0
-2.0
-1.5
2
cm
-1.0
-0.5
Gate Voltage (V)
Slide No. 52
-3
Nsub = 4x10 cm
EOT = 0.62 nm
Dit profile 1
Eric M. Vogel June 11-12, 2005
“Electrical Characterization of MOS Devices”
0.0
CONDUCTANCE
• Theory
• Parameter Extraction
Slide No. 53
Eric M. Vogel June 11-12, 2005
“Electrical Characterization of MOS Devices”
Conductance Theory
rc ( x, t ) = c p p( x, t )nT f ( x, t ) (cm -3 s −1 )
re ( x, t ) = e p nT [1 − f ( x, t )] (cm -3 s −1 )
i p ( x, t ) = q[rc ( x, t ) − re ( x, t )] (A cm3 )
Applying small signal
approximation
q2
Gp =
nT f 0 c p p0 ( x ) (mhos cm 3 )
kT
Slide No. 54
Rate of hole capture
Rate of hole emission
Hole recombination
current due to semi.
bulk traps
Hole conductance
due to semi. bulk
traps
Eric M. Vogel June 11-12, 2005
“Electrical Characterization of MOS Devices”
Conductance Theory
[
G p = Cit (2ωτ p ) ln 1 + (ωτ p )
−1
2
]
1
τp =
exp( Vsub
cp Na
Hole conductance due to
distribution of surface states
)
σ p is the hole capture cross - section
v is the thermal velocity
cp = σ p v
Including band bending fluctuations across the
interfacial plane with variance of banding bending, σs
qD (2πσ
= it
ω
2ωτ p
Gp
Slide No. 55
)
2 −1 2 ∞
s
(
)
⎛ η2 ⎞
2
(
)
⎟
⎜
exp
exp
(
−
η
)
ln
1
+
ωτ
exp 2η dη
−
p
∫−∞ ⎜⎝ 2σ s2 ⎟⎠
Eric M. Vogel June 11-12, 2005
“Electrical Characterization of MOS Devices”
Conductance Theory
Cm Measured Capacitance
Gm Measured Conductance
Cc Capacitance corrected for Rs
Gc Conductance corrected for Rs
Gt DC Tunneling Conductance
Gac
Rs
Gc corrected for Tunneling
Series Resistance
Dit
ω
Cx
Gp
Slide No. 56
Interface State Density
Angular Frequency
Oxide and Poly Capacitance
Interface Trap Conductance
Eric M. Vogel June 11-12, 2005
“Electrical Characterization of MOS Devices”
Conductance Parameter Extraction
1. Determine Rs (see previous section).
2. Determine Cox (see previous section).
3. Determine Gt = dIg(Vg)/dVg
4. Measure Cm(F) and Gm(F) for the gate biases
(trap energies) of interest.
5. Correct Cm and Gm for Rs using (see previous
section if inductance is an issue)
2
Cm
CmCc Rs − Gm
ω
Cc =
2
(1 − Gm Rs ) + ω 2Cm2 Rs2 Gc = Gm Rs − 1
6. Correct Gc for tunneling using
Gac = Gc − Gt
Slide No. 57
Eric M. Vogel June 11-12, 2005
“Electrical Characterization of MOS Devices”
Conductance Parameter Extraction
ωC Gac
= 2
ω Gc + ω 2 (C x − Cc )2
Gp
2
x
14
-9
2
Gp/ω (10 S/rad/cm )
7. Determine interface
trap conductance as
function of
frequency for each
gate bias using
16
Vg= -0.60 V
Symbols: Experiment
Lines: Model
12
10
tox = 2.0 nm
-0.55 V
-0.65 V
8
Rs = 20 Ω
-0.70 V
6
4
2
0
102
103
104
Frequency (Hz)
Slide No. 58
-0.80 V
Eric M. Vogel June 11-12, 2005
“Electrical Characterization of MOS Devices”
105
106
Conductance Parameter Extraction
16
14
-9
2
Gp/ω (10 S/rad/cm )
7. Determine the peak
frequency and G
p
associate
ω fp
conductance for
each gate bias.
8. Determine the
conductance at 5fp
or fp/5 for each gate
bias.
Gp
Gp
ω
Slide No. 59
5 fp
ω
Vg= -0.60 V
Symbols: Experiment
Lines: Model
12
10
tox = 2.0 nm
-0.55 V
-0.65 V
8
Rs = 20 Ω
-0.70 V
6
-0.80 V
4
2
0
102
103
104
Frequency (Hz)
fp 5
Eric M. Vogel June 11-12, 2005
“Electrical Characterization of MOS Devices”
105
106
Conductance Parameter Extraction
Gp
ω
Gp
5 fp
ω
fp 5
p
1.0
[<Gp>/ω]/[<Gpp>/ω]f
9. Determine σs using
the following plot
and the previously
determined
0.9
0.8
High (5fp)
0.7
0.6
Low (fp/5)
0.5
0.4
0
1
2
3
σs (in units of kT/q)
Slide No. 60
Eric M. Vogel June 11-12, 2005
“Electrical Characterization of MOS Devices”
4
5
Conductance Parameter Extraction
0.4
fd(σs)
10. Determine fd using
the following plot.
0.3
0.2
0.1
0.0
0
1
2
3
σs (in units of kT/q)
Slide No. 61
Eric M. Vogel June 11-12, 2005
“Electrical Characterization of MOS Devices”
4
5
Conductance Parameter Extraction
2.7
2.6
2.5
11. Determine ξp using
the following plot.
ξp
2.4
2.3
2.2
2.1
2.0
1.9
0
1
2
3
σs (in units of kT/q)
Slide No. 62
Eric M. Vogel June 11-12, 2005
“Electrical Characterization of MOS Devices”
4
5
Conductance Parameter Extraction
7
12. Calculate the
interface state
density and trap
time constant using
Slide No. 63
-1
-2
4
3
Dit (10
⎛ Gp ⎞
−1
Dit = ⎜ ⎟ [ f D (σ s )q ]
⎝ ω ⎠ fp
ζp
1
τp =
=
exp( Vsub
ω p σ p vN a
5
10
cm eV )
6
~2.0 nm RTO
2.0 nm, 20 Ω
2.2 nm, 20 Ω
1.8 nm, 20 Ω
2.0 nm, 10 Ω
2.0 nm, 18 Ω
2.0 nm, 30 Ω
2
1
)
0
-0.35
-0.30
-0.25
Et-Ei (eV)
Eric M. Vogel June 11-12, 2005
“Electrical Characterization of MOS Devices”
-0.20
-0.15
Conductance of Ultra-thin Oxides
1e-7
8e-8
Gp/ω (S/rad/cm2)
• The very large
tunneling currents
associated with ultrathin oxides begins to
affect the conductance
Symbols: Experiment
Lines: Model
tox = 1.4 nm
Rs = 120 Ω
6e-8
Vg = -0.70
4e-8
2e-8
Vg = -0.65
Vg = -0.75
0
1e+3
1e+4
1e+5
Frequency (Hz)
Slide No. 64
Eric M. Vogel June 11-12, 2005
“Electrical Characterization of MOS Devices”
1e+6
Sensitivity of Conductance with Rs
•
The expected
measured conductance
was determined using
modeling for various
values of device
properties.
A smaller change in
expected Gm with Dit
indicates less
sensitivity.
Slide No. 65
2
•
Gm (fp(Gp/ω)) (S/cm )
100
10-1
10-2
Gt = 0
10-3
Rs, τp
10-4
0 Ω, 10-4 s
100 Ω, 10-4 s
-6
0 Ω, 10 s
-6
100 Ω, 10 s
-6
999 Ω, 10 s
10-5
10-6
109
1010
1011
-2
1012
-1
Dit (cm eV )
Eric M. Vogel June 11-12, 2005
“Electrical Characterization of MOS Devices”
1013
Sensitivity of Conductance with Gt
•
A smaller change in
expected Gm with Dit
indicates less
sensitivity.
Slide No. 66
100
2
The expected
measured conductance
was determined using
modeling for various
values of device
properties.
Gm (fp(Gp/ω)) (S/cm )
•
10-1
Rs = 0
10-2
10-3
τ p , Gt
10-4
10-4 s, 0 S/cm2
10-4 s, 10-3 S/cm2
10-6 s, 0 S/cm2
10-6 s, 10-3 S/cm2
10-5
10-6
109
1010
1011
Dit (cm-2eV-1)
Eric M. Vogel June 11-12, 2005
“Electrical Characterization of MOS Devices”
1012
1013
Interface State Time Constant
1013
Dit (cm-2eV-1)
1012
1011
10-3
ZrO2-SiN
10-4
ZrO2-SiOx
10-5
SiO2
Solid Symbols: D it
1010
O pen Symbols: τ
109
-0.30
-0.25
-0.20
-0.15
E - Ei (eV)
Slid