• Flash Converter
– Comparator
– Binary Encoder
• Interpolation
• Folding
A/D
DSP
EECS 247 Lecture 17: Flash and Folding Converters © 2002 B. Boser 1
• Very fast: only 1 clock cycle per conversion
• High complexity:
2 B -1 comparators
• High input capacitance
R
R
R/2
V
REF
R/2
R
R
V
IN
Encoder
Digital
Output
A/D
DSP
EECS 247 Lecture 17: Flash and Folding Converters © 2002 B. Boser 2

f s
V i+
V i-
A v
Latch
A/D
DSP
• Clock rate f s
• Resolution
• Overload Recovery
• Input capacitance (and linearity!)
• Power dissipation
• Common-mode rejection
• Kickback noise
• …
EECS 247 Lecture 17: Flash and Folding Converters
D o+
D o-
© 2002 B. Boser 3
A. Yukawa, “A CMOS 8-Bit High-Speed A/D Converter IC,” JSSC June 1985, pp. 775-9.
A/D
DSP
EECS 247 Lecture 17: Flash and Folding Converters © 2002 B. Boser 4

I. Mehr and L. Singer, “A 500-Msample/s, 6-Bit Nyquist-Rate ADC for Disk-Drive Read-Channel Applications,” JSSC
July 1999, pp. 912-20.
A/D
DSP
EECS 247 Lecture 17: Flash and Folding Converters © 2002 B. Boser 5
I. Mehr and L. Singer, “A 55-mW, 10-bit, 40-Msample/s Nyquist-Rate CMOS ADC,” JSSC March 2000, pp. 318-25.
A/D
DSP
EECS 247 Lecture 17: Flash and Folding Converters © 2002 B. Boser 6

R
R
R/2
V
REF
R/2
R
R
V
IN
Encoder
Digital
Output
• Comparator input:
– Offset
– Nonlinear input capacitance
– Kickback noise (disturbs reference)
– Signal dependent sampling time
• Comparator output:
– Sparkle codes (… 111101000 …)
– Metastability
A/D
DSP
EECS 247 Lecture 17: Flash and Folding Converters © 2002 B. Boser 7
0
0
1
0
1
0
1
0
1
Binary Output (negative)
Correct Output:
0110 … 1000
Actual Output:
1110
A/D
DSP
EECS 247 Lecture 17: Flash and Folding Converters © 2002 B. Boser 8

Binary Output (negative)
1
0
0
0
1
0
1
0
0
0
Protects against a single sparkle.
Ref: C. Mangelsdorf et al, “A 400-MHz Flash Converter with Error Correction,” JSSC February
1990, pp. 997-1002.
A/D
DSP
EECS 247 Lecture 17: Flash and Folding Converters © 2002 B. Boser 9
0
0
X
1
1
1
0
0
1
Binary Output (negative)
Different gates interpret metastable output X differently
Correct Output: 0111 or 1000
Actual Output: 1111
Solutions:
–Latches (high power)
–Gray encoding
Ref: C. Portmann and T. Meng, “Power-Efficient Metastability Error Reduction in CMOS Flash A/D Converters,”
JSSC August 1996, pp. 1132-40.
A/D
DSP
EECS 247 Lecture 17: Flash and Folding Converters © 2002 B. Boser 10

T
1
0
1
1
1
1
1
1
1
1
1
0
0
1
1
1
1
T
2
Thermometer Code
T
3
T
4
T
5
T
6
0
0
0
1
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
0
1
1
1
0
0
0
0
0
0
1
1
T
7
0
0
0
0
0
0
0
1
G
3
0
0
0
0
1
1
1
1
G
1
0
1
1
0
0
1
1
0
Gray
G
2
1
1
0
0
1
1
0
0
1
1
1
1
B
3
0
0
0
0
Binary
B
2
B
1
0
0
1
1
0
1
0
1
0
0
1
1
0
1
0
1
G
1
=
T
1
T
3
+
T
5
T
7
G
2
G
3
=
=
T
2
T
6
T
4
• Each T i affects only one G i
à Avoids disagreement of interpretation by multiple gates
• Protects also against sparkles
• Follow Gray encoder by (latch and) binary encoder
A/D
DSP
EECS 247 Lecture 17: Flash and Folding Converters © 2002 B. Boser 11
A/D
DSP
E.g. 10-bit “straight” flash
– Input range: 0 … 1V
– LSB = ∆ : ~ 1mV
– Comparators: 1023 with offset << LSB
– Input capacitance: 1023 * 100fF = 102pF
– Power: 1023 * 3mW = 3W
Techniques:
– Interpolation
– Folding
– Folding & Interpolation
– Two-step, pipelining
EECS 247 Lecture 17: Flash and Folding Converters © 2002 B. Boser 12

• Idea
– Interpolation between preamp outputs
• Reduces number of preamps
– Reduced input capacitance
– Reduced area, power dissipation
• Same number of latches
• Important “side-benefit”
– Decreased sensitivity to preamp offset
– à improved DNL
A/D
DSP
EECS 247 Lecture 17: Flash and Folding Converters © 2002 B. Boser 13
Vi
Vin
2*Delta
Vref2
1*Delta
Vref1
1
Vin
Preamp2
A2
Preamp1
A1
A/D
DSP
EECS 247 Lecture 17: Flash and Folding Converters
2
Y
© 2002 B. Boser 14

0
-0.1
-0.2
-0.3
-0.4
-0.5
0.5
0.4
0.3
0.2
0.1
0 0.5
1 1.5
Vin /
∆
2 2.5
3
A
1
A
2
Zero crossings (to be detected by latches) at V in
=
V ref1
V ref2
= 1 ∆
= 2 ∆
A/D
DSP
EECS 247 Lecture 17: Flash and Folding Converters © 2002 B. Boser 15
0.6
0.4
0.2
0
-0.2
-0.4
0
0.6
0.4
0.2
0
-0.2
-0.4
0 0.5
0.5
1 1.5
2
A
1
-A
1
A
2
-A
2
2.5
A
1
+A
2
3
1 1.5
Vin /
∆
2 2.5
3
Zero crossings at V in
=
V ref1
V ref12
V ref2
= 1 ∆
= 0.5*(1+2) ∆
= 2 ∆
A/D
DSP
EECS 247 Lecture 17: Flash and Folding Converters © 2002 B. Boser 16

Half as many reference voltages and preamps
A/D
DSP
EECS 247 Lecture 17: Flash and Folding Converters © 2002 B. Boser 17
• Resistors produce additional levels
• With 4 resistors, the
“interpolation factor” M=8
(ratio of latches/pramps)
A/D
DSP
EECS 247 Lecture 17: Flash and Folding Converters
Ref: H. Kimura et al, “A 10-b 300-
MHz Interpolated-Parallel A/D
Convterter,” JSSC April 1993, pp. 438-446.
© 2002 B. Boser 18

• Preamp offset distributed over
M resistively interpolated voltages:
à impact on DNL divided by M
• Latch offset divided by gain of preamp
à use “large” preamp gain …
A/D
DSP
EECS 247 Lecture 17: Flash and Folding Converters © 2002 B. Boser 19
0.6
0.4
0.2
0
-0.2
-0.4
0
0.6
0.4
0.2
0
-0.2
-0.4
0
0.5
0.5
1 1.5
2
1 1.5
Vin /
2
A
1
-A
1
A
2
-A
2
2.5
A
1
+A
2
3
2.5
3
Linear preamp input ranges must overlap i.e. range > ∆
Sets upper bound on gain
<< V
DD
/ ∆
A/D
DSP
EECS 247 Lecture 17: Flash and Folding Converters © 2002 B. Boser 20

Ref: H. Kimura et al, “A 10-b 300-MHz Interpolated-Parallel A/D Convterter,” JSSC
April 1993, pp. 438-446.
A/D
DSP
EECS 247 Lecture 17: Flash and Folding Converters © 2002 B. Boser 21
V
IN
MSB
ADC
Digital
Output
LSB
ADC
Folding Circuit
• Significantly fewer comparators than flash ~2 B/2+1
• Fast
• Nonidealities in folder limit resolution to ~10Bits
A/D
DSP
EECS 247 Lecture 17: Flash and Folding Converters © 2002 B. Boser 22

• Folder maps input to smaller range
• MSB ADC determines which fold input is in
• LSB ADC determines position within fold
• Logic circuit combines
LSB and MSB results
1.2
1
0.8
0.6
0.4
0.2
0
-0.2
0 0.5
1 1.5
2 2.5
3 3.5
4
LSB
ADC
A/D
DSP
EECS 247 Lecture 17: Flash and Folding Converters
Analog Input
MSB ADC
© 2002 B. Boser 23
0.5
0
-0.5
0
0.5
0
-0.5
0
1
0.5
0
0
0.5
0.5
0.5
1 1.5
2
1
1
1.5
2
1.5
2
Vin /
∆
2.5
2.5
2.5
3
3
3
3.5
3.5
4
4
3.5
4
1
0.5
0
0
0.5
0
-0.5
0
0.5
0
-0.5
0
0.5
0.5
0.5
1 1.5
2
1
1
1.5
2
1.5
2
Vin /
∆
2.5
2.5
2.5
3
3
3
3.5
3.5
4
4
3.5
4
A/D
DSP
EECS 247 Lecture 17: Flash and Folding Converters © 2002 B. Boser 24

R1
1kOhm
3 V
Vo1
3 V
R2
1kOhm
Vo2
A/D
DSP
10 / 1
I1 I1
10 / 1 10 / 1
I2 I2 I2 I2 I2 I2 I2 I2
10 / 1
I3 I3 I3 I3 I3 I3 I3 I3 I3 I3 I3 I3 I3 I3 I3 I3 I3 I3 I3 I3 I3 I3 I3 I3 I3 I3 I3 I3 I3 I3 I3 I3
EECS 247 Lecture 17: Flash and Folding Converters
10 / 1
I4 I4 I4 I4 I4 I4 I4 I4 I4 I4 I4 I4 I4 I4 I4 I4 I4 I4 I4 I4 I4 I4 I4 I4 I4 I4 I4 I4 I4 I4 I4 I4 I4 I4 I4 I4 I4 I4 I4 I4 I4 I4 I4 I4 I4 I4 I4 I4 I4 I4 I4 I4 I4 I4 I4 I4 I4 I4 I4 I4 I4 I4 I4 I4
Vin
© 2002 B. Boser 25
0.5
0
Ideal Folder
CMOS Folder
-0.5
0
0.1
0.05
0
-0.05
-0.1
0
0.5
1
0.5
1
1.5
1.5
2
2
Vin /
∆
2.5
2.5
3
3
3.5
4
3.5
4
Accurate only at zero-crossings
Lowdown à
Most folding ADCs do not actually use the folds, but only the zero-crossings!
A/D
DSP
EECS 247 Lecture 17: Flash and Folding Converters © 2002 B. Boser 26

Fine Flash
ADC 4
Folder 4
V ref
+ 3/4 *
∆
Folder 3
V ref
+ 2/4 *
∆
Folder 2
V ref
+ 1/4 * ∆
Folder 1
V ref
+ 0/4 *
∆
Fine Flash
ADC 3
Fine Flash
ADC 2
Fine Flash
ADC 1
Logic
A/D
DSP
EECS 247 Lecture 17: Flash and Folding Converters © 2002 B. Boser 27
0
-0.1
-0.2
-0.3
-0.4
-0.5
0
0.5
0.4
0.3
0.2
0.1
1
4
F1
F2
F3
F4 • 4 Folders
• 8 Zero crossings
• à only 3 LSB bits
• Better resolution
• More folders
à huge complexity
• Interpolation
5 2
Vin /
∆
3
A/D
DSP
EECS 247 Lecture 17: Flash and Folding Converters © 2002 B. Boser 28

Folder 4
V ref
+ 3/4 *
∆
Folder 3
V ref
+ 2/4 *
∆
Folder 2
V ref
+ 1/4 *
∆
Folder 1
V ref
+ 0/4 *
∆
A/D
DSP
EECS 247 Lecture 17: Flash and Folding Converters
Fine
Flash
ADC
Encoder
© 2002 B. Boser 29
0
-0.1
-0.2
-0.3
-0.4
-0.5
0
0.5
0.4
0.3
0.2
0.1
1 2
Vin /
∆
3 4
A/D
DSP
EECS 247 Lecture 17: Flash and Folding Converters
F1
F2
I1
I2
I3
5
0.05
0.04
0.03
0.02
0.01
0
-0.01
-0.02
-0.03
1.45
1.5
1.55
1.6
1.65
Vin /
∆
1.7
1.75
1.8
F1
F2
I1
I2
I3
© 2002 B. Boser 30

0.5
0.4
0.3
0.2
0.1
0
-0.1
-0.2
-0.3
-0.4
-0.5
0 1 2
Vin /
∆
3 4
F1
F2
I1
I2
I3
5
0.06
0.04
0.02
0
-0.02
-0.04
-0.06
1.5
1.6
1.7
Vin /
1.8
∆
1.9
2
F1
F2
I1
I2
I3
2.1
Interpolate only between closely spaced folds to avoid nonlinear distortion
A/D
DSP
EECS 247 Lecture 17: Flash and Folding Converters © 2002 B. Boser 31
A 70-MS/s 110-mW 8-b CMOS Folding and Interpolating A/D Converter
B. Nauta and G. Venes, JSSC Dec 1985, pp. 1302-8
A/D
DSP
EECS 247 Lecture 17: Flash and Folding Converters © 2002 B. Boser 32

A 70-MS/s 110-mW 8-b CMOS Folding and Interpolating A/D Converter
A/D
DSP
EECS 247 Lecture 17: Flash and Folding Converters © 2002 B. Boser 33
A 70-MS/s 110-mW 8-b CMOS Folding and Interpolating A/D Converter
A/D
DSP
EECS 247 Lecture 17: Flash and Folding Converters © 2002 B. Boser 34