Pulse Width Modulation for Current Source Converters – A Detailed Concept
Michael H Bierhoff
Friedrich W Fuchs
Faculty of Engineering
Faculty of Engineering
Christian Albrechts University
24143 Kiel
Germany
mib@tf.uni-kiel.de
Christian Albrechts University
24143 Kiel
Germany
fwf@tf.uni-kiel.de
Abstract – The current source converter represents the dual
counter part to the better known and more frequently used
voltage source converter. As such due to duality rules many offthe-shelf solutions concerning the VSC can be used in a
modified manner to handle the CSC. This work gives a
comprehensive overview of CSC PWM methods and shows how
they are to be distinguished. Then based on duality
considerations a complete recipe is given on how to utilise usual
micro controller peripherals along with some logic elements to
achieve the most significant PWM methods with little effort.
II. LOSS CHARACTERISTICS
A. Conduction Lossess
The conduction losses as dissipated in the semiconductors
are always caused by two valves being simultaneously
conductive. For IGBT converters this means two IGBTs and
two diodes in total which are necessary as the IGBTs lack the
required reverse blocking capability. With the characteristic
curve of the semiconductors’ conduction voltage
approximated by a displaced straight line these losses can be
expressed by (1), [6], [8].
I. INTRODUCTION
Some work has already been published on the exploitation
of VSC PWM schemes for CSC PWM purposes [1]-[4]. It
also could be shown that discontinuous PWM for the VSC
could be modified to attain optimal switching patterns for the
CSC regarding switching losses on the one hand and
harmonic generation on the other hand up to a certain extend
[2], [3]. Furthermore some work on special software has been
published to operate the CSC by utilising such duality rules
[5]. Other articles describe the influence of different PWM
switching sequences on the switching losses of a CSC [6][8].
However all publications that can be found seem to deal
only with a certain scope of this topic. They only describe
either the effect of certain switching sequences on the
switching losses but not the realisation of such PWM pulse
sequence or they do give a recipe on how to generate only a
special bunch of PWM pulse sequences for the CSC.
This paper contributes both the description of different
PWM methods and their influence on the semiconductor
switching losses and the AC current harmonics as well as the
easy realisation of a basic selection of PWM schemes
resulting from such concerns. Finally an advice is given on
how to combine such basic selection of PWM methods to
create a new optimal PWM switching strategy for the CSC.
The structure of this article is as follows. Section II renders
a brief insight on the basic loss behaviour of the CSC
semiconductors. In section III all possible pulse
combinations for the CSC and their influence on the
semiconductor switching losses are discussed. This is
followed by section IV with a short review on how to realise
CSC PWM pulse sequences out of any such signals for the
VSC. Section V contains a new approach in realising CSC
PWM techniques for all relevant pulse sequences which are
fairly simple to implement on standard micro controllers with
only a little logic extension. Instructions on how to combine
such PWM pulse sequences to one new optimal PWM
method for the CSC are given in Section VI which is
followed by the conclusion.
PC = 2 ⋅ i CE ⋅ (v CE , 0 + v F , 0 + i CE ⋅ (rCE + rF ))
(1)
B. Switching Losses
The nature of switching losses of a CSC can be considered
fairly the same as that of a VSC. In a VSC a commutation
cell obviously always contains a switching device and a
diode. In the diode switching losses are basically caused by
reverse recovery currents that are often neglected. In a CSC a
commutation cell contains two IGBTs and a diode [9]. But in
this case the IGBT on which a negative commutation voltage
is imposed on almost behaves like a diode. Only the
switching device with the positive commutation voltage
generates remarkable switching losses by passing through the
active scope of characteristic curves as can be seen in fig. 1.
This means that in case of fig. 1 during each turn on and
off operation voltage and current appear simultaneously only
at IGBT1 causing losses during switching.
Fig. 1. Basic possibilities of commutation cells, the loss
device is always the semiconductor switch that positive
commutation voltage is imposed on
III. PWM TECHNIQUES
Although dualities are utilised to generate a CSC PWM
pulse train there is no such property like the modulation
function to distinguish the PWM methods, like it would be
the case for the VSC. The actual impact of the PWM method
on semiconductor losses is caused by the sequence of the
basic space vectors being switched within one PWM period
[8]. It can be seen by (1) that the conduction losses are not
affected by the manner of switching. The switching losses on
the other hand are influenced by the PWM method as it gives
the opportunity to vary the mean value of commutation
voltage appearing at the switching devices. Of course the
current spectra is also essentially affected by the PWM
method. But low switching losses and good harmonic
behaviour are competing goals. Hence the final aim would be
to achieve a good compromise between both.
However the basic rule of CSC PWM is that always two
devices, one of the upper three and one of the lower three
have to be forward biased simultaneously. To realise a proper
space vector PWM during one PWM period both adjacent
basic space vectors of any sector that the command space
vector passes through as well as a zero space vector have to
be turned on at least once with their corresponding duration.
Thus the minimum of switching operations during one
switching period would amount to three. An exemplary
switching sequence as could be performed within sector I is
shown in fig. 2. The combination of switching devices as
being turned on simultaneously for the different basic and
zero space vectors is shown in fig. 3. All different CSC
PWM pulse sequences with three and four switching
operations with their respective denotations as used here are
listed in table I.
For the case of three switching operations during one
PWM period the switching losses would be approximated by
(2), assuming linear behaviour of the switching losses with
the mean value of commutation voltages and currents. By
regarding an additional switching operation the sequence of
devices being turned on (sequence of space vectors) along
with the phase angle ϕ between AC current and voltage
fundamental at the CSC terminals determine the switching
losses. It is possible at certain phase angles to chose a
switching sequence with four switching operations such that
the mean commutation voltage as it appears at the switching
devices would be of the same amount as for the three step
solution.
Fig. 2. CSC schematic with switching sequence during an
exemplary PWM period
TABLE I
CSC PWM TYPES DISTINGUISHED BY SPACE VECTOR
SEQUENCE
PWM mode
Space Vector
Sequence
Commutation
Voltage
within Sector I
δ
Mod 1
1–2–0
2–1–0
1–0–2
V12, V23, V31
-
Mod 2
1–2–1–0
V12, V23
π/6
Mod 3
2–1–2–0
V23, V31
-π/6
Mod 4
1–0–2–0
V12, V31
π/2
Fig. 3. Basic space vectors with different switch
combinations, projection axes for the magnitude of
commutation voltages
In the upper image of fig. 3 the six basic active space
vectors can be seen. Furthermore a proposition on how to
chose the zero space vectors within the respective sectors IVI for a minimal number of switching operations is given.
The lower image of fig. 3 reveals the projection axes of the
line to line voltage magnitudes |v12| – |v31| within the complex
space vector plain. The projected values as shown for a
special PWM method in fig. 3 correspond to the
instantaneously occurring commutation voltages (only one
per switching operation each). These commutation voltages
concur with the DC bus current Id only at one switch during
commutation. Hence according to their sign they either
produce turn on or turn off losses. The mean value of the sum
of all momentary absolute values of commutation voltages
has to be weighted according to the resulting switching losses
for the evaluation of a PWM. Of course it has to be
multiplied by the number of switching operations itself.
Furthermore it can be divided by two as symmetrical
circumstances can be assumed, that is each switch is exposed
to the same amount of turn on and turn off losses during the
time span of one fundamental period. If the reverse recovery
losses of the series diodes are neglected and by assuming
linear switching loss behaviour equations (2) and (3) can be
found for the semiconductor switching losses of three step
and four step PWM respectively [8]. The four step PWM
itself can be separated into three basic different methods
distinguished only by their space vector sequence
(symmetrical appearance of the space vector portions within
one PWM period is assumed for all the three of them).
PS ,1 = f PWM ⋅
3
π
⋅ (E ON + E OFF ) ⋅
I d vˆ line
⋅
i ref v ref
⎡ 4 8 ∞ cos[k ⋅ (ϕ + δ )]
⎛ k ⋅ π ⎞⎤
PS , 234 = PS ,1 ⋅ ⎢ − ⋅ ∑
⋅ sin ⎜
⎟⎥
2
k =2
3
k
1
k
−
⋅
(
)
π
⎝ 3 ⎠⎦
⎣
fo even k ' s
(2)
(3)
The switching losses for the three different four step PWM
methods that are denoted by indices 2 - 4 can be calculated
by assigning the values π/6, -π/6 and π/2 to δ respectively.
These expressions can be evaluated with the datasheet
information about the turn on and turn off energy EON, EOFF
as they are given with related reference values for the
switched voltages and currents iref, vref. From (2) it can be
seen by numerical evaluation that the switching losses for all
the three four step PWM methods vary between PS,1 and
√3 PS,1 where PS,1 is the switching loss power as rendered by
the three step PWM. In fig. 4 the proportions of switching
losses for the different PWM techniques are shown by a
diagram versus the phase angle.
It is obvious that at least for the cases of phase angles
ϕ = -π/2, -π/6, π6, π/2 where the switching losses of PWM
methods Mod 2 - 4 assume minima, the four step methods
are favourable as they generate the same amount of
semiconductor losses as the three step method Mod 1 at the
benefit of better AC current spectra resulting in less
harmonic content in the filtered AC current [10].
Regarding PWM methods with a higher number of
switching operations per PWM period it can be stated that a
five step PWM would have an asymmetrical appearance of
pulses over one PWM period which yields a poor harmonic
behaviour at the cost of higher switching losses. With the
introduction of a six step PWM the losses given by (2) would
be doubled for any case which would be the same effect if
the PWM frequency would be just doubled [11] (that in turn
would render a better AC current harmonic behaviour again).
Thus all following considerations are focussed on the
realisation of PWM methods Mod 1 - 4.
Fig. 4. Switching losses of the four step PWM methods
Mod 2 - 4 as compared with the ones of the three step
method Mod 1 versus phase angle ϕ
IV. A SIMPLE METHOD TO REALISE CSC PWM PULSE
PATTERNS
Several articles can be found on the realisation of CSC
PWM by using modified VSC PWM pulses [1], [3], [4]. This
constitutes a good method to control the CSC with minimum
effort by using VSC infrastructure as for example micro
controller PWM peripherals usually are developed to support
VSC issues. By taking also discontinuous VSC PWM into
account it is possible to realise all PWM methods already
mentioned apart of one that is Mod 4 [3], [11]. To create zero
space vectors according to fig. 3 the sector number that the
instantaneous command space vector is located in is required
in addition to the six ignition signals delivered from the VSC
PWM unit. The logic scheme of fig. 5 is an example for the
generation of pulses for the switch V1I of the CSC out of the
pulses intended for the VSC switches (denoted with the index
‘V’). The zero space vector creation is compliant to fig. 3.
The VSC pulse scheme that is shown in fig. 6 corresponds to
the well known and commonly applied suboptimal PWM as
already suggested by [12]. Nevertheless this is not the
optimal solution for the CSC as already stated (PWM
frequency could be doubled and with application of Mod 1
comparable switching loss results would be reached).
It should be pointed out that the additional creation of
overlapping times for alternating pulses is compulsory but is
not shown here as the realisation is trivial.
Fig. 5. Logic scheme to modify VSC PWM pulse trains to
CSC pulses
remaining duty cycles D1* and D2* (see table II) which can
be processed to the VSC PWM unit. The resulting pulses d1*
and d2* are fed to a logic circuitry (in this case realised with
an FPGA) along with the sector number to achieve a zero
space vector sequence as shown in fig. 3. A handshake signal
for synchronisation to reduce the probability of oscillations
(the CSC always is connected to any AC load by a CL filter)
may be used as shown in fig. 7. Eventually the pulses d1* and
d2* are processed to six-pulse schemes that control the CSC
devices by a logic that is shown in table III.
B. Peculiarities
The definition of the modulation index differs for the VSC
(MV) and the CSC (MI) (4). To use VSC procedures
calculating the switch duty cycles the modulation index MI
and the angle αt have to be adjusted according to fig 7.
MV =
Fig. 6. CSC PWM pulse train extracted out of
corresponding VSC PWM pulse sequence
V. A UNIFIED METHOD TO REALISE CSC PWM
PULSE PATTERNS
A. Structure
With the logic scheme as described in this section it is
possible to achieve all four types of CSC PWM methods
mentioned above. The procedure to extract the desired CSC
pulses out of a VSC pulse train basically can be separated
into four parts. Usually a command space vector of certain
magnitude and angle has to be processed to corresponding
per phase switching times D1 – D3 of the semiconductor
switches. Then the duty cycles as intended for a VSC are
transformed by an additional logic block to extract two
2 u*
Ud
;
MI =
i*
Id
(4)
Regarding the VSC switching time calculation any
conceivable method would be usable (they only differ by the
weighting of the two different zero space vectors [13]). The
duty cycles D1* and D2* have to be calculated as shown in
table II for each PWM method (Mod 2 - 4) distinctively.
Depending on the PWM type that is demanded they have to
be toggled to the input of the PWM unit. To achieve the
pulse sequences of Mod 2 - 4 the PWM unit has to be
adjusted to symmetrical operation (corresponds to a triangle
carrier signal). By changing the PWM unit operation from
symmetrical to asymmetrical PWM method Mod 1 can be
realised regardless of the method that was determined by the
block ‘Logic I’.
As mentioned earlier the resulting alternating CSC PWM
pulses have to be supplemented by overlapping times to
ensure that during commutation there is always a DC current
path. These overlapping times should be higher than the dead
times that are generated by the PWM unit. Otherwise overvoltages might occur at the semiconductor devices that could
destroy them. For a safe operation the dead time of the PWM
unit should be set to zero.
Fig. 7. Block diagram of the unified CSC PWM creation using VSC PWM resources
TABLE II
CALCULATION OF DUTY CYCLES D1* AND D2*
PWM
type
D1*
Duty Cycle
D2*
2
(D1–D2)(sec=6) +
(D1–D3)(sec=1) +
(D2–D3)(sec=2) +
(D2–D1)(sec=3) +
(D3–D1)(sec=4) +
(D3–D1)(sec=5)
(D1–D3)(sec=6) +
(D2–D3)(sec=1) +
(D2–D1)(sec=2) +
(D3–D1)(sec=3) +
(D3–D2)(sec=4) +
(D1–D2)(sec=5)
3
(D1-D2)(sec=6) +
(D1–D3)(sec=1) +
(D2–D3)(sec=2) +
(D2–D1)(sec=3) +
(D3–D1)(sec=4) +
(D3–D1)(sec=5)
(D3–D2)(sec=6) +
(D1–D2)(sec=1) +
(D1–D3)(sec=2) +
(D2–D3)(sec=3) +
(D2–D1)(sec=4) +
(D3–D1)(sec=5)
4
(D3–D2)(sec=6) +
(D2–D3)(sec=1) +
(D1–D3)(sec=2) +
(D3–D1)(sec=3) +
(D2–D1)(sec=4) +
(D1–D2)(sec=5)
(D3–D1)(sec=6) +
(D2–D1)(sec=1) +
(D1–D2)(sec=2) +
(D3–D2)(sec=3) +
(D2–D3)(sec=4) +
(D1–D3)(sec=5)+1
TABLE III
CALCULATION OF PULSES FOR THE SWITCHES V1I – V6I
Switch
Mod 2
PWM type
Mod 3
Mod 4
IV. A NOVEL APPROACH TO AN OPTIMAL CSC PWM
SCHEME
From fig. 4 the suspicion arises that it should be possible
(at least for a restricted scope of operation) to adjust the
PWM in such a way that always a four step method with
reduced switching losses would be active. The amount of
losses should converge against that what a three step method
would render. Eq. (3) results out of a fourier analysis as
applied on the mean value of the sum of always two line to
line voltages which appear as commutation voltages for each
PWM method Mod 2 – 4. This term can be explicitly written
as (5) where the absolute values of commutation voltages can
be seen within the integral terms. If now an optimal toggling
between methods Mod 2 – 4 according to table IV (αt’ refers
to the angle of command space vector within one sector that
spans a range of 0...π/3) is achieved a switching loss
behaviour close to that of a three step PWM can be
established. A linear loss behaviour with commutation
voltage provided, this can be proved by numerical solution of
(6). With this new PWM method the merits of all the CSC
PWM methods as mentioned before are combined in one. It
exhibits the same switching losses as a three step scheme at
the favourable harmonic behaviour of a four step method.
This means that the spectral lines of the switched AC current
are shifted to higher frequencies as compared to the three
step method which leads to a lower distortion current behind
the passive AC filter [10].
TABLE IV
TOGGLING OF PWM MODES CORRESPONDING TO ϕ
ϕ
V1I
(sec = 1) ∧ (d1 ∧ d 2) ∨
(sec = 1) ∧ d 2 ∨
(sec = 1) ∧ d 2 ∨
(sec = 3) ∧ d1 ∨
(sec = 3) ∧ d1 ∨
(sec = 5) ∧ d 2 ∨
(sec = 5) ∧ ( d1 ∧ d 2) ∨
(sec = 6)
(sec = 3) ∧ ( d1 ∧ d 2) ∨
(sec = 5) ∧ d1 ∨
(sec = 6)
(sec = 6)
V2I
V3I
V4I
V5I
V6I
(sec = 4) ∧ ( d1 ∧ d 2) ∨
(sec = 3)
(sec = 4) ∧ d 2 ∨
(sec = 2) ∧ d 2 ∨
(sec = 3)
(sec = 4) ∧ d1 ∨
(sec = 6) ∧ d1
(sec = 6) ∧ d1
(sec = 6) ∧ (d1 ∧ d 2)
(sec = 3) ∧ ( d1 ∧ d 2) ∨
(sec = 4) ∧ (d1 ∧ d 2) ∨
(sec = 5) ∧ d1 ∨
(sec = 1) ∧ d 2 ∨
(sec = 2)
(sec = 5)
(sec = 6) ∧ d 2 ∨
(sec = 4) ∧ d 2 ∨
(sec = 5)
(sec = 2) ∧ d1
(sec = 2) ∧ (d1 ∧ d 2)
(sec = 4) ∧ d 2 ∨
(sec = 5)
(sec = 4) ∧ (d1 ∧ d 2) ∨
(sec = 5)
(sec = 6) ∧ d 2 ∨
(sec = 4) ∧ d 2 ∨
(sec = 5)
(sec = 6) ∧ d1 ∨
(sec = 2) ∧ (d1 ∧ d 2)
(sec = 2) ∧ d 2 ∨
(sec = 3)
(sec = 6) ∧ ( d1 ∧ d 2) ∨
(sec = 2) ∧ (d1 ∧ d 2) ∨
(sec = 2) ∧ d1
(sec = 2) ∧ d1
(sec = 5) ∧ d 2 ∨
(sec = 5) ∧ d 2 ∨
(sec = 1) ∧ d1 ∨
(sec = 3) ∧ d 2 ∨
(sec = 4)
(sec = 1) ∧ d1 ∨
(sec = 1) ∧ (d1 ∧ d 2) ∨
(sec = 3) ∧ (d1 ∧ d 2) ∨
(sec = 4)
(sec = 3) ∧ d1 ∨
(sec = 6) ∧ (d1 ∧ d 2) ∨
(sec = 6) ∧ d 2 ∨
(sec = 1)
(sec = 6) ∧ d 2 ∨
(sec = 1)
(sec = 2) ∧ ( d1 ∧ d 2) ∨
(sec = 1)
(sec = 2) ∧ d 2 ∨
(sec = 4) ∧ d1
(sec = 4) ∧ d1
(sec = 4)
(sec = 2) ∧ d1 ∨
(sec = 4) ∧ (d1 ∧ d 2)
PWM mode
0...|ϕ| + π/6
Mod 4
|ϕ| + π/6...π/3
Mod 3
0...π/6 + ϕ
Mod 3
π/6 + ϕ...π/3
Mod 2
0...ϕ - π/6
Mod 2
ϕ - π/6...π/3
Mod 4
-π/2...-π/6
-π/6...π/6
(sec = 6) ∧ d1 ∨
(sec = 5) ∧ (d1 ∧ d 2) ∨
αt’
π/6...π/2
π
PS ,Mod 2
1 6
=
⋅ ∫ ( v12 (ωt , ϕ ) + v23 (ωt , ϕ ) )dωt
PS ,1
vline − π
6
π
PS ,Mod 3
1 6
=
⋅ ∫ ( v23 (ωt , ϕ ) + v31 (ωt , ϕ ) )dωt
PS ,1
vline − π
6
π
PS ,Mod 4
1 6
=
⋅ ∫ ( v12 (ωt , ϕ ) + v31 (ωt , ϕ ) )dωt
PS ,1
vline − π
6
(5)
PS ,opt
PS ,1
⎧−⎛⎜⎝ ϕ + π3 ⎞⎟⎠
⎪ ( v (ωt , ϕ ) + v (ωt , ϕ ) )dωt +
31
⎪ ∫π 12
⎪ −6
⎪ π
π
π
⎪ 6
⎪ ⎛ ∫ π ⎞ ( v23 (ωt , ϕ ) + v31 (ωt , ϕ ) )dωt for − 2 ≤ ϕ < − 6
⎪−⎜⎝ ϕ + 3 ⎟⎠
⎪ −ϕ
⎪ ( v (ωt , ϕ ) + v (ωt , ϕ ) )dωt +
(6)
31
⎪ ∫π 23
1 ⎪− 6
=
⋅⎨
=1
vˆline ⎪ π6
π
π
for − ≤ ϕ <
⎪ ∫ ( v23 (ωt , ϕ ) + v12 (ωt , ϕ ) )dωt
6
6
⎪−ϕ
⎪−⎛⎜ ϕ − π ⎞⎟
⎪ ⎝ 3⎠
⎪ ∫π ( v23 (ωt , ϕ ) + v12 (ωt , ϕ ) )dωt +
⎪ −6
⎪ π
⎪ 6
π
π
⎪ ∫ ( v12 (ωt , ϕ ) + v31 (ωt , ϕ ) )dωt for ≤ ϕ ≤
6
2
π
⎛
⎞
⎪ −⎜ ϕ − ⎟
⎩ ⎝ 3⎠
CONCLUSION
An extensive analysis on PWM solutions for a CSC and
their facilitated realisation is provided by this article.
Thereby the impact of different switching sequences on the
semiconductor losses is derived which leads to the
recommendation of different PWM schemes depending on
the kind of operation. It is shown how to use modified offthe-shelf VSC PWM solutions with some extra logic
circuitry to operate a CSC with the derived PWM methods.
All PWM methods Mod 1 - 4 have successfully been set
into operation to control an experimental CSC laboratory test
set up. This was realised by using both methods which utilise
modified VSC PWM trains as described in sections IV and
V. A dSpace DSP-board was used to create the VSC PWM
pulses with the on board TMS 320. The logic circuitry to
process the PWM pulses coming from the micro controller
was programmed on a Spartan III evaluation board.
Furthermore based on the provided analysis a new optimal
PWM method as a combination of the PWM schemes Mod 2
– 4 has been developed. This novel optimal PWM type
possesses both advantages the low loss behaviour of a three
step scheme at all kinds of operation points and thereby the
good harmonic performance of a four step PWM.
Measurement results regarding the semiconductor losses
for all the different PWM methods will be delivered in future
works as the assembly of a calorimetric measurement set up
is in progress.
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