DesignCon 2007
PCB Design Methods for Optimum
FPGA SerDes Jitter Performance
Steve Weir, Teraspeed Consulting Group
steve@teraspeed.com (866) 675-4630
Scott McMorrow, Teraspeed Consulting Group
scott@teraspeed.com (401) 284-1827
Al Neves, Teraspeed Consulting Group
al@teraspeed.com (503) 430-1065
Tom Dagostino, Teraspeed Consulting Group
tom@teraspeed.com (503) 430-1065
Brian Vicich, Samtec, Inc.
Brian.vicich@samtec.com (812) 944-6733
Abstract
Designing a PCB to obtain minimum SerDes jitter is critical to maximizing high-speed serial link
bandwidth and reliability. The PCB power distribution methodology has a strong impact on SerDes
performance. However, optimization for one impairment often comes at the cost of another.
Considerable debate remains over which effects dominate and how to reliably yield quality designs.
Using carefully designed test vehicles, we characterize Virtex 4™ SerDes sensitivity to specific PCB
impairments and physical PCB design tradeoffs. We reconcile current debate on best practices and offer
a detailed design methodology.
Author(s) Biography
Scott McMorrow, President, Teraspeed Consulting Group LLC- Mr. McMorrow is an experienced
technologist with over 20 years of broad background in complex system design, interconnect & Signal
Integrity engineering, modeling & measurement methodology, engineering team building and
professional training. Mr. McMorrow has a consistent history of delivering and managing technical
consultation that enables clients to manufacture systems with state-of-the-art performance, enhanced
design margins, lower cost, and reduced risk. Mr. McMorrow is a expert consultant and trainer in highperformance design and Signal Integrity engineering recognized worldwide.
Alfred P. Neves, Senior Staff Signal Integrity Engineer, Teraspeed Consulting Group LLC. Mr. Al
Neves has numerous years experience working in design and applications for semiconductor, capital
equipment, and signal integrity software companies. He expertise includes design of low jitter systems,
measurement based modeling and communication system simulation methodology development.
Tom Dagostino, Vice President Modeling, Teraspeed Consulting Group LLC - Tom Dagostino currently
manages and models in the Teraspeed Consulting Group LLC's Device Characterization Division. Mr.
Dagostino has over 9 years experience in Signal Integrity modeling, previously with Zeelan
Technologies and Mentor Graphics. Prior assignments have included over 18 years with Tektronix
program managing, designing and performing market research on Digital Storage Oscilloscopes, real
time oscilloscopes, probes and technology. Mr. Dagostino holds 10 Patents relating to DSO technologies
and product features.
Brian Vicich, Advanced Design Group Engineering Manager, Samtec, Inc. - Brian Vicich currently
manages Research and Development and Advanced Connector Product Design, Signal Integrity Group,
and High Data Rate Cable Groups for Samtec (New Albany, IN). Mr. Vicich has over 10 years of
electro-mechanical design experience. Mr. Vicich was previously employed by Molex, Grayhill, and
the American Electric Cordsets, and he holds four sole inventor patents and is secondary inventor on
another three patents.
Steve Weir, Member Technical Staff, Teraspeed Consulting Group
Steve is an independent consultant with over 20 years plus industry experience with a broad range of
expertise. Steve holds 17 US patents, and has architected a number of TDM and packet based switching
products, consults on patents and is a frequent contributor to the SI-list signal integrity reflector.
FPGA SerDes Design Challenge
For several years FPGAs have incorporated Serializer / Deserializers SerDes devices supporting at least
3.125Gbps operation and sometimes beyond. Currently families include:
• Altera Stratix II GX up to 6.375Gbps –3 speed grade[1]
• Xilinx Virtex 4™ FX up to 6.5Gpbs –12 speed grade[2]
Next generation devices from: Altera- Stratix III GX, Lattice- SC and Xilinx- Virtex 5 FX and will enter
the market this year.
SerDes impose new design challenges that are often foreign to digital engineers. Many of these
challenges occur in the channel design. Gbps serial channel design is similar for ASICs and FPGAs
alike and many excellent works have been published on the subject.
Power delivery however is peculiar to individual IC implementations. Whereas for an entirely digital
device +/-5% and often +/-10% rail noise over a broad spectrum does not present a serious problem,
such noise levels can readily cripple SerDes operation. For this reason, FPGA manufacturers have been
careful to publish power design guidelines, some in the form of rigid recipes.
The recipes are in ways both incomplete and contain also elements that are subject to considerable
debate. Some industry experts have assailed some of these guidelines as either unneccesary or even
worse counterproductive. The current information gaps and requirements uncertainty serve neither users
nor FPGA manufacturers.
In 2006, Samtec Inc andTeraspeed Consulting Group undertook to research actual device requirements.
This paper reports our findings as they relate to transmit jitter in Xilinx Virtex 4™ FX parts. Based on
our research, we believe that these findings will prove consistent on Virtex 5, as well as the Altera
Stratix II and Stratix III parts scheduled for testing later in 2007.
Virtex 4™ Rocket I/O Transmitter ( MGT )
In the Virtex 4™ product line, Xilinx alternately refers to their SerDes offerings as RocketI/Os™ or
Multi-Gigabit Transceivers, MGTs. These devices support up to 3.125Gpbs operation in all speed
grades and up to 6.5Gpbs operation in the fastest speed grade –12[2]. A single FPGA may contain from
eight to twenty-four transceivers arranged in four to twelve tiles of two transceivers each. Each tile
includes eight separate power supply inputs:
Supply
AVCCAUXMGT
AVCCAUXRXA
AVCCAUXRXB
AVCCAUXTX
VTRXA
VTRXB
VTTXA
VTTXB
Function
PLLs
Tile A side receiver
Tile A side receiver
Tile transmitters
Tile A side receive termination
Tile B side receive termination
Tile A side transmit termination
Tile B side transmit termination
Nominal Voltage
2.5V
1.2V
1.2V
1.2V
1.5V
1.5V
1.5V
1.5V
Table 1, MGT Supply Voltages1
Max Current @ 3.125Gbps
5mA
191mA
191mA
307mA
24mA
24mA
105mA
105mA
As an example of the importance of clean SerDes power, Xilinx bluntly states that to receive factory
support, customer designs must conform to each aspect of the stated power design requirements[3]
contained in publication “Virtex-4 RocketIO Multi-Gigabit Transceiver User Guide” UG076 3.0, May
23, 2006, Chapter 6.
•
•
•
•
Linear voltage regulators for each of the at least three MGT voltages:
o AVCCAUXMGT
2.5V nominal
o AVCCAUXRX/TX
1.2V nominal
o VTRX/TX
1.5V nominal
Separate series decoupling filters for each MGT power pin.
o Series ferrite bead TDK MPZ1608S221A
o Shunt bypass capacitor generic 0402 220nF
A specific capacitor bank at both the input and output of each linear regulator:
o 10uF capacitor input,
o 1ea 330uF, 8ea 1uF capacitors output
None of the five analog rails per MGT tile may be shared with digital devices.
The stated goal behind for all of these measures is to supply pristine power to the sensitive analog power
supplies that support the SerDes.
MGT PDN PCB Reference Model
We examine a model of the resulting PDN to determine how it may perform against the stated goals:
Figure 1, Model Xilinx MGT Analog Power Distribution
The model includes three noise sources:
• Intermediate supply rail noise. This is typically the output of a switching power supply
providing 3.3V – 5V input to a low drop-out linear regulator.
• Plane to plane noise coupling. When the stack-up does not insert a shield layer between fill /
plane used by the MGT power distribution, noise from aggressor signals and/or other power
planes couples to the MGT power fill / plane.
• Z axis coupling. Single ended signals adjacent to MGT pads couple through adjacent vias / balls
in the PCB and the FPGA package.
Working against these noise sources are: the linear voltage regulator, bypass capacitors, series
decoupling filters, and finally the low pass filter in the MGT power node of the FPGA itself.
Linear Regulator Ripple Rejection
Even high quality modern linear regulators such as Linear Technology LT1764xx , LT1963xx or similar
exhibit very limited ripple rejection above 100kHz by themselves. Figure 2 replots data sheet ripple
rejection as insertion loss.
Figure 2, Ripple Rejection Linear Regulator
From Figure 2 we can see noise rejection from the regulator feedback loop drops off rapidly from 2kHz
to a projected 0dB intercept near 100kHz. Beyond about 50kHz the regulator series parasitics loaded by
the output bypass capacitor network provide most of the attenuation. Noise feedthrough above 1MHz
depends on layout and bypass network ESL.
Series Ferrite Decoupling Networks
Series ferrite decoupling networks can provide additional loss up to 1GHz. However, unless applied
carefully, ferrite beads can offer unwelcome surprises. At low frequencies ferrites are low loss magnetic
materials. They make excellent high Q inductors. When mated with high Q capacitors, such as ordinary
ceramic bypass capacitors the combination creates a low pass filter with high peaking at FCUT-OFF. If we
wish to use avoid amplifying noise voltage at resonance we have three choices:
•
•
•
Set the filter cut-off frequency to occur at or above the frequency at which the bead Q falls to
approximately 1, ( 25MHz for the MPZ1608221A ).
Add shunt or series damping to drop overall filter Q.
Add enough series loss by other means to compensate resonant peaking.
Figure 3, Z11 TDK MPZ1608221A Ferrite[3]
FCUT-OFF of the low pass network stipulated by Xilinx: MPZ1608221A with a 220nF capacitor occurs
close to 300kHz. 300kHz is a very popular operating frequency for current generation SMPS modules.
The following simulation demonstrates response of the specified filter network to a 300kHz 60mV p-p
sawtooth at the filter input and a 500 Ohm load comparable to the AVCCAUXMGT load of a single
MGT tile.
Figure 4, Transient Simulation, 300kHz SMPS, MPZ1608221A + 220nF
A high quality linear regulator does not damp the filter resonance. It adds enough insertion loss so that
the net insertion loss at FCUT-OFF is positive. Figure 5 illustrates composite frequency response of the
linear regulator based PDN recommended by Xilinx. Beyond the sharp resonance at 300kHz insertion
loss recovers quickly, strongly rejecting noise from less than 1MHz to well over 100MHz. The filter
can be effective against two noise sources:
•
•
High frequency SMPS ringing.
When present noise coupled from another adjacent copper fill layer, or adjacent aggressor
signals.
Properly chosen ferrite beads really shine suppressing high frequency SMPS ringing. It is easy to obtain
more than 30dB insertion loss out to 250MHz or more, reducing even 100mV high frequency ringing to
3mV pp or less.
Figure 5, Ripple Rejection, MGT Linear Supply Plus MPZ1608221A and 220nF
Digital noise coupling depends on the PCB stack-up and routing strategy. Each MGT requires a
minimum of three voltages:
•
•
•
AVCCMGTAUX, 2.5V,
VTRX, typically 1.5V,
AVCCAUXRX, AVCCAUXTX 1.2V.
For FX60 and larger devices all three voltages encircle the package. This dictates use of at least two
PCB layers for MGT power. See Figure 7. A strategy that minimizes bypass capacitor attachment
inductance places MGT power on outer layers. The MGT power may be shielded by assigning GND to
the next layer in on the PCB. The downside of this arrangement is that either signal routing references
VCCINT / VCCAUX on one layer creating a return path continuity issue, or additional GND layers
must be added to the stack-up. Without GND shield layers, the adjacent power layers capacitively
couple directly into the MGT power. Ferrite beads can attenuate this noise.
An alternate strategy is to place MGT power distribution on inner layers. Absent sandwiching each
MGT plane shape between GND shields, noise for any other adjacent layers couples into the MGT
power. Here again, ferrite beads may be used to suppress this noise. We can determine the amount of
noise coupled from tools such as Si-Wave™. What we do not have is a specification of tolerable noise
from Xilinx.
Figure 6 depicts three alternative stack-ups each with MGT power on the outer layers. Only the first
configuration benefits from a series decoupling filter. In each of the latter two configurations a GND
layer shields MGT plane shapes from digital noise pick-up.
Each of these stack-ups suffers drawbacks. The 20 layer design adds the expense of two additional
layers. The first configuration couples noise from both the core and VCCIO into MGTs. Several
hundred pF coupling capacitance is easily obtained. The center configuration protects MGT power at
the expense of complicating digital signal return paths. Aside from board level decoupling, VCCINT
and VCCAUX have little to do with I/O signal transmission.
Figure 6, Stack-up Alternatives, Eight Signal Layers
Z Axis Cross-talk
The ferrite series-decoupling filter is to the left of the third noise source: cross talk from digital I/O
aggressors that couple through the PCB and device package Z axis. Refer to Figure 7.
Figure 7, MGT I/O Map, Xilinx Virtex 4™ FX 1152 Package
The total Z axis path through a typical telecom board and the package is well over 150mils. This proves
long enough to couple enough signal energy to affect MGT jitter performance even with the modest rise
and fall times of Virtex 4™ digital I/Os.
Jitter Evaluation Test Vehicle
We evaluated PCB related jitter sources with a test vehicle that facilitates comparison of the following
design choices and signal effects:
•
•
•
Analog Vcc power supply architecture.
Aggressor signal coupling.
IC package ground bounce
Each vehicle consists of two similarly designed halves designated A and B.
Figure 8, Jitter Evaluation Test Vehicle
Figure 9, Structure, PDN, Jitter Evaluation Test Vehicle
A Side
The A side serves primarily as a reference for the mandated Xilinx networks. The A Side fully
implements the Xilinx MGT power guidelines. The MGT 2.5V and 1.2V rails may source from linear
regulators or from VCCAUX, and VCCINT respectively. Additionally, overdamped 10kHz low pass
filters composed of a single ferrite bead and 3528 size tantalum capacitor, may be switched into each
MGT analog supply. The layout connects AGND BGA pads to PCB GND on all layers.
B Side
The B side eliminates the per power pin series ferrites in favor of direct plane connections. Instead of
one capacitor per MGT power pin, one bypass capacitor on each side of the device bypasses each of the
three analog MGT rails. Finally, the B side mounts the FPGA on a prototype power interposer assembly
from Samtec. As with the A Side, the B Side includes provisions for powering MGT circuitry from
either linear regulators or SMPS regulators that supply the FPGA digital sections. Here we report
results using the SMPS regulators for the 1.2V and 2.5V rails.
Figure 10, Jitter Evaluation PCB, FPGA Backside Detail
Jitter Evaluation Tests
We conducted jitter evaluation tests by configuring both transceivers on one MGT tile for operation at
3.125Gbps using 8b/10b encoding. Our test pattern consisted of PRBS9 for 254 symbol periods
followed by a comma pattern for two symbol periods. We configured digital I/Os to operate at 533Mbps
driving a common PRBS5 pattern. We configured all active I/Os as SSTLII-1.8V Class 2 ( DDR2 ).
Test Results Xilinx Guidelines Based Design
Following the Xilinx guidelines, combined with high quality linear regulators and a careful layout we
obtained very good results at 3.125Gbps-
Figure 11, Jitter Xilinx Guidelines, Optimum PCB
The left side of Figure 10 shows the transmit data eye with no digital I/Os enabled. Jitter for this case is
just 37ps, 11.6% of the 320ps Unit Interval, UI. The right hand capture shows results with all digital
I/Os except those in rows C and AM, and columns 3 and 32 simultaneous switching. Despite a 16A pp
total I/O return current jitter increases by just 1ps to 38ps. The Virtex 4™ package does a good job of
blocking digital return currents from traversing the MGT analog domains.
We may reasonably conclude from this that package GND bounce and any related coupling between
AGND and GND through the IC package is not a problem. Therefore FPGA AGND pads should tie
directly to PCB digital GND.
We evaluated Z axis cross-talk by separately enabling digital aggressors in columns 3/32, and rows
C/AM as seen in Figure 12:
Figure 12, Jitter Evaluation Z Axis Crosstalk
Here we see that jitter increases to 40ps pp. While this remains very small, a minor caution is in order:
These tests drive from the FPGA. Virtex 4™ I/Os have relatively modest transition rates. Memory
devices have transition times 4-6 times faster. Commensurately higher cross talk and jitter should be
expected if memory read data connects to FPGA pins adjacent to MGT pins than recorded here.
Powering SerDes Analog from SMPS
We configured the A-Side to power AVCCAUXRX, and AVCCAUXTX supplies from VCCINT. We
tested both with and without first passing VCCINT through an overdamped noise filter with FCO at
10kHz. Transmit jitter performance degrades, but not critically as seen in Figure 13:
Figure 13, Ferrite Decoupling, AVCCAUXRX, AVCCAUXTX, 1.2V from VCCINT SMPS
Transmit jitter increases to 50ps pp with all digital I/Os switching, including those adjacent the MGT
pins.
AVCCMGTAUX is an entirely different story. This node proves highly sensitive to noise over a wide
spectrum. We first tested with just the original mandated networks. With this configuration jitter
balloons to an unacceptable110ps pp.
Figure 14, Transmit Jitter AVCCAUXRX/TX from AVCCINT, AVCCAUXMGT from VCCAUX
Results improve markedly when we passed VCCAUX through a 10kHz FCO filter as shown in Figure
15:
Figure 15, Transmit Jitter w/ 10kHz LPF in AVCCAUXRX/TX, AVCCAUXMGT
Test Results B Side with Samtec PowerPoser™
The B Side replaces 128 discrete components: 64 ferrites and 64 bypass capacitors with 12 0402 bypass
caps. AVCCAUXRX and AVCCAUXTX source from the SMPS fed 1.2V VCCINT core power
supply, while AVCCAUXMGT obtains 2.5V from FPGA VCCAUX also through a 10kHz low-pass
filter. Resulting jitter is very good. With no outputs switching, or all outputs switching except for the Z
axis aggressors, jitter is 46ps pp. With all digital outputs switching including the Z axis aggressors in
rows C/AM, and columns 3/32 jitter is 50ps pp. A modest improvement in signal ripple is observable
compared to the A side.
Figure 16, B-Side Sourced from VCCINT, VCCAUX
Figure 17, B-Side Sourced from VCCINT, VCCAUX
As with th A-Side, forcing all outputs adjacent to the MGT pins to drive output ‘0’ has essentially the
same effect as leaving those aggressors tri-stated.
Summary
While quantification of hard power supply specifications remains elusive, given careful PDN design,
PCB stack-up and layoutVirtex 4 FX SerDes are capable of low jitter transmit operation. When
implemented with care, the Xilinx design guidelines yield clean, low jitter signaling. These guidelines
include mandatory use of ferrites which we show do help in some circumstances and are unnecessary in
others.
The Virtex 4 package does a good job of isolating MGT circuitry from core and digital I/O ground
bounce. From no digital I/Os switching to all I/Os switching ( exclusive of Z axis aggressors ) jitter
increases only about 1ps pp. Z axis aggressors adjacent to MGT signal pins impart from 2 to 4ps jitter
when simultaneously driven by the FPGA. When driven by faster chips on the user PCB we expect
greater coupling efficiency and higher jitter.
By far the greatest transmit jitter sensitivity in the Virtex 4 is predictably the AVCCAUXMGT power
rail. This rail powers the PLLs and must be kept clean. We have demonstrated that with very simple
10kHz board level filters and the Samtec PowerPoser™ very good jitter performance is obtained even
when sharing switching power supplies with the FPGA core and providing minimal application PCB
decoupling.
Conclusions
•
•
•
•
Xilinx Virtex 4 FX power delivery guidelines when combined with best PCB practices yield low
transmit jitter.
The series decoupling network per pin requirement imposed by Xilinx guidelines benefits only
certain circumstances.
The Samtec PowerPoser™ relieves application PCB of best practice requirements enabling
elimination of over a hundred components and multiple linear regulators.
While IC manufacturers work hard to provide usable design guidelines, users interested in
optimum cost and performance need vendors to express power delivery requirements as tolerable
external noise amplitude and PDN network impedance versus frequency.
References
1.
2.
3.
4.
“Stratix II GX Device Handbook, Volume 1” Altera Corp, February 2006
DS302, “Virtex-4 Data Sheet: DC and Switching Characteristics” Xilinx, June 23, 2006
UG-076, “Virtex-4 RocketIO MGT User Guide” Xilinx, May 23, 2006
E9415-MMZ, “Chip Beads (SMD) for Signal Line”, TDK Corp, June 6, 2006.