Protecting MOSFETs
Against Overcurrent Events
By Todd Kazmirski, President, IsoSense, Cave Creek, Ariz.
While response time is a key metric of overcurrent
protection effectiveness, it must be translated
into peak MOSFET current and power loss to
provide a true measure of robustness.
P
rotecting power transistors against overcurrent
failure has always been a challenging issue
in power circuit design. In order to protect
against even the most potentially destructive
overcurrent events, it is critical to quickly
initiate a shutdown of a power transistor. While fast
response time in overcurrent protection circuits is generally
considered optimal, the implications on reliability are neither
broadly understood nor readily quantified within the power
electronics design industry. For example, most designers
would agree a protection circuit that has a response time of
3 µs instead of 5 µs improves the protection quality. But, the
improvement is difficult to quantify in an objective measure
of design margin or in terms of any characteristic besides
response time.
td
On-OCD
On-OCL
Avalanche
Turn
Tu
rn On
Transistor Current
On
tf
tl
Turn Off
tr
slowing the response time. As always, size and cost are also
important considerations. A sensing technique with marginal
performance is often substituted to provide a faster solution
to meet cost and size constraints, and provide the correct
perceived value for the application.
The issue of response time for power MOSFET protection
is particularly relevant in many power supply applications
and can be addressed in various ways. One technique
proposed here achieves fast response time while meeting cost
and size constraints. To study the MOSFET losses during an
overcurrent event, a simple model for a current waveform
can be applied. This model provides a straightforward means
to determine the impact of response time on MOSFET loss
components and, in turn, the ability to characterize the
benefits of faster response time in design margin terms of
transistor losses and peak operating current.
The protection technique proposed here is included in
a test circuit. The circuit has a MOSFET switching into a
short circuit producing fast-rising overcurrent events. The
protection scheme uses a small, integrated, overcurrent
detector (OCD) to provide a fast-acting, noise-immune
overcurrent signal. This signal ensures fast MOSFET
shutdown and robust protection. The circuit, which allows
the protection response time to be varied, will be used to
examine transistor waveforms for different response times.
Many of the concepts relating to the protection of power
MOSFETs can be applied to other power transistor types such
as IGBTs. Understanding overcurrent protection in general
provides designers with a tool to quantify the margin in
their protection schemes, and in the end improves design
reliability for all power transistor applications.
Shutdown Initiated
Overcurrent Detected
Overcurrent
Over
current Limit
t1
t2
t3
t4 t5
t6
Time
Fig. 1. The model for an overcurrent event waveform defines six distinct
periods of the waveform.
Even when fast response time becomes the design focus
of the protection scheme, the objective is not easy to meet.
When an analog current-sensing technique is employed, the
signal must be converted into a digital overcurrent signal.
While this is straightforward, the conversion can easily be
corrupted by noise in a power-switching environment.
Filtering solves this problem but has a negative impact of
Power Electronics Technology January 2006
Waveform Model
The model for an overcurrent waveform is shown in
Fig. 1. This waveform is divided into six periods based on
the state of operation of the MOSFET, the drain current
14
www.powerelectronics.com
PROTECTING MOSFETS
Equations for
a l l s i x p er i o d s
Drain-to-source voltage ramps down
were developed
Turn On
MOSFET transitioning from off state
from Vt to It ¥ RDS ( ON
ON ) .Drain current
using this same
through
linear
region
to
saturation
region.
(t0 < t < t1)
ramps up from zero to It .
process. This set
of equations was
MOSFET
operating
in
saturation
region.
On
Current rising at a fixed rate. Voltage
then added to a
Drain current hits limit at end of period, but
equal to ID(t) x RDS(ON).
(t1 < t < t2)
overcurrent not detected.
spreadsheet.[1]
To fully specify
MOSFET operating in saturation region.
On-OCL
Current rising at a fixed rate. Voltage
Current over limit throughout period, but
t
h
e
equations,
equal to ID(t) x RDS(ON).
(t2 < t < t3)
overcurrent not detected until end of period.
values for t i , k i ,
I ti a n d Vti m u s t
MOSFET operating in saturation region,
but logic and gate-drive transitioning to
b
e specified
On-OCD
Current rising at a fixed rate. Voltage
start discharging Miller capacitance at end
o
r
calculated.
equal
to
I
(t)
x
R
.
(t3 < t < t4)
D
DS(ON)
of period. Current over limit and detected
Specification is
throughout period.
based on either
circuit operating
Turn Off
MOSFET transitioning from saturation
Voltage rises at a fixed rate to VBRdss.
conditions—
region through linear region to Avalanche.
Current stays fixed at It .
(t4 < t < t5)
operating voltage
Avalanche
and worst-case
Voltage stays fixed at VBRdss. Current
MOSFET in Avalanche.
ramps down to zero at a fixed rate.
current rise rates—
(t5 < t < t6)
or component
Table 1. Overcurrent waveform periods and the simplifying assumptions used in the spreadsheet model.
specifications—
relative to the current limit threshold and the output state MOSFET switching times, MOSFET on-state resistance
of the protection circuit. Table 1 describes current, voltage and current detector response time. For this simulation,
and protection circuit assumptions for each period. These data sheet parameters for an IRFZ48V MOSFET were used.
simplifying assumptions make it straightforward to write Circuit operating and MOSFET data specifications used for
equations for voltage, current and power, and integrate the the simulation are shown in Table 2.
power equation to determine the energy dissipated in the
MOSFET. The series of equations developed for the On Simulation
period is as follows:
Fig. 2 presents the current waveforms for three different
detector
response times (1 µs, 3 µs and 5 µs). Several
t1 £ t £ t 2
observations can be made based on these waveforms. First,
I2 (t) = I t1 + k 2 ¥ (t - t1 )
the portion of the waveform that occurs before the current
exceeds the set limit is the same for all three response times.
V2 (t) = I2 (t) ¥ R DS(ON) = (I t1 + k 2 ¥ (t - t1 )) ¥ R DS(ON
ON )
This is to be expected and leads to the conclusion that
P2 (t) = I2 (t) ¥ V2 (t) = R DS(ON) ¥[(I2t1 - 2 ¥ I t1 ¥ k 2 ¥
the transistor losses in the Turn On and On periods are
independent of response time.
t1 + k 22 ¥ t12 ) + (2 ¥ I t1 ¥ k 2 - 2 ¥ k 22 ¥ t1 ) ¥ t + k 22 ¥ t 2 ]
Second, the On-OCL period is the first period impacted
t
2
2
2
by
the
response time. The end of this period is defined by the
E (t) = P (t) ¥ dt = R
(I - 2 ¥ I ¥ k ¥ t + k ¥ t ) ¥
Period
Description
Voltage and Current Assumptions
0
1
1
4
2
Ú
2
[
DS(ON )
t1
t1
2
1
2
1
t1
(t - t1 ) + (2 ¥ I t1 ¥ k 2 - 2 ¥ k 22 ¥ t1 )
(t
2
- t12
t 3 - t13
+ k 22
2
3
) (
500
)]
Current (A)
P2 AVG = E 2 (t 2 ) ¥ f
where I t1 equals the current at the end of the Turn On
period; k2 equals the rate of current rise; RDS(ON) equals
MOSFET on-resistance at the junction operating temperature;
P2AVG equals the average power dissipation contributed by On
period energy losses in a repetitive pulse-by-pulse, currentlimit mode; and f equals the frequency of the pulse-by-pulse
current limit.
Although these equations are long, they are simple to solve.
Moreover, it’s easy to define the time ending the ith period,
ti, based on setting current rise rates, ki, circuit operating
voltages and currents, and component data sheet parameters.
Power Electronics Technology January 2006
1 �s delay
400
3 �s delay
5 �s delay
300
200
100
0
0
1
2
3
4
5
Time (�s)
6
7
8
Fig. 2. The simulation current waveforms for protection response times
of 1 µs, 3 µs and 5 µs reveal a dramatic increase in current for slower
response times.
16
www.powerelectronics.com
PROTECTING MOSFETS
current at the beginning of the
Avalanche period to the current
It = 10 A
Turn On
at which the avalanche energy
tr = 0.2 µs
Vt = 15.6 V
(t0 < t < t1)
was specified. In this case, the
higher current inherited from
On
k2 (current rise rate) = 75 A/µs
RDS(ON) = 24 m at TJ = 150°C
the On-OCL period will increase
(t1 < t < t2)
Is (current limit threshold) = 75 A
the avalanche energy dramatically
On-OCL
k3 (current rise rate) = 75 A/µs
as well as the duration of the
RDS(ON) = 24 m at TJ = 150°C
Avalanche period.
(t2 < t < t3)
td = 1 µs to 5 µs
A final observation is that the
On-OCD
k4 (current rise rate) = 0
peak current increases significantly
RDS(ON) = 24 m at TJ = 150°C
(t3 < t < t4)
tl = 0.4 µs
for increasing response times.
t f = 0 . 2 ms
The simulation provides a peak
Turn Off
current of 300 A and 450 A for
Vt = VBRdss = 68 V
(t4 < t < t5)
response times of 3 µs and 5 µs,
Avalanche
EA = 0.5 mJ at 75 A; Model scales
respectively. Both of these values
Vt = VBRdss = 68 V
energy based on the square of current.
(t5 < t < t6)
exceed the IRFZ48V’s absolute
maximum pulsed drain current
Table 2. Spreadsheet model input parameters.
rating of 290 A.[2] So, in this case,
first knee in the waveform where it transitions to horizontal. a 3-µs response time would not be adequate to ensure the
This knee is the point at which the overcurrent condition is MOSFET was operating in its safe operating area.
detected. Slower response times cause higher currents and a
This same model is used to calculate the MOSFET
longer time duration in this period. With the MOSFET on, energy loss. Fig. 3 shows the energy loss for each period of
energy loss is proportional to the square of current and time, the waveform with different detector response times. The
so energy loss in this period will dramatically increase with plots show a dramatic increase in total energy loss, 3.7 mJ to
slower response time.
14.1 mJ, as response time is increased from 1 µs to 3 µs.
Another concern is that the On-OCD and Turn Off
This increase is driven primarily by losses generated in
periods also experience higher currents based on the inherited the On-OCL and Avalanche periods. This fact becomes more
current from the On-OCL period. But their durations remain evident when each component loss is normalized to the
unchanged. Therefore, their losses will increase due to higher total for each response time. Fig. 4 presents the normalized
current, but will not include an addition from a larger time components of energy loss. While Turn
T
Off loss makes a
component. The On-OCD loss will increase proportionally significant contribution for fast response times, it is a smaller
to the square of current, and the Turn Off loss will increase driver for longer response times. Losses generated in the
in direct proportion to current.
Turn On, On and On-OCD periods remain small contributors
Furthermore, the model calculates avalanche energy based to loss, regardless of response time.
upon a model input of energy at a lower current level. The
energy is then scaled based on the square of the ratio of the
Period
Circuit Operating Input Parameters
IRFZ48V Input Parameters
1
0
5
6
35
T
Total
Avalanche
On-OCL
Turn Off
On-OCD
On
Turn On
30
MOSFET Energy Loss (mJ)
MOSFET Energy Loss Normalized
60
25
20
15
10
Avalanche
50
On-OCL
Turn Off
40
On-OCD
On
30
Turn On
20
10
5
0
0
1
2
3
4
Detector Response Time (�s)
1
5
3
4
5
Detector Response Time (�s)
Fig. 3. A comparison of the MOSFET energy loss components generated
for protection response times of 1 µs to 5 µs shows a dramatic increase
in energy for slower response times.
Power Electronics Technology January 2006
2
Fig 4. A comparison of the MOSFET normalized energy loss components
generated for 1-µs to 5-µs protection response times shows Avalanche
and On-OCL period losses dominating for slow response times.
18
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peak for the circuit, 75 A. The avalanche energy rose by a
factor of 10 during the overcurrent event, with a response
time of approximately 2 µs. If this was an application where
the MOSFET was normally operated in an avalanche mode
with a higher level of energy, it would be quickly driven past
the device’s repetitive avalanche rating during a repetitive
overcurrent event.
Finally, the model is used to develop average power loss as
a function of response time for hard or repetitive overcurrent
events. Average power is calculated by multiplying the energy
loss by the frequency of the pulse-by-pulse current limit.
Fig. 5 shows average power loss versus response time for
three frequencies.
Two conclusions can be drawn from this figure. First,
regardless of frequency, average power loss increases
significantly with slower response time. This loss may be
80
Average Power Loss (W)
10 kHz
1 kHz
60
100 Hz
40
20
0
1
2
4
3
Detector Response Time (�s)
5
Fig 5. A comparison of MOSFET average power loss for protection
response times of 1 µs to 5 µs and frequencies of 100 Hz to 10 kHz
shows a dramatic increase in power for elevated frequencies as well
as a problem operating with moderate response time and at 10 kHz.
SE555
Astable
clock
A note of caution on the avalanche energy. For response
times of less than 4.5 µs, the value from the simulation
appears to be below the data sheet limit of 15 mJ for repetitive
avalanche rating. However, the limit should be calculated
using the transient thermal impedance of the MOSFET,
avalanche duration and the avalanche duty cycle in order to
ensure safe operation.[3] Second, this simulation used a small
value for avalanche energy, 0.5 mJ, at the normal operating
www.powerelectronics.com
Clock
15 V
74AC74
D
Flip Flop
TC427
FET
Driver
IsoSense
TD-75
6-inch
current loop
for scope
probe
4700 �FF
18 Vdc
Vd
10 �F
+
–
IRFZ48 V
Fig. 6. Test circuit block-schematic diagram using fast-acting OCD and
simple logic for overcurrent protection.
19
Power Electronics Technology January 2006
PROTECTING MOSFETS
For the case of a 10-kHz frequency, a response time of 2 µs
generates nearly 80 W of loss. Assuming a heatsink operating
temperature of 80°C and a thermal resistance from junction
to heatsink of 1.5°C/W, the junction temperature would
approach 200°C. In this case, a secondary level of shutdown
such as a pulse count routine would be required to provide
adequate protection.[4]
Test Circuit
To demonstrate the effectiveness of fast overcurrent
protection and the impact of response time on power
dissipation, a test circuit was built. A simplified schematic
for this circuit is shown in Fig. 6. In the power section of the
circuit, a TD-75 OCD is connected in series with the drain of
an IRFZ48V MOSFET. This series combination is connected
across an adjustable dc power supply.
The TD-75 is a Hall-effect-based current detector whose
output goes low when a 75-A threshold is exceeded. It has
a fast response time, and its output is isolated from the
sensed current so that it can be placed in the drain section
of the circuit without providing further isolation. A 4700µF aluminum electrolytic capacitor and a 10-µF metalized
polyester capacitor are placed across the power supply
connection to minimize the circuit impedance. To achieve
desired current rise times, the dc voltage is adjusted. For this
circuit, an input voltage of 18 V provided an initial current
rise rate of 75 A/µs.
The control, protection and gate-drive logic sections
of the circuit are composed of an SE555 timer driving the
clock input to a 74AC74 D flip flop, which drives a TC427
gate-driver IC. The data input to the flip flop is pulled high
so that whenever the IC is clocked, the gate of the MOSFET
will be driven to 15 V.
Protection is provided by connecting the output of the
TD-75 to the reset input of the flip flop. When the TD-75
detects an overcurrent event, its output resets the flip flop,
which forces the TC427 to force the IRFZ48V gate low for the
remainder of the clock cycle. In order to adjust the protection
response time, an adjustable delay was added to the output
of the OCD. A microcontroller is also used in the circuit to
provide overall circuit supervision and control.
A photograph of the test circuit is shown in Fig. 7. The
heatsink is a 3-in.  2.5-in.  0.25-in. piece of aluminum,
and it is used to provide electrical connection to the drain
of the MOSFET as well as heat dissipation. A 6-in. current
loop is included to
provide a probe point tD (µs) VIN (V) IIN (A) PIN (W)
to display current on the
1.1
17.81
0.306
5.45
oscilloscope.
Fig. 7. Test circuit showing MOSFET, heatsink, OCD and associated
control logic.
higher than normal operating losses, potentially driving
operating temperatures past their design points. Minimizing
the protection response time minimizes the average power
loss in a repetitive overcurrent mode of operation.
A second conclusion is that even relatively moderate
frequencies—5 kHz to 10 kHz—generate losses that will
drive the MOSFET junction temperature past absolute
maximum ratings, with response times of 2 µs and above.
Test Results
This circuit was run at
a 1-kHz frequency with
three different response
times. The first was 1.1
µs, which is the response
Power Electronics Technology January 2006
20
2.0
17.73
0.500
8.87
3.0
17.62
0.778
13.71
Table 3. Test circuit input measurements
demonstrating dramatic increase in
input power with slower response time,
consistent with spreadsheet model.
www.powerelectronics.com
PROTECTING MOSFETS
Even with this decrease in the rise rate of current, the
peak current is coming dangerously close to the absolute
maximum peak pulse current rating. A stiffer power
source, or a slower response time, would force the pulse
current past the absolute maximum rating for the IRFZ48V.
For direct comparison of the three response times,
Fig. 9 shows the corresponding current waveforms on the
same plot. As expected from the simulation, the current
waveforms have an identical form prior to overcurrent
shutdown. Slower response times impact the later portions
of the waveform.
PETech
References
1. “IsoSense Over Current Simulation Spreadsheet,” www.
isosense.com.
2. “Current Rating of Power Semiconductors,” International
Rectifier Application Note AN-949, p. 5, www.irf.com/
technical-info/appnotes/an-949.pdf.
3. “Murray, A.; McDonald, T.; Davis, H.; Cao, J.; Spring, K.
“Extremely Rugged MOSFET Technology with Ultra-low
RDS(ON) Specified for a Broad Range of EAR Conditions,” pp.
4-7, Presented at PCIM 2000, www.irf.com/technical-info/
whitepaper/pcim2000.pdf.
4. Kazmirski, T. “Fast Acting Over Current Power Circuit
Protection Scheme,” Presented at Power Systems World 2005,
www.isosense.com.
Fig. 8. Test circuit waveforms with 3-µs response time created by
adding delay to the output of the OCD. (Trace 1 = VGS , Trace 2 = OCD
out, Trace 3 = VDS and Trace 4 = ID .)
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Fig. 9. Comparison of test circuit current waveforms for response times
of 1 µs, 2 µs and 3 µs shows substantial increases in peak current in the
MOSFET. (Trailing edge of waveforms based on protection response
time. (Trace 1= 1 µs, Trace 2 = 2 µs and Trace 3 = 3 µs.)
time of the TD-75 used in the circuit. The two remaining
runs were made with delays added to provide response times
of 2 µs and 3 µs. Table 3 shows power input measurements for
the three cases. It shows a dramatic increase in input power
when response time is slowed. While not all of this power is
dissipated in the MOSFET, it does show general agreement
with the results provided by the simulation.
Waveforms for the 3-µs case are shown in Fig. 8. The peak
current for the 3-µs case hit a peak of 260 A. This is 77 A
higher than the 1.1-µs case, but lower than expected based on
the initial current rise rate of 75 A/µs. The rise rate decreases
over the pulse duration. This is related to the increasing drop
across the MOSFET at higher currents and the sag in the dc
power supply during the duration of the current pulse.
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21
Power Electronics Technology January 2006