A 1.2 pm CMOS Implementation of a Low-Power
900-MHz Mobile Radio Frequency Synthesizer
Manop Thamsirianunt
Tadeusz A. Kwasniewski"
MITEL Semiconductor, Kanata, Ontario, Canada
*Department of Electronics, Carleton University, Ottawa, Ontario, Canada
Abstract
!
Low-Frequency Parts
A single-chip, low-power all CMOS PLL frequency
synthesizer for digital mobile radio communication systems
is presented. The design of PLL components: VCO, dualmodulus prescaler and phase-frequency detector are
discussed. Novel circuit techniques and design methodology
allow GHz frequency range operation, and result in good
phase noise performance. The measured results of a
m CMOS PLL implementation indicate a
monolithic 1.2 j
frequency range of 800 to 900 MHz with -94 dBc/Hz phase
noise at a 1-MHz carrier offset, and a power consumption of
18 mW at 5 volts.
I. Introduction
The rapid growth in demand for digital mobile radio and
ponable telephones has been met through steady reductions
in cost, terminal size, and power consumption. Many of the
recently reported implementations of frequency synthesizers
use a mixture of high-speed semiconductor technologies, as
shown in Fig. 1. To date, the voltage-controlled oscillator
(VCO) and the dual-modulus divider are implemented in
either bipolar or GaAs Mesfet technologies, while most of
the low-frequency digital circuits are implemented in lowpower high-density CMOS technology. Recently, a CMOS
frequency divider was reported which exhibits an operating
frequency to a few gigahertz [ 11, [2], [3], yet there has been
no report to date on the use of on-chip GHz-range CMOS
VCOs in mobile radio applications.
A monolithic CMOS frequency synthesizer with
performance comparable to that of a discrete component
counterpart poses a great design challenge. The limiting
factor of CMOS circuits for the application considered is
their maximum operating frequency, and therefore circuits
must be optimized for speed. As well, the design topology
for a CMOS VCO has to account for performing in the noisy
digital environment. To successfully integrate an all CMOS
PLL on a single chip, special design techniques that
minimize noise and maximize speed must be developed.
In this paper, a high-speed CMOS PLL synthesizer consisting
of a 900-MHz VCO, a 1.4-GHz frequency divider and a no-
High-Frequency Parts
j(GaAs, Bipolar Traditionally)
(CMOS)
I
.c
I
Dual-Modulus
Prescalar
1
Reference
Frequency
Fref
Phase
Detector
Loop Filter
vco
Fig. I. Spica1 building blocks for a modem RF PLL frequency synthesizer
dead-zone phase-frequency detector is presented. The VCO.
a ring oscillator structure, is based upon the operation of
transistor-only-parasitic-capacitors, with performance and
characteristics evaluated through simulation and postfabrication measurements. It has been recently shown that
speed and phase noise can be simultaneously optimized in a
non-contradicting manner [4]. The novel CMOS circuit
techniques allow achievement of a higher operating
frequency imd lower power consumption for both VCO and
frequency divider [2] than previously reported for any
frequency synthesizer. The synthesizer chip, excluding loop
filter, was fabricated with a 1.2 pm 5-V standard CMOS
technology The VCO shows a phase noise performance
comparable to known bipolar on-chip VCO designs [5], [6].
171. A total power consumption below 18 mW was achieved
for the CMOS components of the 900-MHz synthesizer. The
synthesized output signal conforms with the phase noise
transmission standard requirements for an EIA 30-kHz
channel spacing cellular telephone system[8].
11. Circuit Description
A. Voltage Controlled Oscillator (VCO)
Placing the highest priority on speed implies that the CMOS
oscillator must be constructed using the simplest structures.
such as an odd-number inverter ring oscillator based upon an
RC relaxation oscillator, as shown in Fig. 2. Each inverter in
this ring can be modelled by a Schmitt trigger and its
associated timing components R I , R2 and C,, that form an
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01994 IEEE
RC relaxation oscillator. lnverter ring oscillators consist of
timing elements R , , R2 and C1 that can be circuit parasitics,
and therefore result in frequency of oscillation that can be
extremely high.
Inverter ring oscillators have an inherent drawback. The
frequency stability is dependent on both temperature and
power supply variations. Process variations can also
contribute to a shift of the center frequency. For a well
designed VCO these effects can be corrected by the feedback
action of a PLL. As well, the PLL suppresses phase noise
within the loop bandwidth. The ring oscillator VCO phase
noise outside the loop bandwidth is not suppressed and its
reduction is therefore a major design challenge. One of the
solutions to this problem is to use the fastest switching device
possible to reduce susceptibility to noise induced voltage
uncertainty across the parasitic timing capacitor [9].
p vcc
RC relaxation oscillator
,.,-.-----'
Parasitic-based ring oscillator
Fig. 2. Generalized ring oscillator.
Unlike most bipolar emitter coupled multivibrators, whose
low phase noise levels are achieved at the expense of large
timing capacitance and high biasing current [6],[7], the new
VCO introduced in this work is based upon a modified threestage dynamic inverter ring oscillator.
The oscillator, of Fig. 3, consists of a delay cell where
frequency control is achieved by directly controlling the
current through a series transistor of one inverter stage. The
two remaining inverters are connected to form a closed loop
ring. The circuit contains the least number of components
required for a functional relaxation oscillator.
The unique frequency control mechanism of the oscillator is
the use of short-channel effects (gate-length less than 3p.m) of
controlling transistor to modulate the delay. This scheme
allows a gradual monotonic increase in the current of
transistor Mnl into the saturation region. Therefore, using the
short-channel property of a MOSFET to control the delay
results in two different delay regions. one region where a
MOSFET is in linear operation and another where it is in the
saturation mode. In the linear region, the delay rate of
change is definitely higher than at the boundary of the
saturation region.
The frequency of oscillation for a ring oscillator is a function
of the delay, and therefore its voltage-to-frequency (V/F)
characteristic can be expected to have a similar transfer
characteristic. Most mobile radio frequency bands are limited
to a few tens of megahertz, therefore the operation of the
VCO along the boundary of the saturated delay cell can be
utilized. Fig. 3 shows a simplified version of the proposed
three-stage-ring oscillator employing a single-stage-inverter
delay cell.
Id
Area where short-channel effects
c~ be used for VCO application
f
Fig. 3. Simplified three-stage modified ring oscillator.
B. Dual-Modulus Frequency Divider
A high-speed 1.2pm CMOS 15/16 frequency divider
proposed in [2] was used as an integral part of the monolithic
CMOS synthesizer. The design was well suited for a highspeed, low-power requirement. Figure 4 shows the
functional block diagram of the divider. It consists of a
divide-by-3-or-4 synchronous counter as the first (high
frequency) stage followed by a divide-by-4 asynchronous
counter as the second (low frequency) stage. By employing a
level-triggered differential-logic latch, a maximum speed of
1.4 GHz was achieved.
Fig. 4. Functional block diagram of 15116 frequency divider [2].
C. Phase-Frequency Detector and Loop Filter
Although conventional tri-state CMOS phase-frequency
detectors (PFD) are the most popular for monolithic PLL
designs, the existence of a phase distortion zone or "dead
zone" can lead to PLL spurious noise problems, degrading
the overall performance of the synthesized signal.
A phase detector structure which mitigates this problem is
shown in Fig. 5. The configuration is based upon an extended
range exclusive OR (XOR) with a frequency discriminating
circuit [lo].
This structure delivers a 220' detection range for 50-MHz
operation and eliminates the dead zone by moving it to the
ends of the detection range. When incorporated in a PLL
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Fref
Fvco
-
tput
Fig. 5 . Phase-frequency detector with no dead zone.
synthesizer, this results in the phase detector operating in the
linear region for the lock condition.
For the best possible noise performance, a differential
structure was employed. Differential operation of the phase
detector can be accomplished by replicating the single ended
circuit and cross-coupling the two inputs. In this manner, a
balanced PLL loop filter is required, as shown in Fig. 6 .
The crucial benefit of having a balanced structure is that the
amount of common mode jitter in the zero crossings at the
PFD output due to substrate noise will be cancelled out
though the balanced loop filter. As a result, the structure
provides high immunity to noise coupled from digital
circuitry.
The loop filter was chosen as an off-chip implementation
allowing flexibility of loop gain and pole frequency selection.
(a) Fully differential PFD
were laid out symmetrically to achieve a 50% duty cycle
output, thereby decreasing output harmonics and jitter.
Transistor sizing was carefully optimized through a series of
HSpice extracted layout simulations. Power and ground lines
were laid out as 2Op-n wide metal lines. Star-ground
techniques were also employed to prevent ground loops and
power rail ripples, resulting in lower current spikes and
ground bounce which could potentially lead to increased
VCO phase noise. The phase-frequency detector was
implemented using standard cells because the circuit operates
at much lower frequencies than the VCO and the divider.
Finally, buried ground rings were placed around the VCO
circuit to reduce noise coupling from adjacent circuits. Onchip capacitors of 4pF were placed between Vdd and ground
lines, on unused space, to decouple high frequency noise on
the power supply.
VI. Experimental Results
The chip components, including the VCO, the 15/16 moduluh
prescaler and the fully differential PFD were tested to
characteriz,e performance and functionality of the fabricated
chip. This section presents experimental setups and measured
results performed for the monolithic circuit. A simple test bed
constructed from a printed circuit board and other discrete
components was used to test the synthesizer (see Fig. 7). All
measurements were performed on the bonded IC package.
(b) Second-order loop filter
Fig. 6. Fully balanced configuration of phase detector and loop filter.
111. Circuit Implementation
The circuits were laid out using a 1 . 2 double-poly
~
doublemetal N-well CMOS technology. In this section, layout
related design considerations associated with speed
improvement, noise and circuit partitioning for the proposed
VCO, frequency divider and PFD are presented.
For circuits to operate at frequencies close to those of their
pre-layout simulation results, standard cells had to be
avoided. Instead, custom designs were created for the VCO,
incorporating several optimization techniques.
In order to minimize the parasitic capacitances, the core VCO
and frequency divider layouts were made as compact as
possible, and all interconnections were made using metal
layers. All transistors employed minimum-design features
except for the transistor widths. The polysilicon layer was
used exclusively for transistor gates, and all transistors had a
1 . 2 gate
~ length. All p and n transistors of the VCO circuit
Fig. 7. Single-chip implementation and test setup.
Figure 8 shows the plots of the V/F characteristics for both
simulated and measured results. The operating frequency
range of the VCO was measured at 386-926 MHz for an input
of 1.1-5.0 volts. This appears faster than simulation results by
16%. The phase noise, measured using the HP 3048A phase
noise measurement system, indicated VCO noise levels of 83 dBc/Hz,at 100 kHz offset from a 900-MHz carrier.
The closed loop PLL synthesizer 850-MHz spectral output is
shown in Fig. 9. The PLL operated in a locked condition from
800.6-898.8 MHz for a 16 and 15 divide ratio respectively.
The two peaks at 200 kHz offset indicate the loop bandwidth
of the PLL,. Table 1 summarizes the performance parameters
of the PLL. components in this design.
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’
,
0
’
0
‘3.0 0
carrier offset (-94.0dBdHz at 1 MHz offset). With these
7kHz
greater levels of integration achieved, a CMOS
implementation of a PLL frequency synthesizer should
contribute to more widespread use of wireless
communications in mass-consumer products.
0
........... .. Simulated
Fig. 10. Die photograph of PLL components.
VI. Acknowledgements
The authors would like to thank the assistance of Canadian
Microelectronics Corporation (CMC) for fabrication suppon.
Also, the support of the Canadian International Development
Agency (CIDA), the Telecommunication Research Institute
of Ontario (TRIO) and Micronet are also gratefully
acknowledged.
References
Table 1 Summarized results for PLL components.
I
I
Frequency divider
PFD
11
Operating
11
700 - 1400
65
I
Power
I
I 12.7 (1.4GHz) I
1 1.3 (50 MHz) I
Die area
I
20
I
103
V. Conclusion
The realization of a single-chip high-speed CMOS PLL
synthesizer, which operates in the GHz range, and believed to
be the first all CMOS synthesizer for mobile radio
applications, was presented. The VCO required no external
components yet exhibited low phase noise. The synthesizer
achieved a total power consumption of 18 mW for the CMOS
components on chip, and a phase noise of -78.3 dBc/Hz at 45
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