CK5110
Auto Focus Motor Driver IC
DESCRIPTION
FEATURES
The CKM110 is a single 10-bit DAC with 102.3mA
output current sink capability. It features an internal
reference and operates from a single 2.3V to 5.5V
supply. The DAC is controlled via a 2-wire (I 2 C
compatible) serial interface that operates at clock rates
up to 400KHz.
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The CKM110’s unique and proprietary Slope Control
Modes allow the user to customize the output transient
response thereby overcoming mechanical ringing
associated with reduced form factor voice coil motors
(VCMs).
The CKM110 incorporates a power-on reset circuit,
which ensures that DAC output powers up to 0V and
remains there until a valid write takes place. It has a
power-down feature that reduces the current
consumption of the device to 1μA maximum.
The CKM110 is designed for autofocus, image
stabilization, and optical zoom applications in camera
phones, digital still cameras, and camcorders.
The CKM110 also has many industrial applications,
such as controlling temperature, light, and movement,
over the range -40℃ to +85℃ without derating.
The I2CC address for the CKM110 is 0x18h.
CKM110 has two versions IC about Xshutdown pin:
Ver A: XShutdown pin is active low. (Hard Shutdown mode at Xshutdown =0V)
Ver B: XShutdown pin is active High. (Hard
Shutdown mode at Xshutdown =1.8V)
STRUCTURE
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Silicon CMOS IC
102.3mA current sink
2-wire (I 2 C -compatible) 1.8V serial interface
10-bit resolution DAC
Integrated current sense resistor
Selectable output slope control
2.3V to 5.5V power supply
Guaranteed monotonic over all codes
Power-down to 0.5μA typical
Internal reference
Built-in UVLO shutdown circuit
Power-down function
Power-on reset
Available in 2 x 3 array, 0.809mm x 1.367mm x
0.395mm WLCSP-6 packages
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APPLICATIONS
CONSUMER APPLICATIONS
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Auto focus for 3M～12M Lens
Image stabilization
Optical zoom
Shutters
Iris/exposure
Neutral density (ND) filters
Lens covers
Camera phones
Digital still cameras
Camera modules
Digital video cameras/camcorders
Camera-enabled devices
Security cameras
Web/PC cameras
INDUSTRIAL APPLICATIONS
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Heater controls
Fan controls
Cooler (Peltier) controls
Solenoid controls
Valve controls
Linear actuator controls
Light controls
Current loop controls
CK5110
BLOCK DIAGRAM
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CK5110
APPLICATIONS NOTE
The CKM110 is designed to drive both spring-preloaded and nonspring linear motors used in applications such as lens
autofocus, image stabilization, or optical zoom. The operation principle of the spring-preloaded motor is that the lens
position is controlled by the balancing of a voice coil and spring. Following figure shows the transfer curve of a typical
spring-preloaded linear motor for autofocus. The key points of this transfer function are displacement or stroke, which is
the actual distance the lens moves in mm and the current through the motor in mA.
A start current is associated with spring-preloaded linear motors, which is effectively a threshold current that must be
exceeded for any displacement in the lens to occur. The start current is usually 20mA or greater, the rated stroke or
displacement is usually 0.25mm to 0.4mm, and the slope of the transfer curve is approximately 10μm/mA or less.
The CKM110 is designed to sink up to 102.3mA, which is more than adequate for available commercial linear motors or
voice coils. Another factor that makes the CKM110 the ideal solution for these applications is the monotonicity of the
device, which ensures that lens positioning is repeatable for the application of a given digital word.
Following figure shows a typical application circuit for the CKM110.
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CK5110
ORDER INFORMATION
Valid Part Number
CKM110A
CKM110B
Package Type
6 Pins, WCSP
6 Pins, WCSP
Top Code
5110A
5110B
IC MARK
PIN CONFIGURATION
Bottom view
Top view(Ball side down)
PIN DESCRIPTION
Ball Name
IBBSINKBB
Xshutdown
GND
SDA
VDD
SCL
Ver1.1
Description
Output current sink
Power down, asynchronous power down signal
Ground pin (Power/Analog/Digital ground)
IPP2PPC interface signal
Power supply
IPP2PPC interface signal
4
Ball No.
A1
A2
B1
B2
C1
C2
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CK5110
FUNCTION DESCRIPTION
The CKM110 is a fully integrated, 10-bit DAC with 102.3mA output current sink capability and is intended for driving voice
coil actuators in applications such as lens autofocus, images stabilization, and optical zoom. The block diagram as
following figure is showing connection to voice coil. A 10-bit current output DAC coupled with resistor R generates the
voltage that drives the noninverting input of the operational amplifier. This voltage also appears across the R SENSE
resistor and generates the sink current required to drive the voice coil.
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Resistors R and R SENSE are interleaved and matched. Therefore, the temperature coefficient and any nonlinearities over
temperature are matched and the output drift over temperature is minimized. Diode D1 is an output protection diode.
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SERIAL INTERFACE
The CKM110 is controlled using the industry-standard I 2 C 2-wire serial protocol. Data can be written to or from the DAC
at data rates up to 400KHz. After a read operation, the contents of the input register are reset to all zeros.
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CK5110
I 2 C BUS OPERATION
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An I 2 C bus operates with one or more master devices that generate the serial clock (SCL), and read/write data on the
serial data line (SDA) to/from slave devices such as the CKM110. All devices on an I 2 C bus have their SCL pin connected
to the SDA line and their SCL pin connected to the SCL line. I 2 C devices can only pull the bus lines low; pilling high is
achieved by pull-up resistors R P . The value of R P depends on the data rate, bus capacitance, and the maximum load
current that the I 2 C device can sink (3mA for a standard device).
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When the bus is idle, SCL and SDA are both high. The master device initiates a serial bus operation by generating a start
condition, which is defined as a high-to-low transition on the SDA low while SCL is high. The slave device connected to
the bus responds to the start condition and shifts in the next eight data bits under control of the serial clock. These eight
data bits consist of a 7-bit address, plus a read/write bit, which is 0 if data is to be written to a device, and 1 if data is to be
read from a device. Each slave device on an I 2 C bus must have a unique address. The address of CKM110 is 0001100.
Because the address plus R/W bit always equals eight bits of data, another way of looking at it is that the write address of
the CKM110 is 00011000 (0x18) and the read address is 00011001 (0x19) (see following two figures).
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WRITING
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CK5110
READING
At the end of the address data, after the R/W bit, the slave device that recognizes its own address responds by generating
an acknowledge (ACK) condition. This is defined as the slave device pulling SDA low while SCL is low before the ninth
clock pulse and keeping it low during the ninth clock pulse. Upon receiving ACK, the master device can clock data into the
CKM110 in a write operation. Data must change either during the low period of the clock, because SDA transitions during
the high period define a start condition as described previously, or during a stop condition as described in the Data Format
section.
I 2 C data is divided into blocks of eight bits, and the slave generates an ACK at the end of each block. Because the
CKM110 requires 10-bit of data, two data-words must be written to it when a write operation occurs, or read from it when
a read operation occurs. At the end of a read or write operation, the CKM110 acknowledges the second data byte. The
master generates a stop condition, defined as a low-to-high transition on SDA while SCL is high, to end the transaction.
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DATA FORMAT
As the CKM110 is a 10-bit DAC, it requires a 2 byte write sequence. Data is written to the CKM110 high byte first, MSB
first, and is shifted into a 16-bit input register. After all data is shifted in, data from the input register is transferred to the
DAC register.
Bit 15, the OD bit is a software power down enable. When set to 1, the output circuitry is disabled and the CKM110 goes
into a low power mode. The digital circuitry and I 2 C interface is still active in this mode. When the OD bit is reset back to
zero, the DAC powers up to the value written to the DAC bits at the same time.
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Bit14 must always be set to 1.
Bit13 to bit 4 are DAC data bits D9 to D0.
Bit 3 to bit 0 are the output slope control bits S3 to S0. Data Byte 2 contains DAC data bit3 to bit0.
Data byte 2 also contains the slope control bits S3 to S0.
These bits control the slew rate of the output current. The following graph shows the operation of the slope control bits S0
to S3.
Serial Data Words
Serial Data Bits
Input Register
Function
SD7
R15
OD
High Bye
Low Byte
SD6 SD5 SD4 SD3 SD2 SD1 SD0 SD7 SD6 SD5 SD4 SD3 SD2 SD1 SD0
R14 R13 R12 R11 R10 R9 R8 R7 R6 R5 R4 R3 R2 R1 R0
1
D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 S3 S2 S1 S0
Notes:
1. OD=soft power down and Output Disable
2. D0~D9=DAC Data
3. S3, S2, S1, S0=Output current slope control
4. Slave address of CKM110 is (0001100X)
Write address is 0X18h (00011000)
Read address is 0X19h (00011001)
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CK5110
POWER SUPPLY BYPASSING AND GROUNDING
When accuracy is important in an application, it is beneficial to consider power supply and ground return layout on the
PCB. The PCB for the CKM110 should have separate analog and digital power supply sections. The ground should be
made as close as possible to the CKM110.
Special attention should be paid to the layout of the GND return path and tracked between the voice coil motor and I SINK
to minimize any series resistance. Following figure shows the output current sink of the CKM110 and illustrates the
importance of reducing the effective series impedance of GND and the track resistance between the motor and I SINK . The
voice coil is modeled as inductor L C and resistor R C . The current through the voice coil is effectively a dc current that
results in a voltage drop, V C , when the CKM110 is sinking current; the effect of any series inductance is minimal. The
maximum voltage drop allowed across R SENSE is 100mV, and the minimum drain to source voltage of Q1 is 50mV. This
means that the CKM110 output has a compliance voltage of 150mV. If V DROP falls below 150mV, the output transistor, Q1,
can no longer operate properly and I SINK may not be maintained as a constant.
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As the current increases through the voice coil, V C increases and V DROP decreases and eventually approaches the
minimum specified compliance voltage of 150mV. The ground return path is modeled by the components R G and L G .
The track resistance between the voice coil and the CKM110 is modeled as R T . The inductive effects of L G influence
R SENCE and R C equally, and because the current is maintained as a constant, it is not as critical as the purely resistive
component of the ground return path. When the maximum sink current is flowing through the motor, the resistive
elements, R T and R G , may have an impact on the voltage headroom of Q1 and could, in turn, limit the maximum value of
R C because of voltage compliance.
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For example, if V BAT =3.6V, R G =0.5Ω, R T =0.5Ω, I SINK =100mA, and V DROP =150mV (the compliance voltage), then the
largest value of resistance of the voice coil, R C , is:
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VBAT - [VDROP  (ISINK  R T )  (ISINK  R G )]
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ISINK
3.6V - [150mV  2  (100mA  0.5)]
 33.5
100mA
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CK5110
For the reason, it is important to minimize any series impedance on both the ground return path and interconnect between
the CKM110 and the motor.
The power supply of the CKM110 or the regulator used to supply the CKM110 should be decoupled. As part of best
practice power supply decoupling it is recommended that the power supply be decoupled with a 10μF capacitor. Ideally
this 10μF capacitor should be a tantalum bead-type. However if the power supply or regulator supply is well regulated and
clean then such decoupling may not be required. The CKM110 should be decoupled locally with a 0.1μF ceramic type
capacitor, and this 0.1μF capacitor should be a ceramic type with a low effective series resistance and effective series
inductance. The 0.1μF capacitor provides a low impedance path to ground for high transient currents.
The power supply line should have as large a trace as possible to provide a low impedance path and reduce glitch effects
on the supply line. Clocks and other fast switching digital signals should be shielded from other parts of the board by
digital ground. Avoid crossover of digital and analog signals if possible. When traces cross on opposite sides of the board,
ensure that they run at right angles to each other to reduce feedthrough effects through the board. The best board layout
technique is to use a multilayer board with ground and power planes, where the component side of `the board is dedicated
to the ground plane only and the signal traces are placed on the solder side. However, this is not always possible with a
2-layer board.
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CK5110
OUTPUT SLOPE CONTROL
The CKM110 is designed to drive both spring preloaded and nonspring linear motors used in applications such as lens
autofocus, image stabilization, or optical zoom. The operation principle of the spring-preloaded motor is that the lens
position is controlled by the balancing of a voice coil and spring.
The requirement to reduce optical module form factors has led to a reduction in the size of VCM actuators. As VCM
actuators reduce in size, the preloaded balance spring strength also reduces. When large current transitions occur, the
momentum of the lens can often lead to overshoot and VCM can take some time to settle to its final position. This
phenomenon, often described as mechanical ringing, varies with output current step size and for large lens
displacements can lead to unacceptably long auto focus times. The CKM110’s unique and proprietary output slope
control design allows the user to overcome the mechanical limitations associated with reductions in VCM form factor.
The CKM110 uses an innovative and proprietary scheme to provide the user with the option of three slope control modes.
These control modes are exercised via the I 2 C bus and are controlled by bits S3 to S0 (bit 3 to bit 0) in the data byte.
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P.10 describes the CKM110 slope control modes. The CKM110 contains a 20KHz integrated clock generator and divider
circuitry. This clock generator controls the transition step duration when the slope control bits S2 to S0 are used.
P.12 shows the truth table and current transition step size for the slope control options. The slope control mode feature of
the CKM110 allows the user to customize output transition times and where mechanical ringing is an issue the CKM110
output can be programmed to effectively decelerate the lens movement as it approaches its target position; thereby
reducing the overshoot and minimizing mechanical ringing.
Mode 0
Mode 1
Mode 2
Ver1.1
Direct Load Mode
When S2, S1 and S0 are zero (code 0 and code 8 in the table below), the output will go to the
target code within the CKM110 settling time.
S3 has no effect when S2 to S0 are zero.
Linear Ramp Mode
When S3 is zero and S2 to S0 are non-zero (code 1 to code 7 in the table below), the output will
increment/decrement to the target code in single code steps. The code step duration is selected
by S2 to S0 to be 50s to 3.2ms per step
64/16 Ramp Mode
When S3 is 1 and S2 to S0 are non-zero (code 9 to code 15 in the table below), the output will
transition to the new value in multi-code steps.
 If the Target DAC Code is greater than 128 codes from current DAC code, the CKM110
DAC will increment in 64 DAC code steps.
 When the current position DAC code is between 16 codes and 128 codes from the target
position, the DAC will increment in 16 Code Steps.
 When the current position DAC code is less than 16 codes from the target, it will step
directly to the desired code and therefore the desired current.
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CK5110
Example: If the user wishes to perform a Full Scale Transition of 1023 code the output of the CKM110 will increment by
fourteen 64-code steps (until it is between 16-128 codes from target value). The CKM110 will then effectively decelerate
in terms of output current step size and approach the target output current in seven 16-code steps followed by one final
step to fullscale.
(64 Code Steps x 14) + (16 Code Steps x 7) + (Step to Final DAC code x 1) = 22 steps.
Mode 2 operation of CKM110’s unique slope control as following figure.
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CK5110
SLOPE CONTROL MODE AND SINGLE STEP TRANSITION TIME TRUTH TABLE
Mode
S3
S2
S1
S0
Mode 0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
Mode 1
Mode 2
Single Step
Transition Time
70us
50μs
100μs
200μs
400μs
800μs
1.6ms
3.2ms
70us
50μs
100μs
200μs
400μs
800μs
1600μs
3200μs
Full Scale
Transition Time
70us
51.15ms
102.3ms
204.6ms
409.2ms
818.4ms
1636.8ms
3273.6ms
200us
1.1ms
2.2ms
4.4ms
8.8ms
17.6ms
35.2ms
70.4ms
MODE2 SLOPE
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CK5110
TERMINOLOGY
RELATIVE ACCURACY
For the DAC, relative accuracy or integral nonlinearity is a measurement of the maximum deviation, in LSB, from a
straight line passing through the endpoints of the DAC transfer function.
DIFFERENTIAL NONLINEARITY (DNL)
Differential nonlinearity is the difference between the measured change and the ideal 1 LSB change between any two
adjacent codes. A specified differential nonlinearity of ±1 LSB maximum ensures monotonicity. This DAC is guaranteed
monotonic by design.
ZERO-CODE ERROR
Zero-code error is a measurement of the output error when zero code (0 x 0000) is loaded to the DAC register. Ideally, the
output is 0mA. The zero-code error is always positive in the CKM110 because the output of the DAC cannot go below
0mA. This is due to a combination of the offset errors in the DAC and output amplifier. Zero-code error is expressed in
mA.
GAIN ERROR
This is a measurement of the span error of the DAC. It is the deviation in slope of the DAC transfer characteristic from the
ideal, expressed as a percent of the full-scale range.
GAIN ERROR DRIFT
This is a measurement of the change in gain error with changes in temperature. It is expressed in
LSB/℃.
DIGITAL-TO-ANALOG GLITCH IMPULSE
This is the impulse injected into the analog output when the input code in the DAC register changes state. It is normally
specified as the area of the glitch in nA-s and is measured when the digital input code is changed by 1 LSB at the major
carry transition.
DIGITAL FEEDTHROUGH
It is a measurement of the impulse injected into the analog output of the DAC from the digital inputs of the DAC but is
measured when the DAC output is not updated. It is specified in nA-s and measured with a full-scale code change on the
data bus, that is, from all 0s to all 1s and vice versa.
OFFSET ERROR
It is a measurement of the difference between I SINK (actual) and I OUT (ideal) in the linear region of the transfer function,
expressed in mA. Offset error is measured on the CKM110 with Code 16 loaded into the DAC register.
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OFFSET ERROR DRIFT
This is a measurement of the change in offset error with a change in temperature. It is expressed in µV/℃.
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CK5110
ABSOLUTE MAXIMUM RATINGS
(Unless otherwise specified, Ta=25℃ )
Parameter
VDD to GND
AGND to PGND
SCL, SDA to GND
XShutdown to GND
ISINK to GND
Symbol
V DD
SCL, SDA
SHUTDN
I SINK
Operating temperature
Topr
-40 ~ +85
Unit
V
V
V
V
V
℃
Storage temperature
Tstg
-65 ~ +150
℃
Junction temperature
Tjmax
150
℃
Power dissipation
Operating voltage
Pd
V OP
5
2.3 ~ 5.5
mW
V
Operating frequency (max)
f MAX
~5
MHz
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Rating
-0.3 ~ 5.5
-0.3 to 0.3
-0.3 ~ 3.3
-0.3 ~ V DD +0.3
-0.3 ~ V DD +0.3
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Note:
Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device.
This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this
specification is not implied.
Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
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CK5110
ELECTRICAL CHARACTERISTICS
(Unless otherwise specified, V DD =2.3V to 5.5V, AGND=PGND=GND=0V, RL=25Ω connected to V DD , All specifications
-40℃ to 85℃)
Rating
Parameter
Symbol
Conditions
Unit
Min.
Typ.
Max.
DC Performance
Resolution
100μA/LSB
10
Bit
Relative accuracy
INL
LSB
1.5
4
Differential nonlinearity
Guaranteed monotonic
DNL
LSB
1
(see Note 1)
over all codes
Zero code error
All 0s loaded to DAC
0
mA
(see Note 2)
Offset error @ code 16
0.5
mA
@25℃
Gain error
% of FSR
0.6
Offset error drift
μA/℃
Driftoffset
10
(see Note 2 & 3)
Gain error drift
LSB/℃
Driftgain
0.2
0.5
(see Note 3)
Output Characteristics
Minimum sink current (see
Isink min
3
mA
Note 2)
Maximum sink current
Isink max
Full bit
102.3
mA
Output current during hard
I SINKXDN
Xshutdown=0V(Note4)
80
nA
shutdown
Output current during soft
I SINKSD
Soft shutdown
80
nA
shutdown
Output voltage range
Output compliance
V ISINK
over which maximum
0.15
V DD
V
(see Note 3)
sink current is available
To 10% of F.S., coming
Power up time
Tr
out of Power down mode;
10
μs
V DD =5V
Logic Input (Xshutdown) (see Note 3)
Input current
I IN
μA
1
Input low voltage
V INL
V DD =2.3V~5.5V
0.54
V
Input high voltage
V INH
V DD =2.3V~5.5V
1.3
V
Input capacitance
C IN
3
pF
I 2 C compatible input
Logic Input (SCL, SDA) (see Note 3)
Input low voltage
V INL
V DD =2.3V~5.5V
0.54
V
Input high voltage
V INH
V DD =2.3V~5.5V
1.3
V
Input leakage current
I IN
Vin=0V to VDD
μA
1
Input hysteresis
V HYST
0.05V DD
V
Digital input capacitance
C IN
6
pF
Glitch rejection
Pulse width of spike
50
ns
(see Note 5)
suppressed
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Parameter
Symbol
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VDD
V DD
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IDD (Normal mode)
I DD
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I DDXSD
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I DDSD
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V INH =1.8V, V INL =0V,
Xshutdown=1.8V
V INH =1.8V, V INL =0V,
Xshutdown=0V
V INH =1.8V, V INL =0V,
Xshutdown=1.8V
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UVLO
V DD =5.5V, L=680μH
1/4scale to 3/4scale
(0x100 to 0x300)
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Max.
Unit
Symbol
Conditions
V DD =2.3~5.5V
SCL clock frequency
SCL cycle time
SCL high time
SCL low time
Start/repeated start
condition hold time
Data setup time
Data hold time
Setup time for repeated start
Stop condition setup time
Bus free time between a
stop condition and a start
condition
Rise time of both SCL and
SDA when receiving may be
CMOS driven
Fall time of SDA when
receiving
Fall time of both SCL and
SDA when transmitting
Capacitive load for each bus
line
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fscl
Tscl
Thigh
Tlow
T4
Thd,sta
T5
T6 (see Note 9)
T7
T8
Tsu,dat
Thd,dat
Tsu,sta
Tsu,sto
T9
Tbuf
T10
Tr
T11
Tfr
T11
Tft
Cb (see Note 10)
Cb
2.3
-
5.5
V
-
0.5
2
mA
-
0.5
1
μA
-
0.5
2
mA
1.6
1.8
2.0
V
-
250
-
μs
-
0.15
-
nA-s
-
0.06
-
nA-s
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Major code change glitch
impulse
Digital feedthrough
Ver1.1
Rating
Typ.
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Output current settling time
Parameter
(see Note 8)
Timing Specifications
fscl
T1
T2
T3
Min.
I DD specification is valid for
all DAC codes
Power Requirements
IDD (Power down mode) hard
(see Note 4)
IDD(Power down mode) soft
(see Note 6)
Low voltage detection
voltage(see Note 7)
AC Specifications
Conditions
Min.
Rating
Typ.
Max.
Unit
BB
16
2.5
0.6
1.3
-
400
-
KHz
μs
μs
μs
0.6
-
-
μs
100
0
0.6
0.6
-
0.9
-
ns
μs
μs
μs
1.3
-
-
μs
0
-
300
ns
20+0.1Cb
-
250
ns
20+0.1Cb
-
300
ns
-
-
400
pF
June 2011
CK5110
Notes:
1. Linearity is tested using a reduced code range; Code 64 to Code 1023.
2. To achieve near zero output current, use the power-down feature.
3. Guaranteed by design and characterization; not production tested. SDA and SCL pull-up resisters
are tied to 1.8V.
4. PTC can provide two versions IC about Xshutdown pin:
Ver A: XShutdown pin is active low. (Hard Shutdown mode at VBBXSHUTDIWNBB=0V)
Ver B: XShutdown pin is active High. (Hard Shutdown mode at VBBXSHUTDIWNBB=1.8V)
5. Input filtering on both the SCL and SDA inputs suppresses noise spikes that are less than 50ns.
6. In Softdown mode, the digital circuit work normal and output circuit enters the off state.
7. If the power supply of chip drops to about 1.88V, the low voltage detection(UVLO) circuit is activated and the output circuit enters the off state.
8. Guaranteed by design and characterization; not production tested.
9. A master device must provide a hold time of at least 300ns for the SDA signal (referred to the Vih
min of the SCL signal) to bridge the undefined region of SCL’s falling edge.
10. Cb is the total capacitance of one bus line in pF. Tr and Tf are measured 0.3Vdd to 0.7Vdd.
ESD CAUTION
ESD (electrostatic discharge) sensitive. Electrostatic charges as high as 2000V readily accumulate on the human body
and test equipment and can discharge without detection. Although this product features proprietary ESD protection
circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. Therefore, proper
ESD precautions are recommended to avoid performance degradation or loss of functionality.
Ver1.1
17
June 2011
CK5110
PACKAGE INFORMATION
WLCSP-6
E
A2
A1
D
E1
TOP VIEW
øb
D1
BOTTOM VIEW
Symbols
Ver1.1
Drawing(mm)
Min
Nom
Max
A1
0.14
0.170
0.20
A2
0.200
0.225
0.25
D
1.337
1.367
1.397
D1
-
0.400
-
E
0.779
0.809
0.839
E1
-
0.400
-
b
0.260
0.290
0.320
18
June 2011