1
Ka-band VSAT 4-Channel Phased Array
Receiver Demonstrator
Ioannis Bligiannis
Department of Electrical Engineering, Eindhoven University of Technology, Eindhoven,
Netherlands
i.bligiannis@student.tue.nl
-90.
Abstract— In this paper two well-known antenna concepts, (I)
the reflector antenna and (II) the phased array, are combined
together with the super-heterodyne, low-IF receiver architecture
for RF applications. This leads to a focal-plane array, combining
the “best of both worlds”, such as low-loss, low G/T cost, multibeam functionality, electronic beam-steering, high efficiency and
polarization purity.
The 4-element feed is placed at the focal point of the reflector.
The amplitudes and phases are distributed over the elements and
the antenna beam can be steered electronically. A 4-channel
receiver PCB was designed, operating in the Ka band between 1822 GHz. The outputs of the four receive modules are combined by
a 4:1 Wilkinson power combiner. Using the proper ICs for
amplitude and phase control, as well as mixing down the incoming
signal together with a tunable-LO input, we achieved a stable IF
output placed at 1 GHz with 27 MHz typical channel bandwidth
in VSAT applications.
Index Terms—Ka-band, satellite communications, VSAT,
phased array, beam-steering.
I.
T
INTRODUCTION
HE concept of forming receive antenna beams by
combining the elements amplitude and phase at an
intermediate frequency or in the digital domain has been
pursued for many years. This technique which has been called
array signal processing and beamforming has the primary
advantage of being capable of forming multiple beams,
performing adaptive beamforming or nulling [1]. Interesting
applications like DVB-S, Internet over Satellite (VSAT)
operating at 20 and 30 GHz, where a large scan volume is
required, a single beam system may not be capable of satisfying
all requirements. Array beam forming techniques exist that can
yield multiple, simultaneously available beams. The beams can
be made to have high gain and low sidelobes, or controlled
beamwidth. Adaptive beam forming techniques dynamically
adjust the array pattern to optimize some characteristic of the
received signal. In beam scanning, a single main beam of an
array is steered and the direction can be varied either
continuously or in small discrete steps. Antenna arrays using
adaptive beamforming techniques (spatial filtering, null
steering) in the RF or even at the digital part, can reject
interfering signals having a direction of arrival different from
that of a desired signal. Thus, the need for a more
reconfigurable antenna which is capable of electronic scanning,
is focused on the idea of using focal plane arrays (FPA). This
technology combines the advantages of reflector antenna and
phased arrays.
The phased-array fed reflectors, or focal plane arrays,
provide improved amplitude and phase distribution, but it is
also possible to generate multiple beams with each beam
generated by an array of feeds and adjacent beams share some
of the elements. In fact, the feed (consisting of an array of feeds,
therefore with a large effective aperture) is now more directive,
and at the same time, because of the overlapping approach, the
effective inter-element distance is kept small. This concept can
be applied to next generation TV satellite receivers to
communicate with several satellites simultaneously [2]. The
phased-array consists of multiple individual radiators (N). In
this project, special attention will be given to a 4 element feed,
focal plane array system. Figure 1 shows the schematic view of
the focal plane array.
The layout of the paper is as follows. First, in II the phased
array principle will be described. III will describe the model and
quote the system’s requirements. IV will explain the choice of
the beamforming technique and receiver’s architecture. In V
design considerations will be revealed as well as the analytical
calculation. In VI, we will discuss the PCB layout and design
procedure together with the measured performance and some
conclusions will be provided in VII.
Figure 1. Focal plane array with multibeam capability.
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2
III. MODEL DESCRIPTION AND SYSTEM
REQUIREMENTS
II. PHASED ARRAY PRINCIPLE
The block diagram of an N-element phased array is
shown in Figure 2. “N” identical antennas are equally spaced
by a distance “d” along an axis. Separate phase shifters or
variable time delays are incorporated at each signal path to
control the phases of the signals before combining all the
signals together at the output. A plane-wave beam is assumed
to be incident upon the antenna array at an angle of θ to the
normal direction, where β denotes the difference in phase shift
provided between two successive delay blocks. The radiation
pattern of the array excluding the element pattern is referred to
as the array factor. A general form for a linear array along the
z-axis is given by (1).
AF  A0  A1e j ( kd cos   )  A2e j 2( kd cos   )  ...
 An1e j ( 1)( kd cos   )
Where k

2

(1)
Model Description and System Requirements
The aim of the proposed receiver module is to contribute with
lower cost and complexity, higher functionality and linearity in
many application domains, like DVB-S, Point-to-Point
Communication and low cost Ka band radar applications.
After the placement of 4 antenna elements (patch antennas
designed for 18 GHz and more), in a microstrip linear array at
the focal plane of a 75 cm off-set reflector antenna, this
assignment concentrates on the design, construction and
evaluation of a phased-array receiver prototype, consisting of
the blocks in Figure 2.
The operational frequency range of the system is 18-22 GHz.
For this project a low
specification together with other important parameters, the
values of which are shown in Table 1. The ratio Gr/Ts (or simply
G/T) is known as the Figure of Merit. It indicates the quality of
a receiving satellite earth system and has a unit [dB/K].
,
The array factor of N-elements can be written as (2):
AF ( )   n0 An e j ( n1)( kd cos   )
N
(2)
Table 1 Requirements for this project
The term kdcosθ+β can be written as ψ, so the array factor
becomes
AF ( )   n1 An e j ( n1)
N
G
dB
of 13.5
is required as initial
T
K
Symbol
Description
G/T
Gain/ noise
temperature
13.5 dB/K
B
bandwidth
Typical channel bandwidth in VSAT
(also in broadcast over satellite (DVBS)) is 27 MHz
C/N
Signal to
Noise Ratio
Typical value of 10 dB
Ga
Antenna
Gain
 40dB
NF
Noise
Figure
4 dB
(3)
Figure 2. A 4-channel phased-array antenna. Phase shift in each
channel compensates the phase difference of incoming signals
received by each antenna.
The Array Factor is a function of the positions of the antennas
in the array and the weights used [3]. By tailoring these
parameters the antenna array's performance may be optimized
to achieve desirable properties. A major advantage of this
technique is its capability to provide spatial filtering, meaning
that phased arrays are able to suppress signals emanating from
undesired directions. It is desired to receive the signal from a
specific path while suppressing the others propagating along
other directions. That means, in contrast with other well-known
receiver architectures, there is no need for the first, preselecting
filter, which indicates less cost and complexity and was one of
the key points of this project [4].
Value
Based on these initial values, certain steps and formulas need
to be followed, that will help us during each step for the careful
individual block specifications, i.e. linearity, noise figure and
gain. In this way, the correct components can easier be selected
and clarify the above and calculated specifications.
Based on these requirements, some basic formulas will give
sufficient information, regarding the Minimum Detectable
Signal (MDS), Signal to Noise Ratio (SNR), the Sensitivity and
the Dynamic Range (DR) of the proposed receiver [5]. Finally,
the total cascaded noise figure (NF) of the system is calculated,
whereas it has been assumed NFsys = 4dB for the front-end
module. This calculation mainly proves the performance of the
receiver in practice regarding the assumed noise figure, using
the selected components. A receiver’s noise figure is an
important parameter in determining the weakest signal the
system can process [5].
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3
Nout  FkTBG  ( F )(kT ( Hz ))(
B
)G
Hz
(4)
Turning that to dB, we have that the total output noise power
is given by:
(5)
Nout (dBm)  174dBm  10log10 B  NF  G
In Eq. 4, F gives us the noise factor (Noise Figure NF in dB),
k is the Boltzmann constant, B is the equivalent bandwidth, T
the system noise temperature and G the system gain in dB.
Equation (5) defines the minimum detectable signal (MDS)
and references the output.
The input noise floor is calculated by subtracting the system
gain from the output noise power, thus giving the input MDS in
(6).
MDS  174dBm  10log10 B  NFsys
(6)
The MDS determines the input signal level required to
deliver an output signal to a load equivalent to the output noise
floor, which is directly proportional to the bandwidth as the
equation shows. A specific signal-to-noise ratio of 10 dB for
this application is required to recover the signal with a specific
quality level.
For this carrier-to-noise ratio, we use the path loss equation,
in (7).
It is important to reduce the noise as much as possible, which
means, we need a minimum bandwidth in order to minimize the
noise power. Since the C/N ratio is the ratio of signal power to
noise power, we have that:
G   
C Pr PG
  t t r 0  ,
N Pt
kTBF  4 R 
Pt  100W  20dBW  50dBm,
2
Gr  38dB,
Pr 
(7)
PG
t t Gr
 4 R / 0 
2
C
Sensitivity(dBm)  MDS (dBm)   
 N min
DR  CP1dB,in  MDS
(9)
(10)
Dynamic range is the useful signal level range the receiver
can process within a particular SNR, which is defined as in (10),
the difference in power level between the 1-dB compression
point and the system noise floor, or MDS. The 1-dB
compression point, here referenced to the input, is given by [7]:
CP1dBin  CP1dBout  G  1dB
(11)
For the calculation of the receiver’s dynamic range and the
clarification of its linearity, as a first step, the 1-dB compression
point of the selected LNA was taken into account, which is the
first component after the antenna and together with the mixer,
are the two bottlenecks for the total receiver linearity, gain and
noise figure consequently. The IP3 point is typically about 10
dB above the 1-dB compression point, which is also a good
indicator of an amplifiers linearity [7]. Nevertheless, for our
calculations, the 1-dB compression point was used. Figure 3
illustrates dynamic range based on MDS and 1-dB compression
point referenced to the output [7] [8].
Later, in Section V, it is explained in detail how the 1-dB
compression point is the key parameter for the selection of the
individual components in the receiver chain.
The noise temperature of the antenna is given as Te = 40o K
and the noise temperature of the LNA, using equation 12,
Pr is the power of the carrier signal at the receive antenna.
Equation 6 is known as the link equation and it is essential in
the calculation of power received in any radio link. The term
 4 R /   is known as the Path Loss (Lp). It accounts for the
2
dispersion of energy as an electromagnetic wave travels from a
transmitting source in three-dimensional space [6].
It is also known that the minimum carrier to noise (C/N) ratio
at the input of the receiver is strongly dependent from the carrier
at the antenna, so:
G
C
   carrier at the antenna (dBm)+ (dB) 
T
 N dB
dBm
10 log10 (kT )(
)  10 log10 ( B( Hz ))
Hz
Given the minimum carrier to noise ratio at the input of the
system (10 dB), as well as the bandwidth of 27 MHz and having
calculated the noise temperature of the receiver, the carrier at
the antenna, which will be the minimum signal, can also be
determined.
Now, the minimum detectable signal is right above the noise
floor and we can use that in order to calculate the sensitivity,
which is the absolute power level that gives the required signal
to noise ratio, and the dynamic range, DR, two very important
parameters that influence the linearity of the receiver module.
These are shown below:
(8)
TLNA = 290*(10NF /10 -1) K
(12)
o
Thus, TLNA = 226 K. This results in a total system noise
temperature:
Tsys  Te  TLNA  266o K
(13)
Then, for B = 27 MHz, the noise power at the input of the
LNA would be:
N LNA,in  100.8dBm
(14)
Combining (6) and the given SNR from Table 1, we come to
the result that
(15)
Sensitivity  90.8dBm
This is within the general VSAT requirements range, where
Sensitivity is [-70 dBm, -110 dBm].
We focus on the LNA noise temperature and consequently
the noise figure, see Eq.12, based on the Friis equation:
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4
F = F1 + (F2-1)/G1
(16)
Where F1 and G1 is the noise factor and gain of the 1st stage
(LNA) and F2 is the noise factor of the 2nd stage (rest of the
receiver). Thus, having enough gain, then the noise contribution
of the rest can be considered negligible.
and detailed schematic and description of the LNA can be found
in [19]. A fully differential power combining network is used
to combine outputs of each receiver element, and feed the signal
to an Image Rejection mixer [21] that performs frequency
down-conversion from 18-22 GHz RF to 1 GHz IF with 17-21
GHz external tunable LO.
Figure 4. General super-heterodyne, single down conversion
receiver architecture.
B. Phase shifting element architecture
Figure 3. Dynamic Range.
Easily from (10), the MDS is placed at -100.8 dBm. We come
to the same result using (9), where after the calculations, the
carrier at the antenna, or the minimum detectable signal for this
case, is calculated as -100.8 dBm.
In VI and V, where the architecture and the design
considerations will be discussed, we will be able to calculate
the DR of the receiver, using the total CP1dBin of the system.
For that, we will need the exact specifications of each one of
the components in the receiver’s chain.
IV. BEAMFORMING AND RECEIVER ARCHITECTURE
A. Receiver Architecture
The 18-22 GHz phased-array receiver front-end presented in
this paper is designed to be compatible with the low-IF superheterodyne architecture. The design needs to be optimized in
such a way to achieve the best of the trade-off between gain and
noise/nonlinearity.
As it widely known that the two mostly used receiver
architectures are the direct-conversion and the superheterodyne [9]. In this application, the super-heterodyne, single
down-conversion architecture was chosen, see Figure 4, since
in zero-IF, or direct-detection, even if there is less hardware and
no image problem in the mixer, there are inconveniences that
need to be faced, like LO leakage, DC offset and isolation
imperfection [10]. In our low-IF architecture, the IF (1 GHz) is
far from the DC, there is also no need for the first preselecting
BPF due to the phased array spatial filtering ability, and works
better for high Ka band frequencies [11].
It consists of four RF phase shifting front-ends. Each
contains a self-biased GaAs MMIC LNA, an Analog Variable
Gain Amplifier (VGA) and an Analog Phase Shifter. The LNA
is featuring 22 dB of gain and only 2.5 dB of Noise Figure (NF)
In this specific application, we also managed to reduce the
cost by implementing All-RF beamforming, thus using only one
Image Reject Mixer. That way, we achieved better immunity
from interfering signals and better selectivity. The key element
in this phased array technology, and therefore in our receiver,
is the phase shifter [12]. Phase shifters can be placed at any
stage in the chain. Based on that, phased arrays can be
categorized into four district types: RF-phase shifting, LOphase shifting, IF-phase shifting and digital phased arrays.
Among all the architectures, the RF phase shifting is the most
popular and has been used in many array systems [13].
In the RF phase shifting beamforming, the signals at the
antenna elements are phase-shifted and combined in the RF
domain. The combined signal is then down converted to
baseband using heterodyne mixing as discussed previously.
Since this technique requires only one mixer and there is no
need for LO signal distribution, it usually results in the most
compact architecture among other phased array designs.
Besides that, the architecture is very suitable for building an
array with a large number of channels [14][15].
Another critical part of an N-channel array is the RF
combiner. The RF combiner usually is placed in the center of
the phased array chip and it is easier to design a symmetric
combining network for all channels, see Figure 5a. In contrasts,
LO or IF phase shifting requires an LO distribution network to
feed each mixer. The most important advantage though of the
RF phase shifting architecture over all the other architectures is
the high signal-to-interferer ratio (SIR).
In an RF beamforming receiver the signal combining and the
phase shifting are performed prior to down-conversion by the
mixer. The interferers are filtered out at the RF stage and
therefore a high SIR is achieved. This relaxes the linearity and
the dynamic range of the mixer. Therefore, the All-RF
architecture is chosen in this work. Figure 5 indicates the
complexity of these architectures.
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5
A challenging part of the RF phase shifting process, is the
design or the selection of high performance phase shifters
capable of operating on RF frequencies [12].
Figure 5. Phased array receiver architecture: (a) RF phase shifting,
(b) LO phase, (c) IF phase shifting, and (d) digital beamforming
The IF and LO frequencies must be carefully selected to
avoid image frequencies that are too close to the desired RF
frequencies. This could also degrade the SNR [16].
A system level block diagram, as well as an explanation of
the frequency translation plan can be seen below, in Figure 6.
Later on, the system level design of the receiver in ADS [28],
where single channel as well as four channel receiver
simulations will prove the initial calculations explained in III.
As it is widely known, phase shifters are essential
components in a phased array for adjusting the phase of each
antenna path and steering the beam. Ideally a phase shifter
change the insertion phase (phase of S21) of a network while
keeping the insertion gain (amplitude of S21) constant. The
requirements of phase shifters include large phase-control range
(360o), small phase-shift step size (e.g. 22.5o), low insertion loss
(or even gain) and low variation in loss over all phase states
[17]. The loss and loss-variations of a phase shifter can be partly
overcome using a VGA stage in front of the phase shifter, with
the disadvantage of course of extra power consumption and
larger chip area, explaining the position of each component in
the block diagram below [18].
In Figure 6 we provide a block diagram of the phased array
receiver with the key components in the receiver chain.
To make it clearer, a frequency plan for the proposed receiver
is presented in Table 2 and in order to do so, a tunable LO signal
generator from the lab facilities is used.
Figure 6. 4-Channel Phased Array Receiver Block Diagram.
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6
Table 2. Frequency translation plan
RF
18-19
19-20
20-21
21-22
IF
1-2
1-2
1-2
1-2
LO
17
18
19
20
V. DESIGN CONSIDERATIONS AND ANALYTICAL
CALCULATION
A. Single Channel Receiver
For the frequency domain calculation and in order to prove
the above, Advanced Design System (ADS) was used [22].
Firstly, a single channel receiver with ideal components was
designed and the input signal power was simulated, as well as
the IF output power. The phase shifting capability was checked
and the total NF of the channel has been calculated. For each
individual block, we added indicated values for Gain and Noise
Figure. A single representation of such a channel can be seen in
Figure 7.
Fp.s.  F1 
( F2  1)
G1
(17)
And knowing that NF (dB)  10*log10 ( F ) , (17) will become:
NFp.s. (dB)  10*log10 ( Fp.s. )  10*log10 (1.84)
(18)
NFp.s. (dB)  2.64
We can now plot the achievable gain as well as the input
compression point of this single channel receiver with the given
component characteristics. Below, in Figure 8 , the gain is given
as a function of the input power level of the incoming signal. As
the input signal increases for a practical two-port network, the
output signal increases linearly until distortion product
combines substantially with the fundamental output power. The
result is that distortion products, along with fundamental, are
observed at the output. Figure 8 plots the two-port gain versus
input power level. Low input power values, based of course on
the calculated sensitivity range, provide a constant ratio in
equation 19.
G(dB)  Pout  Pin
(19)
But as the input power level increases, the gain drops (or loss
increases). At a particular input power level, gain drops 1 dB
below small signal gain of equation 17, which we used for the
graph of Figure 8. Given the gain characteristics of each
individual block, the 1-dB input compression point was found
equal to more or less -48 dBm.
From plot in Figure 8, comparing the maximum gain at RF
input power at the sensitivity level, -90 dBm, and the gain drop
by 1 dB, approximately at -48 dBm, we presume that the 1-dB
compression point has this value.
50
45
Having the RF signal placed at 20 GHz center frequency, with
P_RF = [-50, +10] dBm, we also plotted the gain of the receive
chain, see Figure 8, based on each individual block, where the
gain value of the VGA is set to 20 dB, but adjustable, which
means that it can change values within a range when needed.
Furthermore, we know that NFLNA  2.5dB and NFVGA  4dB .
Figure 9 shows the 1-dB compression point, where the input
signal power is set close to sensitivity, from -90 dBm to -20
dBm, while in Figure 10, the output of the this single channel
receiver can be observed, with all the output products present, as
well as the total gain of the receiver channel, regarding the input
RF power and the total calculated noise figure. In order to
generate these plots, we used the harmonic balance simulation
in ADS with center frequency at 20 GHz. Phase shifter’s noise
figure was calculated as in Equation 17-18.
The Image Rejection Mixer’s noise figure is equal to 3 dB.
40
Gain [dB]
Figure 7. Single Channel Receiver with relative Input Power P RF =
[- 50, +10] dBm.
35
30
25
20
-90
-80
-70
-60
-50
-40
-30
Input Power Level [dBm]
Figure 8. Gain versus Input Power, fc = 20 GHz.
-20
The input compression point of the single channel receiver,
using the NF and Gain specifications of the chosen components,
is explained in B, and the formula in Eq. 10. The chosen and
used components can be seen in Table 3. Using Eq. 10, and
considering the mixer as the bottleneck for this design, we can
easily find the input compression point of the receiver.
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7
dBm, higher than our sensitivity and lower than the 1-dB
compression point. Specifically, at IF = 1 GHz, the output signal
power is -20.505 dBm using again the harmonic balance
simulation in ADS.
Table 3. Components Specifications
LNA
[23]
VGA
[24]
17-27
Phase
Shifter
[25]
18-24
I/Q
Mixer
[26]
17-24
Freq. [GHz]
626.5
Gain [dB]
22
20
-4.5
12
1-dB CP
[dBm]
-45.5
- -24.5
-5.5
-10
Output
IF
0
+1
As can be seen from the table above, the total input
compression point of the receiver is -45.5 dBm, at the input of
the LNA, meaning that this is the maximum input signal that the
receiver can process.
Output Power Level [dBm]
-20
-40
-60
-80
-100
-120
-140
20
30
Freq [GHz]
Figure 10. IF Output of the Single Channel Receiver.
0
-10
0
10
40
B. Signal Level Representation of the 4 Channel Rx Module
-20
-30
-40
-90
Output signal power level [dB]
Specifications
-80
-70
-60
-50
-40
-30
-20
Input Power Level [dBm]
Figure 9. System Input 1-dB compression point, fc = 20 GHz.
These first analytical calculations are based on the specific
components, simulating a single channel receiver. In order to
achieve -48 dBm as in Figure 9, we added an attenuator right
after the phase shifter in the simulation of the single channel
receiver chain, in order to compromise with the loss from the
passive phase shifter, and thus, our result to be more accurate.
We can also see the output noise power, delivered to the
matched load, given from (20):
Nout  k Ts  Te  FBG  126.7* G
(20)
Based on this equation, the output noise power is inversely
proportional to the gain. As the input signal level increases, the
gain stays stable, until a certain point (1-dB input compression
point). After that, the gain drops as we saw and the output noise
power starts to increase as the input signal power continues to
increase.
In Figure 10, we can see the output of this proposed module,
for indicated frequencies and input power level -70 dBm, higher
than our sensitivity and lower than the 1-dB compression point.
Specifically, at 1 GHz, the output signal power is -20.505 dBm.
In Figure 10 we can see the mixer output of this proposed
module, for indicated frequencies and input power level at -70
Continuing the system level simulation for the 4-channel
receiver, the improvement in noise figure and gain of the system
can be shown [19].
We tried to simulate the increased power of the output noise
power of the receiver by adding the 4 channels using a
Wilkinson power combiner. We also managed to present the
difference in the input compression point [20].
Following the initial requirements for total Noise Figure of 4
dB, we need an LNA with NF as low as possible, and high gain.
The chosen LNA for the system is a GaAs pHEMT MMIC LOW
NOISE AMPLIFIER, the HMC963LC4 from Hittite. The
amplifier operates between 6 and 26.5 GHz, providing 20 dB of
small signal gain, 2.5 dB noise figure, and output IP 3 of +18
dBm, while requiring only 45 mA from a +3.5 V supply. The
P1dB output power of +10 dBm enables the LNA to function as
a LO driver for balanced, I/Q or image reject mixers. The
HMC963LC4 also features I/O’s that are DC blocked and
internally matched to 50 Ohms, making it ideal for high capacity
microwave radios and VSAT applications. Finally, the
HMC933LP4E Analog Phase Shifter has a typical phase error of
+/- 10 degrees over the frequency range and really low input and
output return loss when we set the at 5 Volts, which helps us for
a more compact power supply system, as can be seen later in the
PCB DC line configuration .
In Figure 11, as indicated, the gain improvement using the 4channel module is provided. As the input power is kept the same,
-70 dBm, the output power combining the four channels is
expected to be larger. From the plot below, (the gain at the input
compression point placed at -48 dBm, is 51.6 dB, while for the
same input power at the single channel module, the gain was
48.6 dB, a difference of 3dB), but the total difference at the
output gain, at the sensitivity level, PRF  100 dBm, is 6 dB
higher, 55.5 dB instead of 49.5 dB for the single channel. This
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8
is also something expectable, since the multi-channel increase at
the IF output, should be 4 times larger, so in terms of dB, this
can be translated as P _ IF4 Rx  4* P _ IF1Rx  P _ IF1Rx  6dB .
The gain compression concept here indicated that as the total
gain is increased, the input compression point should be lower,
decreasing in that way the total dynamic range. Plotting the gain
as a function of the input power, the point where the gain has a
drop of just 1 dB can be identified, and apparently, having higher
gain, this point will be lower. From Figure 8 and Figure 11 we
notice that for a single channel receiver, the 1-dB compression
point is placed at -48 dBm, while using 4 channels, the gain
drops about 1 dB from its maximum value at -53 dBm.
The increase in the output IF power was also proven. Since
the gain is 6 dB higher (assuming ideal combiner), the output
signal power should be 6 dB higher. No change in the NF of the
receiver though is expected, since there is enough gain from the
LNA.
Figure 12. Schematic of the basic 2:1 power combiner.
60
55
Gain [dB]
50
45
40
Figure 13. 4:1 power combiner.
35
30
-100
-90
-80
-70
-60
-50
-40
Input Power Level [dBm]
Figure 11. Gain of the 4 channel receive module.
-30
C. Signal Power Combining
Another important passive circuit for the integrated operation
of the receiver is the Wilkinson power combiner, which adds the
four channels of the system. High-efficiency power combiners
are required to generate high powers.
In Figure 13, we can see the 5 port structure (1 input and 4
outputs), in ADS Momentum, while in Figure 14, Figure 15 and
Figure 16 we provide the S-parameters simulations. The
schematic of this design is also provided in Figure 12. The
results are applied to a power splitter structure, where the port5
is the input and the ports 1, 2, 3 and 4 are the outputs.
A basic 1:4 power divider for phased array application is
shown in Figure 2. A careful observation of Figure 13 shows that
the structure can be subdivided into three 1: 2 power divider,
made in microstrip line, as depicted in Figure 13.
As it can be noticed by the plots in Figure 14, Figure 15 and
Figure 16 below, in the desired frequency range the combiner
provides the gain of each channel (S21, S31, S41, S51),
respectively, the input return loss to be S55, and S11, S22, S33, S44
the 4 output reflection coefficients or output return loss.
When we have a correct power match at each terminal, then
any term should have maximal power. In our case, any output
port of the splitter should have 1 4 of the input power ideally. If
it’s lower, then any loss is caused by insertion loss.
We achieved as minimum input S55 as possible in the desired
frequency band, as the plot below indicates, where specifically,
we took the next results, in Table 4.
The given results can be considered sufficient for this
application.
Table 4. S55 of the Combiner at different frequencies.
F (GHz)
18
20
22
S55 (dB)
-32.8
-21.5
-12.5
The substrate used is shown in Figure 18 and detailed
explanation is provided in VI.A.
It is shown that the performance of the designed signal
combiner is simulated to be within 0.8dB of an ideal combiner.
-30-
9
S-Parameters [dB]
-6
-6.2
-6.4
-6.6
-6.8
18
S31
S21
S41
S51
19
20
21
22
Freq [GHz]
Figure 14. Power distribution in the 4 channels of the
splitter/combiner.
Moving to the output signal representation of the 4-channel
receiver module, having already shown the 6 dB increase in
gain, we also expect an equivalent increase in the IF signal.
In Figure 17, we see the difference in the IF signal power, for
the same input power, -70 dBm, for the 4-channel receiver
module.
Marking the output, it can be seen that for f = 1 GHz, the
output is at -14.503 dBm, which is 6 dB higher than the single
channel output power, as much as the gain increase.
Finally, the total signal-to-noise ratio at the output of the
receiver is calculated. From the initial specifications, Table 1,
SNRIN = 10dB, for single and multi-channel receiver, since the
SNRIN is only dependent on the signal and the noise from the
antenna, which should be the same for any kind of receiver.
The multi-channel structure only increases the SNROUT. From
(21), it is easy to deduct the total SNROUT of the complete system
[7].
FRX 
N * SNRIN , SINGLE _ RX
SNROUT , ARRAY
-10
Where
-15
0
-20
-25
-30
-35
18
19
20
Frequency [GHz]
Figure 15. S55 of the power combiner.
21
22
Output signal power level [dB]
S55 [dB]
-5
FRX is the total noise factor of the receive system.
-40
-60
-80
-100
-120
20
30
Freq [GHz]
Figure 17. IF Output of the 4-Channel Receiver.
-10
S-Parameters [dB]
(21)
-20
-140
-20
0
10
40
The total calculated noise figure of the 5-stage receiver is
found NF = 2.53 dB and the total gain as G = 55.5 dB [21].
-30
S33
S22
S44
S11
-40
-50
18
.
19
20
21
22
Freq [GHz]
Figure 16. Return loss coefficients of the power combiner.
SNROUT 
N * SNRIN , SINGLE _ RX
FRX
. Converting it to dB:
SNROUT [dB]  10*log10 N  SNRIN , SINGLE _ RX  NFRX
SNROUT [dB]  6  10  2.53  13.47 dB
(22)
Compared to the single channel receiver, where,
SNROUT  10  2.53  7.47dB
-31-
(23)
10
The 6 dB difference is obvious, but in the measurements, we
can expect a bit smaller difference, since there will be some loss
in the 4-channel system due to cables and adaptors from the
signal generators to the RF connectors, and thus this loss must
be subtracted from the total SNR. For that reason, the SNR
improvement will be (6-loss) dB.
Below, in Table 5, we provide the system requirements and
the achieved calculated results of the final system for more clear
representation.
the position and orientation of each component, the careful
design of all the transmission lines, with as smooth as possible
transition from non-50 to 50 Ohm dimensions, so as to avoid any
loss there, as well as the low and high frequency decoupling
capacitors, 220pF and 0.2pF respectively. We can also spot the
3 100 Ohm resistors placed at the 3 individual branched of the
Wilkinson Power Combiner.
Table 5. Summarized calculated project Results.
Symbol
Requirements
NF [dB]
4
DR[dB]
 40
Achieved
Results
2.53
47.8
SNR [dB]
13.47
G [dB]
Maximum 55.5
Sensitivity [dBm]
[-70,-110]
-90.8
Figure 18.Substrate definition of the PCB stack.
VI. PCB LAYOUT AND FABRICATION
A. General Considerations
In this section, further details about the procedure and rules
followed will be provided, in order to combine the components
and the designed structures, like RF input and output 50 Ohm
transmission lines, the Wilkinson Power combiner, the bandstop filter that was designed at the output for extra protection for
unwanted signals.
Firstly, the substrate needs to be defined properly. For high
frequency applications like this, the RO3003 was selected from
the Rogers family, providing εr = 3.00. The substrate contains
three metal/conductor layers, as can be seen from Figure 18. The
top layer is the signal path, copper with thickness of 0.035 mm.
Below that level, there is the ground plane, where also additional
slots were added, for surpassing individual DC signals to the
bottom layer, avoiding collision with RF signals, having the
same properties as the top one. RO3003 is placed between the
top layer and the ground plane, with thickness 254 μm. We used
vias, with D = 0.25 mm, between these two layers. In addition,
the material FR4 with thickness = 254 μm was used between the
ground and the bottom signal layer, which is cheaper than
RO3003 and can easily be used for DC signals, providing εr =
4.6.
B. Design Considerations
Figure 19 shows the layout of the top layer of the complete PCB,
including the LNA, VGA, Phase shifter and IR Mixer under Xrays in NXP lab and Figure 19 represents the real prototype.
Many things should be taken into account for this design, from
The four RF inputs, as well as the two IF outputs of the mixer
and the LO input are depicted on the board. The four DC
connectors that control the voltage of the four VGAs are at the
bottom of the PCB, while the two DC supplies at the left provide
3.5V and 5V at the rest of the ICs. Some parts of the DC signals
are passing through the vias to the bottom metal layer and cannot
be seen.
Figure 19. PCB prototype.
With the edge rates of high-frequency signals on boards
increasing dramatically in modern PCB designs, it becomes
more challenging to manage clean power supplies. The number
of decoupling capacitors used for a power delivery system
keeps increasing as well. There are two major problems
regarding the decoupling capacitors. How to determine the
values and the types of decoupling capacitors needed for a
particular design; and where to place the selected capacitors on
board, something that makes it extremely difficult to place and
route capacitors in a limited board space. In fact, the decoupling
capacitor should be added as a DC-block, where we want to
separate the DC voltage but keep the AC signal through it. It
-32-
11
acts like a low-pass filter, where noise caused by other circuit
elements is shunted through the capacitor, reducing the effect it
has on the rest of the circuit. The impedance should be
maintained below a target level to guarantee the power and
signal integrity of a system.
To maintain the impedance of a power distribution system
below a specified level, multiple decoupling capacitors are
placed in parallel and the reason for having more than one
capacitor in parallel are purely practical. If we could have an
ideal capacitor, just having a single one of high value should be
enough to make the supply impedance low across a large
frequency range. In practice, however, capacitors always have
some parasitic series inductance which causes a resonance at a
specific frequency. At that frequency, the impedance of the
capacitor is lower than an ideal capacitor, and very close to zero,
as depicted below in Figure 20.
second capacitor has the same dimensions, value of 0.2 pF and
a resonance frequency at 19.8 GHz, while keeping its impedance
and thus the supply impedance, low from 18 to 22 GHz and
maybe more [30].
There is specific way of placement of that kind of capacitors,
where the via must take as less as possible place in the pad, and
the pads need to have a distance of minimum 100 or 125 μm
from each other and also from the supply pins of the IC.
Once the total circuit is designed in Momentum, there are
some important simulations that can indicate the performance of
the transmission lines from and to the ICs and if they have low
loss across the transmission line, see Figure 21. Because of space
limitation, the lines connecting the RF inputs to the ICs, but also
the lines transferring the signal from an IC’s output to the next
ones input, must be smoothly transformed to 50 Ohm
transmission lines, in order to avoid extra losses.
Figure 21. Smooth transition from LNA to VGA using 50 Ohm
Tline.
We present the above line’s simulation from the LNA to
VGA, with the smooth transition to 50 Ohm and back to the pin
dimension.
In addition, the S21 transmission coefficient is presented in
Figure 22 which needs to be close to zero, for maximum signal
power transfer. The S21 in the range of 18-22 GHz remains
between -0.05 and -0.10 dB.
Figure 20. Self-resonant frequencies of different capacitor values.
However, at frequencies above resonance, the impedance of
the capacitor becomes inductive and therefore quickly rises
above the impedance of an ideal capacitor. By putting multiple
capacitors of different values (and therefore different resonance
frequencies) in parallel, we achieved a low impedance across a
wider frequency range if we choose the capacitors such that
there is always at least one capacitor close to resonance. This
implies that the capacitors should be very close to the supply
pins of the IC, while the “other side” of the capacitor should have
a good connection to ground (usually one or more via to the
ground plane underneath).
From the above information regarding the DC coupling, and
using the Murata software tool [27], two capacitors that need to
be placed in parallel were found, while being able to keep the
impedance low in two important frequency ranges, from DC to
5 GHz, cutting out interfering signals from TV, WiFi, 3G, etc,
and the frequency of interest, from 18 to 22 GHz.
The first one is the 0201 dimension and value of 220 pF
capacitor with specific frequency characteristics, where the
resonance frequency is placed really close to DC [29]. The
Figure 22. S21 of T-Line between LNA and VGA.
C. 18-22 GHz band stop Filter Design
In order to avoid any undesired product at the output of the IF
right after the mixer, we designed a band stop order 3 QuarterWave resonator filter, centered at f = 20 GHz, for extra
-33-
12
protection, since in practice we only added some extra mm of
metal, without important additional cost for the PCB
manufacturing. The IR Mixer, HMC904LC5, has satisfying RF
to LO isolation, typically 40 dB and LO to IF isolation of 20 dB.
Most typically, from simulations we have seen that self-mixing
products appear in the LO  IF area and that is the reason why
the microwave filter was designed with certain frequency
characteristics. Of course, looking at the simulation results, there
is no actual need for the filter at that point, but sometimes the
real time measurements can show differently, due to unexpected
cause.
In order to do so, the fractional bandwidth of the proposed
filter is Δ = 0.15, using 3 quarter-wave stubs (N=3) with 0.5 dB
ripple level. The characteristic impedances of the open-circuited
stubs can be found from Equation 21:
Z0n 
4Z 0
 gn 
A compact design figure of the filter attached to the two IF
ports of the mixer, connected to two RF connectors, can be seen
below, in Figure 24.
(21)
The lumped elements of such filters are replaced with
distributed circuit elements for implementation at microwave
frequencies. The element values are numbered from
generator impedance to
g N 1
g0
at the
at the load impedance for a filter
having N reactive elements. All stubs and transmission line
sections are λ/4 at 20 GHz. The performance of such quarterwave resonator filter can be improved by allowing the
characteristic impedance of the interconnecting lines, Z0n, to be
tunable. Trying this in ADS, we managed to have steeper
attenuation in the design frequency band [22].
In Figure 23 we provide the fully-EM simulation of the band
stop filter. We can see the S11 and S22 parameters, achieving
acceptable isolation in the desired frequency band where IMD
and self-mixing results might appeared.
0
S parameters [dBm]
-10
-20
-30
-40
-50
-60
S11
-70
-80
18
S21
19
20
21
22
Freq [GHz]
Figure 23. EM simulation results of microstrip filter, S21-S11 plot.
Particularly, we can see that in the whole frequency range
from 17 until 22 GHz with the specific filter configuration, the
S11 remains really low and especially at 18.88 GHz it gets as
low as -78.68 dB.
Figure 24. IF outputs driving two band-stop filters.
D. Measurements
The final step for this assignment after the assembly of the
PCB together with the components is to measure it in the lab.
Stability and reliability of the receiver prototype need to be
proven at the lab measurements.
Below, in Figure 25 ,the lab testing pcb with the two upper
channels connected is depicted for this purpose, using two signal
generators as source for 20 GHz center frequency signal, but also
as an external LO source, providing the frequency needed for the
desired IF at the output and 4 DC supply sources, one for the 3.5
V, one for the 5 V, one more for setting the Vctrl of the VGA and
the last one to adjust the Vgg1,2 of the VGA in order to achieve
the desired 170 mA current.
The first step was to check the supply voltages for all the ICs
from the 2-pin DC pads. The first DC pad is controlling the 2 top
channels and the second one the two bottom ones. In that way,
we checked the functionality of the each IC, where we
disconnected the RF and LO signals and we turned on the
supply, first the 3.5 Volts which controls the LNA and the
Mixer, where we saw that they were consuming enough current,
250 mA in total for the three ICs.
The same was done for the 5V supply, controlling the VGA
and the Phase shifter, and we observed 350 mA current
consumption in total. Most of that is due to the VGA, as the
phase shifter has limited current consumption.
-34-
13
below, in Figure 27 and better shielding at the supply, so as not
pick up other signals from the PCB or from other cables. We
also used better cables for the lines carrying the RF and LO
signals going in to reduce the leakage to the outside or picking
up signals from the air. In addition the gain reduction of the
VGA (controlling the Vctrl line), we also used some magnetic
cylinders at the critical supply and RF signal lines.
Figure 25. PCB with upper channels enabled.
As mentioned earlier, the two upper channels were activated,
in order to check the functionality and the reliability of them and
after that we would activate the total 4-channel module.
Initially, the control voltage of the VGA was set low (-4.5V),
which from the datasheet gives the maximum gain, 20 dB. As is
depicted in Figure 25, a power splitter is used, in order to drive
the signal from the RF source to the two upper channels.
Using the spectrum analyzer for the IF output, we saw a lot of
oscillation and noisy signals, while reducing the gain of the
VGA these undesired signals became really low, while some of
them totally disappeared. With LO = 12 GHz and RF = 18 GHz,
we were expecting a signal placed at 6 GHz, but that was really
low. Instead, we observed a signal placed at 5.35 GHz with -8.1
dBm of power and at 10.92 GHz with power of -34 dBm, as can
be seen in Figure 26.
Figure 27. Better quality cables and decoupling at the supply and RF
lines.
After the amalgamation of these steps for improvement of the
PCB performance, we connected the LeCroy oscilloscope and a
probe to observe the signal at the time domain. It was of
significant importance that with every 90 ns, undesired signals
made their appearance, meaning that at 11 MHz there is an
oscillation loop that we managed to identify.
Touching with the probe every line in order to see where this
oscillation is coming from, it came as a result that this was
caused by the 5V supply line, or better the VGA and/or the Phase
Shifter which are controlled by this and the LNA takes also part
at this loop, amplifying that signal as depicted below, in Figure
28.
Figure 26. Result with LO = 12 GHz and RF = 20 GHz.
Turning off the RF signal, nothing changed at the spectrum
analyzer, while doing the same for the LO, all the signals where
down, which means that another signal was mixing down with
the LO in order to get all these “mirroring” outputs, preventing
the RF signal to mix-down. Turning off the supplies and keeping
the LO itself, we could see the one spike at that frequency, while
trying to identify which line (bias, supply, etc.) takes part at the
oscillation. This is typically caused by parasitic coupling of the
output of an amplifier to its input, creating an oscillation.
Another cause is the insufficient decoupling of the supply,
causing an oscillation loop that includes the supply lines
between multiple ICs.
In order to solve this, we needed to effectively filter and shield
the supplies, in order to keep them as close as possible at the
source. For that, we used better quality cables, as can be seen
Figure 28. Identification of 11 MHz oscillation using the LeCroy
oscilloscope.
In order to deal with that, we tried to add extra decoupling for
that oscillation close to the pin of the 5V supply with an 18 pF
capacitor and the noise was significant reduced, see Figure 29.
Of course, more decoupling is needed, in order to avoid this
oscillation, but we couldn’t add this on the circuit in terms of
time.
Finally, there might be multiple oscillations, also from the
3.5V line, that may not be that critical as the above, but
-35-
14
influences the RF signal passing through the blocks as it should
be, because when reducing the gain, the number of spurs reduced
in 3 discrete steps. That means that even if a change doesn’t stop
the instability, it might already have stopped one of the
oscillations and the change might therefore still be useful.
Figure 29. Decoupling the 5V supply line with 18 pF capacitor.
VII. CONCLUSION
Combining two well-known antenna concepts, (I) the
reflector antenna and (II) the phased array, together with the
super-heterodyne, low-IF receiver architecture for RF
applications, we have successfully developed a hybrid approach
for focal plane arrays which is applied to array-fed reflector
antenna applications. This solution combines the best of both
worlds that is the robustness, low-cost and large bandwidth of
conventional reflector-based antenna systems and the flexibility
and adaptivity of phased-arrays. The proposed hybrid receiver
module operates at the frequency window between 18-22 GHz
increasing the receiver linearity and sensitivity, providing high
gain of 55.5 dB and low noise figure of 2.53 dB, which cover
the initial project specifications.
It has been shown that we can use the phased array flexibility
and adaptivity, implementing the RF-beamforming technique to
down-convert the RF signal to IF = 1 to 2 GHz with relative
bandwidth of 27 MHz, thus providing the ability to serve
approximately 37 users with satisfying SNR of 13.5 dB at the
output of the receiver module.
ACKNOWLEDGMENT
E. Recommendations for further research
From the lab tests we carried out, we observed undesired
spurs at frequencies at high frequencies, because of the mixing
with the LO signal. We realized that the 5V supply line, caused
an oscillation every 90 ns, and with extra decoupling we
managed to reduce it.
For further research, it is recommended to identify all the
oscillations that take part at the loop in order to cut them out,
either by extra decoupling or with other techniques depending
on the oscillation factor.
Checking which lines carry the RF and LO signals (e.g.
supply, biasing, etc.) and adding extra decoupling to keep these
signals on the PCB and reduce their impact as close to the source
as possible is something that needs to be carried out. Using the
oscilloscope this can be identified, since it is fast and sensitive
enough to pick up such signals on the supply/control lines.
Another step that could decrease the impact of those
oscillations is the use of better shielded lines for the supply and
especially biasing and gain control lines. The RF and LO cables
were substituted with higher quality ones, to avoid the crosstalk
as well as to prevent signals to leak out or pick up signals from
the air.
Since we managed to identify a first loop and reduce it as
much as possible, causes that we couldn’t guess at the design
process need to be taken care of with the above steps. This strong
oscillation happened at 11 MHz, which is really low based on
the application and the specified components and that is why we
didn’t add extra decoupling capacitors with that resonant
frequency. One last observation comes from the mixer
specifications, which allows LO frequency up to 12.3 GHz, but
it was able to support really low 1-dB compression point, thus
preventing the LNA from saturation at higher input signals. That
means that we might need a second down conversion mixer right
after the first IF output, in order to translate the signal at 1 GHz,
becoming easier for the digital conversion part of the receiver.
The author wish to express his gratitude to the persons who
guided him through this project. Firstly, Mojtaba Zamanifekri
for his daily support on theory, papers, modelling, design and
his overall enthusiasm, his unswerving support throughout the
project and for his critical review of the finished paper.
Secondly, Dr. Ir. Zhe Chen for his ongoing educational insight,
general guidance and tips about modern Transceiver electronics
and simulations in ADS, but also for reviewing my paper. And
lastly Ir. Ad Reniers and Ir. Rainier van Dommele who were the
first to guide me through the lab facilities and show me how realtime measurements for this type of PCBs are being held.
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Low Noise Amplifier, HMC963LC4, Hittite, available online:
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Analog Variable Gain Amplifier, HMC997LC4, Hittite, available
online:
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470° Analog Phase Shifter, HMC933LP4E, Hittite, available online:
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GaAs MMIC I/Q Down converter, HMC904LC5, Hittite, available
online:
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Sim Surfing, Murata, available online:
http://ds.murata.co.jp/software/simsurfing/en-us/index.html#
Agilent Advanced Design System (ADS)”,2014, available online:
http://www.keysight.com/en/pc-1297113/advanced-design-systemads?cc=NL&lc=dut
Multilayer Ceramic Capacitors MLCC - SMD/SMT 220pF 250Volts
5%, Murata Electronics, available online:
http://nl.mouser.com/Search/ProductDetail.aspx?R=GRM21A7U2E2
21JW31Dvirtualkey64800000virtualkey81-GRM21A7U2E221JW1D
Multilayer Ceramic Capacitors MLCC - SMD/SMT 0201 0.2pF
25Volts C0G +/-0.1pF, Murata electronics, available online:
http://nl.mouser.com/Search/ProductDetail.aspx?R=GJM0335C1ER2
0BB01Dvirtualkey64800000virtualkey81-GJM0335C1ER20BB01
-37-35b-