Dynamic-Threshold Logic for Low-Power VLSI Design
Alan J. Drake
University of Michigan
ajdrake@umich.edu
Richard B. Brown
University of Michigan
brown@umich.edu
IBM Technical Contact
Jeffrey L. Burns
Austin Research Lab
jlburns@us.ibm.com
Abstract
Power dissipation is a serious concern for circuit designers. Partially-depleted SOI provides a Dynamic Threshold
MOS transistor that may be useful in reducing static power
and dynamic power. DTMOS can be used to choke off
leakage current and improve performance of transistors
under lower voltage conditions, but suffers from high bodycontact resistance, Miller capacitance, area penalties, and
limited operating voltage. Driving the body with a separate conditioning signal and careful design are proposed
as ways to offset the above problems and still take advantage of DTMOS. A ring oscillator has been implemented to
verify the use of this technology in various configurations.
This information will be helpful in the design of circuits
for datapath elements.
1. Introduction
Power dissipation is a problem of increasing concern to
designers of VLSI circuits. Figure 1 shows the estimated
power dissipation trend of high-performance microprocessors through 2005 taken from the SIA roadmap [1]. Low200
Total Power
Static Limit
Static Power
150
)sttaW( rewoP
100
2. SOI technology
50
0
1999
power microprocessors follow a similar curve. Both the
dynamic and static components are increasing rapidly. The
power dissipation of digital VLSI systems is composed
mostly of dynamic power that is derived from the equation
2 f , where αC is the effective or switching
P dyn = αC L V dd
L
capacitance, Vdd is the power supply voltage, and f is the
operating frequency [2]. Since frequency is associated
with improved performance, the way to reduce dynamic
power is though a reduction of Vdd or the switching capacitance.
Static power is dissipated largely in source and drain
leakage currents whose magnitudes are roughly dependent
on the threshold voltage, VT, and the subthreshold slope of
the transistors used. The higher VT is with respect to the
voltage used to turn off the transistor, the lower the leakage
current will be. Unfortunately, the drive strength of transistors depends on the relationship Vdd-VT so leakage currents are increasing as Vdd and VT scale to maintain drive
current. The roadmap estimates that designs must eliminate 88% of the static power in low-power designs and
81% of the static power in high-performance designs by
2005 in order to return static power dissipation to an
acceptable level, and suggests using multi-VT circuits as a
solution. SOI technology provides for a dynamic-threshold transistor (DTMOS) that can be used to address both
static and dynamic power dissipation by providing both
low-leakage transistors and low-Vdd operation. The pros
and cons of DTMOS and a ring-oscillator experiment
designed to test DTMOS configurations will be described.
2.1. SOI technology overview
2000
2001
2002
2003
2004
Year
Figure 1: Projected power dissipation
2005
The main advantage of SOI is its reduced junction
capacitance due to oxide isolation of individual circuit ele-
ments, resulting in lower-power operation. Additional
advantages are good short-channel effects due to shallow
source/drain junction depth, latchup immunity, and good
soft-error immunity. There are two types of SOI technology, fully-depleted (FD) and partially-depleted (PD). FDSOI fully depletes the silicon under the channel of charge
carriers for the best short-channel behavior in SOI and no
floating-body effects; but it suffers from high source/drain
resistance and poor processing control of VT. PD-SOI,
shown in Figure 2, has good VT processing control but
does not fully deplete the silicon under the gate of charge
carriers, leaving a floating body that affects the performance of the transistor. The floating body causes hysteretic timing patterns, increased subthreshold leakage
currents, and the parasitic bipolar effect. The increased
subthreshold current occurs due to charge accumulating on
the body which lowers VT. The parasitic bipolar effect
occurs when the source, drain, and body are at the same
potential and then the source is quickly pulled down, creat-
Gate–[G]
N+
N+
tSi
[B]
P
O x id e
Oxide
[D]
tOX
[S]
2.2. SOI design techniques
tBOX
Buried Oxide (BOX)
P Substrate–[X]
(a)
G
nFET
S
D
I npn
Cgb
Csb
Csx
Isb
Ibd
Figure 3: DTMOS NFET and threshold-voltage
variation curve. [10]
ing a large voltage drop from the body to the source, which
forms a base-emitter pair. The parasitic bipolar transistor
turns on and conducts current when the device should be
off [3].
In spite of these problems, the potential for 20-35%
improvement in performance at a given power load over
comparable bulk CMOS technology makes SOI the technology of choice for some modern microprocessors [4]-[7].
Cdb
Cdx
B
Cbx
X
(b)
Figure 2: (a) Schematic cross section of a PDSOI NFET. (b) Equivalent circuit model. (Inpn is
the parasitic lateral npn current, the diodes are
the base-emitter and base-collector junction
diodes, Isb and Ibd are impact ionization currents.) [3]
All major circuit families can be implemented in SOI.
Leakage currents can be offset with weak keepers, levelrestoring transistors, or complementary pull-up networks.
Floating body effects are mitigated by one or more of the
following methods: pre-discharging internal nodes, alternately pre-charging and pre-discharging nodes, re-mapping
logic to eliminate large soft nodes, moving parallel transistors closer to ground, and re-arranging or cross-coupling
inputs [7][8]. A small margin may also be added to latch
hold times or timing requirements may be relaxed. SOI
designs can take advantage of current tool sets but there is
a disadvantage in that the tools are structured around bulk
design techniques which do not leverage SOI’s benefits
such as increased series stacks [7].
3. DTMOS
An added degree of freedom in PD-SOI arises from the
floating back-gate which can be controlled as an additional
port. If the gate of the transistor is connected to the body,
see Figure 3, a dynamic-threshold transistor (DTMOS)—
also called Body Controlled MOS and Variable Threshold
MOS—is created [10]. Notice that as the voltage on the
gate rises, the body voltage is forward-biased with respect
(a)
(b)
ref
(c)
(d)
(e)
ref
ref
Logic
Circuits
ref
Boosted Gnd
Vreff
(f)
(g)
(h)
Figure 4: Body-biasing schemes in the literature [12]
to the source and VT drops. At 0 V gate input, VT is the
same as a normal, floating-body transistor. DTMOS transistors have the advantages of low leakage current, high
current drive, and little history effect while operating at
low Vdd. There are also a number of disadvantages: the
body-source and body-drain diodes limit the power supply
voltage to below 0.7 V to prevent forward biasing these
diodes; the high resistance of the body limits the operating
frequency of the circuits; the body-drain capacitor forms a
Miller capacitance that may eliminate any gain from added
current drive; and the body contacts reduce integration levels [11].
The resistive body connection and low integration levels are technology constraints that exist regardless of circuit topology and must be mitigated with careful design.
Such techniques include contacting both sides of devices,
using multi-fingered FETs, and carefully selecting which
transistors need body contacts.
The other DTMOS problems of low supply voltage and
Miller capacitance depend on the circuit topology. A variety of DTMOS body connections in inverters that try to
solve one or more of these problems have been described
[12]–[14]. The n-networks are shown in Figure 4 with the
p-networks being the dual of those shown. Circuits (a)–(j)
extend the operating voltage range and switching speed of
DTMOS transistors [12] [13] and the circuit in (j) is used
to boost the ground and limit the voltage drop across the
circuits to about 0.5–0.7 V [14]. Simulations show that
below 1.3V the delay and power-delay product of inverters
designed using (a)–(i) was better than floating-body or
bulk-like circuits for slightly more power dissipation due to
the added transistor [12]. The configurations of Figure 4
lose some of the DTMOS advantages by adding extra tran-
(i)
(j)
[14]
sistors and thus load capacitance. Since operating voltages
are expected to drop to 0.8 V for low power and 1.1V for
performance chips by 2005, which is only 100 to 400 mV
higher than the 0.7 V for DTMOS, this added complexity
may be unwarranted. The threshold-lowering of DTMOS
at 0.7 V could make it a higher performer than floatingbody circuits at 0.8 V and higher. If the Miller capacitance
is too high, a separate signal, such as a pre-charge, can condition the body voltage without the added transistors
shown in Figure 4. This technique, of driving the body
with a conditioning voltage separate from the gate, will be
referred to as decoupled DTMOS.
The potential of DTMOS was demonstrated in a 32-bit
ALU designed using pass-gate logic [14]. At 0.5V operating voltage, the off-state VT was 0.15V and the on-state VT
was -0.05V while the ALU operated at 260 MHz and dissipated 2.5 mW. The power dissipation, was 1/50 and the
power-delay-product was 1/20 that of a bulk pass-gate
design with similar design rules.
4. Controlled body conditioning
Another problem with DTMOS is that the conditioning
on the body is delayed with respect to the input and a positive body condition is not established until after switching
has begun or completed. A more aggressive approach
involves pre-conditioning the body to establish better
switching conditions before the input arrives. For example, the third inverter in Figure 5(a) has the body being
driven by an inverter controlled by some external signal. It
would be preferable to have the n-transistor body high
before the input goes high to maximize drive current in the
5. Ring-oscillator test chip
Vfb’
Vin
Vout
Vin
Vout
Vin
Vout
Vfb
(a) Ring-oscillator inverters
Vin
Vfb’
Strong N
Strong P
Vout
(b) Positive body conditioning
Vin
Vfb’
Strong P
Strong N
Vout
(c) Negative body conditioning
Figure 5: Ring-oscillator inverters and timing diagrams for body contacts
n-transistor as it pulls down the output as in Figure 5(b).
This may be referred to as positive body condition since
the body voltage positively affects the drive strength of the
transistor. Figur e5(c) shows the opposite case, or negative
body condition, where the n-transistor body is low, causing
a weak transistor trying to pull down the output against a
strong p-transistor. By varying the shape and position of
the body bias, favorable conditions can be obtained to
maximize gain and minimize leakage currents in the transistors. The ideal case would be a positive body condition
only while the transistor is driving the output and a negative body condition at all other times to minimize leakage.
This technique is particularly applicable to synchronous
circuits where clock shaping and conditioning already
takes place and phased signals are readily available. A
separate clock phase, or a phase already generated, can be
routed to the circuits in the datapath to provide biasing in a
manner that enhances the drive of transistors in the circuit
while reducing leakage currents. The challenge will be in
shaping that signal and aligning it for maximum benefit.
A ring-oscillator test macro with 17 ring-oscillators has
been designed in a 0.13 µm, 8 metal layer, 1.2V, copper
PD-SOI process to compare floating-body versus DTMOS
inverters and to explore the effects of body conditioning.
Each oscillator is 41 stages and implements either floatingbody, standard DTMOS, or decoupled DTMOS as show in
Figure 5(a). The signal of each ring-oscillator is output on
a common bus and divider. An additional bus and divider
are provided to output the feed-back body-conditioning
signal in the decoupled DTMOS ring-oscillators. To simulate the effect of shifting the body signal with respect to the
input signal, decoupled DTMOS is implemented with the
output of each inverter stage being fed forward or fed backward to drive the body of another inverter in the ring-oscillator. Figure 6 shows the implementation of feed-forward
one inverter (a) and feed-back one inverter (b). Ring-oscillators implement feeding the body conditioning signal forward from one to seven inverters and backward from 0 to 7
inverters, covering a wide range of body conditions with
respect to the input signal. An inverter was added to drive
the body of the de-coupled oscillators to isolate the body
signal from the gate and remove the extra Miller capacitance of DTMOS. This macro will allow power dissipation
and frequency to be measured and compared between SOI
configurations over a range of power supply voltages and
body conditions. Mature circuit models for body-contacted transistors have recently become available and the
ring oscillator data will help verify the validity of those
models.
s1
s2
s4 0
s4 1
Vb
Vb
Vb
Vb
(a) Feed-back 1 oscillator
s1
s2
s40
s41
Vb
Vb
Vb
Vb
(b) Feed-forward 1 oscillator
Figure 6: Feed-back and feed-forward configurations
6. Conclusion
SOI has become a mainstream technology used for
some modern high-performance microprocessors. It is
seen to be beneficial for performance and power dissipation. The controllability of the body of the transistors
allows for DTMOS circuits to be implemented. DTMOS
provides both low leakage and high current drive but must
be carefully used to offset decreased area and lower supply
voltages. In spite of its limitations, DTMOS shows promise for power-conscious designs. When off, a DTMOS
transistor chokes off leakage current and when on it
enhances its current drive to offset its low operating voltage. A ring-oscillator macro was developed to test the performance of DTMOS in a 0.13 µm, 8 metal, 1.1V, copper
SOI process. Data from this macro will be used in developing low-power circuit styles to use for datapath elements. These circuits will be tested in a multiplyaccumulate unit which will be built in the next phase of
this research.
7. References
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[2] Rabaey, J. M., Digital Integrated Circuits: A Design Perspective, 1st ed Upper Saddle River, New Jersey: Prentice Hall, 1996.
[3] Chuang, C. T., Lu, P. F., Anderson, C. J., “SOI for Digital
CMOS VLSI: Design Considerations and Advances,” Proceedings of the IEEE, vol. 86, no. 4, pp. 689-720, Apr. 1998.
[4] Park, S. B. et. al., “A 0.25-µm, 600-MHz, 1.5-V, Fully
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[5] Canada, M. et. al., “A 580MHz RISC Microprocessor in
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[6] Aipperspach, A. G. et. al., “A 0.2-µm, 1.8-V, SOI, 550-MHz,
64-b PowerPC Microprocessor with Copper Interconnects,” IEEE
J. Solid-State Circuits, vol. 34, no. 11, pp. 1430-1434, Nov. 1999.
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Automation Conference, pp. 892-897, June 1999.
[8] Das, K. K. and Brown, R. B., “Evaluation of Circuit Design
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2000.
[9] Sleight, J., Mistry, K. R., and Antoniadis, D. A., “Transient
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[10] Assaderaghi, F., “DTMOS: Its Derivatives and Variations,
and their Potential Applications,” Int. Conf. on Microelectronics,
pp. 9-10, Nov. 2000.
[11] Bernstein, K. and Rohrer, N. J., SOI Circuit Design Concepts, Boston: Kluwer Academic Publishers, 2001.
[12] Casu, M. R. et. al., “Comparative Analysis of PD-SOI Active
Body-Biasing Circuits,” Proc. IEEE International SOI Conference, pp. 94-95, Oct. 2000.
[13] Gil, J. et. al., “A High Speed and Low Power SOI Inverter
using Active Body-Bias,” Int. Symp. Low Power Electronics and
Design, pp. 59-63, Aug. 1998.
[14] Fuse, T. et. al., “A 0.5V 200MHz 1-Stage 32b ALU using a
Body Bias Controlled SOI Pass-Gate Logic,” ISSCC, pp. 286287, Feb. 1997.