Faculty of Engineering, Architecture and Science
Department of Electrical and Computer Engineering
Course Outline
ELE 714: System Testing and Design-for-Testability
Prerequisites
ELE 504 and ELE 635 and ELE 639
Website
All course related information, announcements and material such as lab
documents are available at the course website. It is student’s responsibility to
check this website regularly.
Compulsory
Texts
1) Digital System Test and Testable Design: Using HDL Models and
Architectures
Zainalabedin Navabi
Publisher: Springer; 2011
ISBN-10: 1441975470
ISBN-13: 978-1441975478
2) Lecture notes from Dr. Kaamran Raahemifar and published scientific papers.
Reference
Text
1) An Introduction to Mixed-Signal IC Test and Measurement
Mark Burns and Gordon W. Roberts
Publisher: Oxford University Press, 2011
ISBN-10: 0199796211
ISBN-13: 978-0199796212
2) VLSI Test Principles and Architectures: Design for Testability
Laung-Terng Wang, Cheng-Wen Wu, Xiaoqing Wen,
Publisher: Morgan Kaufmann; 1st, 2006
ISBN-10: 0123705975
ISBN-13: 978-0123705976
3) Testing of Digital Systems
N. K. Jha and S. Gupta
Publisher: Cambridge University Press , 2003
ISBN-10: 0521773563
ISBN-13: 978-0521773560
4) Electronic Test Instruments: Analog and Digital Measurements
Robert A. Witte
Publisher: Prentice Hall, 2002
ISBN-10: 0130668303
Laboratory
manual
Calendar
Description
ISBN-13: 978-0130668301
ELE 714 Laboratory Manual, Ryerson University.
Faults, errors, and noise are some of major issues facing designs at every
level. This course provides insights into detection and correction of these
significant issues. This course consists of two parts.
The first part focuses on digital circuit test methodologies from algorithm
perspectives to gate- and transistor-level designs. This part targets faults
in combinational and sequential circuit. Test-generation algorithms are
covered. Measurement and calibration issues are discussed in details.
Errors are classified at the circuit level and solutions are provided to
detect and remove the errors.
The second part focuses on digital system design and testing. First,
digital system design is discussed briefly. The systems are those that are
used on a daily basis in industry. On systems that are already built, the
course provides detailed explanation on how to test various parts of the
system. It identifies sources of faults at the system level. These could
include but not limited to DC power lines, Memory testing, and
Input/Output testing. Built-in self-test techniques are discussed. Scan
techniques are explained. Design-for-testability methods are explored at
the system level design.
The laboratory component of this course consists of six labs on test
generation algorithms, fault-free and faulty circuit designs using
MATLAB and Circuit simulation tools. Labs are done in group of two.
This course has a better testable design project due at the end of the term where they apply the knowledge gained through this course. Students are encouraged to either built it or use existing circuit simulation tools. Students learn to observe performance of digital systems, locate the faults, and measure enhanced performance after modifying the design.Course Weight: 1.00
Billing Units: 1
Learning
Objectives
At the end of this course, the successful student will be able to:
1) Interconnect engineering concepts related to errors, faults, and noise in
digital, analog, and mixed-mode circuits and systems for real-world
applications (1c – Engineering fundamentals and sciences).
Assessment Methods: Mid-term examination and final examination,
laboratories and course project.
Assessment Measures: Mid-term and final examination questions. Successful
completion of the laboratories and course project.
2) Improve their capabilities of using the technical knowledge of behavioral
analysis of errors, faults and noise using analytical approaches, and design
the circuits and systems with these issues in mind for particular applications
(4d – Generate solutions). Utilize computer-aided design (CAD) tools for
analysis and design to iteratively improve designed circuits and systems to
meet the design specifications of given applications (4h - Iterations).
Assessment Methods: Final examination, laboratories, and course project.
Assessment Measures: Final examination questions. Successful completion of
laboratory (performance measurements using CAD tools) and course project
where a complex but enhanced circuit or system that utilizes the course
materials is to be developed and designed.
3) Proficiency in use of computer-aided design tools for circuit design and
analyze complex systems. (5c – Use of engineering tools)
Assessment Methods: All laboratories and course project.
Assessment Measures: Successful completion of all laboratories and course
project where a testable circuit or improved circuit/system performance that
utilizes the course materials is to be developed and designed.
4) Write professionally prepared course project report in confirmation to IEEE
format. Project reports will be evaluated on their completeness, English,
and quality of graphics (7a - Written) and (7d - Graphical)
Assessment Methods: Laboratory reports and course project reports.
Assessment Measures: Laboratory reports and course project reports.
5) Understand the importance of reducing noise or errors in circuits and
systems and its impact on the environment (9a – Environment).
Assessment Methods: Mid-term and final examination, laboratories, and
course projects.
Assessment Measures: Mid-term and final examination questions, laboratories
and course project report.
Note: Numbers in parentheses refer to the graduate attributes required by the
Canadian Engineering Accreditation Board. For more information, see:
http://www.feas.ryerson.ca/quality_assurance/accreditation.pdf
Course
Organization
Lecture 3 hrs
Lab: 2 hrs.
Course
Evaluation
Labs: Pre-lab, implementation, and post-lab
reports (Lab 1 has 0%, and each lab
afterwards has 4%)
Project Report: A formal project report + onsite presentation
Mid-term Exam:A 2 hour closed book exam
Final Exam: A 3-hour closed-book exam
Students will be examined for the outcome of their
exam and final exam.
Examination
20%
10%
30%
40%
course projects, midterm
Course Content
Week
1 Topics
Introduction to Testing
Hours
3 What is Testing? Testing terminologies. Types of Faults. Fault Models. Single and
Multiple Stuck-at Faults. Fault Detection and Location. Hardware and Software
Testing. Economy of Test. Online and Offline Testing. Concurrent Testing.
Performance testing. Human Factors. Test Planning and Management.
Automated testing. 2,3 Combinational Circuit Test Generation
6 Critical Paths. Redundancy. D-Algorithm. Minimal Test Sets and Fault Collapsing.
Gate-Level Testable Designs (Reed-Muller Technique). 4 Sequential Circuit Test Generation 3 Expansion Method. Simulation-Based ATPG. Block-Level Testable Designs
(Scan-Based designs). 5 Transistor-Level Testing
3 Test Generation for Stuck-at faults. Timing Verification. Delay Fault Testing. I_ddq
Fault Testing. Transistor-level testable Designs. 6 7, 8 Midterm
2 Layout-Level Testing
6 Initialization. Ground fault testing. Power fault testing. Leakage currents. Supply
currents. Reference voltages. Timing fault testing. Glitches. Loading fault testing.
Open- and short-circuit fault testing. Physical Test Pads. Noise. 9 Digital System Design: An Overview
3 The design process as it applies to digital systems. Application of microcontrollers
in industrial designs. Inter-component communication schemes. Practical
considerations in Digital System Designs such as component selections. Design
Examples. 10, 11 Digital System Testing
The need for digital system testing. Characteristics of digital system faults.
Memory Testing. Input and Output (I/O) Testing. Microcontroller Testing. Fault
6 location techniques. Existing and Emerging Test Standards.
12, 13 System-level Design-for-Testability
7 Built-In Self-Test (BIST). BIST controls and boundary techniques. Scan-based
designs. Linear-Feedback-Shift-Register (LFSR) for Test Pattern Generation
(TPG): Fibonacci and Galois techniques. Application of LFSR for Test Response
Analysis (TRA). Design-for-Testability for Digital Systems. Lab Schedule
Project
Topics
Week #
1 Automatic test Generation Algorithms for combinational Circuits.
2 2 Design-For-testability for combinational designs.
3 3 Automatic test Generation Algorithms for Sequential Circuits.
4 4 Design-For-testability for Sequential designs.
5 5 Testing Transistor Level Designs.
6 6 Review of DC and AC Test Equipment. Measurements.
7 7 Course Project I: Designing a Digital System.
8 Course Project II: Built-in-Self-Test for digital systems.
8, 9 10, 11 Course Developer ______________________________ Date ________________________________
Approved by _______________________________
Associate Chair, Program Director or Department Chair
Date ________________________________