830
IEEE TRANSACTIONS ON ELECTRON DEVICES, VOL. 50, NO. 3, MARCH 2003
Ultimately Thin Double-Gate SOI MOSFETs
Thomas Ernst, Sorin Cristoloveanu, Fellow, IEEE, Gérard Ghibaudo, Senior Member, IEEE, Thierry Ouisse,
Seiji Horiguchi, Member, IEEE, Yukinori Ono, Member, IEEE, Yasuo Takahashi, Member, IEEE, and Katsumi Murase
Abstract—The operation of 1–3 nm thick SOI MOSFETs, in
double-gate (DG) mode and single-gate (SG) mode (for either front
or back channel), is systematically analyzed. Strong interface coupling and threshold voltage variation, large influence of substrate
depletion underneath the buried oxide, absence of drain current
transients, degradation in electron mobility are typical effects in
these ultra-thin MOSFETs. The comparison of SG and DG configurations demonstrates the superiority of DG-MOSFETs: ideal
subthreshold swing and remarkably improved transconductance
(consistently higher than twice the value in SG-MOSFETs). The
experimental data and the difference between SG and DG modes
is explained by combining classical models with quantum calculations. The key effect in ultimately thin DG-MOSFETs is volume
inversion, which primarily leads to an improvement in mobility,
whereas the total inversion charge is only marginally modified.
Index Terms—Double gate, mobility, MOS transistor, MOSFET,
SOI, thin film.
ulations have demonstrated the advantage of DG-MOSFETs
down to 10 nm and below [9], [18], [19]. Impressive compact
and analytical models for DG-MOSFETs, which account for
quantum, volume-inversion, short-channel, and nonstatic effects have been proposed in [20], [21]. Thanks to the excellent
control of the potential, it is admitted that DG-MOSFETs will
presumably represent the final stages of the Si microelectronics
[6], [9], [18], [20].
Starting from this postulate, our work is focussed on extreme
thickness effects. We first compare the experimental characteristics and performance of single-gate (SG) and double-gate
(DG) SOI MOSFETs (Section III). Although the transistors are
long, a clear advantage is observed for DG-MOSFETs, which is
discussed in Section IV, based on self-consistent quantum calculations. The benefits of volume inversion are evaluated in terms
of total charge, average vertical field, and effective mobility.
I. INTRODUCTION
T
HE silicon on insulator (SOI) technology is extremely attractive in terms of performance (high speed, low power
consumption, radiation-hard) and advanced scalability [1]. As
compared to bulk silicon, the architecture of SOI MOSFETs is
more flexible because more parameters—such as thicknesses of
film and buried oxide, substrate doping, and back gate bias—can
be used for optimization and scaling. It is well known that the
short-channel effects are remarkably reduced in ultra-thin SOI
films [1]–[9]. 50 nm long MOSFETs were already processed on
2–6 nm SOI films [10]. But what are exactly the meaning and
the limits of an “ultra thin” film? We will demonstrate in Section II that transistors with a 1nm-thick body can be fabricated
and operated successfully.
A direct application of these extremely thin films is the
double-gate transistor (DG-MOSFET), which makes use of
the volume inversion concept formulated, in 1987, by Balestra
et al. [11]. Recently, these devices have received considerable
attention from the viewpoint of their technological feasibility
and theory. Several approaches for the device architecture have
been explored: gate-all-around (GAA) [7], Delta [12], lateral
epitaxial overgrowth [13], [14], folded-gate [15], Fin-gate [16],
self-alignment [17] etc. Electrostatic and Monte-Carlo sim-
II. TRANSISTOR FABRICATION
N-channel MOSFETs were fabricated at the NTT laboratories (Japan) on low-dose SIMOX wafers; the buried oxide
(BOX) is 62 nm thick. The transistor body, left undoped (initial
cm ), was thinned down to 1–6 nm
doping:
by sacrificial oxidation. The cross-section of a 3-nm-thick SOI
film is shown in Fig. 2(a). The film thickness was measured
by ellipsometry and interferometry with 0.5 nm accuracy.
The control of the thickness uniformity is very difficult. In
particular, 1-nm-thick MOSFETs contain Si holes leading
to “swiss-cheese” effects: the effective length is increased
(because electrons have to bypass Si holes) while the effective
width is strongly reduced.
The source and drain terminals are much thicker (elevated
structures) which allows maintaining reasonable source and
drain series resistances. To minimize the influence of the device
topology, only long channels (from 3 to 30 m) have been
fabricated. Double-gate operation requires quasi symmetrical
front and back gate oxides. Since the BOX cannot be thinned
aggressively, a thick gate oxide (50 nm) has been grown instead.
III. SINGLE-GATE AND DOUBLE-GATE OPERATION
A. Front-Channel Characteristics
Manuscript received May 1, 2002; revised February 19, 2003. The review of
the paper was arranged by Editor S. Kimura.
T. Ernst, S. Cristoloveanu, G. Ghibaudo, and T. Ouisse are with the Institute of
Microelectronics, Electromagnetism and Photonics (UMR CNRS, INPG UJF)
ENSERG, 38016 Grenoble Cedex 1, France.
S. Horiguchi, Y. Ono, and Y. Takahashi are with the NTT Basic Research
Laboratories, NTT Corporation, Kanagawa 243-0198, Japan.
K. Murase was with the NTT Basic Research Laboratories, NTT Corporation,
Kanagawa 243-0198, Japan. He is now with the NTT Electronics Corporation,
Kanagawa 243-0198, Japan
Digital Object Identifier 10.1109/TED.2003.811371
curves are shown for
Typical front-channel current
a 1-nm-thick record transistor in Fig. 1. In spite of the fact that
only 3–4 mono-layers of silicon are involved, the characteristics
are still MOS-like and well behaved. We therefore expect that
the MOS “gene” can be transmitted further down to 1–2 atoms
of Si.
Moreover, since the characteristics look pretty conventional,
it follows that standard techniques can be applied for the param-
0018-9383/03$17.00 © 2003 IEEE
CRISTOLOVEANU et al.: ULTIMATELY THIN DOUBLE-GATE SOI MOSFETS
831
Fig. 1. Drain current versus front gate voltage (in weak and strong inversion),
with the back gate bias as a parameter, in a 1-nm-thick SOI MOSFET (V
50 mV, L = 30 m, W = 100 m).
=
Fig. 3. Front-channel threshold voltage and subthreshold swing versus back
gate bias ( - experiment, - - - model; same device as in Fig. 2). The insert shows
schematically the conventional V (V ) curve (Lim and Fossum model).
The lateral shift of these curves denotes the strong decrease in
with increasing the back
the front channel threshold voltage
. The classical coupling relation [22], can still be
gate bias
applied
(1)
where
lation
is the threshold voltage for back channel accumu-
(a)
(2)
and
is the corresponding back gate bias
(3)
(b)
Fig. 2. A 3-nm-thick SOI MOSFET. (a) TEM cross section showing the upper
gate oxide (50 nm), the silicon film, and the bottom buried oxide (62 nm). (b)
Drain current and transconductance versus front gate voltage, with the back gate
bias as a parameter (V = 50 mV, L = 30 m, W = 100 m).
eter extraction in ultra-thin transistors. We have primarily used
proposed by Ghibaudo
the quasilinear function
[23]. The threshold voltage is given by the intercept with the
horizontal axis and the carrier mobility can be derived from the
slope.
In the following, we will concentrate on 3-nm-thick MOSFETs (Fig. 2) which suffer much less from thickness fluctuaand transconductance
tions. Not only are the current
characteristics reproducible from device-to-device
[Fig. 2(b)], but also they look very similar to those currently
observed in much thicker fully-depleted SOI MOSFETs, except
that the interface coupling effect is reinforced dramatically.
is the depleIn the above equations,
tion charge which can be safely ignored in ultra thin and
is the depleted-film capacitance,
low-doped films,
are front- and back-gate oxide capaciare interface-trap capacitances,
tances,
and
are flat-band and Fermi potentials.
Keeping in mind that the capacitance of such extremely thin
films exceeds the oxide and trap capacitances, (1) reduces to
(4)
data with the theFig. 3 compares the experimental
oretical curve predictable from (1). The overall agreement is
very good: the variation is linear and the slope
corresponds to (4).
Several intriguing aspects should be emphasized.
• The threshold voltage increases steadily in SOI films
thinner than 6 nm (Fig. 4), due to the occurrence of
quantum effects [39].
• The small discontinuity, observed around
(Fig. 3), is due to the formation of a depletion region,
underneath the buried oxide, which increases the apparent
832
Fig. 4.
(V
IEEE TRANSACTIONS ON ELECTRON DEVICES, VOL. 50, NO. 3, MARCH 2003
Threshold voltage and effective mobility as a function of film thickness
= 0 V) .
thickness of the BOX in (4). The dotted, parallel curves,
, have been calculated by assuming the
separated by
substrate either accumulated or inverted.
curve does not reach saturation (i.e.,
• The experimental
) which means that the back interface cannot
be biased in accumulation. This is so because the corre, becomes
sponding back-gate voltage,
very large in ultra thin films and cannot be attained before
the failure of the oxide. In other words, the experiment
covers actually just a narrow region (shown by a circle in the
insert of Fig. 3) of the whole Lim and Fossum curve [22].
The latter feature explains why the SOI transient effects do
not occur in our devices. In thicker fully-depleted MOSFETs, a
current undershoot is normally observed when the front gate is
biased in inversion and the back gate is suddenly switched from
depletion to accumulation [1]. The immediate need for majority
carriers results in a temporary lowering of the front surface potential and drain current [24]; equilibrium is reached through
carrier generation mechanisms. An advantage of extremely thin
devices is that they do not suffer from such transients, simply
because the back interface cannot be driven in accumulation.
For the same reason (i.e., permanent depletion of the back
interface), the subthreshold swing (Fig. 3) is rather constant
mV/dec
(5)
Note that the poor value of the swing is merely explained by
the use of front and back oxides with comparable thicknesses.
, which again is
Fig. 3 shows a dip in the swing for
indirectly due to the substrate depletion effect [i.e., apparently
thicker BOX in (5)]. The substrate depletion is directly observable by probing the back channel and will be clarified in the next
paragraph.
The drain current and transconductance curves of Fig. 2(b)
are expressed by
(6)
(7)
Fig. 5. Inversion charge concentration as a function of front-gate voltage,
deduced from Shubnikov-de-Haas measurements at low temperature.
where
is the front channel mobility, and
is the mobility
degradation factor.
is available from (6), if the
The effective mobility
is determined independently. A widely
inversion charge
accepted technique in thin-oxide MOSFETs consists of split
measurements [25]. However, the tested devices had
rather thick oxides (i.e., very small capacitance values), so
is still
that the conventional equation
valid. This has been verified by measuring Shubnikov-de-Haas
oscillations [26], which yield direct and accurate values for the
density of charge carriers. It is clear from Fig. 5 that, even with
is pertwo activated gates, the linear relationship
fectly obeyed. (This linearity is no longer satisfied in thin-oxide
method becomes more
MOSFETs, where the split
appropriate.) It follows that equation
can be safely utilized to derive (7). Equation (7) then is used
from which the
to construct the function
mobility is extracted [23].
An acceptable value of the electron mobility (210 cm /Vs)
is found in 3-nm-thick MOSFETs, which implies that the
drastic thinning process has not destroyed the quality of the
Si-film and interface. However, the density of defects (oxidation-induced stacking faults essentially) does increase during
thinning, hence the carrier mobility decreases in the film and
at both interfaces. The front-channel mobility is a monotonic
function of thickness (Fig. 4): 260 cm /Vs in 5-nm-thick and
650 cm /Vs in 45-nm-thick transistors. A mobility degradation in 5 nm and 10 nm thick SOI films was also observed by
Mastrapasqua et al. [27].
We have already seen that the back interface of ultra-thin
films is “permanently” depleted. An interesting consequence
is the relative insensitiveness of the transconductance shape
and mobility value to back gate bias [i.e., more or less parallel
curves in Fig. 2(b)]. This is totally different from
the case of much thicker films (45 nm), where the back gate
voltage can induce an inverted or an accumulated back channel:
as the vertical field increases significantly from inversion to
accumulation, the transconductance peak is reduced by a factor
of two and the curves are qualitatively modified [1].
was evaluated from the depenThe series resistance
dence of the mobility degradation factor on channel length.
k
m is far below the
The estimated value
CRISTOLOVEANU et al.: ULTIMATELY THIN DOUBLE-GATE SOI MOSFETS
833
combination of the BOX capacitance and substrate depletion
capacitance
(8)
Fig. 6. Drain current and transconductance versus back gate bias, with the
front gate bias as a parameter (increasing V shifts the curves to the left; V
50 mV; same device as in Fig. 2).
=
Fig. 7. Transconductance versus gate voltage in a 3-nm-thick SOI MOSFET
operated in DG mode (V
0:8V ) and SG modes (front channel with
V = 0, back channel with V = 0, L = 30 m, V = 50 mV, T =
300 K).
'
channel resistance (for the present range of channel lengths
and gate voltages) and does not alter significantly the electrical characteristics. The low series resistance, combined with
the small value of the oxide capacitance, explains why the
transconductance degradation is very limited in strong inverV . Coefficient
tends to increase as the
sion
back gate bias becomes positive.
B. Back-Channel Characteristics
The back channel has been probed by varying the substrate
(back gate) bias, with the front-gate voltage as a parameter
curves match the previously discussed
(Fig. 6). These
front-channel characteristics: strong coupling, linear
variation, constant swing. The effective mobility in the front
and back channels is comparable (Fig. 7) and the transconductance degradation coefficient is very low.
A very distinct feature is observed in the narrow range
V: the drain current exhibits a plateau and
the transconductance drops severely. The reason is that, for
this voltage range, the substrate becomes depleted underneath
from 1 V to 1 V, most
the buried oxide. Increasing
of the incremental voltage drops across the expanding depletion region and no longer serves to raise the drain current.
The back-channel transconductance is affected by the serial
The global effect of substrate depletion can be viewed as
an apparent increase of the BOX thickness, which causes a
transconductance hump to occur. Small back-channel transconductance humps have been observed earlier and used to
asses the doping level of the silicon substrate [28]. In Fig. 6,
the transconductance hump is huge (75%) and indicates a
0.55- m-deep depletion region; the corresponding doping level
cm
is realistic for SIMOX wafers, which
are subjected to oxygen donor formation [1].
In regular SOI MOSFETs, the buried oxide is much thicker
(0.4 m), hence the substrate depletion has a minor effect even
on the back channel. Moreover, the front channel is hardly affected because it is “protected” by the very small ratio between
the thicknesses of the front and back oxides [see (1)–(5)]. In
our devices however, the substrate effect is exacerbated for several reasons: 1) the BOX is relatively thin, 2) the front and
back oxides have equivalent thickness, and 3) the ultra-thin Si
film maximizes the coupling effects. Note also the good agreement between the drop in the front channel swing (from 108 to
70 mV/decade, Fig. 3) and the 75% drop in the back channel
transconductance (Fig. 6).
C. Double-Gate Characteristics
Double-gate operation has been achieved by biasing simultaneously the front and the back gates. The difference in oxide
thickness and threshold voltage has been accounted for by
, where
taking
are the values measured with the opposite gate grounded. This
condition guarantees the symmetry of the vertical field at the
two interfaces.
The experimental curves (Fig. 7) reveal a surprisingly large
advantage for DG transistors: the transconductance peak is
almost four times higher than for operation in single-gate mode.
Measurements on other ultra-thin devices show that while the
transconductance gain DG/SG is not fully reproducible, it
always varies between 250% and 400%. The general trends,
which still need to be confirmed with other DG technologies,
are
• the transconductance decreases more rapidly with gate
voltage in DG-MOSFETs, so indicating a larger value of
;
the mobility degradation factor
• the comparison of the data presented in Fig. 7 (long
channel) and Fig. 8 (shorter channel) shows that the
transconductance gain DG/SG at 300 K tends to decrease
in shorter channels;
• the gain DG/SG in transconductance peaks (i.e., field-effect mobility) increases at lower temperature (Fig. 8) as
acoustic phonon scattering is gradually attenuated.
It is worth noting that 200% (more precisely the sum of
front- and back-channel transconductance) is the gain achievable in thick transistors, where DG operation brings nothing
834
IEEE TRANSACTIONS ON ELECTRON DEVICES, VOL. 50, NO. 3, MARCH 2003
Fig. 8. Front-channel, back-channel and double-gate transconductance peaks
versus temperature in a 3-m-long, 1.5-m-wide, 5-nm-thick transistor.
(a)
but the superposition of the front and back channels, independent from each other. In Section IV, the difference between DG
and SG transistors in terms of current, transconductance, and
mobility is explained based on volume inversion and quantum
arguments.
IV. QUANTUM MODELING
The analysis of the carrier transport mechanisms in ultra-thin
SOI MOSFETs proceeds from the comparison between 1)
physics-based analytical and compact models [20], 2) advanced classical numerical simulations [2], [3], [5], and 3)
quantum simulations [29]–[38]. Since our devices are “long,”
the discussion of short-channel effects and scalability issues
is beyond the scope of this work. To clarify the remarkable
DG-transconductance gain (Fig. 7), the profiles of the carrier
mobility, concentration and electric field across the film depth
are calculated by solving self-consistently the 1-D Poisson
and Schrödinger equations. Similar simulations have been
described earlier [30]–[34], [36], hence we only discuss the
representative case of our 3-nm-thick SG and DG quantum
wells.
A. Potential Profile
The carrier confinement in very narrow potential wells is governed by the wave functions and energy levels of the various subbands. As the film becomes thinner than 10 nm, the energy levels
and their separation increases, making them harder to populate:
the threshold voltage increases (Fig. 4) [39]. The difference between asymmetrical SG and symmetrical DG wells is illustrated
in Fig. 9(a). Two distinct regions of operation are predicted in
3-nm MOSFETs.
1) At low and moderate vertical field (corresponding to
the regions of weak inversion, moderate inversion, and
transconductance peak), the potential well is essentially
thickness-defined. The electrons are confined mainly by
this “infinitely-deep” rectangular well; little additional
contribution arises from the potential profile, which is
quasiflat. The energy levels and the wave functions are
very similar in SG and DG modes.
2) At high electric field (strong inversion), the “triangular”
shape of the film potential becomes more pronounced,
primarily in SG-MOSFETs, and induces additional
carrier confinement. The quantization effects are lesser
in DG-MOSFETs than in SG-MOSFETs [Fig. 9(a)]; the
(b)
Fig. 9. (a) DG and SG potential wells and corresponding energy subbands
in strong inversion. (b) Quantum distributions of minority carriers (strong
inversion) in various subbands of a DG-well (- - - classical, nonquantum
profile).
threshold voltage is therefore slightly lower in DG-mode
than in SG-mode. The attenuated confinement in DG
mode allows several subbands to contribute to carrier
transport [Fig. 9(b)]. By contrast, in SG wells, the
population of the ground level is still overwhelming.
B. Carrier Profile in Ultra-Thin Devices
The “classical” distribution of charge [dotted line in
Fig. 9(b)], defined by the Poisson equation, indicates that more
carriers flow near the two interfaces [11], [29]. The striking
feature obtained by coupling the Schrödinger equation is that
the carrier profile is qualitatively modified: most of the carriers
flow in the middle of the film, not at the interfaces [Fig. 9(b)].
In other words, quantum calculations reinforce the volume
inversion concept as compared to the classical viewpoint.
In SG-MOSFETs, the in-depth electron distribution is rather
symmetrical in weak inversion and becomes more and more
increases in strong inversion (dotted line
asymmetrical as
in Fig. 11). The DG-MOSFET profile illustrated in Fig. 9(b)
can be approximately retrieved by superimposing the two SG
bias applied to
profiles that correspond to the same
either the front or the back gate [33]. The simulations indicate
that, in strong inversion, the total charge in DG-mode is marginally higher than twice the inversion charge in SG-mode (a
few percent difference comes from the slight imbalance in the
threshold voltages). This result is universal and can be simply
predicted using the Gauss’ theorem:
CRISTOLOVEANU et al.: ULTIMATELY THIN DOUBLE-GATE SOI MOSFETS
Fig. 10. Inversion charge versus gate voltage in weak and strong inversion, for
DG and SG modes (t = 3 nm).
in SG mode, or twice as much in DG mode. (Note also that
the formulation of the gate capacitance in inversion mode is,
in general, modified when considering the population of the
various subbands; however, for very thick oxides, the classical
description still holds.)
The variation of the inversion charge with gate voltage is
compared for the two modes in Fig. 10. The subthreshold
swing in DG-mode is ideal (60 mV/decade), far better than in
SG-mode where the existence of front and back oxides with
similar thicknesses is a handicap [see (5)]. In strong inversion,
there is no distinct advantage of volume inversion in terms of
total charge, except for the natural 200% gain. This implies
that the experimental difference (exceeding a factor of 2) in
transconductance between SG- and DG-modes is primarily
related to the carrier mobility rather than to a charge effect.
C. Carrier Mobility in Ultra-Thin Films
The behavior of the carrier mobility in very thin SOI films is
not very well understood. Special mechanisms are expected to
come into play but they may be obscured by imperfections in the
Si-crystal. Above 50 nm, the low-field mobility does not change
with thickness [40]. From 20 nm down to 8 nm, the electron
mobility tends to decrease more [41] or less [27]. Below 10 nm,
several mechanisms are competing [33], [35], [42].
• The size-induced quantization has a beneficial impact on
the mobility. The redistribution of electrons in several subbands causes a simultaneous reduction in the density of
available states, the intervalley scattering rates, and the effective mass [35], [43].
• The carrier confinement increases, leading to enhanced
electron-phonon scattering [33], [35], [44].
• Surface roughness and Coulomb interactions increase
[35], [37]. The carriers can also sense the defects existing
at the opposite Si–SiO interface [35], [41].
• The thinning process may degrade the film and generate
new scattering centers [41], [45].
A promising conclusion is that the carrier mobility may increase in ultra-thin SOI films [33], [35], [42], with a maximum
expected for 3.5 nm [33], [35]. Unfortunately, in current Si and
SOI materials, surface roughness scattering strongly affects the
motion of carriers [46]–[48]. Before an exhaustive model becomes mature, we tentatively use a first-order approach to il-
835
Fig. 11. Quantum profiles of minority carriers and electric field calculated for
a 3 nm thick transistor operated in DG and SG modes. The carrier mobility is
assumed to be severely degraded in the interface areas ( 1 nm, dark grey).
'
lustrate phenomenologically the impact of the carrier and field
distributions. The electric field is negligible in the middle of
the DG-MOSFET where most of the inversion charge is located
(Fig. 11). As electron-phonon and surface-roughness scattering
strongly depend on the field, the mobility is presumably enhanced in the center of the film [see also (10)]. It is also reasonable to assume that, due to surface roughness, the local mobility
nm [46],
is highly degraded over a characteristic length
[47], near each interface (dark-grey areas in Fig. 11).
The in-depth average values of the electric field and carrier
mobility, weighed by the carrier distribution, are
(9)
where
as
and the local, low-field mobility is expressed
(10)
nm and
V/cm.
with
) shows
Integration over the whole film depth (i.e.,
that the effective fields in SG and DG modes are identical for
bias, and the DG mobility is just twice as large
constant
as in SG mode. These average values are well approximated by
(11)
for SG mode and
for DG mode. Besides the
with
gain in , this analysis does not reveal any additional advantage
of volume inversion on mobility.
However, if we assume that the inversion charge does not connm (where
), near
tribute to current over a depth
each interface, a clear difference appears between SG and DG
modes (Fig. 12). Since the average field is much lower, the average field-effect mobility is far higher in DG-mode than twice
the value in SG-mode. This is so because, in SG-MOSFETs, the
vertical field is stronger and many carriers flow in the “rough”
region near the front interface (Fig. 11).
836
IEEE TRANSACTIONS ON ELECTRON DEVICES, VOL. 50, NO. 3, MARCH 2003
V. Le Goascoz (STMicroelectronics), for total support, and to
Professors E. Sangiorgi, F. Gamiz, A. Spinelli, and A. Lacaita
for illuminating discussions.
REFERENCES
Fig. 12. Average values of the electric field and carrier mobility versus gate
voltage, calculated with (9) and (10) for the 3 nm thick transistor of Fig. 2 (DG
and SG modes, 1 nm, t
= 50 nm, t
= 62 nm).
=
An accurate description of the mobility behavior can only
be provided by Monte Carlo simulations by including various
scattering mechanisms in ultra-thin films as well as practical
concerns (strain effects, extra defects, thickness fluctuations,
series resistances). Preliminary computations show that volume
inversion increases phonon-limited mobility, by up to 20%, in
3-nm-thick DG-MOSFETs [49]. The advantage of 3 nm films is
maintained when the effective field is increased and even when
surface-roughness scattering is included in the simulation.
On the experimental side, Hall effect measurements performed in 80-nm-thick DG-MOSFETs did not show any
particular behavior of the mobility [50]. However, recent transport measurements in sub-10-nm films tend to confirm that the
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D. Conclusion
The feasibility and proper operation of ultimately thin transistors, down to 3–4 monolayers of silicon, has been demonstrated
and used to analyze thickness-related mechanisms: strong interface coupling, influence of substrate depletion, quantization
effects. This opens new perspectives for the fabrication of advanced quantum SOI devices.
The operation of ultra-thin transistors in DG mode brings
significant advantages: scalability, ideal subthreshold slope,
high current drive, and excellent transconductance. The gain
in transconductance, as compared to SG operation, has been
explained based on volume inversion, which is extremely
prominent an effect in DG-MOSFETs. It does not modify
directly the total charge but modifies the carrier profile in
the thin film, thus leading to an indirect improvement of the
effective mobility. Our empirical model supports the experiment and allows understanding the mobility enhancement in
volume-inversion DG transistors. However, there are still many
open questions, in particular regarding the quantum transport
in ultra-thin SOI films.
ACKNOWLEDGMENT
The prospective part of this work has been performed at the
Center for Projects in Advanced Microelectronics (CPMA),
Grenoble, France. The CPMA is a multiproject institute
operated by the CNRS, the LETI, and several universities.
Special thanks are due to our colleagues M. Gri (IMEP) and
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Thomas Ernst was born in Toulouse, France, in
1974. He received the M.Sc. and Ph.D. degrees in
electrical engineering from the Institut National
Polytechnique, Grenoble, France, in 1997 and 2000
respectively. While pursuing the Ph.D., he worked
on SOI low-voltage and low-power technologies
electrical characterization, simulation and modeling.
In November 2000, he joined LETI, Grenoble, as a
Research Staff Member. Since then, he is involved in
SiGe:C based strained-channel sub-50 nm MOSFET
devices integration and characterization.
Dr. Ernst received the best paper award at the IEEE SOI conference in 1999
for work derived from his Ph.D. thesis.
Sorin Cristoloveanu (M’91–SM’96–F’01) received
the M.Sc. and Ph.D. degrees in electronics in 1974
and 1976, respectively, and the French Dr.Sci. degree
in physics in 1981 from the National Polytechnique
Institute, Grenoble, France.
From 1975 to 1977, he was an Assistant Professor
at the Ecole Nationale Supérieure d’Electronique
et de Radioélectricité de Grenoble (ENSERG).
He joined the Centre National de la Recherche
Scientifique (CNRS) in 1977 as an Associate
Researcher. He became a Senior Scientist in 1982
and a Director of Research in 1989. In 1989, he joined the Department
of Electrical Engineering at the University of Maryland, College Park, as
an Associate Professor for one sabbatical year. He also worked at the Jet
Propulsion Lab, Pasadena, CA, Motorola, Phoenix, AZ, and the University
of Florida, Gainesville. From 1993 to 1999, he served as the director of
the Laboratoire de Physique des Composants a Semiconducteurs (LPCS) of
ENSERG. Between 1999 and 2000, he was in charge of the creation of the new
Center for Advanced Projects in Microelectronics (CPMA Grenoble). He is the
author or coauthor of 160 technical journal papers (including 22 invited/review
papers) and 290 communications at international conferences (including 52
invited presentations). He is the author or the editor of 13 books, and he has
organized eight international conferences. He has led several research teams
on the electrical characterization and modeling of semiconductor materials
and devices: integrated magnetic transducers, magnetoelectric phenomena,
silicon-on-insulator structures, and hot-carrier effects in short-channel components. He has supervised 37 Ph.D. students and 70 research projects.
Dr. Cristoloveanu has received five Best Paper Awards, the Romanian
Academy of Science Award (1995), and the Electronics Division Award of the
Electrochemical Society (2002). He is a Fellow of the Electrochemical Society.
838
Gérard Ghibaudo (SM’02) was born in France in 1954. He graduated from
Polytechnics Institute of Grenoble, France, in 1979, received the Ph.D. degree
in electronics in 1981 and the State Thesis degree in physics from the same
University in 1984.
He became Associate Researcher at CNRS, Grenoble, in 1981, and is now Director of Research at Laboratories of Semiconductor devices (LPCS/ENSERG
now IMEP/ENSERG). During the academic year 1987-1988, he spent a sabbatical year at Naval Research Laboratory in Washington, DC, where he worked
on the characterization of MOSFETs. His main research activities were and are
in the field of electronics transport, oxidation of silicon, MOS device physics,
fluctuations and low frequency noise and dielectric reliability. During his career
he has been author or co-author of about 196 articles in international refereed
journals, 310 communications and 35 invited presentation in international conferences and 12 book chapters. He is a member of the editorial board of Solid
State Electronics.
Dr. Ghibaudo was or is a member of several technical/scientific committees
of International Conferences (ESSDERC 1993, WOLTE, ICMTS, MIEL 19952004, ESREF 1996, 1998, 2000, 2003, SISC, MIGAS, ULIS, IEEE/IPFA). He
was co-founder of the First European Workshop on Low Temperature Electronics (WOLTE 94) and organizer of eight Workshops/Summer School during
the last ten years. During his career he has been author or co-author of about 196
articles in International Refereed Journals, 310 communications and 35 invited
presentation in International Conferences and of 12 book chapters.
Thierry Ouisse worked under a contract between Thomson-CSF (TCS) and
the Laboratoire de Physique des Composants à Semiconducteurs (LPCS) from
1988 to 1991, the research being aimed at improving the immunity against hot
carrier injection and the radiation hardness of SOI devices. In 1991–1992, he
worked at LETI-CEA, Grenoble, France, where he was in charge of the hot carrier reliability of the SOI CMOS technologies. In 1992, he became a researcher
at the Centre National de la Recherche Scientifique (CNRS). At LPCS, he has
managed the silicon carbide activity from 1992 to 2001, which focused on SiC
devices for high power, high temperature or high frequency applications. He
was also involved in the modelling of SOI-based nano-scaled devices, and has
recently spent one sabbatical year at the Microelectronics Institute of the National Center for Scientific Research “Demokritos” Athens, Greece, where he
was involved in the study of Si nanostructures for light emission. He is now
with the Laboratoire de Spectrométrie Physique (LSP), Grenoble, working in
the field of conducting and light-emitting conjugated polymers.
Seiji Horiguchi (M’85) received the B.Sci., M.Sci.
and Dr.Sci. degrees from Waseda University, Tokyo,
Japan, in 1976 and 1978 and 1997, respectively.
In 1978, he joined the Musashino Electrical
Communication Laboratory, Nippon Telegraph
and Telephone (NTT) Public Corporation. He is
currently a Senior Research Scientist, Supervisor,
at NTT Basic Research Laboratories, Kanagawa,
Japan. Since he started working for NTT, he has
been mainly engaged in research on physics and
technology of MOS devices. During 1987-1988,
he was a Visiting Researcher at Massachusetts Institute of Technology,
Cambridge. His current research interest is in silicon nanodevices such as
silicon quantum wires and silicon single-electron transistors.
Dr. Horiguchi is a member of the Physical Society of Japan and the Japan
Society of Applied Physics.
IEEE TRANSACTIONS ON ELECTRON DEVICES, VOL. 50, NO. 3, MARCH 2003
Yukinori Ono (M’98) received the B.Eng., M.Sci.,
and Dr.Eng. degrees from Waseda University, Tokyo,
Japan, in 1986, 1988, and 1996, respectively.
In 1988, he joined Nippon Telegraph and Telephone (NTT) Corporation, Kanagawa, Japan, where
he has been engaged in the research on physics and
technologies of SiO/Si interfaces. From November
1996 to November 1997, he was a Visiting Scientist
at the Massachusetts Institute of Technology,
Cambridge. Currently, he is a Senior Research
Engineer at Basic Research Laboratories, NTT. His
research interests include physics and technology of Si nanodevices, including
single-electron devices for LSI applications.
Dr. Ono is a Member of the Japan Society of Applied Physics.
Yasuo Takahashi (M’95) received the B.S., M.S.,
and Ph.D. degrees in electronics from Tohoku University, Sendai, Japan, in 1977, 1979, and 1982, respectively.
In 1982, he joined the Musashino Electrical
Communication Laboratories, Nippon Telegraph
and Telephone (NTT) Public Corporation, Tokyo,
Japan. Since then, he has been engaged in research
on physics and chemistry of the surface and interface
of semiconductors. Since 1996, he has been with
Basic Research Laboratories, NTT, Kanagawa,
Japan, where he is a Leader of the Silicon Nanodevice Research Group and
a Executive Manager of the Device Physics Laboratory. His current research
includes quantum physics of Si nanostructure and electronic device applications
particularly to Si single-electron devices.
Dr. Takahashi is a member of the Japan Society of Applied Physics and the
Institute of Electrical Engineers of Japan.
Katsumi Murase received the Dr. Eng. degree from
Kyoto University, Kyoto, Japan, in 1984.
He joined Nippon Telegraph and Telephone Public
Corporation (NTT) in 1974, and started his research
on Si process technology at Musashino Electrical
Communications Laboratories. His research field
at NTT covers materials science of amorphous Si
and the physics and technology of Si single-electron
devices. In 2001, he moved to NTT Electronics
Corporation, Kanagawa, Japan, where he has been
engaged in the development of ultrahigh-speed
InP-based integrated circuits for optical communications.
Dr. Murase is a member of the Japan Society of Applied Physics.