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[6]
[7]
[8]
[9]
[10]
Fig. 4.
Reduction of flatband voltage shift by electron injection from the gate.
annealed at 700 ◦ C for 20 min, there are also a small amount of trapped
ions of 2 × 1012 ions/cm2 that cannot be neutralized by the electron
injection. For the sample annealed at 900 ◦ C for 20 min, as discussed
earlier, the thermal annealing has reduced the number of the trapped
ions to the lowest limit (i.e., 1 × 1012 ions/cm2 ) and, therefore, the
electron injection does not lead to a significant change in the flatband
voltage shift.
IV. CONCLUSION
The effect of Si ions trapped in the gate oxide on the C–V
characteristics and the flatband voltage has been examined through
the thermal-annealing experiments. The flatband voltage shift due to
the trapped Si ions can be reduced drastically by thermal annealing.
For the sample annealed at 250 ◦ C for ∼ 20 min, although only
∼ 0.2% of the implanted Si ions is remaining, it can cause a flatband
voltage shift of as much as ∼ −38 V. However, annealing at 900 ◦ C
for 20 min has reduced the number of the trapped ions to the lowest
limit (∼ 1 × 1012 ions/cm2 ), which corresponds to a flatband voltage
shift of ∼ −0.1 V. Higher annealing temperature or a longer annealing
time does not show any obvious improvement. On the other hand, the
flatband voltage shift is reduced by electron injection from the gate,
indicating that the trapped ions can be neutralized by the electron
injection.
[11]
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capacitance magnitude by charging/discharging in silicon nanocrystals
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Y. C. Liu, “A study on Si nanocrystal formation in Si-implanted SiO2
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D. Gui, and A. L. K. Tan, “Dielectric functions of Si nanocrystals embedded in a SiO2 matrix,” Phys. Rev. B, Condens. Matter, vol. 68, no. 15,
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in Si nanocrystals embedded in gate dielectric,” Nanotechnology, vol. 16,
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vol. 82, no. 2, pp. 200–202, Jan. 2003.
Effect of Source Extension Junction Depth and Substrate
Doping Concentration on I-MOS Device Characteristics
Woo Young Choi, Jae Young Song, Jong Duk Lee,
and Byung-Gook Park
Abstract—Some device design issues of the impact-ionization MOS
(I-MOS) device are discussed in terms of the junction depth of the source
extension region and the substrate doping concentration. It is found that
the source extension region is needed to be as shallow as possible in order
to minimize the avalanche breakdown voltage. Furthermore, it is observed
that the dependence of the threshold voltage of the I-MOS device on the
substrate doping concentration is contrary to that of the MOSFET, which
is an interesting phenomenon. It is related to the junction abruptness
between the channel and the i-region, which is explained by using the
concept of maximum lateral electric field.
Index Terms—Avalanche breakdown voltage, design, impact-ionization
MOS (I-MOS) device, junction depth, maximum lateral electric field,
substrate doping concentration.
R EFERENCES
[1] O. Gonzalez-Varona, B. Garrido, S. Cheylan, A. Perez-Rodriguez,
A. Cuadras, and J. R. Morante, “Control of tunnel oxide thickness in
Si-nanocrystal array memories obtained by ion implantation and its impact in writing speed and volatility,” Appl. Phys. Lett., vol. 82, no. 13,
pp. 2151–2153, Mar. 2003.
[2] G. Molas, B. DeSalvo, G. Ghibaudo, D. Mariolle, A. Toffoli, N. Buffet,
R. Puglisi, S. Lombardo, and S. Deleonibus, “Single electron effects and
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[3] T. Gebel, J. Borany, H.-J. Thees, M. Wittmaack, K.-H. Stegemann, and
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[4] A. Kohno, H. Murakami, M. Ikeda, S. Miyazaki, and M. Hirose,
“Memory operation of silicon quantum-dot floating-gate metal-oxidesemiconductor field-effect transistors,” Jpn. J. Appl. Phys. 2, Lett., vol. 40,
no. 7B, pp. L721–L723, Jul. 2001.
[5] J. von Borany, T. Gebel, K.-H. Stegemann, H.-J. Thees, and M.
Wittmaack, “Memory properties of Si+ implanted gate oxides: From
I. INTRODUCTION
Recently, aggressive scaling down of the MOSFET has aggravated some important problems [1], [2]. The impact-ionization MOS
(I-MOS) device was proposed in order to overcome one of them,
Manuscript received November 10, 2005. This work was supported in
part by the BK21 Program and in part by the Nano-Systems Institute (NSINCRC) Program sponsored by the Korea Science and Engineering Foundation
(KOSEF). The review of this brief was arranged by Editor M.-C. Chang.
The authors are with the Inter-University Semiconductor Research Center
and the School of Electrical Engineering, Seoul National University, Seoul
151-742, Korea (e-mail: claritas@paran.com).
Digital Object Identifier 10.1109/TED.2006.872097
0018-9383/$20.00 © 2006 IEEE
IEEE TRANSACTIONS ON ELECTRON DEVICES, VOL. 53, NO. 5, MAY 2006
Fig. 1. Simulated device structure referring to [7]. Source extension region
consists of plane and cylindrical regions. The shallower the source extension
is, the smaller the radius of curvature becomes, which leads to the reduction of
the avalanche BV. Emax is defined as the maximum lateral electric field at the
edge of the channel.
Fig. 2. Dependence of threshold voltage on source extension junction depth,
when the source voltage is fixed at −5.5 V, and the source voltage needed to
maintain a threshold voltage of 0.6 V.
namely, subthreshold swing less than 60 mV/dec at room temperature
[3]. Its basic concept is the modulation of the avalanche breakdown
voltage (BV) of a gated p-i-n structure in order to control output
current. Up to now, we have proposed a novel biasing scheme based on
device physics [4] and successfully fabricated 130-, 100-, and 80-nm
I-MOS devices [5]–[7]. However, the design issues of the I-MOS
device have not been fully discussed yet [8]. In this brief, we focus
on some critical issues in device design, namely, the effect of source
extension junction depth (xjs ) and substrate doping concentration
(Nsub ) on I-MOS device characteristics. Two-dimensional and twocarrier simulation was performed by a commercially available simulator ATLAS on a 100 silicon substrate. The simulated device structure
refers to the n-channel version of experimental data in [7], which is
depicted in Fig. 1. The simulation was done considering band-to-band
tunneling, impact ionization, Shockley–Read–Hall recombination, and
conventional mobility model. In the case of the impact ionization
model, Selberherr’s model was selected [9].
II. EFFECT OF THE SOURCE EXTENSION JUNCTION DEPTH
Fig. 1 shows the device structure of the I-MOS device presented
in [7]. One of its merits is that the voltage for avalanche breakdown is
reduced with the aid of shallow source extension. The source extension
region consists of plane and cylindrical regions. It is derived from
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Fig. 3. Threshold voltage and maximum lateral electric field with varying
substrate doping concentrations. It is observed that the threshold voltage
decreases as the substrate doping concentration increases, which is contrary
to the MOSFET case.
the planar processes. When a p-n junction is formed by implantation
or diffusion through a window in a mask layer, the dopants will
diffuse downward and also sideways. It has been reported that this
cylindrical region has critical effects on junction, especially for the
avalanche breakdown process [10]. As the junction depth of the source
extension is reduced, the radius of curvature of the cylindrical region
decreases, and, finally, the voltage necessary for inducing avalanche
breakdown also decreases [11]. This reduction of avalanche BV has
no apparent theoretical limit [12]. A continuous decrease in the
radius of curvature leads to a continuous decrease of the BV until
other breakdown mechanisms dominate and carrier multiplication is
therefore no longer an important factor. Because the device structure in
Fig. 1 can form extremely shallow source extension region by adopting
double sidewall spacer [7], the biasing voltage of the source region can
be reduced.
In order to investigate the relationship between the junction depth
of the source extension region and the source voltage, we relied
on device simulation. Fig. 2 shows that the threshold voltage and
the source voltage to maintain constant threshold voltage strongly
depend on the junction depth of the source extension region. When
the threshold voltage was extracted, the drain voltage was fixed at
0.1 V. As the junction depth of the source extension region is reduced
from 120 to 40 nm, the source voltage to maintain the threshold
voltage of −0.6 V is reduced from −5.7 down to −4.9 V. If one
sticks to the source voltage of −5.5 V, the threshold voltage will be
reduced down to 0.1 V. Thus, if we combine the proposed fabrication
method with state-of-the-art shallow-junction formation technologies,
the voltage for inducing the avalanche breakdown is expected to be
further reduced.
III. EFFECT OF THE SUBSTRATE DOPING CONCENTRATION
Inasmuch as the I-MOS device has a gated p-i-n structure, the substrate doping concentration influences the device characteristics. Thus,
a study on the optimal substrate doping concentration is useful and
indispensable to device design. From now on, the effect of the substrate
doping concentration on the device characteristics will be discussed
particularly in terms of the threshold voltage and ON / OFF current
ratio. As a result of the device simulation, a unique characteristic of
the I-MOS device was found for the first time as shown in Fig. 3:
the threshold voltage of the I-MOS device (VTH,I-MOS ) decreases
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IEEE TRANSACTIONS ON ELECTRON DEVICES, VOL. 53, NO. 5, MAY 2006
Fig. 5. Dependence of ON and OFF current characteristic on the substrate
doping concentration. Both ON and OFF currents increase as the substrate
doping concentration becomes higher.
Fig. 4. Additional gate biasing with varying substrate doping concentrations.
The inserted figure shows comparison between the threshold voltage of the
I-MOS device and the MOSFET as a function of the substrate doping
concentration.
as the substrate doping concentration increases, which is contrary to
that of the MOSFET (VTH,MOS ). It is easily understood considering
the fact that the turn-on mechanism of both devices is quite different
each other. In the MOSFET, the threshold voltage is defined as the
gate voltage when the surface potential reaches twice the potential
difference between intrinsic and extrinsic Fermi levels [13], [14]. On
the other hand, the threshold voltage of the I-MOS device is defined
as the gate voltage when the avalanche breakdown begins to occur
between the channel and the source. To understand this phenomenon,
we have adopted, as a criterion, the maximum lateral electric field
(Emax ) when the gate is biased at 0 V as shown in Fig. 1. Because
VTH,MOS has a negative value as shown in the inset of Fig. 4, when
the gate voltage is 0 V, there exists an inversion layer below the gate.
Hence, the lateral electric field has its maximum value at the edge of
the channel. As it becomes higher, smaller increase of the gate voltage
can induce the avalanche breakdown, and vice versa. Fig. 3 shows
that the maximum lateral electric field increases with the increase of
the substrate doping concentration, which results from the junction
abruptness between the channel and the i-region. Therefore, high substrate doping concentration will lead to the increase of the maximum
lateral electric field and finally reduce the threshold voltage of the
I-MOS device. For further analysis, we have compared VTH,I-MOS
with VTH,MOS and found that the former is larger than the latter as
depicted in the inset of Fig. 4. It means that even if the surface potential
reaches an inversion point, additional gate biasing (VTH,I-MOS −
VTH,MOS ) is still necessary to get enough carriers injected from the
source in the I-MOS device. Additionally, with the substrate doping
concentration increased, it becomes harder to form the inversion
layer but easier to induce the avalanche breakdown. Therefore, the
additional gate biasing is reduced as the substrate doping concentration
becomes higher as shown in Fig. 4.
Fig. 5 illustrates the effect of the substrate doping concentration
on the output current. We have found that both ON and OFF currents increase and that the VTH,I-MOS decreases as the substrate
doping concentration becomes higher. Therefore, it can be thought
that the substrate doping concentration should be determined considering the application for which the I-MOS device is used. For example, high-purity substrate is necessary for low-power consumption
(high threshold voltage and low OFF current) and moderately doped
substrate is for high performance (low threshold voltage and high
ON current).
We have studied the effect of the substrate doping concentration on
the I-MOS characteristics in terms of the threshold voltage and the
ON and OFF current. An interesting relationship between the substrate
doping concentration and the threshold voltage was observed, which
was explained by the maximum lateral electric field. Additionally,
it was also found that the substrate doping concentration was an
important design parameter to the device applications—either low
power or high performance.
IV. CONCLUSION
We have studied some device design issues in terms of the junction depth of the source extension region and the substrate doping
concentration. It is found that the avalanche BV can be significantly
reduced by introducing extremely shallow source extension region and
that the dependence of the threshold voltage of the I-MOS device on
the substrate doping concentration is contrary to that of the MOSFET.
The substrate doping concentration should be carefully determined
considering device applications.
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IEEE TRANSACTIONS ON ELECTRON DEVICES, VOL. 53, NO. 5, MAY 2006
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