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IEEE TRANSACTIONS ON ELECTRON DEVICES, VOL. 48, NO. 12, DECEMBER 2001
Low Field Electron and Hole Mobility of SOI
Transistors Fabricated on Ultrathin Silicon Films for
Deep Submicrometer Technology Application
David Esseni, Marco Mastrapasqua, Member, IEEE, George K. Celler, Member, IEEE, Claudio Fiegna, Member, IEEE,
Luca Selmi, and Enrico Sangiorgi, Member, IEEE
Abstract—In this paper, we present a comprehensive experimental characterization of electron and hole effective mobility
( e ) of ultrathin SOI n- and p-MOSFETs. Measurements have
been performed at different temperatures using a special test
structure able to circumvent parasitic resistance effects.
Our results indicate that, at large inversion densities ( inv ), the
mobility of ultrathin SOI transistors is largely insensitive to silicon
thickness ( SI ) and is larger than in heavily doped bulk MOS because of a lower effective field. At small inv , instead, mobility
of SOI transistors exhibits a systematic reduction with decreasing
SI .
The possible explanation for this e degradation in extremely
thin silicon layers is discussed by means of a comparison to
previously published experimental data and theoretical calculations. Our analysis suggests a significant role is played by an
enhancement of phonon scattering due to carrier confinement in
the thinnest semiconductor films.
The experimental mobility data have then been used to study the
possible implications for ultrashort SOI transistor performance
using numerical simulations.
Index Terms—Mobility, SOI MOSFETs, SOI performance, ultrathin silicon films.
I. INTRODUCTION
B
ESIDES the well-known advantages of SOI MOSFETs
in terms of radiation tolerance, latchup immunity, and reduced source/drain capacitances, ultrathin SOI transistors have
recently raised considerable interest for their application below
the 0.1- m technology node because of their scalability [1], [2].
has
In fact, the reduction of the silicon layer thickness
been proved very effective for the suppression of short-channel
effects (SCEs) [3]–[5] and can thus represent a valid alternative
to the increase of the substrate doping normally employed in
is scaled down to
bulk devices [6]–[8]. In particular, when
approximately 5 nm, devices with a channel length of about 40
nm have already been demonstrated using essentially undoped
silicon layers [9], [10]. Furthermore, it has been recently pointed
Manuscript received May 29, 2001; revised July 30, 2001. This work was
supported in part by the Italian MURST (PRIN program).
D. Esseni, L. Selmi, and E. Sangiorgi are with the DIEGM, University of
Udine, Udine 33100, Italy. The review of this paper was arranged by Editor T.
Skotnickz.
M. Mastrapasqua and G. K. Celler are with the Agere Systems, Murray Hill,
NJ 07974 USA.
C. Fiegna is with the Department of Electrical Engineering, University of
Ferrara, Ferrara 44100, Italy.
Publisher Item Identifier S 0018-9383(01)10095-X.
out that an adequate scaling of the buried oxide thickness
of SOI transistors is also important in order to control SCE [11]
and to reduce the threshold voltage fluctuations due to possible
variations [12], [13].
In bulk devices with substrate doping concentrations exceeding 10 cm , as required below the 0.1- m technology
is an appreciable
node [14], the depletion charge density
fraction of the total charge in the semiconductor even at large
. Consequently,
significantly
inversion densities
experienced
contributes to increase the effective field
by the carriers in the inversion layer [15]. Since mobility is a
, especially at high
strongly decreasing function of
values where it is essentially limited by surface roughness scatthrough an
tering [16], then large substrate dopings reduce
[16], [15], besides the obvious
degradation
increase of
caused by ionized-impurity scattering which is observed at low
[16].
For a given inversion density, ultrathin fully depleted SOI dethan highly doped
vices can realize significantly smaller
bulk MOSFETs, thus leveraging possible benefits on low field
, in turn, are known to be very important for
mobility. Large
the current drivability of deep submicrometer devices. In fact,
numerical simulation revealed that a high mobility is essential
to design MOS transistors where the carrier velocity along the
channel can remarkably exceed the bulk-silicon saturation value
[17], [18], thus pushing the device toward its maximum current
drivability which is eventually limited by the ballistic transport
regime [19]–[22].
nm electron
Until now, however, while for
in SOI transistors was shown to have an essentially universal,
bulk-like behavior as a function of a properly defined effective
below approximately 10 nm the experfield [23], [24], for
imental data are not fully consistent [25], [26]. In particular,
degradation [25] raising
some authors observed a drastic
legitimate questions on possible mechanisms that might inherin these extremely thin silicon films. In addiently degrade
tion, to our best knowledge, no hole mobility measurements in
ultrathin SOI MOSFETs have been reported yet.
In this paper, we extend the preliminary results presented in
measurements
[27] and report accurate hole and electron
on SOI transistors for silicon thicknesses down to 5 nm and for
temperatures between 225 K and 375 K. Our results show that
is largely insensitive to
and,
at high inversion densities,
, is remarkably larger than heavily doped bulk
for a given
0018–9383/00$10.00 © 2001 IEEE
ESSENI et al.: LOW FIELD ELECTRON AND HOLE MOBILITY
2843
transistors. At relatively low inversion densities, instead, a more
dependence is observed and
is reduced for
pronounced
at a given
.
decreasing
On the basis of a comparison with previously published experimental and theoretical results, we discuss the physical origin
dependence on
and emphasize the possible effect
of this
of phonon scattering modulation due to the spacial confinement
of carriers in the silicon layer. The threshold voltage dependence
confirms that the silicon thickness affects the electronic
on
structure of the inversion layer.
Finally, we use two-dimensional (2-D) numerical simulations
to estimate whether or not the high mobility of SOI devices at
can bring about an appreciable improvement of curlarge
rent drivability over conventional bulk-MOS transistors.
II. DEVICE FABRICATION AND SILICON THICKNESS
DETERMINATION
Device processing started with Unibond SOI wafers produced
by the Smart Cut Process and featuring a 200-nm (100) Si film
nm. The
over a buried oxide whose thickness was
silicon film was then thinned down to 9, 13, 20, and 60 nm nominal thicknesses through a series of oxidations at 1000 C followed by etching of the sacrificial oxide. Typical thickness confor the thinnest
trol was 1.5 nm that is about 25% variation of
SOI, still acceptable for our study because, as explained below,
individually on the same transiswe were able to determine
tors that were used for mobility measurements. Local oxidation
(LOCOS) tailored to consume the entire Si film provided lateral
isolation.
After LOCOS, simplified processing of n-MOS and p-MOS
devices was adopted. The transistor channel is a p-type
film that was left essentially undoped with a resulting resistivity of 10 -cm corresponding to a doping concentration
cm . The energy of the source/drain implants was
values to make sure the depth of
adjusted to the different
the maximum doping concentration is within the silicon film.
No LDD extensions were used and the formation of the spacers
was also skipped. The oxide thickness at the front-gate was
nm. Fig. 1 is a high-resolution TEM micrograph of
a cross section under the gate for the thinnest Si film.
An accurate determination of the silicon thickness is a mandatory step for this study which is intended to investigate the de. In particular, since a range of final
pendence of mobility on
values was found within each wafer because of the thinning process, the characterization technique described in [28]
on the same
was employed to extract an electrical value for
devices which are then used for mobility measurements.
extraction procedure is based on capacitance-voltage
The
) characteristics, as illustrated in Fig. 2(a). The
(
channel-to-gate capacitance is measured versus the front-gate
with a large, positive voltage applied to the
voltage
which induces an inversion layer at the back
back-gate
interface.
is low enough to switch off the inversion layer at
When
the front-interface [below approximately 0.5 V in Fig. 2(a)],
then the front-gate can modulate the charge at the back-interface
through the series capacitance given by the front-gate oxide and
Fig. 1. High-resolution TEM micrograph of a cross section of a device with
minimum T value. Oxide and silicon film thickness is indicated.
0
Fig. 2. (a) C V measurements for large back-gate voltages V
used to
extract an electrical T according to [28]. The relation used to determine T
from the low V constant capacitance values at low V is also indicated. (b)
Correlation between electrical and ellipsometric T values. Filled symbols are
n-MOS and open symbols p-MOS devices. A very good correlation between the
two T determinations was found.
the silicon film. The value of
can thus be easily extracted
from the corresponding, nearly constant region of the
characteristics. The silicon thicknesses indicated in Fig. 2(a) are
the electrical estimates obtained following the above procedure.
Fig. 2(b) illustrates the comparison between the electrical
values and the ellipsometric measurements performed after silicon thinning but before device processing. A very good corredeterminations was found for
lation between the different
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IEEE TRANSACTIONS ON ELECTRON DEVICES, VOL. 48, NO. 12, DECEMBER 2001
Fig. 3. Schematic top view of the MOSFETs used for measurements.
V and V were measured at the voltage probes and used to determine the
independent of possible series
exact intrinsic drain to source voltage V
resistances. Geometrical dimensions are in micrometers.
both n- and p-MOSFETs. The constant offset indicating larger
ellipsometric than electrical values is consistent with the further
thinning produced by device processing.
In the remainder of this paper we will always refer to the
obtained by
measurements.
electrical value of
III. MOBILITY MEASUREMENTS
Since no elevated source/drain structures were employed in
the device processing, the resulting MOS transistors fabricated
on the thinnest silicon films exhibit quite large series resistances
that could affect the extracted mobility values.
In order to circumvent this difficulty, all mobility measurements were performed on the specially designed MOS structures shown in Fig. 3. The structure is symmetrical with respect
to the channel length direction and two pairs of voltage probes
and
within the channel so that we esallow us to measure
sentially performed four-probe measurements of the transistor
conductance. In fact, we determined the intrinsic drain to source
voltage as
(1)
and then calculated the intrinsic conductance as
. During all these measurements the external
) was adjusted to maintain
mV. We
verified that conductance measurements are not affected by
either switching the two voltage probes or by contacting both
determination is
pairs at once. It is apparent that this
inherently unaffected by possible series resistances.
Once the conductance is known, mobility can be readily calculated as
(2)
are the device length and width, respectively,
where and
while the inversion density is determined directly through gatemeasurements at a frequency of 5 kHz, that we
channel
verified to be low enough to avoid the possible influence of
channel resistance on the measured capacitance [29], [16].
Fig. 4. Measured room temperature electron mobility versus inversion charge
for different T . A comparison with previously published data
density N
for bulk transistors [16] is illustrated.
IV. ULTRATHIN SOI MOSFETS MOBILITY
Fig. 4 shows electron
obtained from our measurements
for different silicon thicknesses and compared with previously
published bulk MOSFETs data [16].
Mobility has been reported as a function of the inversion denbecause, in order to obtain MOSFETs with high cursity
rent drivability, it is particularly important to realize devices that
values at large inversion charges [21]. Hence,
offer high
from a practical viewpoint, it is appropriate to compare different
.
designs of the MOS transistor for the same
Furthermore, it is worth noting that the density of the depletion charge in the fully depleted SOI devices of this work is negrange
ligible compared to the inversion density in the entire
of practical interest (i.e., above approximately 10 cm ). In
fact, the low doping concentration on the silicon film (10
cm ) leads to
of approximately
and
cm for
and
nm, respectively. Consequently, for
in the range of Fig. 4, SOI transistors with different
a given
have essentially the same
and they also have virtually
as the lightly doped bulk MOSFETs of Fig. 4
the same
cm for
cm
where
[16].
The comparison of Fig. 4 shows that at high inversion densiis largely independent of
and consistent with lightly
ties
doped bulk MOSFETs. Furthermore, as a result of a lower
for a given
, SOI devices offer a remarkable mobility improvement with respect to heavily doped bulk MOSFETs. At
, instead, the two SOI devices with the
relatively small
values very close to those of
thickest silicon films exhibit
lightly doped bulk transistors and essentially independent of
, whereas a clear and systematic reduction of
is observed
values.
for the smallest
Fig. 5 illustrates the results obtained for hole mobility. A similar qualitative behavior as for electrons is found but a weaker
dependence at small inversion densities is observed.
V. DISCUSSION
In order to gain some physical insight concerning the
dependence of the electron mobility, in this section we will
ESSENI et al.: LOW FIELD ELECTRON AND HOLE MOBILITY
Fig. 5. Measured room temperature hole mobility versus inversion charge
for different T . A comparison with previously published data
density N
for bulk transistors [16] is illustrated.
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Fig. 7. Measured room temperature electron mobility versus the effective field
E
either at the front-interface (open symbols) or at the back-interface (filled
symbols) for a SOI transistor with T
9:4 nm.
=
Fig. 7 shows the front-gate
for
nm at different
(open symbols) versus the effective field that was calculated as [25], [30]
(3)
where
(4)
Fig. 6. Measured room temperature electron mobility versus inversion charge
for different T . A comparison with previously published data
density N
for SOI transistors [25], [26] is illustrated.
first compare our mobility data with previously reported experbeimental and theoretical results and then investigate the
havior as a function of temperature.
A. Comparison With Previous Experimental Data
Fig. 6 compares our electron mobility measurements with the
data reported in [25] and [26]. For relatively thick silicon layers
values are very consistent (for the sake of
we found that all
around 50 nm are not
clarity the data from [25], [26] and
below approximately 10 nm the
included in Fig. 6), but for
degradation that
data reported by Choi et al. exhibit a drastic
might indicate a poor quality of the silicon film as suggested in
values reported by Toriumi et al. are in
[25]. Instead, the
reduction
very close agreement with ours, confirming the
at low
.
with decreasing
, it was suggested by
As for this mobility dependence on
the centroid of the inverToriumi et al. that, since for smaller
reduction
sion charge gets closer to the back-interface, then
could be mainly due to additional scattering mechanisms at this
back-interface whose quality could be poorer than the front-interface.
In order to assess a possible mobility degradation induced
at the
by the proximity of the back-interface, we measured
and also
front-interface for different back-gate voltages
at the back-interface.
is the oxide field at the back-interface and we have assumed the
where
and
are the
simplification
front- and back-gate oxide capacitances, respectively.
is the flat-band voltage at the back-gate and all other symbols
in (3) and (4) have their standard meaning. We verified that the
value calculated with (3) is in very close agreement with
the average electric field in the inversion layer weighted over the
carrier concentration that is obtained by numerical simulations
with a coupled Schrödinger-Poisson solver [31].
As can be seen in Fig. 7, the data obtained for different
lay essentially on the same curve even if negative
values
tend to push the centroid of the inversion layer farther from the
back-interface. These results on the one hand argue against an
important role of additional scatterings caused by the proximity
of the back-interface in our devices, on the other hand indicate
the effective field is still a physically meanthat for a given
ingful concept also in ultrathin SOI transistors.
Fig. 7 also reports the mobility extracted when the inversion layer is induced at the back-interface (filled symbols) for
two different values of the front-gate voltage. The determination of the inversion charge and hence mobility for these bias
conditions corresponding to a back-interface conduction can be
carried out by means of an experimental procedure that will
be more thoroughly explained elsewhere. The effective field
was obtained by means of numerical simulations accounting for
poly-depletion and subband quantization in the silicon film [31],
because the presence of the thin front-gate oxide makes it questionable the application of a simple expression as in (3). As can
of the back-interface is essentially the same
be seen, the
as the front-gate mobility thus demonstrating that the quality
of the thermally grown back-interface produced by a Smart-Cut
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IEEE TRANSACTIONS ON ELECTRON DEVICES, VOL. 48, NO. 12, DECEMBER 2001
Fig. 8. Measured room temperature electron mobility versus inversion charge
compared with the results of numerical simulations reported in
density N
[34].
process is comparable to that of the front-interface fabricated
during a standard device processing.
Similar front- and back-interface mobility measurements per-nm devices led to very similar results
formed for the
confirming that in our devices there is no clear evidence of a
degradation caused by the interaction of carriers
significant
with the back-interface.
B. Modulation of Phonon-Scattering and Mobility
Temperature Dependence
Besides possible nonidealities of either the silicon film or the
with decreasing
is also
back-interface, a reduction of
expected because a narrower confinement of the carriers in the
space,
real space implies a delocalization in the reciprocal
which increases phonon scattering.
This effect has been originally elucidated for phonon scattering in quantum wells [32], [33] and recently discussed by several authors for SOI MOS transistors [34]–[37]. Furthermore, it
is exactly the same physical mechanism responsible for the
dependence of phonon limited mobility in bulk MOSFETs [38].
Fig. 8 compares our experimental data with numerical simuand
nm. In these simlations reported in [34] for
reduction for decreasing
at small
is
ulations, the
due exclusively to the above mentioned enhancement of phonon
scattering due to spacial confinement. The experimental mois reduced from 50 to apbility reduction observed when
proximately 10 nm is reproduced fairly well by numerical results.
has also been investiThe temperature dependence of
gated in the range between 225 K and 375 K. Besides the clear
practical interest, the analysis of the temperature dependence
can also help identify the dominant scattering mechanisms limiting mobility for a given bias condition. Fig. 9(a) shows
for
nm versus the inversion density and for different
values the curves exhibit
temperatures. At relatively small
an almost rigid vertical shift (in logarithmic scales) indicating
variations with around room temperature
that the relative
. Similar results have been found
are nearly independent of
values. Fig. 9(b) reports mobility versus
also for different
showing that, in the studied
temperature for
Fig. 9. (a) Measured room temperature electron mobility versus inversion
charge density N
for different temperatures. A fairly rigid shift of the (in logarithmic scales) is observed at low N
values. (b) Measured electron
mobility versus temperature for different T and for N
2 10 cm .
A power law with an exponent of approximately 1.4 is found in the explored
temperature range.
0
= 2
temperature range, mobility exhibits a
dependence which
behavior observed for phonon limited mois close to the
bility in bulk MOS transistors [16].
Both the temperature dependence of Fig. 9(b) and the quantitative agreement with numerical simulations illustrated in Fig. 8
suggest that the enhancement of phonon scattering due to cardependence of
rier confinement plays a relevant role in the
at least for
down to approximately 9 nm and around
room temperature. On the basis of our data we cannot rule out
additional mechanisms for thinner silicon films or for very low
temperatures which strongly reduce phonon scattering.
Finally, as an additional independent indication that the electronic structure of the inversion layer is affected by the silicon
for the
thickness, Fig. 10 reports the threshold voltage
n-MOS devices as a function of the silicon thickness. In order to
of the mobility dependence
rule out a possible influence on
, in the data of Fig. 10 the threshold voltage was simply
on
characteristics and it
calculated by the integration of the
cm .
is defined as the gate voltage that induces
with decreasing
is clearly observed in
The increase of
reduction with dethese devices because the counteracting
caused by the reduction of the depletion charge is
creasing
negligible when the doping of the silicon layer is as low as 10
ESSENI et al.: LOW FIELD ELECTRON AND HOLE MOBILITY
Fig. 10. Measured (symbols) and simulated (dashed lines) threshold voltage
(V ) versus silicon thickness for n-MOS transistors. V is defined as the gate
voltage inducing an inversion density N
= 2 1 10 cm .
TABLE I
MAIN TECHNOLOGICAL PARAMETERS OF THE SOI AND BULK MOSFETS
FEATURING A 70-nm GATE LENGTH. PERFORMANCE IS COMPARED BY
MEANS OF 2-D NUMERICAL SIMULATIONS
cm [39], [40]. The
dependence of
is due to the increase of the electron eigenvalues within the extremely thin silicon film as confirmed by the good agreement with the numerical calculations obtained with a Schrödinger-Poisson solver
[31].
VI. DEVICE IMPLICATIONS
In Section IV, we have experimentally demonstrated that ultrathin SOI transistors can achieve higher mobility than heavily
doped bulk devices because the former can realize a lower
for a given inversion density. In this section we will try to assess
the possible improvements of current drivability due to a higher
mobility, in the sub-0.1- m technology range.
To this purpose, the intrinsic performance of ultrathin SOI
devices with 70-nm gate length has been compared with that
of bulk n-MOSFETs by means of hydrodynamic device simulations [41]. The main technological parameters used for the
two transistor designs are summarized in Table I. Series resistance effects have been deliberately minimized by assuming
ideal contacts extended over the entire source/drain regions with
the exception of the under-diffusion below the gate. A midgap
Fermi level gate material is assumed for the thin SOI devices in
order to achieve the same target threshold voltage as the bulk
n-MOSFET used for the comparison. Quantization effects are
accounted for with the model of Van Dort et al. [42]. The accuracy of this approach in reproducing the inversion charge of
SOI devices was verified comparing simulated to experimental
characteristics of the large area transistors used for mobility characterization.
degradation at the Si-SiO
As for mobility, the model for
interface proposed in [43] has been adopted, with slightly modified parameter values in order to improve the fit to the experof heavily doped bulk devices [16] (
imental
2847
Fig. 11. Experimental and simulated effective mobility for highly doped
bulk and thin-SOI MOSFETs. Parameter tuning was necessary in order for
the mobility model to fit experimental data. The increase of SOI device
is indicated.
cm ) up to high
. Furthermore, in the
case of the 5.2-nm SOI device, the low-field maximum mobility
was reduced to 1000 cm /Vs to match our experimental results.
The results of these empirical adjustments are shown in Fig. 11
illustrating that the experimental mobility increase of SOI devices is quantitatively reproduced by simulations.
This simulation approach is believed to provide realistic renm because first-order nonsults for MOSFETs with
stationary effects such as carrier heating and velocity overshoot
are accounted for. Ballistic effects (occurring when the channel
length becomes comparable to or shorter than the electron mean
free path) are not accounted for in these simulations. However,
this should not cause relevant errors even for the shortest simulated devices. In fact, the calculated velocities reported in the
following do not exceed the upper limit set by quasi-equilibrium
diffusion from the source in the ballistic regime [19], [22].
The results of our simulations point out that, in order to compare the current drivability of SOI versus bulk structures, the
effect of two counteracting factors must be considered.
Fig. 12(a) shows the simulated average electron velocity along the channel for the two devices biased at
V. The work function of the SOI transistor
was adjusted to have the same off current as the bulk device
1 nA/ m for
V. As a consequence of different 2-D electric field patterns and different mobilities within
the channel, different profiles of average electron velocity are
of SOI
obtained. In particular, the increased low-field
devices leads to a higher electron velocity near the source of
the device. The lower velocity in the drain region, instead, is
due to smaller maximum longitudinal field at the drain end of
the channel. However, the SOI design of the transistor with an
essentially undoped silicon film implies that the centroid of the
inversion layer is farther from the Si-SiO interface than in the
highly doped bulk MOSFET. This electrostatic effect results in
a degradation of the control capacitance of the SOI device for
a given oxide thickness which is illustrated in Fig. 12(b) and
is reduced.
becomes progressively more severe when
In the case of the 70-nm long device simulated in this work
the increase of the electron velocity at the source and the reduced control capacitance tend to cancel out. In fact, when bulk
, essentially the
and SOI devices are compared at the same
(i.e.,
for
V) was
same on-current
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IEEE TRANSACTIONS ON ELECTRON DEVICES, VOL. 48, NO. 12, DECEMBER 2001
samples the proximity of the back-interface does not play a relevant role in the mobility reduction observed at the smallest
.
Instead, the comparison with numerical simulations and the experimental temperature dependence indicate that an increased
phonon scattering due to spacial confinement in the silicon layer
dependence
could be an important ingredient to explain the
of mobility at least in the explored temperature range and for
silicon thicknesses down to approximately 9 nm.
improvement of SOI
Finally, the possible impact of the
devices on the current drivability of 70-nm gate length transistors was discussed by means of 2-D numerical simulations.
Within the predictive capabilities of the models used for the
, the improved
analysis, our results suggest that, for a given
mobility and the degraded control capacitance of SOI transistors
as
tend to compensate leading to approximately the same
bulk MOSFETs.
ACKNOWLEDGMENT
The authors would like to thank F. H. Baumann for providing
the TEM micrograph. They also acknowledge the help of the
staff of the Murray Hill Silicon Fabrication Research Lab, especially F. Klemens and W. Mansfield. Encouragement and support from S. Hillenius, J.T.C. Lee, C. Rafferty, and M. Banu are
also gratefully acknowledged.
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Fig. 12. (a) Simulated electron average velocity along the channel of thin-SOI
and bulk L
70-nm devices biased at V
= V
= 1:5 V. I
is
1 nA/m for both transistors. The velocity increase of SOI device is indicated.
(b) Simulated gate to channel capacitance C
for large devices corresponding
to thin-SOI and bulk technologies. T
= 1:5 nm and 3:6 nm are representative
of the 70-nm and 180-nm technology nodes.
=
found, so that, within the predictive capabilities of the model,
the current drivability of the two MOSFET designs turned out
to be very similar.
VII. CONCLUSION
In this paper, we have presented an extensive experimental
study of electron and hole mobility in ultrathin SOI devices. Our
values ranging from approximately
measurements span over
50 nm down to 5 nm and over the temperature range of applicative interest between 225 K and 375 K. A special test structure
was used to circumvent possible effects of series resistance on
.
the determination of
At large inversion densities both n- and p-type SOI MOSFETs exhibit mobilities which are very similar to those of lightly
range. When compared
doped bulk transistors in the entire
to heavily doped bulk devices suitable for deep submicrometer
technologies, ultrathin SOI transistors can lead to a remarkable
mobility improvement for a given inversion density because the
negligible depletion charge of SOI devices results in a significantly smaller effective field.
, a neat, systematic mobility reducAt relatively small
is observed. The investigation of the
tion with decreasing
mobility dependence on the back-gate bias suggests that in our
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David Esseni received the Laurea degree and the
Ph.D. degree in electronic engineering from the
University of Bologna, Italy, in 1994 and 1998,
respectively.
In 1999, he became an Assistant Professor at the
University of Udine, Italy. During 2000, he was a
Visiting Scientist at Bell Labs, Lucent Technologies,
Murray Hill, NJ. His research interests include
characterization techniques for electrical parameters
in MOS devices and several aspects related to
hot-electron in MOSFETs and Flash EEPROMs.
In particular, he has investigated low voltage and substrate enhanced hot
electron phenomena with an emphasis on their practical implications for
Flash EEPROM devices. More recently, he was involved in the experimental
characterization and modeling of low-field mobility in ultrathin SOI MOSFETs
and in the experimental investigation of the physical mechanisms responsible
for thin oxides degradation.
Marco Mastrapasqua (M’91) received the Doctor
of Nuclear Engineering degree (summa cum laude)
from the Politecnico di Milano, Milano, Italy, in
1990.
In 1990, he worked at the Center for Quantum
Electronics and Electronics Instrumentation of the
National Research Council, Milano, on silicon
single photon detector. From 1991 to 1994, he was
consultant and Post-Doctoral member of Technical
Staff at AT&T Bell Laboratories, Murray Hill, NJ.
During 1995, he was Visiting Scientist, Department
of Physics, Eindhoven University of Technology, Eindhoven, The Netherlands.
Since 1996, he is Member of Technical Staff, High Speed Electron Device,
Agere Systems (formerly Lucent Technologies, Bell Laboratories), Murray
Hill. His research interests include SiGe bipolar transistor and novel devices
on SOI.
George K. Celler (M’86) received the M.Sc. degree
from the University of Warsaw, Warsaw, Poland, and
the Ph.D. degree in solid state physics from Purdue
University, West Lafayette, IN.
He is Chief Scientist at SOITEC/USA, Peabody,
MA. Before his current assignment, he spent 25 years
at Bell Laboratories, Murray Hill, NJ, where he was
Distinguished Member of Technical Staff and a Technical Manager. He has investigated interactions of intense light beams with materials, laser annealing and
rapid thermal processing of semiconductors, formation of silicon-on-insulator structures and their applications in electronics and
MEMS, and also diffusion phenomena in Si and silicon dioxide. Between 1988
and 1996, he lead a large team that was developing advanced lithography for
deep submicron applications. He has published over 170 articles, edited five
books, and was issued 14 patents.
Dr. Celler is a Fellow of the American Physical Society and of The Electrochemical Society, and a member of the Materials Research Society. He received
the 1994 Electronics Division Award of The Electrochemical Society, and two
Bell Labs President’s Gold Awards (in 1999 and 2000).
2850
Claudio Fiegna (M’99) was born in Bologna, Italy,
in 1963. He received the Laurea and Ph.D. degrees
in electrical engineering from the University of
Bologna.
From 1989 to 1992, he was with the Department
of Electronics, University of Bologna, working in
the field of electron devices. In particular, he has
worked on the study and characterization of latchup
in CMOS technology, characterization and modeling
of hot-electron effects in MOSFETs and Monte
Carlo device simulation. From July 1992 to July
1993, he was Visiting Researcher at the Toshiba ULSI Laboratories, Kawasaki,
Japan, where he was engaged in the study of ultra-small MOSFETs. In 1994,
he was appointed Research Associate at the University of Ferrara, Italy, where
he is presently Associate Professor of electronics.
Luca Selmi was born in 1961.
In 2000, he became Full Professor of electronics
at the University of Udine, Italy. During 1989-1990,
he was a Visiting Scientist at Hewlett Packard
Microwave Technology Division, Santa Rosa, CA.
His research interests include characterization and
simulation of silicon devices, with emphasis on
Monte Carlo transport techniques and hot carrier
effects in MOSFETs and nonvolatile memory cells,
leakage currents and reliability of ultrathin oxides,
device optimization. These activities have been
conducted in cooperation with international research centers such as Bell Labs,
IBM T. J. Watson Research Center, Philips Research Laboratories, INPG, and
LETI Grenoble. He coauthored approximately 90 papers, including 18 IEDM
papers.
Dr. Selmi was a member of the IEDM technical subcommittee on “Modeling
and Simulation” in 1995–1996. Since 2001, he helds the same position in the
“Circuit and Interconnect Reliability” subcommittee.
IEEE TRANSACTIONS ON ELECTRON DEVICES, VOL. 48, NO. 12, DECEMBER 2001
Enrico Sangiorgi (S’85–M’95) was born in Faenza,
Italy, in 1954. He received the Laurea degree in electrical engineering from the University of Bologna,
Italy, in 1979.
In 1993, he was appointed Full Professor of
electronics at the University of Udine, Italy, where
he started the Electrical Engineering Program. Since
1985, he has been a Consultant to Bell Laboratories,
Lucent Technologies, Murray Hill, NJ, where he
has been a Resident Visitor for more than three
years. In 1983, 1984, and 1991, he was a Visiting
Scientist at the Center for Integrated Systems, Stanford University, Stanford,
CA. His research interests include the physics, characterization, modeling, and
fabrication of silicon solid-state devices and integrated circuits. In particular,
he has been working on several aspects of device scaling, its technological,
physical, and functional limits, as well as device reliability for silicon MOS
and bipolar transistors. In order to tackle and eventually overcome the hurdles
of device scaling, he has devised and developed several original concepts and
methods in the characterization and modeling of nanoscale silicon devices.
He coauthored 26 IEDM papers and more than 140 papers on journals and
refereed conference proceedings.
Dr. Sangiorgi has been an Editor of the IEEE ELECTRON DEVICE LETTERS
since 1994. He has been a member of the Technical Committees of several International Conferences on Electron Devices: IEDM (1991-1993), ESSDERC,
INFOS, etc.