TPS70358M
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DUAL-OUTPUT LOW-DROPOUT VOLTAGE REGULATORS
WITH POWER UP SEQUENCING FOR SPLIT VOLTAGE DSP SYSTEMS
FEATURES
1
•
•
•
•
•
•
•
•
•
•
•
•
Dual Output Voltages for Split-Supply
Applications
Selectable Power Up Sequencing for DSP
Applications
–55°C to 125°C Operating Temperature
Output Current Range of 1 A on Regulator 1
and 2 A on Regulator 2
Fast Transient Response
Voltage Options Are 3.3 V/2.5 V
Open Drain Power-On Reset With 120-ms
Delay
Open Drain Power Good for Regulator 1
Ultralow 185-µA (typical) Quiescent Current
2-µA Input Current During Standby
Low Noise: 78-µVRMS Without Bypass
Capacitor
Quick Output Capacitor Discharge Feature
•
•
•
•
•
Two Manual Reset Inputs
2% Accuracy Over Load and Temperature
Undervoltage Lockout (UVLO) Feature
20-Pin Ceramic Flatpack Package
Thermal Shutdown Protection
HKH PACKAGE
(TOP VIEW)
VIN1
VIN1
MR2
MR1
EN
SEQ
GND
VIN2
VIN2
NC
1
2
3
4
5
6
7
8
9
10
20
NC
19
18
17
16
15
14
13
12
VOUT1
VOUT1
VSENSE1
PG1
RESET
VSENSE2
VOUT2
VOUT2
11
NC
NC - No internal connection
DESCRIPTION
The TPS70358 is designed to provide a complete power management solution for TI DSP, processor power,
ASIC, FPGA, and digital applications where dual output voltage regulators are required. Easy programmability of
the sequencing function makes this family ideal for any TI DSP applications with power sequencing requirement.
Differentiated features, such as accuracy, fast transient response, SVS supervisory circuit (power on reset),
manual reset inputs, and enable function, provide a complete system solution.
1
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
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TPS70358M
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TPS70358M
5V
VIN1
DSP
3.3 V
VOUT1
I/O
22 µF
0.22 µF
VSENSE1
250 k Ω
PG1
PG1
VIN2
MR2
MR2
>2 V
<0.7 V
0.22 µF
>2 V
250 k Ω
RESET
RESET
EN
EN
<0.7 V
MR1
VSENSE2
SEQ
MR1
>2 V
<0.7 V
2.5 V
VOUT2
Core
47 µF
DESCRIPTION (CONTINUED)
The TPS70358 regulator offers very low dropout voltage and dual outputs with power up sequence control, which
is designed primarily for DSP applications. These devices have low noise output performance without using any
added filter bypass capacitors and are designed to have a fast transient response and be stable with 47-µF low
ESR capacitors.
The TPS70358 has a fixed 3.3-V/2.5-V voltage option. Regulator 1 can support up to 1 A, and regulator 2 can
support up to 2 A. Separate voltage inputs allow the designer to configure the source power.
Because the PMOS pass element behaves as a low-value resistor, the dropout voltage is very low (typically 160
mV on regulator 1) and is directly proportional to the output current. Additionally, since the PMOS pass element
is a voltage-driven device, the quiescent current is very low and independent of output loading (maximum of 250
µA over the full range of output current). This LDO family also features a sleep mode; applying a high signal to
EN (enable) shuts down both regulators, reducing the input current to 1 µA at TJ = 25°C.
The device is enabled when the EN pin is connected to a low-level input voltage. The output voltages of the two
regulators are sensed at the VSENSE1 and VSENSE2 pins respectively.
The input signal at the SEQ pin controls the power-up sequence of the two regulators. When the device is
enabled and the SEQ terminal is pulled high or left open, VOUT2 turns on first and VOUT1 remains off until VOUT2
reaches approximately 83% of its regulated output voltage. At that time VOUT1 is turned on. If VOUT2 is pulled
below 83% (i.e. overload condition) of its regulated voltage, VOUT1 will be turned off. Pulling the SEQ terminal low
reverses the power-up order and VOUT1 is turned on first. The SEQ pin is connected to an internal pullup current
source.
For each regulator, there is an internal discharge transistor to discharge the output capacitor when the regulator
is turned off (disabled).
The PG1 pin reports the voltage conditions at VOUT1. The PG1 pin can be used to implement a SVS (power on
reset) for the circuitry supplied by regulator 1.
The TPS70358 features a RESET (SVS, POR, or power on reset). RESET is an active low, open drain output
and requires a pullup resistor for normal operation. When pulled up, RESET goes to a high impedance state (i.e.
logic high) after a 120-ms delay when all three of the following conditions are met. First, VIN1 must be above the
undervoltage condition. Second, the manual reset (MR) pin must be in a high impedance state. Third, VOUT2 must
be above approximately 95% of its regulated voltage. To monitor VOUT1, the PG1 output pin can be connected to
MR1 or MR2. RESET can be used to drive power on reset or a low-battery indicator. If RESET is not used, it can
be left floating.
Internal bias voltages are powered by VIN1 and require 2.7 V for full functionality. Each regulator input has an
undervoltage lockout circuit that prevents each output from turning on until the respective input reaches 2.5 V.
2
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ORDERING INFORMATION (1)
PRODUCT
TPS70358M
(1)
VOLTAGE (V)
VOUT1
VOUT2
PACKAGE-LEAD
(DESIGNATOR)
TJ
ORDERABLE PART
NUMBER
TOP-SIDE
MARKING
3.3 V
2.5 V
DFP-20 (HKH)
–55°C to 125°C
TPS70358MHKH
TPS70358MHKH
For the most current package and ordering information, see the Package Option Addendum at the end of this document, or see the TI
website at www.ti.com.
DETAILED BLOCK DIAGRAM - FIXED VOLTAGE VERSION
VOUT1 (2 Pins)
VIN1 (2 Pins)
10 k Ω
Current
UVLO1
Sense
Shutdown
2.5 V
VSENSE1
ENA_1
(see Note A)
ENA_1
Reference
GND
+
Vref
Thermal
FB1
Vref
Shutdown
UVLO1
PG1
FB1
Rising Edge
Deglitch
0.95 × Vref
VIN1
MR2
Shutdown
RESET
FB2
UV Comp
Rising Edge
Falling Edge
Deglitch
Delay
0.95 × Vref
FB2
Falling Edge
0.83 × Vref
Deglitch
Power
VIN1
ENA_1
Sequence
FB1
Logic
Falling Edge
ENA_2
MR1
Vref
FB2
Deglitch
0.83 × Vref
UV Comp
-
EN
VIN1
2.5 V
UVLO2
Current
SEQ
(see Note B)
Sense
+
ENA_2
VSENSE2
ENA_2
(see Note A)
10 k Ω
VOUT2(2 Pins)
VIN2 (2 Pins)
NOTES: A. For most applications, VSENSE1 and VSENSE2 should be externally connected to VOUT as close as possible to the device.
For other implementations, refer to SENSE terminal connection discussion in the Application Information section.
B. If the SEQ terminal is floating at the input, VOUT2 powers up first.
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VIN2
VRES
(see Note A)
VRES
t
VOUT2
VIT+ (see Note B)
VIT +(see Note B)
Threshold
Voltage
VIT (see Note B)
VIT (see Note B)
t
RESET
Output
120 m s
Delay
120 m s
Delay
Output
Undefined
Output
Undefined
t
NOTES: A. VPG is the minimum input voltage for a valid PG. The symbol VPG is not currently listed within EIA or JEDEC
standards for semiconductor symbology.
B. VIT - Trip voltage is typically 5% lower than the output voltage (95%VO) VIT- to VIT+ is the hysteresis.
Figure 1. RESET Timing Diagram (With VIN1 Powered Up and MR1 and MR2 at Logic High)
VIN1
VUVLO
VUVLO
VPG1
(see Note A)
VPG1
t
VOUT2
VIT +(see Note B)
VIT+ (see Note B)
Threshold
Voltage
VIT (see Note B)
VIT (see Note B)
t
PG1
Output
Output
Undefined
Output
Undefined
t
NOTES: A. VPG is the minimum input voltage for a valid PG. The symbol VPG is not currently listed within EIA or JEDEC
standards for semiconductor symbology.
B. VIT - Trip voltage is typically 5% lower than the output voltage (95%VO) VIT- to VIT+ is the hysteresis.
Figure 2. PG1 Timing Diagram
4
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TERMINAL FUNCTIONS
TERMINAL
NAME
NO.
I/O
EN
5
GND
7
MR1
4
I
Manual reset input 1, active low, pulled up internally
3
I
Manual reset input 2, active low, pulled up internally
MR2
I
DESCRIPTION
Active low enable
Regulator ground
NC
10, 11, 20
No connection
PG1
16
O
Open drain output, low when VOUT1 voltage is less than 95% of the nominal regulated
voltage
RESET
15
O
Open drain output, SVS (power on reset) signal, active low
SEQ
6
I
Power up sequence control: SEQ=High, VOUT2 powers up first; SEQ=Low, VOUT1 powers up
first, SEQ terminal pulled up internally.
VIN1
1, 2
I
Input voltage of regulator 1
VIN2
8, 9
I
Input voltage of regulator 2
VOUT1
18, 19
O
Output voltage of regulator 1
VOUT2
12, 13
O
Output voltage of regulator 2
VSENSE2
14
I
Regulator 2 output voltage sense
VSENSE1
17
I
Regulator 1 output voltage sense
DETAILED DESCRIPTION
The TPS70358 low dropout regulator family provides dual regulated output voltages for DSP applications that
require a high performance power management solution. These devices provide fast transient response and high
accuracy, while drawing low quiescent current. Programmable sequencing provides a power solution for DSPs
without any external component requirements. This reduces the component cost and board space while
increasing total system reliability. TPS703xx family has an enable feature which puts the device in sleep mode
reducing the input current to 1 µA. Other features are the integrated SVS (power on reset, RESET) and power
good (PG1). These monitor output voltages and provide logic output to the system. These differentiated features
provide a complete DSP power solution.
The TPS703xx, unlike many other LDOs, features very low quiescent current which remains virtually constant
even with varying loads. Conventional LDO regulators use a PNP pass element, the base current of which is
directly proportional to the load current through the regulator (IB = IC/β). The TPS703xx uses a PMOS transistor
to pass current. Because the gate of the PMOS is voltage driven, operating current is low and stable over the full
load range.
PIN FUNCTIONS
Enable
The EN terminal is an input which enables or shuts down the device. If EN is at a logic high signal the device is
in shutdown mode. When the EN goes to voltage low, then the device is enabled.
Sequence
The SEQ terminal is an input that programs which output voltage (VOUT1 or VOUT2) is turned on first. When the
device is enabled and the SEQ terminal is pulled high or left open, VOUT2 turns on first and VOUT1 remains off until
VOUT2 reaches approximately 83% of its regulated output voltage. If VOUT2 is pulled below 83% (i.e., over load
condition) VOUT1 is turned off. This terminal has a 6-µA pullup current to VIN1.
Pulling the SEQ terminal low reverses the power-up order and VOUT1 is turned on first. For detail timing diagrams
refer to Figure 35 through Figure 41.
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Power Good (PG1)
The PG1 terminal is an open drain, active high output terminal which indicates the status of the VOUT1 regulator.
When the VOUT1 reaches 95% of its regulated voltage, PG1 goes to a high impedance state. PG1 goes to a low
impedance state when VOUT1 is pulled below 95% (i.e., over load condition) of its regulated voltage. The open
drain output of the PG1 terminal requires a pullup resistor.
Manual Reset Pins (MR1 and MR2)
MR1 and MR2 are active low input terminals used to trigger a reset condition. When either MR1 or MR2 is pulled
to logic low, a POR (RESET) occurs. These terminals have a 6-µA pullup current to VIN1. It is recommended that
these pins be pulled high to VIN when they are not used.
Sense (VSENSE1, VSENSE2
The sense terminals of fixed-output options must be connected to the regulator output, and the connection
should be as short as possible. Internally, the sense terminals connect to high-impedance wide-bandwidth
amplifiers through resistor-divider networks and noise pickup feeds through to the regulator output. It is essential
to route the sense connections in such a way to minimize/avoid noise pickup. Adding RC networks between the
VSENSE terminals and VOUT terminals to filter noise is not recommended because it can cause the regulators to
oscillate.
RESET Indicator
RESET is an active low, open drain output and requires a pullup resistor for normal operation. When pulled up,
RESET goes to a high impedance state (i.e. logic high) after a 120-ms delay when all three of the following
conditions are met. First, VIN1 must be above the undervoltage condition. Second, the manual reset (MR) pin
must be in a high impedance state. Third, VOUT2 must be above approximately 95% of its regulated voltage. To
monitor VOUT1, the PG1 output pin can be connected to MR1 or MR2.
VIN1 and VIN2
VIN1 and VIN2 are inputs to the regulators.
VOUT1 and VOUT2
VOUT1 and VOUT2 are output terminals of each regulator.
6
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ABSOLUTE MAXIMUM RATINGS (1)
over operating free-air temperature range (unless otherwise noted)
VIN1, VIN2
VOUT1,
VSENSE1,
VOUT2,
VSENSE2
VALUE
UNIT
Input voltage range (2)
–0.3 to 7
V
Voltage range at EN
–0.3 to 7
V
Output violtage range
5.5
V
7
V
Maximum RESET, PG1 voltage
Maximum MR1, MR2 and SEQ voltage
VIN1
Peak output current
TJ
Internally limited
Operating virtual junction temperature range
Package thermal impedance
–55 to 150
θJC (die to package top)
17.2
θJC (die to package bottom)
5.49
θJB (die to standard PCB trace)
Tstg
Storage temperature range
(2)
°C/W
38.4
–65 to 150
°C
2
kV
ESD rating (HBM, human body model)
(1)
°C
Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under “recommended operating
conditions” is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
All voltages are tied to network ground.
RECOMMENDED OPERATING CONDITIONS
over operating free-air temperature range (unless otherwise noted)
MIN
VI
Input voltage (1)
IO
Output current
TJ
Operating virtual storage temperature
(1)
NOM
MAX
2.7
6
Regulator 1
0
1
Regulator 2
0
2
–55
125
To calculate the minimum input voltage for maximum output current, use the following equation: VI(min) = VO(max) + VDO(max
UNIT
V
A
°C
load).
ELECTRICAL CHARACTERISTICS
over operating junction temperature range (TJ = –55°C to 125°C) VIN1 or VIN2 = VOUTX(nom) + V, IOUTX = 1 mA, EN = 0,
COUT1 = 22 µF, COUT2 = 47 µF (unless otherwise noted)
PARAMETER
VO
Output voltage (1) (2)
TEST CONDITIONS
2.5 V output
(VOUT2)
3.5 V < VI < 6 V,
3.3 V output
(VOUT1)
4.3 V < VI < 6 V,
3.5 V < VI < 6 V
Ouput voltage line regulation
for regulator 1 and regulator
2 (1)
VO + 1 V < VI < 6 V,
2.55
3.3
3.234
V
3.366
185
1
TJ = 25°C
UNIT
µA
mV
0.01%
mV
Regulator 1
Regulator 2
(3)
MAX
250
TJ = 25°C
(2)
2.45
TJ = 25°C
Load regulation for VOUT1 and VOUT2 (3)
(1)
TYP
2.5
TJ = 25°C
4.3 V < VI < 6 V
Quiescent current (GND current) for regulator 1
and regulator 2, EN = 0 V (2) (1)
MIN
TJ = 25°C
VO + 1 V < VI < 6 V,
5.6
6.25
Minimum input operating voltage is 2.7 V or VO(typ) + 1 V, whichever is greater. Maximum input voltage = 6 V, minimum output current is
1 mA.
Input voltage(VIN1 or VIN2) = VO(Typ) − 100 mV. For the 2.5-V regulators, the dropout voltage is limited by input voltage range. The
3.3-V regulator input voltage is set to 3.2 V to perform this test.
IO = 1 mA to 1 A for regulator 1 and 1 mA to 2 A for regulator 2.
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ELECTRICAL CHARACTERISTICS (continued)
over operating junction temperature range (TJ = –55°C to 125°C) VIN1 or VIN2 = VOUTX(nom) + V, IOUTX = 1 mA, EN = 0,
COUT1 = 22 µF, COUT2 = 47 µF (unless otherwise noted)
PARAMETER
Ouput current limit
TEST CONDITIONS
Regulator 1
Regulator 2
MIN
VO = 0 V
Thermal shutdown junction temperature
II(standby)
Standby current
TYP
MAX
1.75
2.2
3.8
4.5
150
EN = VI,
TJ = 25°C
1
EN = VI
UNIT
A
°C
2
10
µA
RESET TERMINAL
Minimum input voltage for valid RESET
I(RESET) = 300 µA,
Trip threshold voltage
VO decreasing
Hysteresis voltage
Measured at VO
t(RESET) (4)
RESET pulse
duration
tr(RESET)
(4)
V(RESET) ≤ 0.8 V
92%
VI = 3.5 V,
Leakage current
V(RESET) = 6 V
1.45
V
98%
VO
0.5%
TJ = 25°C
80
Rising edge deglitch
Output low voltage
1
95%
120
VO
160
µs
30
I(RESET) = 1 mA
0.15
ms
0.4
V
1
µA
1
1.45
V
95%
98%
VO
PG TERMINAL
Minimum input voltage for valid PG
I(PG) = 300 µA,
Trip threshold voltage
VO decreasing
Hysteresis voltage
Measured at VO
tr(PG1)
Rising edge deglitch
Output low voltage
VI = 2.7 V,
Leakage current
V(PG1) = 6 V
V(PG1) ≤ 0.8 V
92%
I(PG) = 1 mA
0.5%
VO
30
µs
0.15
0.4
V
1
µA
EN TERMINAL
High–level EN input voltage
2
V
Low–level EN input voltage
Input current (EN)
-1
0.7
V
1
µA
SEQ TERMINAL
High–level SEQ input voltage
2
V
Low–level SEQ input voltage
0.7
SEQ pullup current source
V
µA
6
MR1 / MR2 TERMINAL
High–level input voltage
2
V
Low–level input voltage
0.7
Pullup current source
6
V
µA
VOUT2 TERMINAL
VOUT2 UV comparator - positive–going input
threshold voltage of VOUT2 UV comparator
VOUT2 UV comparator - hysteresis
VOUT2 UV comparator - falling edge deglitch (4)
VSENSE2 decreasing below threshold
Peak output current
2-ms pulse width
Discharge transistor current
VOUT2 = 1.5 V
80% VO 83% VO 86% VO
V
3% VO
mV
140
µs
3
7.5
A
mA
VOUT1 TERMINAL
VOUT1 UV comparator - positive–going input
threshold voltage of VOUT1 UV comparator
VOUT1 UV comparator - hysteresis
VOUT1 UV comparator - falling edge deglitch
(4)
8
VSENSE1 decreasing below threshold
80% VO 83% VO 86% VO
V
3% VO
mV
140
µs
Not production tested. Specified by design.
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ELECTRICAL CHARACTERISTICS (continued)
over operating junction temperature range (TJ = –55°C to 125°C) VIN1 or VIN2 = VOUTX(nom) + V, IOUTX = 1 mA, EN = 0,
COUT1 = 22 µF, COUT2 = 47 µF (unless otherwise noted)
PARAMETER
Dropout voltage (5)
TEST CONDITIONS
IO = 1 A,
VIN1 = 3.2 V,
IO = 1 A,
VIN1 = 3.2 V
MIN
TJ = 25C
TYP
MAX
UNIT
160
400
mV
Peak output current
2-ms pulse width
1.2
A
Discharge transistor current
VOUT1 = 1.5 V
7.5
mA
VIN1 / VIN2 TERMINAL
UVLO threshold
2.3
UVLO hysteresis
(5)
2.65
110
V
mV
Input voltage(VIN1 or VIN2) = VO(Typ) − 100 mV. For the 2.5-V regulators, the dropout voltage is limited by input voltage range. The
3.3-V regulator input voltage is set to 3.2 V to perform this test.
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TYPICAL CHARACTERISTICS
Table 1. TPS70358M
VOLTAGE (V)
PRODUCT
TPS70358M
VOUT1
VOUT2
PACKAGE-LEAD
(DESIGNATOR)
3.3 V
2.5 V
DFP-20 (HKH)
SPECIFIED
TEMPERATURE
RANGE (TJ)
ORDERING
NUMBER
TOP-SIDE
MARKING
–55°C to 125°C
TPS70358MHKH
TPS70358MHKH
Table 2. Table of Graphs
FIGURE
VO
Output voltage
PSRR
ZO
vs Output current
Figure 3, Figure 4
vs Junction temperature
Figure 5, Figure 6
Ground current
vs Junction temperature
Power supply rejection ratio
vs Frequency
Figure 8 - Figure 11
Output spectral noise density
vs Frequency
Figure 12 - Figure 15
Output impedance
vs Frequency
Figure 16 - Figure 19
vs Temperature
Figure 20, Figure 21
vs Input voltage
Figure 22, Figure 23
Dropout voltage
Figure 7
Load transient response
Figure 24, Figure 25
Line transient response
VO
Figure 26, Figure 27
Output voltage and enable voltage
vs Time (start–up)
Figure 28, Figure 29
Equivalent series resistance
vs Output current
Figure 31 - Figure 34
TPS70351
OUTPUT VOLTAGE
vs
OUTPUT CURRENT
TPS70351
OUTPUT VOLTAGE
vs
OUTPUT CURRENT
3.33
1.815
VIN1 = 4.3 V
TJ = 25 ° C
VOUT1
VIN2 = 2.8V
TJ = 25 ° C
VOUT2
1.81
VO - O utput Voltag e - V
VO - O utput Voltag e - V
3.32
3.31
3.30
3.29
1.805
1.8
1.795
1.79
3.28
1.785
3.27
0
200
400
600
800
1000
0
I O - O u tp u t C u rre n t - m A
1000
1500
2000
I O - O u tp u t C u rre n t - m A
Figure 3.
10
500
Figure 4.
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TPS70351
OUTPUT VOLTAGE
vs
JUNCTION TEMPERATURE
3.354
VIN1 = 4.3 V
VOUT1
VO - O utput Voltag e - V
3.334
3.314
IO = 1 m A
3.294
IO = 1 A
3.274
3.254
3.234
-40 -25
-10
5
20
35
50
65
80
95
110 125
T J - Ju n c tio n Te m p e ra tu re - ° C
Figure 5.
TPS70351
OUTPUT VOLTAGE
vs
JUNCTION TEMPERATURE
TPS70351
GROUND CURRENT
vs
JUNCTION TEMPERATURE
1.834
210
VIN2 = 2.8 V
VOUT2
Regulator 1 and Regulator 2
200
1.814
1.804
G round C urrent - µ A
VO - O utput Voltag e - V
1.824
IO = 2 A
IO = 1 m A
1.794
IOUT1 = 1 mA
IOUT2 = 1 mA
190
180
IOUT1 = 1 A
IOUT2 = 2 A
170
1.784
160
1.774
1.764
-40 -25
-10
5
20
35
50
65
80
95
110 125
150
-40 -25
T J - Ju n c tio n Te m p e ra tu re - ° C
Figure 6.
-10
5 20
35 50 65
80 95
T J - Ju n c tio n Te m p e ra tu re - ° C
110 125
Figure 7.
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TPS70351
OUTPUT VOLTAGE
vs
JUNCTION TEMPERATURE (continued)
TPS70351
POWER SUPPLY REJECTION RATIO
vs
FREQUENCY
TPS70351
POWER SUPPLY REJECTION RATIO
vs
FREQUENCY
0
VIN1 = 4.3 V
VOUT1 = 3.3 V
IO = 1 0 m A
CO = 22 µ F
-20
P S R R - Pow er S upply R ejection R atio - dB
P S R R - Pow er S upply R ejection R atio - dB
-10
-30
-40
-50
-60
-70
-80
VIN1 = 4.3 V
VOUT1 = 3.3 V
IO = 1 A
CO = 22 µ F
-10
-20
-30
-40
-50
-60
-70
-80
-90
-100
-90
10
100
1k
10 k
100 k
10
1M
100
1k
Figure 8.
1M
Figure 9.
TPS70351
POWER SUPPLY REJECTION RATIO
vs
FREQUENCY
TPS70351
POWER SUPPLY REJECTION RATIO
vs
FREQUENCY
0
0
VIN2 = 2.8 V
VOUT2 = 1.8 V
IO = 1 0 m A
CO = 47 µ F
-10
-20
P S R R - Pow er S upply R ejection R atio - dB
P S R R - Pow er S upply R ejection R atio - dB
100 k
f - Frequency - Hz
f - Frequency - Hz
-30
-40
-50
-60
-70
-80
-90
-100
VIN2 = 2.8 V
VOUT2 = 1.8 V
IO = 2 A
CO = 47 µ F
-10
-20
-30
-40
-50
-60
-70
-80
-90
-100
10
12
10 k
100
1k
10 k
100 k
1M
10
100
1k
10 k
f - Frequency - Hz
f - Frequency - Hz
Figure 10.
Figure 11.
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1M
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TPS70351
OUTPUT VOLTAGE
vs
JUNCTION TEMPERATURE (continued)
OUTPUT SPECTRAL NOISE DENSITY
vs
FREQUENCY
OUTPUT SPECTRAL NOISE DENSITY
vs
FREQUENCY
10
10
IO = 1 0 m A
TJ = 25 ° C
1
0.1
0.01
100
1k
10 k
VIN2 = 2.8 V
VOUT2 = 1.8 V
COUT2 = 47 µ F
Hz
O utput S pectral N oise D ensity - µ V /
O utput S pectral N oise D ensity - µ V /
Hz
VIN1 = 4.3 V
VOUT1 = 3.3 V
COUT1 = 22 µ F
IO = 1 0 m A
TJ = 25 ° C
1
0.1
0.01
100
100 k
1k
f - Frequency - Hz
Figure 12.
OUTPUT SPECTRAL NOISE DENSITY
vs
FREQUENCY
10
10
O utput S pectral N oise D ensity - µ V /
IO = 1 A
TJ = 25° C
1
0.1
1k
10 k
VIN2 = 2.8 V
VOUT2 = 1.8 V
COUT2 = 47 µ F
IO = 2 A
TJ = 25 ° C
Hz
VIN1 = 4.3 V
VOUT1 = 3.3 V
COUT1 = 22 µ F
Hz
O utput S pectral N oise D ensity - µ V /
100 k
Figure 13.
OUTPUT SPECTRAL NOISE DENSITY
vs
FREQUENCY
0.01
100
10 k
f - Frequency - Hz
100 k
1
0.1
0.01
100
1k
10 k
f - Frequency - Hz
f - Frequency - Hz
Figure 14.
Figure 15.
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TPS70351
OUTPUT VOLTAGE
vs
JUNCTION TEMPERATURE (continued)
OUTPUT IMPEDANCE
vs
FREQUENCY
OUTPUT IMPEDANCE
vs
FREQUENCY
VOUT1 = 3.3 V
IO = 1 A
CO = 22 µ F
Z O - O utput Im pedance - Ω
Z O - O utput Im pedance - Ω
VOUT1 = 3.3 V
IO = 1 0 m A
CO = 22 µ F
1
0.1
0.01
10
100
1k
10 k
100 k
1M
1
0.1
0.01
10
10 M
100
1k
f - Frequency - Hz
Figure 16.
10 M
1M
10 M
VOUT2 = 1.8 V
IO = 2 A
CO = 47 µ F
Z O - O utput Im pedance - Ω
Z O - O utput Im pedance - Ω
14
1M
OUTPUT IMPEDANCE
vs
FREQUENCY
VOUT2 = 1.8 V
IO = 1 0 m A
CO = 47 µ F
1
0.1
0.01
100
100 k
Figure 17.
OUTPUT IMPEDANCE
vs
FREQUENCY
10
10 k
f - Frequency - Hz
1k
10 k
100 k
1M
10 M
1
0.1
0.01
10
100
1k
10 k
100 k
f - Frequency - Hz
f - Frequency - Hz
Figure 18.
Figure 19.
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TPS70351
OUTPUT VOLTAGE
vs
JUNCTION TEMPERATURE (continued)
TPS70351
DROPOUT VOLTAGE
vs
TEMPERATURE
TPS70351
DROPOUT VOLTAGE
vs
TEMPERATURE
250
25
VOUT1
VIN1 = 3.2 V
VOUT1
VIN1 = 3.2 V
200
20
D ropout Voltag e - m V
D ropout Voltag e - m V
IO = 1 A
150
100
50
IO = 1 0 0 m A
15
10
5
IO = 1 m A
IO = 1 0 m A
0
-40 -25
-10
5
20
35 50 65
80
T - Te m p e ra tu re - ° C
95
0
-40 -25
110 125
-10
5
20
35
50
65
Figure 20.
95
110 125
Figure 21.
TPS70302
DROPOUT VOLTAGE
vs
INPUT VOLTAGE
TPS70302
DROPOUT VOLTAGE
vs
INPUT VOLTAGE
300
300
VOUT1
IO = 1 A
VOUT2
IO = 2 A
250
250
TJ = 125 ° C
D ropout Voltag e - m V
D ropout Voltag e - m V
80
T - Te m p e ra tu re - ° C
200
TJ = 25 ° C
150
100
TJ = 125 ° C
200
TJ = 25 ° C
150
TJ= - 40 ° C
100
TJ= - 40 ° C
50
0
2.5
50
3
3.5
4
4.5
5
5.5
0
2.5
3
3.5
4
4.5
VI - Input Voltage - V
VI - Input Voltage - V
Figure 22.
Figure 23.
5
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TPS70351
OUTPUT VOLTAGE
vs
JUNCTION TEMPERATURE (continued)
LOAD TRANSIENT RESPONSE
I O - O utput C urrent - A
I O - O utput C urrent - A
LOAD TRANSIENT RESPONSE
VIN1 = 4.3 V
VOUT1 = 3.3 V
CO = 22 µ F
TJ = 25 ° C
1
0.5
0
2
VOUT2 = 2.5 V
IO = 2 A
CO = 47 µ F
1
TJ = 25° C
0
∆ V O - C hang e in
O utput Voltag e - m V
∆ V O - C hang e in
O utput Voltag e - m V
50
0
-50
-100
0
0.2
0.4
0.6
0.8
1
1.2
1.4
1.6
1.8
50
0
-50
0
2
0.2
0.4
0.6
t - T im e - m s
1.4
1.6
1.8
2
180
200
V I - Input Voltag e - V
LINE TRANSIENT RESPONSE
VOUT1 = 3.3 V
IO = 1 A
CO = 22 µ F
4.3
∆ V O - C hang e in
O utput Voltag e - m V
V I - Input Voltag e - V
∆ V O - C hang e in
O utput Voltag e - m V
1.2
Figure 25.
LINE TRANSIENT RESPONSE
50
0
-50
-100
VOUT2 = 2.5 V
IO = 2 A
CO = 47 µ F
3.8
2.8
100
0
-100
-200
0
16
1
t - T im e - m s
Figure 24.
5.3
0.8
20
40
60
80
100
120
140
160
180
200
0
20
40
60
80
100
120
t - T im e - µs
t - T im e - µ s
Figure 26.
Figure 27.
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160
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TPS70351
OUTPUT VOLTAGE
vs
JUNCTION TEMPERATURE (continued)
OUTPUT VOLTAGE AND ENABLE VOLTAGE
vs
TIME (START-UP)
OUTPUT VOLTAGE AND ENABLE VOLTAGE
vs
TIME (START-UP)
VO - O utput Voltag e- V
3
VOUT1 = 3.3 V
IO = 1 A
CO = 22 µ F
2
VIN1 = 4.3 V
SEQ = Low
1
0
E nable Voltag e - V
E nable Voltag e - V
VO - O utput Voltag e- V
4
5
0
0
0.2
VI
0.4
0.6
0.8
1
1.2
1.4
1.6
1.8
2
2
1
0
VOUT2 = 1.8 V
IO = 2 A
CO = 47 µ F
VIN2 = 2.8 V
SEQ = High
5
0
0
0.2
0.4
0.6
0.8
1
1.2
1.4
t - T im e (S ta rt-U p ) - m s
t - T im e (S ta rt-U p ) - m s
Figure 28.
Figure 29.
1.6
1.8
2
To Load
IN
OUT
+
CO
RL
EN
GND
ESR
Figure 30. Test Circuit for Typical Regions of Stability
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TYPICAL REGION OF STABILITY
EQUIVALENT SERIES RESISTANCE (ESR)(1)
vs
OUTPUT CURRENT
TYPICAL REGION OF STABILITY
EQUIVALENT SERIES RESISTANCE (ESR)(1)
vs
OUTPUT CURRENT
10
10
VOUT1 = 3.3 V
CO = 220 µ F
Ω
E S R - E quivalent S eries R esistance -
E S R - E quivalent S eries R esistance -
Ω
VOUT1 = 3.3 V
CO = 22 µ F
REGION OF INSTABILITY
1
0.1
50 m Ω
0.01
REGION OF INSTABILITY
1
0.1
15 m Ω
0.01
0
0.1
0.2
0.3
0.4
0.5
0.6
0.7
0.8
0.9
0
1
0.1
0.2
IO - Output Current - A
0.3
Figure 31.
0.6
0.7
0.8
0.9
1
0.9
1
TYPICAL REGION OF STABILITY
EQUIVALENT SERIES RESISTANCE (ESR)(1)
vs
OUTPUT CURRENT
10
10
REGION OF INSTABILITY
Ω
E S R - E quivalent S eries R esistance -
Ω
REGION OF INSTABILITY
E S R - E quivalent S eries R esistance -
0.5
Figure 32.
TYPICAL REGION OF STABILITY
EQUIVALENT SERIES RESISTANCE (ESR)(1)
vs
OUTPUT CURRENT
VOUT2 = 1.8 V
CO = 47 µ F
1
0.1
50 m Ω
0.01
VOUT2 = 1.8 V
CO = 680 µ F
1
0.1
15 m Ω
0.01
0
18
0.4
IO - Output Current - A
0.1
0.2
0.3
0.4
0.5
0.6
0.7
0.8
0.9
1
0
0.1
0.2
0.3
0.4
0.5
0.6
IO - Output Current - A
IO - Output Current - A
Figure 33.
Figure 34.
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0.7
0.8
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APPLICATION INFORMATION
Sequencing Timing Diagrams
The following figures provide a timing diagram of how this device functions in different configurations.
SEQ = Low
Application Conditions Not Shown in Block Diagram:
VIN1 and VIN2 are tied to the same fixed input voltage greater than the VUVLO; SEQ is tied to logic low; PG1 is tied
to MR2; MR1 is not used and is connected to VIN.
TPS70358
(Fixed Output Option)
VOUT1
VI
VIN1
0.22 µ F
VOUT1
22 µ F
VSENSE1
250 k Ω
PG1
VIN2
0.22 µ F
EN
MR2
RESET
EN
MR1
MR2
RESET
MR1
VIN
>2 V
<0.7 V
VSENSE2
SEQ
VOUT2
VOUT2
47 µ F
Explanation of Timing Diagram:
EN is initially high; therefore, both regulators are off and PG1 and RESET are at logic low. With SEQ at logic low,
when EN is taken to logic low, VOUT1 turns on. VOUT2 turns on after VOUT1 reaches 83% of its regulated output
voltage. When VOUT1 reaches 95% of its regulated output voltage, PG1 (tied to MR2) goes to logic high. When
both VOUT1 and VOUT2 reach 95% of their respective regulated output voltages and both MR1 and MR2 (tied to
PG1) are at logic high, RESET is pulled to logic high after a 120-ms delay. When EN is returned to logic high,
both devices power down and both PG1 (tied to MR2) and RESET return to logic low.
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EN
SEQ
VOUT2
95%
83%
95%
VOUT1
83%
PG1
MR1
MR2
(MR2 tied to PG1)
RESET
t1
(see Note A)
120 ms
NOTE A: t1 - Time at which both VOUT1 and VOUT2 are greater than the PG thresholds and MR1 is logic high.
Figure 35. Timing When SEQ = Low
SEQ = High
Application Conditions Not Shown in Block Diagram:
VIN1 and VIN2 are tied to the same fixed input voltage greater than the VUVLO; SEQ is tied to logic high; PG1 is
tied to MR2; MR1 is not used and is connected to VIN.
TPS70358
(Fixed Output Option)
VI
VOUT1
VIN1
0.22 µ F
VOUT1
22 µ F
VSENSE1
250 k Ω
PG1
VIN2
0.22 µ F
EN
EN
MR2
MR2
RESET
RESET
MR1
MR1
VIN
>2 V
VSENSE2
<0.7 V
SEQ
VOUT2
VOUT2
47 µ F
20
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Explanation of Timing Diagram:
EN is initially high; therefore, both regulators are off and PG1 and RESET are at logic low. With SEQ at logic
high, when EN is taken to logic low, VOUT2 turns on. VOUT1 turns on after VOUT2 reaches 83% of its regulated
output voltage. When VOUT1 reaches 95% of its regulated output voltage, PG1 (tied to MR2) goes to logic high.
When both VOUT1 and VOUT2 reach 95% of their respective regulated output voltages and both MR1 and MR2
(tied to PG1) are at logic high, RESET is pulled to logic high after a 120-ms delay. When EN is returned to logic
high, both devices turn off and both PG1 (tied to MR2) and RESET return to logic low.
EN
SEQ
VOUT2
95%
83%
VOUT1
95%
83%
PG1
MR1
MR2
(MR2 tied to PG1)
RESET
t1
(see Note A)
120ms
NOTE A: t1 - Time at which both VOUT1 and VOUT2 are greater than the PG thresholds and MR1 is logic high.
Figure 36. Timing When SEQ = High
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Toggled MR1
Application Conditions Not Shown in Block Diagram:
VIN1 and VIN2 are tied to the same fixed input voltage greater than the VUVLO; SEQ is tied to logic high; PG1 is
tied to MR2; MR1 is initially at logic high but is eventually toggled.
TPS70358
(Fixed Output Option)
VOUT1
VI
VIN1
VOUT1
22 µ F
0.22 µ F
VSENSE1
250 k Ω
PG1
VIN2
0.22 µ F
EN
MR2
RESET
EN
MR1
MR2
RESET
MR1
2V
>2 V
0.7 V
VSENSE2
<0.7 V
SEQ
VOUT2
VOUT2
47 µ F
Explanation of Timing Diagram:
EN is initially high; therefore, both regulators are off and PG1 and RESET are at logic low. With SEQ at logic
high, when EN is taken low, VOUT2 turns on. VOUT1 turns on after VOUT2 reaches 83% of its regulated output
voltage. When VOUT1 reaches 95% of its regulated output voltage, PG1 (tied to MR2) goes to logic high. When
both VOUT1 and VOUT2 reach 95% of their respective regulated output voltages and both MR1 and MR2 (tied to
PG1) are at logic high, RESET is pulled to logic high after a 120-ms delay. When MR1 is taken low, RESET
returns to logic low but the outputs remain in regulation. When MR1 is returned to logic high, since both VOUT1
and VOUT2 remain above 95% of their respective regulated output voltages and MR2 (tied to PG1) remains at
logic high, RESET is pulled to logic high after a 120-ms delay.
22
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EN
SEQ
VOUT2
95%
83%
95%
VOUT1
83%
PG1
MR1
MR2
(MR2 tied to PG1)
RESET
t1
(see Note A)
120 ms
120 ms
NOTE A: t1 - Time at which both VOUT1 and VOUT2 are greater than the PG thresholds and MR1 is logic high.
Figure 37. Timing When MR1 is Toggled
VOUT1 FAULT
Application Conditions Not Shown in Block Diagram:
VIN1 and VIN2 are tied to the same fixed input voltage greater than the VUVLO; SEQ is tied to logic high; PG1 is
tied to MR2; MR1 is not used and is connected to VIN.
TPS70358
(Fixed Output Option)
VOUT1
VI
VIN1
0.22 µ F
VOUT1
22 µ F
VSENSE1
250 k Ω
PG1
VIN2
0.22 µ F
EN
EN
MR2
MR2
RESET
RESET
MR1
MR1
VIN
>2 V
VSENSE2
<0.7 V
SEQ
VOUT2
VOUT2
47 µ F
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Explanation of Timing Diagram:
EN is initially high; therefore, both regulators are off and PG1 and RESET are at logic low. With SEQ at logic
high, when EN is taken low, VOUT2 turns on. VOUT1 turns on after VOUT2 reaches 83% of its regulated output
voltage. When VOUT1 reaches 95% of its regulated output voltage, PG1 (tied to MR2) goes to logic high. When
both VOUT1 and VOUT2 reach 95% of their respective regulated output voltages and both MR1 and MR2 (tied to
PG1) are at logic high, RESET is pulled to logic high after a 120-ms delay. When a fault on VOUT1 causes it to fall
below 95% of its regulated output voltage, PG1 (tied to MR2) goes to logic low.
EN
SEQUENCE
VOUT2
95%
83%
95%
VOUT1
83%
Fault on VOUT1
PG1
MR1
MR2
(MR2 tied to PG1)
RESET
t1
(see Note A)
120 ms
NOTE A: t1 - Time at which both VOUT1 and VOUT2 are greater than the PG thresholds and MR1 is logic high.
Figure 38. Timing When a Fault Occurs on VOUT1
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VOUT2 FAULT
Application Conditions Not Shown in Block Diagram:
VIN1 and VIN2 are tied to the same fixed input voltage greater than the VUVLO; SEQ is tied to logic high; PG1 is
tied to MR2; MR1 is not used and is connected to VIN.
TPS70358 (Fixed Output Option)
VOUT1
VI
VIN1
VOUT1
22 µ F
0.22 µ F
VSENSE1
250 k Ω
PG1
VIN2
RESET
0.22 µ F
EN
MR2
EN
MR1
MR2
RESET
MR1
VIN
>2 V
VSENSE2
<0.7 V
SEQ
VOUT2
VOUT2
47 µ F
Explanation of Timing Diagram:
EN is initially high; therefore, both regulators are off and PG1 and RESET are at logic low. With SEQ at logic
high, when EN is taken low, VOUT2 turns on. VOUT1 turns on after VOUT2 reaches 83% of its regulated output
voltage. When VOUT1 reaches 95% of its regulated output voltage, PG1 (tied to MR2) goes to logic high. When
both VOUT1 and VOUT2 reach 95% of their respective regulated output voltages and both MR1 and MR2 (tied to
PG1) are at logic high, RESET is pulled to logic high after a 120-ms delay. When a fault on VOUT2 causes it to fall
below 95% of its regulated output voltage, RESET returns to logic low and VOUT1 begins to power down because
SEQ is high. When VOUT1 falls below 95% of its regulated output voltage, PG1 (tied to MR2) returns to logic low.
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ENABLE
SEQUENCE
95%
83%
VOUT2
Fault on VOUT2
95%
VOUT1
83%
PG1
MR1
MR2
(MR2 tied to PG1)
RESET
t1
(see Note A)
120 ms
NOTE A: t1 - Time at which both VOUT1 and VOUT2 are greater than the PG thresholds and MR1 is logic high.
Figure 39. Timing When a Fault Occurs on VOUT2
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Split Voltage DSP Application
Figure 40 shows a typical application where the TPS70358 is powering up a DSP. In this application, by
grounding the SEQ pin, VOUT1(I/O) is powered up first, and then VOUT2(core).
TPS70358
5V
DSP
3.3 V
VOUT1
VIN1
0.22 µ F
22 µ F
VSENSE1
I/O
250 k Ω
PG1
PG1
MR2
VIN2
MR2
VIN
250 k Ω
0.22 µ F
>2 V
RESET
RESET
EN
MR1
EN
MR1
VIN
<0.7 V
VSENSE2
SEQ
2.5 V
VOUT2
Core
47 µ F
EN
SEQ
VOUT2
(Core)
95%
83%
VOUT1
(I/O)
95%
83%
PG1
RESET
t1
(see Note A)
120ms
NOTE A: t1 - Time at which both VOUT1 and VOUT2 are greater than the PG1 thresholds and MR1 is logic high.
Figure 40. Application Timing Diagram (SEQ = Low)
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Figure 41 shows a typical application where the TPS70358 is powering up a DSP. In this application, by pulling
up the SEQ pin, VOUT2(Core) is powered up first, and then VOUT1(I/O).
TPS70358
DSP
5V
3.3 V
VOUT1
VIN1
0.22 µ F
22 µ F
VSENSE1
I/O
250 k Ω
PG1
PG1
MR2
VIN2
MR2
VIN
250 k Ω
0.22 µ F
MR1
EN
>2 V
RESET
RESET
MR1
VIN
EN
<0.7 V
VSENSE2
SEQ
2.5 V
VOUT2
Core
47 µ F
EN
SEQ
VOUT2
(Core)
95%
83%
VOUT1
(I/O)
95%
83%
PG1
RESET
t1
120ms
(see Note A)
NOTE A: t1 - Time at which both VOUT1 and VOUT2 are greater than the PG1 thresholds and MR1 is logic high.
Figure 41. Application Timing Diagram (SEQ = High)
Input Capacitor
For a typical application, a ceramic input bypass capacitor (0.22 µF − 1 µF) is recommended to ensure device
stability. This capacitor should be as close as possible to the input pin. Due to the impedance of the input supply,
large transient currents causes the input voltage to droop. If this droop causes the input voltage to drop below
28
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TPS70358M
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the UVLO threshold, the device turns off. Therefore, it is recommended that a larger capacitor be placed in
parallel with the ceramic bypass capacitor at the regulator’s input. The size of this capacitor depends on the
output current, response time of the main power supply, and the main power supply’s distance to the regulator.
At a minimum, the capacitor should be sized to ensure that the input voltage does not drop below the minimum
UVLO threshold voltage during normal operating conditions.
Output Capacitor
As with most LDO regulators, the TPS70358 requires an output capacitor connected between each OUT and
GND to stabilize the internal control loop. The minimum recommended capacitance value for VOUT1 is 22 µF and
the ESR (equivalent series resistance) must be between 50 mΩ and 800 mΩ. The minimum recommended
capacitance value for VOUT2 is 47 µF and the ESR must be between 50 mΩ and 2 Ω. Solid tantalum electrolytic,
aluminum electrolytic, and multilayer ceramic capacitors are all suitable, provided they meet the requirements
described above. Larger capacitors provide a wider range of stability and better load transient response. Below is
a partial listing of surface-mount capacitors usable with the TPS703xx for fast transient response application.
This information, along with the ESR graphs, is included to assist in selection of suitable capacitance for the
user’s application. When necessary to achieve low height requirements along with high output current and/or
high load capacitance, several higher ESR capacitors can be used in parallel to meet the guidelines above.
VALUE
MANUFACTURER
PART NO.
680 µF
Kemet
T510X6871004AS
470 µF
Sanyo
4TPB470M
150 µF
Sanyo
4TPC150M
220 µF
Sanyo
2R5TPC220M
100 µF
Sanyo
6TPC100M
68 µF
Sanyo
10TPC68M
68 µF
Kemet
T495D6861006AS
47 µF
Kemet
T495D4761010AS
33 µF
Kemet
T495C3361016AS
22 µF
Kemet
T495C2261010AS
Regulator Protection
Both TPS70358 PMOS-pass transistors have built-in back diodes that conduct reverse currents when the input
voltage drops below the output voltage (e.g., during power down). Current is conducted from the output to the
input and is not internally limited. When extended reverse voltage is anticipated, external limiting may be
appropriate.
The TPS70358 also features internal current limiting and thermal protection. During normal operation, the
TPS70358 regulator 1 limits output current to approximately 1.75 A (typ) and regulator 2 limits output current to
approximately 3.8 A (typ). When current limiting engages, the output voltage scales back linearly until the
overcurrent condition ends. While current limiting is designed to prevent gross device failure, care should be
taken not to exceed the power dissipation ratings of the package. If the temperature of the device exceeds
150°C(typ), thermal-protection circuitry shuts it down. Once the device has cooled below 130°C(typ), regulator
operation resumes.
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29
PACKAGE OPTION ADDENDUM
www.ti.com
15-Jul-2009
PACKAGING INFORMATION
Orderable Device
Status (1)
Package
Type
Package
Drawing
TPS70358MHKH
ACTIVE
CFP
HKH
Pins Package Eco Plan (2)
Qty
20
25
TBD
Lead/Ball Finish
Call TI
MSL Peak Temp (3)
N / A for Pkg Type
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in
a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check
http://www.ti.com/productcontent for the latest availability information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements
for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered
at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and
package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS
compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame
retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material)
(3)
MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder
temperature.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is
provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the
accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take
reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on
incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited
information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI
to Customer on an annual basis.
OTHER QUALIFIED VERSIONS OF TPS70358M :
• Catalog: TPS70358
NOTE: Qualified Version Definitions:
• Catalog - TI's standard catalog product
Addendum-Page 1
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