Accepted manuscript posted September 24, 2014. doi:10.1115/1.4028629
Copyright (c) 2014 by ASME
Overview and Outlook of 3D IC Packaging, 3D Si Integration, and 3D IC Integration
John H. Lau
ASM Pacific Technology
16-22 Kung Yip Street, Kwai Chung, N.T., Hong Kong
852-2619-2757, john.lau@asmpt.com
ABSTRACT
Co
py
ed
ite
d
3D integration consists of 3D IC packaging, 3D Si integration, and 3D IC integration. They are different
and in general the TSV (through-silicon via) separates 3D IC packaging from 3D Si/I
Si/IC integrations since
ndd 3D IIC integration are
the latter two use TSV but 3D IC packaging does not. 3D Si integration and
mp, wh
while 3D Si integration
different. 3D IC integration stacks up the thin chips with TSV and microbump,
Si
stacks up thin wafers with TSV alone (i.e., bumpless). TSV is the heart off 3D Si/I
Si/IC integrations and is
end of 3D integration will be
the focus of this investigation. Also, the state-of-the-art, challenge, and trend
volume
olume m
presented and examined. Furthermore, supply chain readiness for high-volume
manufacturing of TSVs is
discussed.
rip
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ot
I. INTRODUCTION
The Electronics Industry has been the largest industry since 1996
996 and may well reach 1.6 trillion dollars
(i.e., $1.5x1012) by the end of 2015 [1, 2, 3]. The most important
ortant
tant in
invention of the Electronics Industry is,
en, Wal
arguably the transistor (1947), which earned John Bardeen,
Walter Brattain, and William Shockley the
g ated ccircuit (IC) by Jack Kilby in 1958 (which
gra
1956 Nobel Prize in Physics. The invention of the integrated
earned him the 2000 Nobel Prize in Physics), and six months later by Robert Noyce (who didn't share the
19
Nobel Prize with Jack Kilby because he passed awayy in 1990
1990) excited the generations of IC integrations.
pt
ed
Ma
nu
sc
stors
ors oon an IC chip (for minimum costs and innovations)
The proposal of doubling the number of transistors
also ca
ccalled Moore’s law) [4] has been the most powerful
every 24 months by Gordon Moore in 1965 (also
ctronics
tronic industry in the past ~50 years. This law emphasizes
driver for the development of the microelectronics
su
lithography scaling and integration (on a 2D surf
surface) of all functions on a single chip, perhaps through
nd, the in
system-on-chip (SoC). On the other hand,
integration of all these functions can be achieved through
aging [[1], 3D IC integration [1-3], [5-70], [107-125] and 3D Si
3D integrations such as 3D IC packaging
n in F
i
igu
integration [1-3], [69-125] as shown
Figure
1 [1-3].
Don’t use TSV
Ac
ce
3D IC Packaging
Maturity
ty
Applied
R&D
Basic/
Applied
R&D
3D Si Integration
Full swing production for memories.
Mass
Mas
Production
Prod
Produ
Commercia
C
-lization
Use TSV
3D IC Integration
Volume production for mobile
products.
Die
Stacking
with wire
bonds
Active applied R&D is undertaken.
In the phase of industrialization.
Samples are shipping. Small
volume production
Package
on
Package
(PoP)
Stacking
C2C, C2W
Stacking
Still in upstream research.
Challenges such as knowngood-die, yield & device
architecture, and electronic
design automation are key
issues.
W2W
Stacking
Technology
Figure 1 3D integration technologies vs. maturity [2]
Accepted manuscript posted September 24, 2014. doi:10.1115/1.4028629
Copyright (c) 2014 by ASME
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Deep Pits (TSVs)
Figure 2 TSV invented by Shockley (US Patent#3,044,909)
09)
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ot
Co
py
TSV was invented more than 50 years ago [1, 126] by the 1956 Nobel
bell Laur
Laureate
Laure
in Physics, William
Shockley. (Yes, the same Shockley who co-invented the transistor, which is generally considered the
Semicond
micon
greatest invention in Semiconductor industry.) He filed the patent “Semiconductive
wafer and method of
atent (3,044,909)
(3,0
making the same” on October 23, 1958, and as granted the U.S. patent
on July 17, 1962. One
ductor world
w
of the key claims is shown in Figure 2, which gets the Semiconductor
so excited today. Basically,
allo
al ow the
th signals from its top side to its
the “deep pits” (which are called TSVs today) on the waferr allow
bottom side and vice versa.
nu
sc
rip
ation [[1
atio
TSV is the heart of 3D Si integration and 3D IC Integration
[1, 127]. It provides the opportunity for the
d siz
size and pitch of interconnects. Compared with
shortest chip-to-chip interconnects and the smallest pad
onding the advantages of TSV include: (a) better
other interconnection technologies, such as wire bonding,
mption,
ption, ((c) wider data width and thus bandwidth, (d)
electrical performance, (b) lower power consumption,
ighter
ghter w
we
higher density, (e) smaller form factor, and (f) lighter
weight, [1-3] and [5-125].
ed
Ma
disrupti
TSV is a disruptive technology. As with alll disrup
disruptive technologies, the questions to ask are: “What is it
Unfortu
Unfortun
displacing?” and “What’s the cost?” Unfortunately,
TSV is trying to displace the wire-bonding
high-y
technology, which is a most mature, high-yie
high-yield, and low-cost technology [128]. However, just like
29, 13
130
solder-bumped flip-chip technology [129,
130], because of their unique advantages, TSVs will be here to
gh-per
h-pe for
f
stay and for a very long time for high-performance
and high-density applications.
ce
pt
oduction
uction for MEMS (micro-electro-mechanical systems) [131, 132] and
TSV has been in volume production
al--oxide
oxid
CMOS (complementary metal-oxide-semiconductor)
image sensor [133, 134]. However, they are out of
ich
ch is foc
the scope of this study, which
focused on memory, logic, processor, and SoC.
Ac
ation is
i a very old idea [69, 70] which consists of two or more layers of active
3D (IC and Si) integration
ntss that
tha are integrated vertically through TSV (it used to be called vertical
electronic components
s
sin
interconnection) into a single
circuit. It was trigged by the advance of the silicon-on-insulator (SOI)
technology first reported by Gat and his colleagues more than 35 years ago [135], when semiconductor
people thought Moore’s law could be hitting the wall by the 1990s. Of course, the fact showed otherwise.
3D IC integration is to stack up the thin chips with TSVs and microbumps. While 3D Si integration is to
stack up the thin wafers/chips with TSVs alone, i.e., bumpless. The advantages of 3D Si integration over
3D IC integration are: (1) better electrical performance, (2) less power consumption, (3) lower profile, (4)
less weight, and (5) higher throughput.
The most powerful proponent on 3D IC/Si integration is the 1965 Nobel Physics laureate, Richard
Accepted manuscript posted September 24, 2014. doi:10.1115/1.4028629
Copyright (c) 2014 by ASME
Feynman. Almost thirty (30) years ago, during his lecture, Computing Machines in the Future in 1985,
said he: “Another direction of improvement (of computing power) is to make physical machines three
dimensional instead of all on a surface of a chip. That can be done in stages instead of all at once – you
can have several layers and then add many more layers as time goes on.” In this study, the overview,
challenge, and outlook of 3D IC integration, and 3D Si integration will be presented and discussed. 3D
IC packaging will be briefly mentioned first.
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II. OVERVIEW AND OUTLOOKS OF 3D IC PACKAGING
Figure 1 shows that chip stacking by wire bonding and package-on-package (PoP) are now mature for
high volume manufacturing (HVM). Chip-to-chip interconnects and 3D fan-out embedded wafer-level
packaging are potential candidates for manufacturing.
Co
py
(a) Chip Stacking by Wire Bonding
The first paper on stacking of memory chips in 3D by die-attach material
all and A
Au wire bonding was
published by nCHIP [136] more than 20 years ago. Since then, memory chip
(especially the NAND Flash)
hip (espe
(espec
stacking by Au wire bonding has been in high volume production for, e.g.,
g., the smartphones and tablets.
Because of the surge in Au prices and research and development progress
ress
ss in Cu
C wire-bonding technology,
many companies have been looking for low-cost solutions, and the shift
hift from Au to Cu wire bonding as
shown in Figure 3 is genuinely picking up.
Top
Chip
Ma
n
Bottom
om Chi
Chip
Substrate
Figure 3 AMKOR’s 3D
D IC pack
packaging
pac
(stacked chips by Cu wirebonding)
Ac
ce
pt
ed
(b) Package-on-Package (PoP)
PoP comes from many different forms.
4 shows a wirebond package on top of a flip chip package.
rms. Figure
F
Fi
ckage
kage con
cconsists of two chips cross stacked and wire bonded on a package
It can be seen that the top package
ded.
d. The
T h bottom package consists of a solder bumped flip chip on another
substrate and then over molded.
package substrate with underfill.
All these package substrates are with solder balls. Again, PoP is in high
derfill.
fill. Al
A
.g.,
g., the sm
volume production for, e.g.,
smartphones and tablets [6].
Figure 4 3D wirebonding package on flip chip package. TOP: Schematic, BOTTOM: Photo image
Accepted manuscript posted September 24, 2014. doi:10.1115/1.4028629
Copyright (c) 2014 by ASME
(c) Chip-to-Chip Interconnects
Figure 5 shows the schematic of a 3D chip-to-chip interconnect [137] developed by IME. It consists of
the mother chip which is face-to-face connected to a daughter chip. The backside of the mother chip can
be attached to a heat spreader (and a heat sink if necessary). The whole module is attached (through the
flip chip mother die) to a rigid or flexible substrate. It is a very cost-effective 3D IC package without
using the TSVs [137]. In 2012, SONY’s PlayStation (CXD53135GG) attached Samsung’s 1Gb wide I/O
SDRAM (synchronous dynamic random access memory) face-to-face to the processor and then wire
bonded to the next level interconnects.
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Heat spreader/sink (optional)
Mother Die
Solder
Bump
Daughter Die
py
Rigid or Flex Substrate
Microbump
Co
Mother Die
NiAu
Daughter Die
ot
Cu + AuSn
tN
Figure 5 3D IC packaging (chip-to-chip
chip in
interconnects) [13]
Ma
nu
sc
rip
Figure 6 shows Amkor’s double POSSUMTM multi-stacked
stacked die configurations [138] without the use of
TSVs. It can be seen that the grandma die is supporting
upporting
pportin the mother die, which is supporting the 3
daughter dies. The grandma die is solder bumped
d flip chip
ch on a package substrate, which is then attached
ges
es show
sho
on to a PCB (printed circuit board). The packages
shown in Figures 5 and 6 are not in manufacturing yet,
however they are the potential candidates for medium
medium-range performance applications.
Ac
ce
pt
ed
Daughter
aughter Die
D
Package
Packag
Subs
Substra
Substrate
Grandma Die
PCB
Cu Pillar Micro-bumps
with SnAg solder caps
Mother Die
SnAg
Cu
Figure 6 3D IC packaging (Amkor’s multiple chip-to-chip interconnects) [138]
(d) 3D Fan-Out Embedded Wafer-Level Package
Figure 7 shows the cross section SEM (scanning electron microscopy) images of a 3D fan-out embedded
wafer-level package [139] developed by StatsChipPAC. It consists of a bottom package which is a
fan-out embedded wafer-level ball grid array package (eWLB) and a top package which is a memory
package. It can be seen that (a) the eWLP contains the logic, baseband, or application processor, (b) the
eWLB is only 450μm thick, (c) the top package is 520μm thick and is housing the memory chips with
wire bonding, and (d) the interconnection is from the PCB, solder balls, RDLs (redistribution layers), to
processor, and solder balls, RDL, to the memory chips. This package is a potential candidate for mobile
Accepted manuscript posted September 24, 2014. doi:10.1115/1.4028629
Copyright (c) 2014 by ASME
and wearable products.
Top Package
450μm
Bottom
eWLB
520μm
Top Memory Package
Bottom eWLB
Si Chip
RDL
0.9mm
450μm
Solder balls
PCB
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PCB
Figure 7 3D IC packaging (STATSChipPAC’s package-on-package)
kage)
age) [139]
[139
[1
ot
Co
py
(e) Outlook of 3D IC Packaging
The outlook of 3D IC packaging is great! Stacked dies with wirebonding
nding
ding and
an PoP are in HVM for
p interc
intercon
commercial products such as smartphones and tablets. Chip-to-chip
interconnects
are going to follow
afer--lev package is also a strong
SONY and get into manufacturing soon. 3D fan-out embedded wafer
wafer-level
candidate for production. All these 3D packaging technologies have been keeping 3D IC/Si integration
technologies away from HVM.
Ac
ce
pt
e
an
u
cr
ip
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F 3D S
Si INTEGRATION
III. OVERVIEW, CHALLENGES, AND OUTLOOK OF
orm the bonding operation for 3D Si integration
Basically, wafer-to-wafer (W2W) is the only way to perform
o bo
bon
nd on the good chips). In addition, the absence
and yield is a big issue (e.g., some bad chips are forced to
bond
al mana
manag
of (or an infinitesimal) gap between wafers and thermal
management could be a problem. Furthermore, the
he surfac
requirements of the bonding conditions, such as the
surface cleanness, surface flatness, and the class of
clean room for 3D Si integration are very high.
Figure 8 3D Si integration:
on:: ((L
(L)
L) IBM/RPI’s
I
IB
Cu-to-Cu bonding [71]. (R) NIMS/AIST/Toshiba/University of
Tokyo’s Cu-to-Cu bonding [74]
There are at least two different
iffe
ff
W2W bonding methods for 3D Si integration, namely, Cu-to-Cu bonding
and oxide-to-oxide bonding, as shown in Figures 8 and 9, respectively. In general, for Cu-to-Cu bonding,
the TSVs have to be fabricated before bonding. On the other hand, for oxide-to-oxide bonding, the TSVs
are fabricated after bonding. Figure 8a shows a high-quality bonding interface by IBM and RPI [71 - 73].
Before bonding, the Cu interconnects (pads) are fabricated with the standard back-end-of-line damascene
process, followed by the oxide CMP (chemical-mechanical polishing) process (oxide touch-up) to recess
the oxide level to 40 nm lower than the Cu surface. The bonding temperature is ramped up to 400°C.
Figure 8b shows a cross-section of the interface between the bumpless Cu-to-Cu electrodes (pads) given
by the NIMS/AIST/Toshiba/University of Tokyo [74-80].
Accepted manuscript posted September 24, 2014. doi:10.1115/1.4028629
Copyright (c) 2014 by ASME
ed
(a)
e
(b)
Co
py
Figure 9 3D Si integration: (a) MIT’s oxide-to-oxide bonding [81-87]. (b)) Leti/Freescale/
STMicroelectronics’
Leti/F
Leti/Fre
oxide-to-oxide bonding [88-89]
nu
sc
rip
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ot
Figure 9a shows a cross section of MIT’s oxide-to-oxide bonding
nding structure
st
of three-layer 3D (ring
llayers are bonded and interconnected
oscillator) bonded at 275°C [81-87]. It can be seen that: (1)) the laye
with W-plugs, (2) the conventional inter level connections are in the
t bottom two layers, and (3) the 3D
vias are located in the isolation (field) region
between transistors. Figure 9b shows
n betw
ric
ic bonding
bon
b
Leti/Freescale/STMicroelectronics’ dielectric-to-dielectric
structure of two device layers bonded
tall level
leve is formed on a 200 mm bulk wafer and SOI
at ~400°C [88-90]. It can be seen that: (a) first, a metal
nd then the bulk silicon of the SOI wafer is removed
wafer; next, these wafers are bonded face-to-face, and
1.5μm iinterstrata vias (ISVs) are formed, which make
down to the BOX (buried oxide) layer; (b) the ~1.5μm
etal la
lay
contact from upper strata to lower strata; (c) a metal
layer is formed at the top of the back side of the SOI
oth
h the tto
wafer, and (d) this ISV makes contact with both
top and bottom metal layers.
ce
pt
ed
Ma
In order to use the 3D Si integration technology
echnolog
chnolo to HVM products, many research and development
efforts have to be performed. Besides thermal
therma management, vias formation, thin-wafer handling, more
research and development efforts should
also
o
ould
aals be placed on areas such as: cost reduction, design and
process parameter optimization, bonding
onding
ding environment, W2W bonding alignment, wafer distortion, wafer
bow (warpage), inspection and testing,
testing contact performance, contact integrity, contact reliability, and
manufacturing yield issues. In
addition, packaging the 3D Si integration module systematically and
n additio
addit
reliably to the next level of interconnect
pose another great challenge.
nterconn
tercon
Ac
Besides technology issues
mentioned, the EDA (electronic design automation), which is the soul of
ess just m
3D Si integration [127]] is far fr
from ready. Urgently, the industry needs to build standard and infrastructure
and form an ecosystem
m for 33D Si integration. Then, the EDA can write the design, simulation, analysis &
i preparation, and test software with the following guidelines: (1) design
in
verification, manufacturing
automation from high level description to layout generation/optimization, (2) verification all dedicated
and tuned to 3D integration, (3) addressing the 3rd dimension not like a packaging bumping, (4)
addressing the true 3rd dimension, with partitioning, floor planning, automatic placing and routing, (5)
full extraction with the 3rd dimension, full 3D DRC (design rule checks), 3D LVS (layout vs. schematic)
with all tiers together in a same database, and (6) the 3D integrations have then to be seen as a whole
system distributed in several tiers, and not just a stack of predefined chips.
In the next 10 years, the industry will be hard-pressed for HVM with the 3D Si integration technology,
except for very niche applications. However, it should be noted and emphasized that 3D Si integration is
Accepted manuscript posted September 24, 2014. doi:10.1115/1.4028629
Copyright (c) 2014 by ASME
the right way to go and compete with Moore’s law. The industry should strive to make this happen!
IV. OVERVIEW, CHALLENGES, AND OUTLOOK OF 3D IC INTEGRATION
Unlike 3D Si integration, 3D IC Integration stacks up thin IC chips in the 3rd dimension with TSVs and
microbumps (< 25μm) [1] to achieve performance, low power consumption, wide bandwidth, and small
form factor. The ones which are in and going into low volume production are: memory stacking with
TSVs, hybrid memory cube (HMC) or wide I/O (input/output) DRAM, wide I/O DRAM 2, high
bandwidth memory (HBM), and 2.5D IC integration (passive interposer).
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(a) Memory Stacking with TSVs
Samsung mass-produced (August 2014) industry’s first TSV-based 64GB DDR4 (double
dou data rate type 4)
DRAM module which consists of 36 DDR4 DRAM chips, each of which consists
sts of fo
ffour 4-gigabit (Gb)
DDR4 DRAM dies. The module performs twice as fast as a module that usess wire bonding
packaging,
bbo
while consuming approximately half the power. The module is for server application.
plication
plication.
Co
py
¾ The hybrid memory
mory
ry cube is a
h one with 2
4-DRAM (each
2000+
ic contro
TSVs) on a logic
controller
ze is
s slightly larger
(which size
than the DRAMs) wi
with TSVs
ybrid
brid memory
memor
me
¾ The hybrid
cube is on
an organic
anic
nic pack
package
pa
substrate.
¾ The
e TS
TSV
TSV-DRAM
RAM is ~50μm thick.
he
e TSV-D
TSV-D
¾ The
TSV-DRAM
is with 20μm
(tall) Cu pillar + solder cap
microb
microbump.
¾ The m
memory cube is assembled
on DRAM at a time with
one
thermal compression bonding.
¾ The
T heat dissipation is from
10W to 20W.
¾ TSV diameter ~ 5 to 6μm.
sc
rip
Package Substrate
tN
ot
DRAM Stack
Microbump
bump
mp
nu
Figure 10 Micron’s sample
ple on hy
hyb
hybrid memory cube (HMC) [140]
Ac
ce
p
te
d
Ma
(b) Hybrid Memory Cube (HMC)
Figure 10 shows the very first sample [140]
by Micron/IBM at the end of September 2013. It is a
140]
40] shipped
sh
ship
hybrid memory cube (HMC) which consists
onsist of 4 DRAMs each with 2000+ TSVs stacking on top of a
onsists
MC is th
logic controller with TSVs. The HMC
then attached to an organic package substrate. The TSV DRAM
cube is fabricated by Micron and
TSV controller is fabricated by IBM. The microbumps are Cu
nd
d the T
pillars (20μm-tall) with solder caps.
aps.
¾ 5X the bandwidth vs.
GDDR5
¾ Up to 16GB
¾ One-third the footprint
¾ Half the energy per bit
¾ Managed memory
stack for optimal levels
of reliability,
availability and
serviceability
Figure 11 Intel’s Knights Landing processor unit with Micron’s HMC
At the 2014 International Supercomputing Conference it was announced that Intel “Knights Landing”
processor unit would debut in 2015. It will support for up to 384GB of on board DDR4 (double data rate
type 4) RAM and 16GB of Micron HMC stacked DRAM on-package, providing up to 500GB/sec of
memory bandwidth (Figure 11). Micron reports that having such HMC in the CPU (central processor unit)
Accepted manuscript posted September 24, 2014. doi:10.1115/1.4028629
Copyright (c) 2014 by ASME
package is expected to deliver 5X the sustained memory bandwidth vs. GDDR5 (graphics double data
rate type 5) with one-third the energy per bit in half the footprint.
40μm
2880μm
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40μm
1000μm
120μm
200μm
py
Figure 12 Schematic of JEDEX’s Wide I/O 2. Patent of quadrants
drants
ants oof microbumps
ce
pt
ed
TSV/RDL
Interposer
Ma
nu
sc
Hynix’s HBM
rip
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ot
Co
(c) Wide I/O DRAM and Wide I/O 2
JEDEC standard (JESD229) [141], Wide I/O Single Data Rate
(Wide I/O SDR), was published in
ate
te (Wi
December 2011 and JEDEC standard (JESD229-2) [141], Wi
Wide
de I/O 2 (WideI/O2), was published in
August 2014. They are meant for a stack of DRAMs with TSVs
SVs oon a logic controller with TSVs; very
similar to the HMC. The microbumps are divided into 4 quadrants
uadrants
adrant with signal assignments mirrored both
horizontally and vertically as shown in Figure 12, where the bu
bump pitch (40μm) of the area array is also
shown. The dimensions of each quadrant are 2880μm x 200μ
200μm. There will be a space between quadrants
200
in the x-direction (1000μm) and in the y-direction (120μm)
20μm) [141].
[1
TSV HBM DRAM
Microbump
GPU/CPU/SoC
GP
Optional
Base Chip
HBM Interface
Organic Package Substrate
PCBPCB
Ac
Underfill is needed between the interposer and the organic substrate. Also, underfill
Under
i needed between the interposer and the GPU/CPU and the HBM cube
is
Figure
re 13 Schematic
S
of JEDEX/Hynix’s High Bandwidth Memory (HBM)
(d) High Bandwidth Memory (HBM)
Figure 13 shows schematically a high bandwidth memory system developed by Hynix/AMD, which is
based on JEDEC standard (JESD235) [142], High Bandwidth Memory (HBM) DRAM, published in
December 2013. It is meant for graphics applications supporting bandwidth from 128GB/s to 256GB/s.
A TSV/RDL interposer is used to support/connect mainly the lateral communication (HBM interface)
between the HBM DRAM memory cube with TSVs and the SoC such as graphic processor unit (GPU)
or central processor unit (CPU) without TSVs. The optional base chip is used for buffering and signal
re-routing of the HBM DRAM cube.
Accepted manuscript posted September 24, 2014. doi:10.1115/1.4028629
Copyright (c) 2014 by ASME
Underfill
UBM
Cu Pillar
Chip 1
Solder
Chip 2
RDLs
RDLs for lateral
communication
of chips
(Redistribution
layers)
TSV
Underfill
Si
Interposer
UBM
Solder Bumps
Build-up
Layers
Package Substrate
Solder Balls
Not-to-scale
ye
di
te
d
Figure 14 TSV/RDL passive interposer supporting chips on packagee substr
substrate
substra
Ma
nu
sc
rip
t
No
tC
op
(e) Passive Interposer (2.5D IC Integration)
piece of device-less silicon
A 2.5D IC integration is a TSV/RDL interposer system which consists off a piec
less
ess TSV
TS silicon (also called a
with TSVs, RDLs, and IC chips without TSVs. This piece of device-less
ity,
y, fine
passive interposer) is used to support the high-performance, high-density,
fine-pitch chips and has RDLs
hematica
ematic
(mainly) for lateral communication between the chips as shown schematically
in Figure 14. Figure 15
2]. It can be seen that even with more
shows a sample designed and fabricated by Altera/TSMC [41, 42].
ill
ll not enough
een
than 12 buildup layers (6-2-6) on the package substrate, it is still
to support the four sliced
n, a passive
pass
pas
28nm FPGA (field-programmable gate array) chips. In addition,
TSV interposer with 200,000+
ascene
scene layers and one aluminum layer) at a
microbumps on 45μm-pitch and four RDLs (three Cu damascene
minimum of 0.4μm-pitch is needed. This type of structure (Figure
(Figures 14 and 15) is called by TSMC as chip
d has been in small production for Xilinx since
on (interposer) wafer on (package) substrate (CoWoS) an
and
the early of 2013.
Interposer
TSV
Chip
C4 Bumps
Package
Substrate
Build-up Layers
Bui
Solder
Balls
Cu
Pillar
Solder
The package substrate is at least (6-2-6)
RDLs
Ac
ce
p
TSV
Interposerr
¾4 RDLs: 0.4μm-pitch line width and spacing
¾Each FPGA has >50,000 μbumps on 45μm pitch
¾Interposer is supporting >200,000 μbumps
Figure 15
5 Altera/TSMC’s
Altera
Altera/
chips on wafer on substrate (CoWoS) [42]
Si substrate
TSV
DRIE
SiO2
S
SiO2 by
thermal
oxidation
or PECVD
Strip resist
Photoresist
Photoresist
SiO2
Mask, Litho/
Patterning
SiO2 etch
Ti/Cu
or Ta/Cu
Cu Plating.
Then anneal at
400oC for 30m
Cu
SiO2
PECVD or SACVD
SiO2, PVD barrier
layer (Ti or Ta)
and seed layer
(Cu)
Cu TSV
Ti/Cu or Ta/Cu
CMP the
overburden
Cu, Cu seed
layer, and
barrier layer
Figure 16 TSV fabrication process flow
Accepted manuscript posted September 24, 2014. doi:10.1115/1.4028629
Copyright (c) 2014 by ASME
0.40μm
10.1μm
0.83μm
TSV
100μm
0.44μm
Co
py
ed
ite
d
(e1) Fabrication of TSVs
The fabrication process of TSVs for interposer is shown in Figure 16. The process starts with a SiNx/SiOx
insulation layer by either thermal oxidation or PECVD (plasma enhanced chemical vapor deposition) as
shown in Figure 16. After photoresist and TSV lithography, the TSV is etched into the Si substrate by
Bosch-type DRIE (deep reactive ion etch) [45] to form a high aspect ratio (10.5) via structure. The
etched TSV structure is then processed with a SiOx liner by SACVD (subatmosphere chemical vapor
deposition), a Ta barrier layer, and a Cu seed layer by PVD (physical vapor deposition) [17]. Cu
electroplating is used to fill the TSV structure. The final blind TSV has a top opening of approximately
10μm in diameter and a depth of about 105Pm, which gives an aspect ratio of 10.5. In such a high aspect
ratio via structure, a bottom-up plating mechanism is applied to ensure a seamless TS
TSV with a reasonably
low Cu thickness in the field.
rip
tN
8.67μm
Figure 17 SEM images of TSV
SV ccross sections [5]
nu
sc
The SEM cross-sectional images are shown in Figure
gure
re 117.
7. It can be seen that the diameter of the TSV is
slightly decreased at the bottom, which is expected
ected
ed fr
from the etching process. The Cu thickness at the
field is <5μm. The post plating anneal is at 400qC
0qC
C for 30
3 min. To complete the TSV process, excess Cu in
the field is removed by CMP [13].
Ac
ce
pt
ed
Ma
(e2) Fabrication of RDLs
There are at least two ways to fabricatee RDL
RDLs [1, 2, 3, 5]. The first method is by using polymers, such as
polyimide (PI) PWDC 1000 (Dow
benzocyclobutene (BCB) cyclotene 4024-40 (Dow
ow
w Corning),
Cor
Corn
Chemical), polybenzo-bisoxazolee (PBO)
(PBO HD-8930 (HD Micro Systems), and the fluorinated aromatic
AL-X 2010 (Asahi Glass Corporation)
oration)
ration to make the passivation layer and electroplating (such as Cu) to
make the metal layers. This method hhas been used by the OSAT (outsourced semiconductor assembly
(withou
withou using semiconductor equipment) for wafer-level (fan-in) chip scale
and test) to fabricate RDLs (without
ed wafe
wafer
package [134], embedded
wafer-level (fan-out) ball grid array package [143 - 147], and (fan-out)
ckage
age [148,
[[14 149]. The second method is the Cu damascene method, which is
redistribution chip package
rom
om the conventional
c
primarily modified from
semiconductor back-end-of-line to make the Cu metal RDLs
nF
Fig
such as those shown in
Figure 15. In general, much thinner structures (both dielectric layers and Cu
RDLs), finer pitches, smaller line-widths, and spacing can be obtained with the dual Cu damascene
method, which will be briefly stated in the following.
If starting with the wafer from Figure 16, the fabrication process of RDLs with a dual Cu damascene
technique is primarily based on the semiconductor back-end-of-line process. The details are shown in
Figure 18 and listed in the following [5]: (1) SiO2 layer by PECVD, (2) apply photoresist and mask, then
use photolithography techniques (align and expose) to open vias on the SiO 2, (3) RIE (reactive ion etch)
of SiO2, (4) strip off portion of the photoresist, (5) repeat step 3, (6) strip off the photoresist, (7) sputter
Ti and Cu and electroplate Cu over the entire wafer, (8) CMP the Cu and Ti/Cu and RDL1 is completed,
Accepted manuscript posted September 24, 2014. doi:10.1115/1.4028629
Copyright (c) 2014 by ASME
and (9) repeat step 1 through step 8 to complete RDL2 and any additional layers.
SiO2
TSV
(Cu)
SiO2
Mask. litho
TSV
Ta/Cu
or
Ti/Cu
Si
RIE of SiO2
SiO2
TSV
SiO2 by PECVD
TSV
Strip resist
TSV
Photoresist
TSV
TSV
Sputter Ti/Cu
and plate Cu
V01
RDL1
TSV
TSV
RDL2
DL2
DL1
RIE of SiO2
TSV
CMP Cu
and Ti/Cu
V01
ed
ite
d
Mask, litho
RDL1
V12
DL12
DL01
V01
TSV
py
Figure 18 Process flow for fabricating RDLs by dual Cu
u damascene
damasc
damas
ot
Co
SEM images of the RDL cross sections fabricated by the Cu damascene
cene
ene technique
tec
tech
are shown in Figure
RD
R
19. The minimum RDL line width is 3 μm. The thickness of RDL11 and RDL2
is 2.6 μm and of RDL3 is
1.3 μm. The passivation thickness between RDLs is 1 μm.
tN
UBM
RDL3
RDL2
V23
V12
RDL1
V01
nu
sc
rip
TSV
TU
TO
RDL3
RDL
V23
V
V12
RDL1
V01
TSV
Ma
RDL
2
d
Figure 19 SEM images of cross sections
sectio of RDLs fabricated by the Cu damascene method [5]
Ac
c
ep
te
(e3) Backside Processing and Assembly
sembl
The process flow of backside and aass
assembly [5] is shown in Figure 20. It can be seen that after the
fabrication of TSV, RDLs, passivation,
and UBM (under bump metallurgy), the topside of the interposer
assivation
sivat
UBM
Passivation
Si Substrate
RDL/Pass.
TSV
Interposer
Adhesive
Carrier #1
C
Interposer
Carrier #1
Backgrinding
Temporary
Bonding Carrier #1
Carrier #1
Carrier #1
Silicon Etching
Pass., and Cu
Revealing
Chip
Carrier #1
Carrier #1
UBM
Carrier #2
C4 Wafer Bumping
Chip
Chip
Chip
TSV
Wafer Micro
bumping &
dicing
Carrier #2
De-bonding
Carrier #1
Not-to-scale
Carrier #2
Chip-on-Wafer.
Underfill
Temporary
Bonding Carrier #2
De-bonding
Carrier #2 and
dicing
RDLs
Interposer
Package Substrate
Assemble the TSV module on package
substrate, then test. Underfill
Figure 20 Conventional process flow for chip on interposer wafer on package substrate [8]
Accepted manuscript posted September 24, 2014. doi:10.1115/1.4028629
Copyright (c) 2014 by ASME
wafer is temporary bonded to a carrier by adhesive. The next step is backgrinding the interposer wafer, Si
etching, low temperature passivation, and Cu revealing. Next, backside RDL (optional), UBM, and C4
(controlled collapse chip connection) wafer bumping are carried out. After that, the next step is to
temporary bond another carrier wafer to the backside (with solder bumps) and de-bond the first carrier
wafer. This step is followed by chip-on-wafer bonding and underfilling. After the whole (chip-on)
interposer wafer is completed, the next step is to de-bond the second carrier wafer and transfer the thin
interposer wafer with attached chips to a dicing tape for singulation. The individual TSV/RDL interposer
with chips is attached to the package substrate by natural reflow and then underfilled.
Support Carrier
Complete
SiO2 frontside
RDLs &
UBM
Si
Si
Ta/Cu
Support Carrier
Adhesive
TSV
Si
TSV
Adhesive
Si
Adhesive
TSV
CMP for
SiN/SiO2
buffing,
and barrier
and Cu
seed layers
polishing
Ta/Cu
Adhesive
ive
ve
Ti/Cu
Cu
Adhesive
Si
TSV
Si dry etch
(RIE) to a
few microns
below the
TSV
Support Carrier
Adhesive
Si
TSV
Ti/Cu
TSV
Cu
C
Solder
So
Sputter
Ti/Cu
RDLs
and
UBM
passivation
SiN/SiO2
tN
ot
Support Carrier
Strip
resist
a
and
e
et
etch
Ti/Cu
Support Carrier
rrier
Si
SiN/SiO2 SiO2
TSV
Cu
Solder
SiN/SiO2
Support Carrier
Photoresist,
Mask,
litho, Cu
plating,
solder
plating
ng
g
Support Carrier
Si
passivation
Temporary
bonded to
a carrier by
adhesive.
Backgrinding
to a few
microns to
the TSV
Low
temperature
SiN/SiO2
Adhesive
ite
d
TSV
Co
py
ed
RDLs and UBM
Not-to-Scale
No
rip
Figure 21 Backside Cu reveal and UBM/solder
UBM/so
BM/s
plating process flow
Ma
nu
sc
(e4) Cu Revealing
Figure 21 shows more details on Cu revealing. Right af
after the temporary bonding of the support carrier,
backgrinding the wafer to a few microns to thee tip oof TSVs, Si dry etching (by RIE) to a few microns
below the tip of TSVs, and low-temperature
passiving the SiN/SiO 2 are performed. Then, CMP for
ture
re pa
pass
d layers ppolishing are carried out. Cu revealing is completed and
SiN/SiO2 buffing and barrier and Cu seed
shown in Figure 22 [5]. These processess also aapp
apply to device TSV wafers.
SiO2
SiO2
Cu
TSV
Si
Si
Cu
TSV
Si
Ac
Si
Figure 22 TSV Cu revealing.
vealing
al
(L) Before dry etch of Si. (R) After Si dry etching, low-temperature SiN/SiO2,
and removal (CMP) of the isolation, barrier, and seed layer [5]
(f) Outlook of 2.5D/3D IC Integration
TSVs straight through the same memory chips, e.g., DRAMs to enlarge the memory capacity, increase
the bandwidth, lower the power consumption, lower the latency (enhance the electrical performance),
and reduce the form factor is the right thing to do and will be the major application of 3D IC integration.
Besides Intel, HMC samples with capacities of 4GB and 8GB have already shipped to server and chip
companies for testing. The first HMC modules will be used on FPGAs. HMC is targeted for high
performance computing, cloud computing, in-memory database, networking, energy, wireless
communications, transportation, security, and high-end servers and the potential customers are Intel,
Accepted manuscript posted September 24, 2014. doi:10.1115/1.4028629
Copyright (c) 2014 by ASME
Altera, Fujitsu, Cray, Cisco, Huawei, Xilinx, HP, etc.
TSV/RDL interposer (2.5D IC integration) is in small volume manufacturing by Xilinx/TSMC for the
sliced FPGAs, which cannot be supported by the package substrate even with 12 build-up layers. Thus,
interposer is for very high performance, high density, high I/O, and fine-pitch applications such as
networking, communications, high-end servers, etc.
ed
ite
d
V. HVM SUPPLY CHAINS FOR TSVS AND MEOL
(a) Supply Chains before the TSV Era
Before the TSV era, the technology supply chains are very well defined and understood. Descriptions of
the various entities comprising the supply chain before the TSV era are presented below.
bel
el
py
(a1) FEOL (front-end-of-line)
This is the first portion of IC fabrication where the individual devices such as trans
transistors or resistors are
transis
patterned. This process is from a bare wafer to (but not including) the deposition
position
sition oof metal layers. FEOL
is usually performed in semiconductor fabrication plants (fabs).
tN
ot
Co
(a2) BEOL (back-end-of-line)
This is the fabrication in which active devices are interconnected with wir
wiring on the wafer. This process
starts from the first layer of metal to bonding pads with passivation.
ion.
on. IIt aalso includes insulators and metal
contacts and is called MOL (middle-of-the-line). The term “MOL”
MOL” is
i seldom used and embedded in the
BEOL. Again, BEOL is usually performed in the fabs.
sc
rip
(a3) OSAT (outsourced semiconductor assembly and tes
test)
te
t)
This term is also called packaging, assembly and test.
st. The pprocess starts when the passivated wafer is
received from the fab and then goes through circuitt probing
probing, bumping, thinning, dicing, wiring bonding,
probin
flip-chip, molding, ball mounting, final testing, and
ndd eetc.
tc.
Ma
nu
(b) Supply Chains for the TSV Era – Who Makes tthe TSV?
The following steps in the TSV fabrication
process impact the various considerations that must be
ion
n pro
proc
addressed:
pt
ed
(b1) TSVs Fabricated by the Via-First
rst Process
Proc
Pro
The TSVs are fabricated before thee FEOL
FEOL.
FEO
L This can only be done by the fab. However, even in the fab,
this seldom happens because the devices
evices ((e.g., transistors) are much more important than the TSVs.
Ac
ce
(b2) TSVs Fabricated by the
Via-Middle
Process
he Via
Via-M
The TSVs are fabricated right
after the FEOL (e.g., transistors) and MOL (e.g., metal contacts), and
ight aft
before the BEOL (e.g., metal
layers).
In this case, the MOL is no longer embedded in the BEOL because
etal la
lay
the TSV fabrication process
rocess is between them. Owing to logistics and equipment compatibilities, usually
the TSV by the via-middle
is done by the fab.
middle
ddle process
pr
p
(b3) TSVs Fabricated by the Via-Last (From the Frontside) Process
The TSVs are fabricated (from the frontside of the wafer) after the FEOL, MOL, and BEOL. As of today,
there is not a single creditable paper published with this process.
(b4) TSVs Fabricated by the Via-Last (From the Backside) Process
The TSVs are fabricated (from the backside of the wafer) after the FEOL, MOL, and BEOL process
flows. The CMOS image sensor is an example. Strictly speaking, CMOS image sensors are not examples
of 3D IC integration. For CMOS device sample wafers, the only creditable publication is given by LETI,
et al., [150]. However, because of technical issues, such as hitting the various embedded alignment
Accepted manuscript posted September 24, 2014. doi:10.1115/1.4028629
Copyright (c) 2014 by ASME
targets in the x-, y- and z-directions (to enable the alignment between the metal layers on the topside of
the wafer and the positioning of TSVs formed from the backside), TSVs fabricated by the via-last (from
the backside) process should be avoided until these issues are resolved.
Based on the above discussions, it seems that for active device wafers being used for 3D IC integration
applications, TSVs are better fabricated using the via-middle process. Also, the TSVs should be
fabricated by the fabs, where all the equipment and expertise already exist and the cost to fabricate the
TSVs is less than 5% of the cost in fabricating the (≤32nm) device wafers!
ed
ite
d
(b5) How About the Passive TSV Interposers?
When the industry defined the TSV processes for 3D IC integration, there were no pa
passive interposers yet.
Also, since there is no active device in the passive interposers, thus they don’t
n’t fi
fit into any of the
preceding!
Co
py
(b6) Who Wants to Fabricate the TSV for Passive Interposers?
Both the fab and OSAT want to do it! It depends on the layout, design,
ign,
gn, and fabrication capabilities,
especially the line width and spacing of the RDLs and the diameterr of th
the TSVs. Usually, for a few
microns of line width and spacing of the RDL and ≥ 5μm of TSV diameter
meter it can be done by the OSAT.
Otherwise, it should be done by the fabs.
sc
rip
tN
ot
(c) Supply Chains for the TSV Era - Who Does the MEOL??
For the thicknesses of memory-chip stacking and DRAMss in HMC
HM and HBM, and interposers under
consideration, all the TSVs fabricated are blind vias. The
he blind TSV wafer is followed by temporary
bonding, backgrinding, TSV revealing, thin wafer handling,
cleaning, solder bumping, etc.
ndlin
dling
ng,, debonding,
d
which, taken together, are called MEOL (middle-end-of-line).
Except for the vertically integrated
end
nd--of
offl
companies (e.g., TSMC and Samsung), it is better for the MEOL process flow to be performed by the
OSAT.
Ma
nu
Vss and MEOL
M
(d) Outlook of HVM Supply Chains for TSVs
For device wafers, the TSVs should be fabricated
bricated
ricated by the via-middle process and manufactured by the
fabs. For deviceless wafers, it depends on
n the lline
lin width/spacing of the RDLs and the diameter of the
TSVs. As to the MEOL, for both devicee and deviceless
wafers, it should be done by the OSAT.
dev
de
ce
pt
ed
VI. SUMMARY AND RECOMMENDATIONS
MEND
ENDAT
The overview, challenge, and outlook
tlook
ook oof 3D IC packaging, 3D IC integration, and 3D Si integration have
been presented and discussed. The fa
fabrication processes of TSVs and RDLs have also been mentioned.
fabr
ains
ns of T
Furthermore, the supply chains
TSVs and 3D IC integration at HVM have been examined. Some
mmendat
mendat
important results and recommendations
are summarized in the following.
Ac
orces fo
for consumer products such as smartphones, tablets, and wearables are cost,
¾ The driving forces
t. The cost-effective
co
cost, and cost.
3D IC packaging such as the stacked dies by wirebonding, PoP,
chip-to-chip interconnect,
and 3D fan-out embedded wafer-level packaging are just the right
erc
technologies for these products.
¾ The driving forces for high performance computing, cloud computing, networking, wireless
communications, high-end servers are performance and reliability. The considerable high-cost
2.5D/3D IC integrations such as memory chip stacking with TSVs, HMC, HBM, wide I/O 2, and
passive interposer are the right technologies for these products.
¾ For device wafers, the TSVs should be fabricated by the via-middle process and manufactured
by the fabs. For interposer wafers, if the diameter of the TSVs is ≥ 5μm and the line
Accepted manuscript posted September 24, 2014. doi:10.1115/1.4028629
Copyright (c) 2014 by ASME
width/spacing of the RDLs is ≥ 3μm then it can be manufactured by the fabs and OSAT,
otherwise it should be done by the fabs. However, since most interposers are for very high
performance, high density, and fine-pitch applications, thus the TSV diameters and RDLs line
width and spacing are most likely falling into the fabs’ territory.
¾ As to the MEOL, assembly, and test of both the TSV device and deviceless wafers they should
be performed by the OSAT except the vertical integrated companies such as TSMC and
Samsung. There are many important tasks in MEOL, assembly, and test, thus the ODAT should
strive to make themselves ready for a robust and high-yield manufacturing process.
ed
ite
d
VII. ACKNOWLEDEGMENTS
The author would like to thank his colleagues at Institute of Microelectronics,, Hong Kong University
M Paci
Pacifi
Science and Technology, Industrial Technology Research Institute, and ASM
Pacific Technology for
their stimulating and fruitful discussions.
Ac
ce
pt
ed
Ma
nu
sc
rip
tN
ot
Co
py
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