Liberty for Low Power Design
Predictable Success
Agenda
• What’s needed for Low Power?
• New power capabilities
ƒ Approved by Liberty TAB
• Need more ?
© 2006 Synopsys, Inc. (2)
Predictable Success
Multi-Voltage Design
Dynamic and Leakage Power Reduction
• Multiple Vdd designs
are becoming popular
Voltage 1
1.0V
300 MHz
Voltage 2
0.8V
250 MHz
• Dynamic Voltage &
Frequency Scaling is
another technique
3
Voltage 4
1.2V
1.5V
400 MHz
500
Libraries Need Delay and Power Models for a Wide Range of Vdd
© 2006 Synopsys, Inc. (3)
Predictable Success
Power Integrity
•
Tools to compute:
ƒ Voltage drop on instance rail pins
Voltage-drop
ƒ Impact of voltage drop on delay
Dynamic Voltage-drop
V(t) = I(t) R + L di(t)/dt
Static IR-drop
Vstatic = I R
Time
Libraries Need New Models For Power Integrity Analysis
© 2006 Synopsys, Inc. (4)
Predictable Success
Liberty™ is an Industry Standard
Over 750 libraries
available
100+ Semiconductor Vendors
Liberty
Supported by all major
IP Providers
Supported by over 60 EDA
vendors and over 75 tools
At the heart of Semiconductor Design
© 2006 Synopsys, Inc. (5)
Predictable Success
What’s Needed for Low Power Design ?
•
Accurate Modeling of Critical Power Effects
ƒ Voltage Scaling (timing, power, noise) – accurate across a broad range
ƒ Cell/rail currents plus equivalent parasitics
ƒ Gate leakage and channel leakage
ƒ Macro modeling capabilities
•
Power / Ground (PG) pins
ƒ A place to attach rail/currents and equivalent parasitics
ƒ Automated power & control connection and checking, especially for special
cells:
• Level Shifters, Isolation, Retention
•
Switch Cells
ƒ Coarse-grained and Fine-grained
ƒ DC I/V Curve Voltage Drop
ƒ Automated power & control connection and checking
© 2006 Synopsys, Inc. (6)
Predictable Success
Accurate Modeling of Critical Power Effects:
Voltage and Temperature Scaling
•
CCS enables high accuracy analysis for wide range
of Voltages and Temperatures
ƒ
For power-aware design styles:
• Single Vdd
• Multiple Vdd
• Dynamic voltage & frequency scaling (DVFS)
lib_1.2v.db
ƒ Accounting for IR Drop impact on delay
•
What is scaled:
ƒ Driver model (timing)
lib_1.0v.db
ƒ Receiver model (timing)
ƒ Timing constraints:
• setup, hold, recovery, removal, MPW
lib_0.8v.db
ƒ Noise models
ƒ Power analysis
•
Library Characterization is Straightforward
© 2006 Synopsys, Inc. (7)
Separate CCS
Libraries
Predictable Success
Accurate Modeling of Critical Power Effects:
Cell/rail currents plus equivalent parasitics
Dynamic Current
Waveform per
transition per Rail
0.7
0.5
i(t)
0.1
input
.023 .047 .065 .078 .091
slew
output cap
Leakage current per state
per rail
Equivalent
Parasitics
© 2006 Synopsys, Inc. (8)
0.2
Parasitics per state
Predictable Success
Accurate Modeling of Critical Power Effects:
Gate Leakage & Channel Leakage
•
Channel leakage Modeling
ƒ Static current from source to drain
ƒ State dependent
A
state
A
A
A
•
Gate leakage Modeling
ƒ Static current from driver cell to transistor gates of load cell
ƒ State dependent
© 2006 Synopsys, Inc. (9)
Predictable Success
Accurate Modeling of Critical Power Effects:
Gate Leakage & Channel Leakage
cell(cell_name) {
...
leakage_current() {
when : state_1;
pg_current(pg_pin_1) {
value : val_1_1;
}
...
pg_current(pg_pin_n) {
value : val_1_n;
}
gate_leakage(input_1) {
input_low_value : val_low_1_1;
input_high_value : val_high_1_1;
}
...
}
gate_leakage(input_n) {
input_low_value : val_low_1_n;
input_high_value : val_high_1_n;
}
}
leakage_current() {
when : state_2;
...
}
leakage_current() {
/* default state */
...
2 levels of state dependency for Gate Leakage
– based on PG pin state and gate input
© 2006 Synopsys, Inc. (10)
Predictable Success
Accurate Modeling of Critical Power
Effects: Macro modeling capabilities
•
Asynchronous Operation Modeling
ƒ
Asynchronous Read access
ƒ Model multi-input events
cell(cell_name) {
power_cell_type : macro;
dynamic_current(event_name) { /* the label is optional */
when : state_1;
related_inputs : related_input_list;
switching_group() {
input_switching_condition(input_sense);
min_input_switching_count: min_val;
•
Consolidated equivalent parasitic
© 2006 Synopsys, Inc. (11)
Predictable Success
Power/Ground (PG) Pin Support
Place to attach rail/currents and equivalent parasitics
Dynamic Current
Waveform per
transition per Rail
0.7
0.5
i(t)
0.1
input
.023 .047 .065 .078 .091
slew
output cap
Leakage current per state
per rail
Equivalent
Parasitics
© 2006 Synopsys, Inc. (12)
0.2
Parasitics per state
Predictable Success
PG Pin Support
Special Cells
•
•
Provides support for real PG library pins where:
ƒ
power pin means current source pin and
ƒ
ground pin means current sink pin
Provides mapping from:
ƒ
PG pins to related inputs & outputs
ƒ
PG pins to automatically connected power nets
Level Shifter
© 2006 Synopsys, Inc. (13)
Predictable Success
PG-Pin syntax example
library(sample) {
voltage_map(VDD1, 3.0);
voltage_map(VDD2, 3.1);
voltage_map(GND1, 0.3);
voltage_map(GND2, 0.0);
…
cell(test) {
pg_pin(P1) {
voltage_name : VDD1;
pg_type : primary_power;
}
…
pg_pin(G2) {
voltage_name : VDD2;
pg_type : primary_ground;
}
…
leakage_power() {
when : “!A”;
value : 1.5;
related_pg_pin : P1;
© 2006 Synopsys, Inc. (14)
pin(A) {
direction : input;
Associate power & ground
with signals
related_power_pin : P2;
related_ground_pin : G2;
Referenced
by pg_pin
input_signal_swing() {
low : 2.0;
high : 2.8;
}
…
}
…
Valid values of the pg_type attribute are : primary_power, primary_ground,
backup_power, backup_ground, internal_power and internal_ground
Predictable Success
PG Pins: Automated Connection and Checking
connect_power_domain automatically connects cells
in four different ways:
ƒ ‘primary’ power or ground net for a power domain
ƒ ‘backup’ (always on) power or ground net for a power domain
ƒ ‘internal’ (switched) power or ground net for a power domain
ƒ Via use-defined power_connection_type when more
automated connections are needed.
• Checking based on ranges defined in the
•
min/max/hi/low values in input/output voltage groups
Note: May be adjusted as UPF is developed
© 2006 Synopsys, Inc. (15)
Predictable Success
Switch Cell Support
• Liberty extended to support switch cells
ƒ Power down logic to save power
• Fine grain (per cell)
• Coarse grain (per block)
A
B
Fine Grain
switch
Z
Logic
Partition
Coarse Grain
Switch_cell_type: fine_grain or coarse_grain.
Switch_function: defines the condition to turn off switch/partition
Switch_pin: identifies pin as switch pin
© 2006 Synopsys, Inc. (16)
Predictable Success
Switch Cells:
Coarse-Grained & Fine- Grained
cell(NAND2SLP) {
switch_cell_type : fine_grain;
leakage_power () {
when : SL;
value : 0.008;}
pin(Z) {
function : “!(A*B)”; /* switch pin not in here */
switch_function : “!SL";
direction : output;
cell ( CG_SWITCH ) {
switch_cell_type : coarse-grain;
pg_pin ( VDD ) {
type : primary_power;
voltage_name : VDD;}
pg_pin ( VVDD ) {
type : internal_power;
switch_function : “CTL”}
© 2006 Synopsys, Inc. (17)
Predictable Success
Switch Cells: DC I/V Curve Voltage Drop
pin ( CTL ) {
switch_pin : true;
capacitance: 0.034;}
/* I/V curve information */
dc_current ( ivt1 ) {
related_switch_pin : CTL; /* control pin */
related_pg_pin : VDD; /* source */
related_virtual_pg_pin : VVDD; /* drain */
/* index_1 is used to specify the input_voltage
values
of the switch pin */
/* index_2 is used to specify the voltage
difference
values between the related_pg_pin and
related_virtual_pg_pin */
values(“0.010, 0.020, 0.030, 0.030, 0.030”, \
“0.011, 0.021, 0.031, 0.031, 0.031”, \
“0.012, 0.022, 0.032, 0.032, 0.032”, \
“0.013, 0.023, 0.033, 0.033, 0.033”, \
“0.014, 0.024, 0.034, 0.034, 0.034”);
© 2006 Synopsys, Inc. (18)
Predictable Success
Switch Cells: Automated power &
control connection and checking
cell ( CG_SWITCH ) {
…
switch_cell_type : coarse-grain;
pg_pin ( VDD ) {
type : primary_power;
voltage_name : VDD;
}
pg_pin ( VVDD ) {
type : internal_power;
switch_function : “CTL”
}
pin ( CTL ) {
switch_pin : true;
capacitance: 0.034;
© 2006 Synopsys, Inc. (19)
Predictable Success
Need more information ?
• Full Liberty Documentation, Parser & Messageboards
ƒ Tap-in website & Si2 Liberty TAB websites
ƒ http://www.synopsys.com/partners/tapin/tapin_program.html
ƒ http://si2.org/?page=701
• Using Liberty with Low Power commands
ƒ Accellera UPF Technical Subcommittee
ƒ http://www.accellera.org/activities/upf
© 2006 Synopsys, Inc. (20)
Predictable Success