Doctoral Class
MICROELECTRONIC DESIGN CAD TOOLS - I
ANALOG TUTORIAL INTRODUCTION
José Luis González Jiménez
(Based upon the Hit-Kit documentation and tutorial by AMS)
Departament d’Enginyeria Electrònica
Universitat Politècnica de Catalunya
CAD-I. Analog Tutorial Introduction 1
Analog Tutorial Outline:
• Create a schematic of an OpAmp
• Create a symbol for the OpAmp
• Create a simulation testbench
• Start Analog Circuit Design Environment
• Setup a simulation
• Run the simulation
• Postprocess simulation results using the Calculator
CAD-I. Analog Tutorial Introduction 2
1
Calculator
Calculator uses RPN
An expression like
4*5/(3-2) has to be
entered like:
4↵5 ↵3 ↵2 - / *
(where ↵ means ‘enter’
button)
Calculator has powerful
waveform postprocessing !
CAD-I. Analog Tutorial Introduction 3
AHDL model
OpAmp Model
(INP-INN)×gain
INP
_
INN
R
×
Internal node
C
fg=1/(2πRC)
VSS
A lot of examples can be found in the ahdlLib at $CDSDIR/tools/dfII/artist/ahdlLib
CAD-I. Analog Tutorial Introduction 4
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AHDL model
// VerilogA for ana_tut, op_amp, veriloga
`include "constants.h"
`include "discipline.h"
// Pin declarations
module op_amp(OUT, INN, INP, VDD, VSS);
output OUT;
input INN,INP,VDD,VSS;
electrical OUT,INN,INP,VDD,VSS;
Definitions of pins,
// params and variables
parameters & variables.
parameter real cut_off_frequency = 50.0;
parameter real gaindB = 100;
real c0;
real r0;
real gain;
// internal node
electrical internal_node;
analog begin
// initial calculations
@ (initial_step or initial_step("dc")) begin
Only once performed
r0 = 1/(2*3.141592654*cut_off_frequency*10e-6);
gain = pow(10, (gaindB/20));
calculations.
end
c0 = 10e-6;
// always et to 10u
V(internal_node) <+ gain*V(INP,INN);
Concurrently
V(internal_node,OUT) <+ I(internal_node,OUT)*r0; // resistor equation
performed
I(OUT,VSS) <+ ddt(c0*V(OUT,VSS)); // capacitor equation
end
‘actions’
endmodule
CAD-I. Analog Tutorial Introduction 5
AHDL model
Concurrently performed statements:
Statements like:
I(OUT,VSS) <+ ddt(c0*V(OUT,VSS));
I(OUT,VSS) <+ V(OUT,VSS)/100e3;
are calculated concurrently. In this case, we have a capacitor and a
parallel resistor. These equations do not exclude each other!
V(OUT,VSS) <+ 2.0;
V(OUT,VSS) <+ 1.0;
would cause 3.0 Volts between the nodes OUT and VSS.
CAD-I. Analog Tutorial Introduction 6
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