Nuclear Instruments and Methods in Physics Research A 436 (1999) 281}284
Analog readout modules for the ZEUS microvertex detector
T. Fusayasu *, K. Tokushuku
Department of Physics, University of Tokyo, Tokyo, 7-3-1 Hongo, Bunkyo-ku, Tokyo 113-0033, Japan
Tanashi-branch, Institute of Particle and Nuclear Studies, KEK, Midori-cho 3-2-1, Tanashi, Tokyo 188-8501, Japan
Abstract
Analog readout modules have been developed for a silicon microvertex detector of the electron}proton collision
experiment ZEUS. Analog signals kept in the front end are read out and digitized by ADCs and processed afterwards to
reduce the data volume while keeping the signal information. We have developed prototype modules with 10-bit 10 MHz
ADCs and digital processors built in Field Programmable Gate Arrays. Their performance was investigated. 1999
Elsevier Science B.V. All rights reserved.
1. Introduction
The ZEUS detector [1] is a versatile detector for
the electron}proton collision experiment at HERA.
In order to improve its vertex measurements, a silicon microvertex detector (MVD) [2] will be installed around the beampipe in the year 2000. The
MVD enables more precise measurements of the
vertex positions and decay length of short lifetime
particles such as q's and heavy mesons.
The MVD consists of two parts; the barrel detector and the forward detector. The barrel detector
has a three-layer structure. Each layer is composed
of 6 cm;60 cm ladders. Each ladder is built up
with two layers of single-sided silicon microstrip
detectors of 6 cm;6 cm square and 300 lm thick.
They have a strip every 20 lm and a readout strip
every 120 lm. The strips of each layer run in orthogonal directions, which allows two-dimensional
position measurements. The forward detector con-
* Corresponding author.
E-mail address: fusa@helios.tanashi.kek.jp (T. Fusayasu)
sists of four wheels, which are similar to the barrel
but made of trapezoid-shape detectors.
The total number of readout strips amounts to
about 200 000. It is necessary to have signal multiplexing at the front end readout and online data
reduction soon after the analog-to-digital conversion.
The next section gives a brief description of the
front end readout. Functions of the ADC module
are described in Section 3. The performance of the
analog part is presented in Section 4.
2. Front end electronics
We have selected the HELIX chips [3] for the
front end readout. The HELIX was developed by
the ASIC Labor Heidelberg for the HERA-B experiment. Some modi"cations are being made for
our purpose. One HELIX chip contains 128 channels of charge ampli"ers and shapers followed by
141-cell analog pipelines. Once a trigger received,
128 analog data signals in pipeline cells are sent out
through a single analog line synchronized with an
0168-9002/99/$ - see front matter 1999 Elsevier Science B.V. All rights reserved.
PII: S 0 1 6 8 - 9 0 0 2 ( 9 9 ) 0 0 6 3 4 - 8
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T. Fusayasu, K. Tokushuku / Nuclear Instruments and Methods in Physics Research A 436 (1999) 281}284
3. ADC module design
developed by the NIKHEF group, and fed to the
ADC module. At the input of the ADC module, the
signal range is 0}2 V, which corresponds to
0}10 MIP.
A schematic view of the ADC module is shown in
Fig. 2. One ADC module processes eight analog
input channels. Each ADC unit (ADCU) handles
one analog input line. It consists of a 10-bit 10 MHz
analog-to-digital converter (AD9200) and a data
processor implemented in a programmable gate
array (the XC4028EX of XILINX). The processed
data are stored in FIFOs. A data formatter, implemented in another XC4028EX, reads out the
FIFOs of all ADCUs and writes formatted data
into data bu!ers, which are accessible from the
VME bus.
The data processor in the ADCU is similar to
that proposed for the CMS microstrip tracker [4].
The block diagram of the data processor is shown
in Fig. 3. First, 10-bit ADC data are processed for
pedestal and common mode subtraction. Then,
strips with charge greater than threshold values are
kept for cluster "nding. A threshold is set to the
total charge of the cluster for further data reduction. The size of the input raw data volume is
estimated to be reduced to about 2% after the
threshold cut and to about 0.1% after the cluster
cut. An ADCU has 3 FIFOs for the output data: for
the raw data, for the strip data, which consist of
strip I.D. and the ADC values, and for the cluster
data, which contain the total charge and the location of the cluster.
The readout system is data driven in the sense
that the HELIX outputs the analog signal with its
own scheduling after a trigger and there is no way
for the ADC module to control the #ow, except to
set a trigger veto for a data bu!er full condition.
Therefore, we need to have several checks in the
ADC module to ensure correct event processing.
The length of the input data is checked for its
correspondence to the number of expected data.
The cell number is decoded from trailer data and
checked to "nd out whether it is that from other
HELIX chips in the same token ring. The data
arrival times are measured with respect to the
The output of the HELIX daisy chain is ampli"ed and transferred by an analog link board, being
1 MIP corresponds to about 24 000 electrons at the ampli"er
input.
Fig. 1. Output signal of the HELIX chip.
Fig. 2. Schematic view of the ADC module.
output clock. At the end of the transfer of the strip
data, an 8-bit trailer, which encodes the cell location, is generated (see Fig. 1). In the daisy chain
mode, signals from several chips can be read out
through one analog line. In case of the ZEUS
MVD, data of 8 HELIX chips are read out per line,
which results in 206 analog links in total. The chip
could run at up to 40 MHz, but we use a 10.41 MHz
clock, synchronized to the HERA bunch crossing
cycle.
T. Fusayasu, K. Tokushuku / Nuclear Instruments and Methods in Physics Research A 436 (1999) 281}284
283
Fig. 4. ADC counts distributions for 4 types of charge injection.
Fig. 3. Block diagram of the Xilinx processor on the ADC unit.
trigger timing. Too early or late arrival is de"ned as
an error. Error conditions are indicated in the
header. Implementing all the data processor logic,
about 90% of con"gurable logic blocks in
XC4028EX are used.
We have produced prototype boards with 2
ADCUs in 6U;340 mm. The analog parts are
detachable such that several di!erent designs can
be tested. The "nal module will contain eight ADC
units per board.
common mode rejection are applied o%ine. Fig. 4
shows the distribution of ADC counts for each test
charge values. The resolution estimated from the
"gure is about 0.1 MIP in RMS. The broad distribution was found to be due to several instrumental
problems in the measurement: mainly due to an
instability of HELIX pedestals caused by a noise
from the power line and due to channel-to-channel
and global variations of injected charge. After removing these known e!ects, the noise level of the
analog system is estimated to be less than 2 ADC
counts. More precise tests will be performed in the
future.
The digital processing part is tested separately
with digital test patterns stored in memory implemented in the module. The data formatter is under
development. A total integrated test from HELIX
to the data formatter will be performed.
5. Summary
We have been developing ADC modules for the
ZEUS MVD. Prototype modules were produced.
The analog part and the digital processing part are
tested separately.
4. Status and performance of the ADC module
The performance of the analog part was quickly
investigated with internal charge injection on the
HELIX. The HELIX has a test sequence to generate a test charge in a repetitive pattern of #2, #1,
!1 and !2 MIP into each channel. Digital data
of the ADCU are recorded with a logic analyzer.
Signal processing such as pedestal subtraction and
Acknowledgements
We would like to thank the ZEUS MVD group
for useful discussions and valuable advice. This
work was supported by Japan's Ministry of Education, Science, Sports and Culture (the Monbu-sho)
and its Grants for Scienti"c Research.
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References
[1] The ZEUS Detector, Status Report 1993, DESY 1993.
[2] A Microvertex Detector for ZEUS, ZEUS Collaboration,
DESY-PRC 97/01.
[3] Helix128-2.x User Manual, Wolfgang Fallot-Burghardt
et al., HD-ASIC-33-0697. The modi"cations for ZEUS
(HELIX 3.0) are described in http://wwwasic.ihep.uniheidelberg.de/ I feuersta/projects/Helix/index.html.
[4] M.D.M. de Fez Laso et al., Proceedings of 2nd Workshop
on Electronics for LHC Experiments, CERN/LHCC/96-39,
1996, p. 499.