AT91EB40
Evaluation Board
.............................................................................
User Guide
Table of Contents
Section 1
Overview............................................................................................... 1-1
1.1
1.2
1.3
Scope ........................................................................................................1-1
Deliverables ..............................................................................................1-1
The AT91EB40 Evaluation Board .............................................................1-1
Section 2
Setting Up the AT91EB40
Evaluation Board .................................................................................. 2-1
2.1
2.2
2.3
2.4
2.5
2.6
2.7
Electrostatic Warning ................................................................................2-1
Requirements............................................................................................2-1
Layout .......................................................................................................2-1
Jumper Settings ........................................................................................2-2
Powering Up the Board .............................................................................2-2
Measuring Current Consumption on the AT91R40807 .............................2-3
Testing the AT91EB40 Evaluation Board .................................................2-3
Section 3
The On-board Software ........................................................................ 3-1
3.1
Flash Memory Organization ......................................................................3-1
3.1.1
Flash Write Access.............................................................................3-1
3.1.2
Boot Software .....................................................................................3-2
3.1.3
Functional Test Software (FTS)..........................................................3-2
3.1.4
SRAM Downloader .............................................................................3-2
3.1.5
Angel Monitor .....................................................................................3-3
Section 4
Circuit Description................................................................................. 4-1
4.1
4.2
4.3
4.4
4.5
4.6
4.7
4.8
AT91EB40 Top Level................................................................................4-1
AT91R40807 Processor............................................................................4-1
I/O Expansion ...........................................................................................4-1
External Bus Interface...............................................................................4-1
Power, Crystal Oscillator and Clock Distribution.......................................4-1
JTAG Interface, Reset, Interrupts and LEDs ............................................4-2
Serial Interface ..........................................................................................4-2
Layout Drawing .........................................................................................4-2
i
Table of Contents
Section 5
Appendix A – Configuration Links and SRAM Bank 1 .......................... 5-1
5.1
5.2
5.3
Jumpers (LK2) ..........................................................................................5-1
Surface Mount Links (LK1, LK3 - 9) ..........................................................5-1
Increasing Memory Size ...........................................................................5-2
Section 6
Appendix B - Schematics...................................................................... 6-1
6.1
ii
Schematics ...............................................................................................6-1
Section 1
Overview
1.1
Scope
The AT91EB40 Evaluation Board enables real-time code development and evaluation.
It supports the AT91x40 series with its various memory options.
This guide focuses on the AT91 Evaluation Board as an evaluation and demonstration
platform:
1. Section 1 provides an overview.
2. Section 2 details the setup of the development board.
3. Section 3 describes the on-board software.
4. Section 4 gives the circuit description.
Following are two appendixes covering configuration links and memory data, and schematics including pin connectors.
1.2
Deliverables
The evaluation board is supplied with a DB9 plug to DB9 socket straight through serial
cable to connect the target evaluation board to a PC. There is also a bare power lead
with a 2.1 mm jack on one end for connection to a bench power supply.
To use the evaluation board the user needs to provide a host computer and a debugging
system.
1.3
The AT91EB40
The board consists of an AT91R40807 together with several peripherals:
Evaluation Board ■ Two serial ports
■
Reset button
■
Three applicative buttons (FIQ, TIOB0, IRQ0)
■
Three LEDs (TIOA0, TIOA1, TIOB0)
■
512K bytes 16-bit SRAM (upgradable to 2048K bytes)
■
128K bytes 16-bit Flash (of which 64K bytes is available for user software)
■
20-pin JTAG interface connector
If required, user-defined peripherals can also be added to the board. See Section 5,
“Appendix A – Configuration Links and SRAM Bank 1” on page 5-1 for details.
AT91EB40 Evaluation Board User Guide
1-1
Overview
Figure 1-1. AT91EB40 Block Diagram
AT91R40807
8K Byte
RAM
JTAG
ICE
Connector
128K Byte
Extended
SRAM
SRAM
Flash
ARM7TDMI
Processor
EBI
Monitor
Points
EBI
ASB
AMBA
Bridge
Buttons
Reset
Controller
Interrupt
Controller
Watchdog
Timer
Reset
1-2
Counter
Timers
APB
Serial
Ports
LEDs
RS232
Drivers
Clock
Generator
I/O
Expansion
Points
Voltage
Regulator
AT91EB40 Evaluation Board User Guide
Section 2
Setting Up the AT91EB40
Evaluation Board
2.1
Electrostatic
Warning
The AT91EB40 Evaluation Board is shipped in protective anti-static packaging. The
board must not be subjected to high electrostatic potentials. A grounding strap or similar
protective device should be worn when handling the board. Avoid touching the component pins or any other metallic element.
2.2
Requirements
Requirements in order to set up the AT91EB40 Evaluation Board are:
■ the AT91EB40 Evaluation Board itself
■
2.3
Layout
DC power supply capable of supplying 7.5V to 9V @ 500 mA (not supplied)
Figure 2-1 shows the layout of the AT91EB40 Evaluation Board.
AT91EB40 Evaluation Board User Guide
2-1
Setting Up the AT91EB40 Evaluation Board
Figure 2-1. Layout of the AT91EB40 Evaluation Board
LK2
2.4
Jumper Settings
LK2 is used to select the clock frequency and by default, is set to 32,768 MHz. For more
information about this jumper and the various surface mount links, see Section 5,
“Appendix A – Configuration Links and SRAM Bank 1” on page 5-1.
2.5
Powering Up the
Board
DC power is supplied to the board via the 2.1 mm socket (J4) shown below in Figure 22. The polarity of the power supply is not critical. The minimum voltage required is 7V.
Figure 2-2. 2.1 mm Socket
positive (+)
or
negative (-)
2.1 mm connector
The board has a voltage regulator providing +3.3V. The regulator allows the input voltage to be from 7V to 9V. When you switch the power on, the red LED marked “POWER”
will light up. If it does not, switch off and check the power supply connections.
2-2
AT91EB40 Evaluation Board User Guide
Setting Up the AT91EB40 Evaluation Board
2.6
Measuring
Current
Consumption on
the AT91R40807
2.7
Testing the
Connect the straight cable between Serial A and Serial B. With the FIQ button
depressed, power-up the board, or generate a reset. The three LEDs (green, amber,
AT91EB40
Evaluation Board red) light up. Release the FIQ. The three LEDs go off and then blink once.
The board is designed to generate the whole power supply of the AT91 device, and only
the AT91 device, through the wirelink WL2. This feature enables measurements to be
made of the current consumption of the AT91 device.
Press the TIOB1 button. The red LED lights up. Release the TIOB1. The red LED goes
off. If the board has 512K bytes SRAM, the green LED blinks twice. If the board has
2048K bytes SRAM, the green LED blinks four times.
Press the FIQ button. The amber LED lights up. Release the FIQ. The amber LED goes
off and the green LED blinks four times. If the green LED blinks twice and then the red
LED blinks twice, the straight cable is not connected.
Press the IRQ0 button. The amber and red LEDs light up. Release the IRQ0. The LEDs
go off and the green LED blinks twice.
AT91EB40 Evaluation Board User Guide
2-3
Setting Up the AT91EB40 Evaluation Board
2-4
AT91EB40 Evaluation Board User Guide
Section 3
The On-board Software
3.1
Flash Memory
Organization
The Flash memory is an AT29LV1024 (64K x 16). It is arbitrarily located at the address
0x01000000 by the boot software. It has been split in two different spaces:
■ 0x01000000 up to 0x0100FFFF = boot and Angel software
■
0x01010000 up to 0x0101FFFF = application software
The switch SW1 allows the signal “SW_A16” to be set (see Figure 6-3, “External Bus
Interface”), which drives the bit A15 of the Flash part:
■ “LOWER MEM” uses the bit A16 of the AT91R40807. The entire Flash can be
reached by the AT91R40807, and the boot software at location 0x01000000 is
executed at the reset.
■
“UPPER MEM” uses the VCC. Only the upper 64K can be reached, at the location
defined by the application software executed at the reset.
It is important to note that the mapping defined by the boot software is the following:
■ Flash at address 0x01000000
■
SRAM at address 0x02000000
Nevertheless, when SW1 is set with “UPPER_MEM”, these addresses are under user
application responsibility.
At delivery, the Flash is programmed with the following software:
Boot from 0x01000000 up to 0x01001FFF
■
3.1.1
Flash Write Access
■
Angel from 0x01002000 up to 0x0100FFFF
■
Demo application from 0x01010000 up to 0101FFFF
The upper 64K of the Flash can be overwritten whatever the position of the switch SW1.
This can also be done by using Angel rather than the EmbeddedICE.
The lower 64K are write-protected, whatever the position of the switch SW1. This is to
prevent the boot and Angel software stored in the lower 64K bytes from being erased.
Nevertheless, it is always possible to make this space unprotected by setting a jumper
or a link on the footprint J7.
Note:
If the lower 64K are not protected, the user must be especially careful. Even
though one of the features of the boot is the ability to restore Angel, it cannot be
saved itself. Once it is overwritten, the only way to restore the Flash is to use an
EmbeddedICE.
AT91EB40 Evaluation Board User Guide
3-1
The On-board Software
3.1.2
Boot Software
The boot software is started at the reset if SW1 is switched to “LOWER MEM”.
It first initializes the EBI, then executes the REMAP procedure, and then checks the
state of the buttons:
■ If the button FIQ is pressed, all the LEDs are lit and the Functional Test Software
(FTS) is activated.
3.1.3
Functional Test
Software (FTS)
■
If the button TIOB1 is pressed, the red LED is lit and the SRAM downloader is
activated.
■
If neither TIOB1 nor FIQ are pressed, the amber LED is lit and Angel is activated.
The FTS is a part of the boot software that allows testing of the AT91EB40. It is started
by the boot if the FIQ button is pressed at reset. At start of the FTS, the LEDs 1, 2 and 3
light up. The user must then release the FIQ button. The LEDs switch off and then blink
once.
The FTS then waits for one of the following user actions on the buttons:
If the TIOB1 button is pressed, the memory size is checked and the green LED blinks:
■
- 1 = 256K bytes
- 2 = 512K bytes
- 3 = 1024K bytes
- 4 = 2048K bytes
■
If the FIQ button is pressed, the USART are tested:
- Transfer one character from USART 0 to USART 0 (loopback mode)
- Transfer one character from USART 1 to USART 1 (loopback mode)
- Transfer one character from USART 0 to USART 1 (normal mode)
- Transfer one character from USART 1 to USART 0 (normal mode)
For each case, the green or the red LED blinks once following the positive or negative result of the test. Note that the second and third tests can succeed only if the
straight serial cable (provided) is connected between Serial A and Serial B.
■
If the IRQ0 button is pressed, the buses of the SRAM are tested:
- Address bus
- Data bus
In each case, the green or the red LED blinks once following the positive or negative
result of the test.
3.1.4
SRAM Downloader
The SRAM downloader is a part of the boot software and allows an application in the
SRAM to be loaded at the address 0x02000000 when activated. It is started by the boot
if the button TIOB1 is pressed at reset.
The procedure is as follows:
1. Connect the AT91EB40 to the host PC using either the straight serial cable (provided) on Serial A, or a crossed serial cable (not provided) on Serial B.
2. Set the clock frequency (LK2) to the desired frequency. Note that this directly
determines the baud rate for the download (See Table 3-1).
3. Generate a power-on or a reset with the TIOB1 pressed down. Wait for the red
LED to light up and then release the TIOB1 button.
4. Start the BINCOM utility available in the AT91 library on the host computer:
Select the port and the baud rate for communications, then open the file to download and send it. Wait for the end of the transfer.
5. Press the button IRQ0 to terminate the download. The control is switched to the
address 0x02000000.
3-2
AT91EB40 Evaluation Board User Guide
The On-board Software
Table 3-1 shows the relationship between the clock rate on the board and the serial
baud rate.
Table 3-1. Clock Rate vs. Serial Baud Rate
Frequency
Serial A
Serial B
16 MHz
57600
19200
32 MHz (master)
115200
38400
Note that if the debugger is started through ICE while the SRAM downloader is on, then
both serial channels are enabled.
3.1.5
Angel Monitor
The Angel monitor is located in the Flash from 0x01002000 up to 0x0100FFFF. It is
started by the boot if neither TIOB1 nor FIQ are pressed at reset.
When Angel starts, it recopies itself into the SRAM in order to run faster. The SRAM
used by Angel is from 0x02020000 to 0x02040000, i.e., the highest half of the SRAM.
The Angel on the AT91EB40 can be upgraded regardless of the version programmed
on it.
Note that if the debugger is started through ICE while the Angel monitor is on, the
Advanced Interrupt Controller (AIC) and the USART channel are enabled.
AT91EB40 Evaluation Board User Guide
3-3
The On-board Software
3-4
AT91EB40 Evaluation Board User Guide
Section 4
Circuit Description
4.1
AT91EB40 Top
Level
The top level schematic in Section 6, “Appendix B - Schematics” shows the blocks in
the system (see Figure 6-1). Each block is described in the appropriate section below.
4.2
AT91R40807
Processor
This schematic shows the AT91R40807 (see Figure 6-7). The footprint is for a 100-pin
TQFP package.
Wirelink (WL2) can be removed by the user to allow measurement of the current
demand by the microcontroller.
4.3
I/O Expansion
The I/O expansion connector makes available to the user the general-purpose I/O
(GPIO) lines, VDD and ground. Surface mount links 5, 6, 7, 8 and 9 are used to select
between the I/O lines being used by the evaluation board or by the user via the I/O
expansion connector. The connector is not fitted at the factory; however, the user can fit
any 17 x 2 connector on a 0.1" (2.54 mm) pitch.
4.4
External Bus
Interface
This schematic shows one AT29LV1024-15JC with a 128 KB 16-bit Flash and four
512K x 8 SRAM devices. See Figure 6-3.
Note: The AT91EB40 is fitted with four 128K x 8 SRAM devices.
The schematic also shows the bus expansion connector which, like the I/O expansion
connector, is not fitted at the factory. The user can fit any 32 x 2 connector on a 0.1"
(2.54 mm) pitch to gain access to the data, address, chip select, read/write, oscillator
output and wait state pins. Pin 8 on this connector can be used to apply an external
clock frequency to the board, assuming the clock select jumper is fitted accordingly (see
Section 5). VDD and ground are also available on the connector.
Switch 1 shown on this schematic is used to select either read-only access of all locations in Flash or allow read/write access to the top 64K bytes. This is to prevent the
Angel debug program, which is stored in the lower 64K bytes, from being erased.
4.5
Power, Crystal
Oscillator and
Clock
Distribution
The system clock is derived from a single 32.768 MHz crystal oscillator. This is divided
by a 4-bit binary counter to give alternate clock frequencies of 32.768 MHz divided by 2,
4 or 8. The system clock frequency is selected by fitting a jumper link in one position of
the link field (LK2) and details of this can be found in Section 5. One position in LK2
selects an external oscillator to be applied via the expansion bus interface.
Note that the 4-bit binary counter is not fitted at the factory; this function is optional.
AT91EB40 Evaluation Board User Guide
4-1
Circuit Description
The voltage regulator provides 3.3V to the board and will light the red POWER LED
when operating. Power can be applied via the 2.1 mm connector to the regulator in
either polarity because of the diode rectifying circuit. The regulators can tolerate supply
transients to 30V although they will shut down without damage if they overheat.
4.6
JTAG Interface,
Reset, Interrupts
and LEDs
An ARM ® -standard 20-pin box header (J2) is provided to enable connection of an
EmbeddedICE interface (using an EmbeddedICE to Multi-ICE adapter) or Multi-ICE
interface to the JTAG inputs on the AT91. This allows code to be developed on the
board without the use of system resources such as memory and serial ports.
The IRQ, FIQ and TIOB0 switches are debounced and buffered. A supervisory circuit
has been included in the design to detect and consequently reset the board when the
3.3V supply voltage drops below 3.08V. It also provides a debounced reset signal.
The schematic also shows LEDs 1, 2 and 3, which are for general purpose use and are
connected to timer (or I/O) pins TIOA0/P1, TIOA1/P4 and TIOB0/P2.
4.7
Serial Interface
Two 9-way D-type connectors (J5/6) are provided for serial port connection. Serial portA
(J5) is used primarily for host PC communication and is a DB9 female connector. TXD
and RXD are swapped so that a straight-through cable can be used. CTS and RTS are
connected together, as are DCD, DSR and DTR.
Serial port B (J6) is a DB9 male connector with TXD and RXD obeying the standard
RS-232 pinout. Apart from TXD, RXD and ground, the other pins are not connected.
RS-232 level conversion is provided by a MAX3223 device (U13) and associated bulk
storage capacitors.
4.8
Layout Drawing
The layout diagram schematic shows an approximate floorplan for the board. This has
been designed to give the lowest board area, while still providing access to all test
points, links and switches on the board. See Figure 6-2.
The size is approximately 4.5 inches square with four mounting holes, one at each corner, into which feet are attached. The board has two signal layers and two power
planes.
4-2
AT91EB40 Evaluation Board User Guide
Section 5
Appendix A – Configuration Links
and SRAM Bank 1
5.1
Jumpers (LK2)
The LK2 jumper is used to select the clock frequency. The frequency options are
32,768 MHz, 32.768 MHz divided by 2, 4 or 8, or an external clock applied via the
expansion bus interface.
LK2
1
2
EBI
3
4
MAST
5
6
/2
7
8
/4
9
10
/8
Note that before using this function, the user must fit the 4-bit binary counter used to
divide the 32.768 MHz clock.
5.2
Surface Mount
Links
(LK1, LK3 - 9)
By adding the I/O expansion and the bus expansion connectors, the user can add his
own peripherals to the evaluation board. These peripherals may require more I/O lines
than available while the board is in its default state. Extra I/O lines can be made available by disabling some of the on-board peripherals. This is done using the surface
mount links detailed below. If these links need to be changed, a fine-tipped soldering
iron is required. All links are 0R 0805 resistors unless stated otherwise.
LK1 should be left unaltered unless a memory upgrade is required. If this is the case,
see the paragraph “Increasing Memory Size” on page 5-2.
LK1
Function
A-C
A18 is used as the chip select for SRAM Bank 1. Should be in this position
for 128K x 8 SRAMs
B-C
A20 is used as the chip select for SRAM Bank 1. Should be in this position
for 512K x 8 SRAMs
LK3
Function
A-C
Alternate boot mode NOT selected
B-C
Alternate boot mode selected
Note:
Use a 10K resistor.
AT91EB40 Evaluation Board User Guide
5-1
Appendix A – Configuration Links and SRAM Bank 1
LK4
Function
A-C
RXD lines are set tri-state on the RS-232 transceiver so that the receiver
signals to AT91 can be used for external I/O via the I/O connector.
B-C
Receive pins on AT91 used by on-board serial ports
Note:
5.3
Increasing
Memory Size
Use a 10K resistor.
LK5
Function
A-C
TXD0 connects to I/O connector
B-C
TXD0 connects to RS-232 Transceiver
LK6
Function
A-C
AT91 IRQ0 pin connects to I/O connector
B-C
AT91 IRQ0 input is from IRQ switch
LK7
Function
A-C
AT91 FIQ pin connects to I/O connector
B-C
AT91 FIQ input is from FIQ switch
LK8
Function
A-C
TXD1 connects to I/O connector
B-C
TXD1 connects to RS-232 Transceiver
LK9
Function
A-C
TIOB1 connects to I/O connector
B-C
AT91 TIOB1 input is from TIOB1 switch
The AT91EB40 is supplied with four 128K x 8 byte SRAM memories. If, however, the
user needs more than 512K bytes of memory, the devices can be replaced with four
512K x 8 3.3V 15/20 ns SRAMs giving, in total, 2048K bytes. If this is done, LK1 must be
moved to position B-C.
The user must either have 128K x 8 SRAMs or 512K x 8 SRAMs fitted in Bank 0 and, if
desired, Bank 1. The two SRAM sizes cannot be mixed.
5-2
AT91EB40 Evaluation Board User Guide
Section 6
Appendix B - Schematics
6.1
Schematics
The following schematics are appended:
• Figure 6-1. AT91EB40 Evaluation Board
• Figure 6-2. PCB Layout
• Figure 6-3. External Bus Interface
• Figure 6-4. JTAG Interface, Reset, Interrupts and LEDs
• Figure 6-5. I/O Expansion
• Figure 6-6. Power, Crystal Oscillator and Clock Distribution
• Figure 6-7. AT91R40807 in TQFP Package
• Figure 6-8. Serial Interface
The pin connectors are indicated on the schematics:
■ J1 = EBI Expansion – External Bus Interface (Figure 6-3)
■
J2 = JTAG Interface – JTAG Interface, Reset, Interrupts and LEDs (Figure 6-4)
■
J3 = I/O Expansion – I/O Expansion (Figure 6-5)
■
J5 = Serial A – Serial Interface (Figure 6-8)
■
J6 = Serial B – Serial Interface (Figure 6-8)
AT91EB40 Evaluation Board User Guide
6-1
6-2
D
C
B
A
1
1
TCK
TDI
TDO
TMS
TIOA0
TIOA1
TIOB0
TIOB1_ONB
P12/FIQ
IRQ[2 ..0]
P12/FIQ_ONB
IRQ0_ONB
TIOA[2..0]
TIOB[2..0]
TCLK[2..0]
TIOB1_ONB
JTAG
TCK
TDI
TDO
TMS
2
NRST
TIOA0
P12/FIQ_ONB
TIOA1
IRQ0_ONB
TIOB0
TIOB1_ONB
JTAG, RESET, INTERRUPTS & LEDs
IOEXP
P23
P[19..16]
P24/BMS
NWDOVF
TXD[1..0]
RXD[1..0]
SCK[1..0]
TXD_ONB[1..0]
P12/FIQ
IRQ[2..0]
P12/FIQ_ONB
IRQ0_ONB
TIOA[2..0]
TIOB[2..0]
TCLK[2..0]
TIOB1_ONB
I/O EXPANSION
2
NRST
P12/FIQ_ONB
IRQ0_ONB
P23
P[19..16]
P24/BMS
NWDOVF
TXD[1..0]
RXD[1..0]
SCK[1..0]
TXD_ONB[1..0]
3
3
TCK
TDI
TDO
TMS
TIOA[2..0]
TIOB[2..0]
TCLK[2..0]
P12/FIQ
IRQ[2 ..0]
AT91CLK
P25/MCKO
D[15..0]
A[23..0]
4
AT91PROC
TCK
TDI
TDO
TMS
TIOA[2..0]
TIOB[2..0]
TCLK[2..0]
P12/FIQ
IRQ[2..0]
AT91CLK
P25/MCKO
D[15..0]
A[23..0]
AT91M40400
4
P23
P[19..16]
P24/BMS
TXD[1..0]
RXD[1..0]
SCK[1..0]
NWDOVF
NRST
NCS[3..0]
NWR1/NUB
NRD/NOE
NWR0/NWR
NWAIT
5
P23
P[19..16]
P24/BMS
TXD[1..0]
RXD[1..0]
SCK[1..0]
NWDOVF
NRST
NCS[3..0]
NWR1/NUB
NRD/NOE
NWR0/NWR
NWAIT
5
DRAWING.SCH
BOARD OUTLINE
6
6
RS232
TXD_ONB[1..0]
Thursday, August 20, 1998
7
Document Number
ARM EOI-0042 (AT91EB0X.SCH)
Date:
AT91M40400 Evaluation Board
RXD[1..0]
NRST
Size
B
Title
90 Fulbourn Road
Cherry Hinton
Cambridge
CB1 4JN
AT91CLK
EBI_MCKI
P25/MCKO
SERIAL INTERFACE
EBI
NCS[3..0]
NWR1/NUB
NRD/NOE
NWR0/NWR
NWAIT
D[15..0]
A[23..0]
EBI
OSCPOWER
EBI_MCKI
OSCILLATOR & POWER
(c) ARM LTD.
TXD_ONB[1..0]
NCS[3..0]
NWR1/NUB
NRD/NOE
NWR0/NWR
NWAIT
D[15..0]
A[23..0]
EBI_MCLK
7
Sheet
1
8
of
RXD[1..0]
NRST
EBI_MCLK
P25/MCKO
AT91CLK
8
8
Rev
B
D
C
B
A
Appendix B - Schematics
Figure 6-1. AT91EB40 Evaluation Board
AT91EB40 Evaluation Board User Guide
D
C
1
2
112mm
LT1086
POWER
RESET
SWITCH
RESET
EBI
J1
MAX6315
74LV14D
OSC.
R21 - 26
3
U1
SRAM
LK3
LED
J2
U2
LK1
2x32 header
U6
74LVC139D
R4
JTAG
JTAG INTERFACE
(20 WAY BOX HEADER)
U4
U5
TIOB1
SWITCH
LK2
4
LED3
LED2
LED1
AT91M40X0X
LOWER
MEM
FIQ
SWITCH
SW1
UPPER
MEM
IRQ0
SWITCH
2x1 PIN HEADER
FLASH
5
J7
DB9 PLUG
SERIAL B
6
GROUND PLANE &
VDD PLANE
74LVC00 MAX3223
LK5 - 9
LK4
6
STARPOINT
0.1" PITCH
J3
SERIAL A
DB9 SOCKET
2x17 header
124.3mm
5
LEAVE SPACE AROUND 2x32 HEADER TO FIT A DIN41612 SKT (ROWS A,B)
CONNECTOR IN ITS PLACE IF NECESSARY
2x5 header
74LV161
EBI
MAST
SRAM
J4
/8
2.1mm
POWER
SOCKET
/2
/4
POWER
SRAM
TIOB1
SPDT
B
LAYOUT SUGGESTION
LEDs
I/O EXP.
4
J6
HOLE HAS
CONTACT
WITH
CHASSIS
PLANE
J5
CHASSIS PLANE
3
FIQ
2
IRQ0
AT91EB40 Evaluation Board User Guide
SRAM
A
1
7
4mm MOUNTING
HOLES
Document Number
ARM EOI-0042 (DRAWING.SCH)
Thursday, Augu st 20, 1998
Date:
PCB layout
Size
A2
Title
90 Fulbourn Road
Cherry Hinton
Cambridge
CB1 4JN
(c) ARM Ltd.
GROUND SIGNAL FROM DB9 PLUG WILL
BE PLACED OVER CHASSIS PLANE AND
WILL CONNECT TO GROUND NEAR
STARPOINT
WRITING IN THIS FONT SHOULD BE PRINTED
ONTO PCB
7
8
Sheet
8
2
of
8
Rev
B
D
C
B
A
Appendix B - Schematics
Figure 6-2. PCB Layout
6-3
D
C
B
NRST
EBI_MCKI
NWAIT
P25/MCKO
NRD/NOE
NWR1/NUB
NWR0/NWR
NCS[3..0]
D[15..0]
A[23..0]
1
3
5
7
9
11
13
15
17
19
21
23
25
27
29
31
33
35
37
39
41
43
45
47
49
51
53
55
57
59
61
63
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
42
44
46
48
50
52
54
56
58
60
62
64
GND
NWR1/NUB
NWAIT
EBI_MCKI
NCS1
NCS3
NRST
A1
A3
A5
A7
GND
A9
A11
A13
A15
VDD
A17
A19
A21
A23
GND
D1
D3
D5
D7
VDD
D9
D11
D13
D15
GND
1
Connector not fitted on AT91EB01.
AT91EB02 has a straight pin header
connector fitted
CON64AB
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
J1
Bus Expansion Connector
Print on PCB EBI
GND
NWR0/NWR
NRD/NOE
P25/MCKO
NCS0
NCS2
VDD
A0
A2
A4
A6
GND
A8
A10
A12
A14
VDD
A16
A18
A20
A22
GND
D0
D2
D4
D6
VDD
D8
D10
D12
D14
GND
2
VDD
If an external interrupt source is attached to the
Bus Expansion Connector it must be open-drain
or open-collector.
NRST
EBI_MCKI
NWAIT
P25/MCKO
NRD/NOE
NWR1/NUB
NWR0/NWR
NCS[3..0]
D[15..0]
A[23..0]
R1
10K
VDD
VDD
VDD
A
C4
100n
C2
100n
GND
VDD
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
A17
A0
A1
A2
A3
CS
I/O0
I/O1
VDD
GND
1/O2
1/O3
WE
A4
A5
A6
A7
A18
NC
A16
A15
A14
A13
OE
1/O7
1/O6
GND
VDD
I/O5
I/O4
A12
A11
A10
A09
A08
NC
C6
100n
R4
0R
512Kx8 SRAM
A17
A0
A1
A2
A3
CS
I/O0
I/O1
VDD
GND
1/O2
1/O3
WE
A4
A5
A6
A7
A18
3
1
2
3
4
5
6
7
8
9
10
D2
11
D3
12
NWR0/NWR 13
A5
14
A6
15
A7
16
A8
17
A19
18
A18
A1
A2
A3
A4
CS_BANK1
D0
D1
D13
D12
A13
A12
A11
A10
A9
A17
A16
A15
A14
NRD/NOE
D15
D14
CS_BANK1
1
2
3
A18
A18/A20
A20
4
16
15
14
13
12
11
10
9
Test Point
TP3
74LVC139D
VDD
E
2E
1A0
1A1 2A0
1Y0 2A1
1Y1 2Y0
1Y2 2Y1
1Y3 2Y2
GND 2Y3
Print on PCB the position
of 0R resistor i.e. A-C and B-C
SMLINK
A
C
B
LK1
Test Point
TP1
1
2
3
4
5
6
7
8
U6
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
5
5
Do Not Fit
VDD
36
35
34
33
32
31
30
29
28
27
26
25
24
23
22
21
20
19
36
35
34
33
32
31
30
29
28
27
26
25
24
23
22
21
20
19
U14
VDD
VDD
C3
100n
FLASH_WE
TP17
Test Point
6
D7
D6
D5
D4
D12
D11
D10
D9
D8
NWR0/NWR
Test Point
C55
100n
74LVC00
14
13
12
11
10
9
8
C5
100n
1A VDD
1B
4B
1Y
4A
2A
4Y
2B
3B
2Y
3A
GND 3Y
VDD
1
2
3
4
5
6
7
6
TP16
D13
D12
A13
A12
A11
A10
A9
A17
A16
A15
A14
NRD/NOE
D15
D14
D5
D4
A13
A12
A11
A10
A9
A17
A16
A15
A14
NRD/NOE
D7
D6
A16
CON2AP
J7
R2
10K
NC
A16
A15
A14
A13
OE
1/O7
1/O6
GND
VDD
I/O5
I/O4
A12
A11
A10
A09
A08
NC
512Kx8 SRAM
A17
A0
A1
A2
A3
CS
I/O0
I/O1
VDD
GND
1/O2
1/O3
WE
A4
A5
A6
A7
A18
U5
512Kx8 SRAM
NC
A16
A15
A14
A13
OE
1/O7
1/O6
GND
VDD
I/O5
I/O4
A12
A11
A10
A09
A08
NC
Bank 1
SRAM
A17
A0
A1
A2
A3
CS
I/O0
I/O1
VDD
GND
1/O2
1/O3
WE
A4
A5
A6
A7
A18
U2
VDD
GND
GND
Fit only if bank 1
is populated
D10
D11
NWR1/NUB
A5
A6
A7
A8
A19
A18
A1
A2
A3
A4
CS_BANK1
D8
D9
When fitting 128Kx8 SRAM parts align
pin 1 of the SRAM to where pin 2 would
be if a 512K part were fitted.
D5
D4
A13
A12
A11
A10
A9
A17
A16
A15
A14
NRD/NOE
D7
D6
NCS1
GND
A18/A20
CS_BANK0
Test Point
TP2
36
35
34
33
32
31
30
29
28
27
26
25
24
23
22
21
20
19
36
35
34
33
32
31
30
29
28
27
26
25
24
23
22
21
20
19
0R resistor factory fitted in position
A-C for AT91EB01 board.
For AT91EB02 0R resistor factory
fitted in position B-C
VDD
NC
A16
A15
A14
A13
OE
1/O7
1/O6
GND
VDD
I/O5
I/O4
A12
A11
A10
A09
A08
NC
512Kx8 SRAM
U4
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
Fit only if Bank 1
is not populated
D10
D11
NWR1/NUB
A5
A6
A7
A8
A19
A18
A1
A2
A3
A4
CS_BANK0
D8
D9
D2
D3
NWR0/NWR
A5
A6
A7
A8
A19
A18
A1
A2
A3
A4
CS_BANK0
D0
D1
Bank 0
SRAM
U1
1
TP
1
TP
2
+ +
1
4
1
TP
R3
10K
I/O12
I/O11
I/O10
I/O9
I/O8
GND
NC
I/O7
I/O6
I/O5
1/O4
SW1
2
SW_A16
39
38
37
36
35
34
33
32
31
30
29
8
VDD
A9
A8
A7
A6
Document Number
ARM EOI-0042 (EBI.SCH)
Thursday, August 20, 1998
Date:
Sheet
3
8
of
8
A14
A13
A12
A11
A10
C1
100n
Leave space on PCB to print
Lower mem and Upper mem which
will be indicated by the position of the
switch.
1
3
External Bus Interface
7
U3
A13
A12
A11
A10
A9
AT29LV1024-15JC
GND
NC
A8
A7
A6
A5
Size
B
Title
90 Fulbourn Road
Cherry Hinton
Cambridge
CB1 4JN
(c) ARM Ltd.
16-BIT wide Flash
Test Point
TP19
TP18
Test Point
A16
VDD
7
8
9
10
11
12
13
14
15
16
17
7
FLASH_WE
3
1
TP
D13
D14
D15
NCS0
D3
D2
D1
D0
NRD/NOE
2
TP
1
1
TP
1
TP
SW_A16
A15
6
5
4
3
2
1
44
43
42
41
40
I/O13
I/O14
I/015
CE
NC
NC
VDD
WE
NC
A15
A14
1/O3
1/O2
1/O1
1/O0
OE
DC
A0
A1
A2
A3
A4
18
19
20
21
22
23
24
25
26
27
28
6-4
A1
A2
A3
A4
A5
1
Rev
B
D
C
B
A
Appendix B - Schematics
Figure 6-3. External Bus Interface
AT91EB40 Evaluation Board User Guide
AT91EB40 Evaluation Board User Guide
D
C
B
A
VDD
GND
VDD
1
FIQ
Interrupt
Button
SW3
SWITCH HORIZ
System Reset
SW2
SWITCH HORIZ
VDD
R12
10K
+
R5
10K
MR
VDD
GND RESET
U8
VDD
4
2
9
2
8
74LV14D
U7D
R6
10K
NRST
R7
10K
3
3
User
Defined
Button
SW4
SWITCH HORIZ
P12/FIQ_ONB
MAX6315US31D3-T
3
1
C25
470n
TANT
Reset Threshold = 3.08V
Reset held low for 140ms min.
TDO
TDI
TMS
TCK
2
R8
10K
VDD
NRST
R13
10K
C16
10pF
C7
10pF
C10
10nF
1
3
5
7
9
11
13
15
17
19
+
+
+
+
+
+
+
+
+
+
J2
+
+
+
+
+
+
+
+
+
+
C18
22pF
+
C26
470n
TANT
11
20 way box
header
10
4
74LV14D
U7E
C11
10nF
5
IRQ
Interrupt
Button
5
SW5
SWITCH HORIZ
TIOB1_ONB
C20
10nF
C12
10nF
C21
10nF
C13
10nF
C22
10nF
C14
10nF
VDD
TIOB0
TIOA1
TIOA0
R14
10K
+
C23
10nF
C15
10nF
C27
470n
TANT
13
TIOB0
TIOA1
TIOA0
Place capacitors as close as possible
to the connector.
C19
10nF
2 VDD
GND
4
GND
6
GND
8
GND
10
GND
12
GND
14
GND
16
GND
18
20 GND
JTAG Interface
Print on PCB
CON20AP
JTAG
TDO
NRST
TDI
TMS
TCK
VDD
C9
10pF
Print on PCB the function of each push
button i.e. FIQ, TIOB1, IRQ0, RESET
C17
10pF
C8
10pF
4
To reset the TAP controller hold TMS high for
5 TCK cycles.
12
6
74LV14D
U7F
6
10K
10K
10K
5
3
1
4
6
74LV14D
U7C
74LV14D
U7B
C24
100n
470R
R11
470R
R10
470R
R9
5
3
1
VDD
Document Number
ARM EOI-0042 (JTAG.SCH)
Thursday, August 20, 1998
Date:
Sheet
4
8
of
8
Rev
B
GREEN
6
LED3
TRI-LED
D1C
VDD
AMBER
4
LED2
TRI-LED
D1B
VDD
RED
2
LED1
TRI-LED
D1A
Print on PCB the name of each LED
i.e. LED1, LED2, LED3
Size
B
7
8
AT91EB01 will have individual
LEDs for D1A, D1B and D1C.
AT91EB02 has the LEDs in a
single package hence the
reference names.
JTAG interface, Reset, Interrupts & LEDs
90 Fulbourn Road
Cherry Hinton
Cambridge
CB1 4JN
Title
2
74LV14D
U7A
Factory fitted
WIRE LINK
WL1
Decoupling capacitor for
74LV14
(c) ARM Ltd.
VDD
R26
R25 0R
R24
R23 0R
R22
7
The chassis plane will be joined to
the signal ground plane at one point
only. See Drawing.sch for suggested
position of the wire link.
R21 0R
IRQ0_ONB
TIOB0
TIOA1
TIOA0
IRQ_ONB0
1
D
C
B
A
Appendix B - Schematics
Figure 6-4. JTAG Interface, Reset, Interrupts and LEDs
6-5
D
C
B
1
P24/BMS
P23
P[19..16]
TIOB1_ONB
P12/FIQ_ONB
IRQ0_ONB
TXD_ONB[1..0]
NWDOVF
P12/FIQ
IRQ[2..0]
TCLK[2..0]
TIOB[2..0]
TIOA[2..0]
SCK[1..0]
RXD[1..0]
TXD[1..0]
P24/BMS
P23
P[19..16]
2
TIOB1_ONB
P12/FIQ_ONB
TXD_ONB[1..0]
NWDOVF
P12/FIQ
IRQ[2..0]
TCLK[2..0]
TIOB[2..0]
TIOA[2..0]
SCK[1..0]
RXD[1..0]
TXD[1..0]
3
VDD
TXD_ONB1
TXD1
TXD1_EXP
Test Point
TP7
TXD_ONB0
TXD0
TXD0_EXP
3
2
1
SMLINK
B
C
A
LK8
SMLINK
B
C
A
3
2
1
LK6
SMLINK
B
C
A
Print on PCB the position
of 0R resistor i.e. A-C and B-C
5
0R Resistor factory fitted in position B-C
for all of these surface mount links
IRQ0_ONB
IRQ0
IRQ0_EXP
TIOB1_ONB
TIOB1
TIOB1_EXP
Test Point
3
2
1
3
2
1
6
SMLINK
B
C
A
LK9
SMLINK
B
C
A
LK7
Print on PCB I/O EXP.
P12/FIQ_ONB
P12/FIQ
P12/FIQ_EXP
TP8
6
Connector not fitted on AT91EB01.
AT91EB02 has a straight pin header
connector fitted
Test Point
4
VDD
2
4 TXD1_EXP
RXD1
6
SCK1
8
10 TIOB0
12TIOB1_EXP
14 TIOB2
16 GND
VDD
18
20IRQ0_EXP
22 IRQ1
IRQ2
24
26P12/FIQ_EXP
P17
28
P19
30
32 NWDOVF
GND
34
CON34AP
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
TP6
LK5
J3
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
Test Point
VDD
1
TXD0_EXP 3
RXD0
5
SCK0
7
TIOA0
9
TIOA1
11
TIOA2
13
GND 15
VDD
17
TCLK0 19
TCLK1 21
TCLK2 23
P16
25
P18
27
P23
29
P24/BMS 31
GND 33
I/O Expansion
5
TP5
3
2
1
4
Test Point
GND
TP4
VDD
A
3
TP
1
2
TP
1
TP
1
TP
1
TP
6-6
1
1
(c) ARM Ltd.
Tuesday, July 14, 1998
7
Document Number
ARM EOI-0042 (IOEXP.SCH)
Date:
I/O EXPANSION
Size
B
Title
90 Fulbourn Road
Cherry Hinton
Cambridge
CB1 4JN
7
Sheet
5
8
8
of
8
Rev
B
D
C
B
A
Appendix B - Schematics
Figure 6-5. I/O Expansion
AT91EB40 Evaluation Board User Guide
D
C
B
A
1
2
3
3
1
C31
22nF(T)
1
Test Point
TP
2
2
1
Test Point
TP14
TP 1
U11
2
GND
VDD
VDD
4
3
VDD
C33
100n
GXO-U108
32.768MHz
3V3
EN
GND
VDD
OUT
Place as near as
possible to AT91
R19
10K
C32
100n
1
2
VDD
Note : Power supply is input
protected to 30V however
regulator will trip out
Place capacitors as close as possible
if it gets to hot.
to the connector.
Voltage input range :
7.5 to 9V, 0.5A
2.1mm Power Socket
J4
1
3
TP9
2
1
1
ES1B
D4
ES1B
D2
GND
VDD
VDD
1
2
3
4
5
6
7
8
3
Binary 4-bit
counter
74LV161
1
Test Point
TP10
+
C29
10uF(35V)
16
15
14
13
12
11
10
9
VDD
VDD
3
2
1
1
R16
220R
1206
R17
360R
1206
Ra
Rb
+
+
+
+
+
2
4
6
8
10
4
GND4
TESTPIN
GND3
TESTPIN
GND2
TESTPIN
5
6
C30
10u
33R
R18
AT91CLK
Place as near as
possible to
AT91
+
VDD
6
TP13
Test Point
System Power Supply - VDD (3V3)
Print on PCB where to position jumper
for the various clock
frequencies i.e.MAST, /8, /4, /2, EBI
Insert jumper in
one position only
CON10AP
+
+
+
+
+
Distibute test pins
over board
1
3
5
7
9
possible to AT91
Link field allows selection of
on board clock or divide by
2, 4 and 8, or external
clock source connected
via EBI
Place as near as
LK2
5
Voltage Regulator Output
Vout = 1.25(1 + (Rb/Ra))
TP11
Test Point
TP
LT1086CM
IN
OUT
ADJ
U9
VIN
GND1
TESTPIN
Place as near as
possible to
AT91
/2
/4
/8
Make as short
as possible
EBI_MCKI
Note : Ground will be approx. 0.7V
higher than the power supply ground
ES1B
D5
ES1B
D3
MR VDD
CLK TC
D0
Q0
D1
Q1
D2
Q2
D3
Q3
CEP CET
GND PE
U10
EBI_MCKI
Test Point
TP12
2
22nF(T)
1
TP
1
2
2
C28
1
1
4
1
3
1
AT91CLK
VDD
2
POWER
LED
7
Tuesday, July 14, 1998
7
Document Number
ARM EOI-0042 (OSCPOWER.SCH)
Date:
Sheet
Power, Crystal oscillator and clock distribution
Size
B
Title
90 Fulbourn Road
Cherry Hinton
Cambridge
CB1 4JN
VDD
Print on PCB Power
D6
LED-RED
R15
470R
(c) ARM LTD.
1
TP
1
TP
1
AT91EB40 Evaluation Board User Guide
VDD
2
GND
1
6
8
8
of
8
Rev
B
D
C
B
A
Appendix B - Schematics
Figure 6-6. Power, Crystal Oscillator and Clock Distribution
6-7
D
C
B
A
C35
100n
1
1
2
3
VDD_PROC
C37
100n
2
4K7 resistor factory fitted
in position C-B. This selects
alternate boot mode which
makes the AT91 boot from
external 16-bit wide Flash.
P24/BMS
VDD
P24/BMS
NWAIT
NWR0/NWR
NRD/NOE
P23
NWDOVF
NWR1/NUB
P[19..16]
NCS[3..0]
C36
100n
SMLINK(4K7)
A
C
B
LK3
Print on PCB the position
of 4K7 resistor i.e. A-C and B-C
P24/BMS
NWAIT
NWR0/NWR
NRD/NOE
P23
NWDOVF
NWR1/NUB
P[19..16]
NCS[3..0]
C34
100n
Place one of these capacitors on each
side of the AT91.
A[23..0]
+
3
C38
10u
A21
A22
A23
A15
A16
A17
A18
A19
A20
A8
A9
A10
A11
A12
A13
A14
A1
A2
A3
A4
A5
A6
A7
A0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
VDD_PROC
Factory fitted
WIRE LINK
WL2
NCS3
NCS2
NCS1
NCS0
NWAIT
A0/NLB
GND
A1
A2
A3
A4
A5
A6
A7
VDD_PROC
A8
A9
A10
A11
A12
A13
A14
GND
GND
A15
A16
A17
A18
A19
P28/A20/CS7
D[15..0]
NWR0/NWR
NRD/NOE
TCK
TDO
TDI
TMS
4
D0
D1
D2
D3
D4
VDD
4
5
NWDOVF
NRST
3
P25/MCKO
P24/BMS
P23
AT91CLK
D5
D6
D7
D8
D9
D10
D11
2
A[23..0]
NWR1/NUB
RXD1
100
99
98
97
96
95
94
93
92
91
90
89
88
87
86
85
84
83
82
81
80
79
78
77
76
P21/TXD1/NTR1
P20/SCK1
P19
P18
P17
P16
P15/RXD0
P14/TXD0
P13/SCK0
P12/FIQ
GND
P11/IRQ2
P10/IRQ1
VDD_PROC
VDD_PROC
P9/IRQ0
P8/TIOB2
P7/TIOA2
P6/TCLK2
P5/TIOB1
P4/TIOA1
P3/TCLK1
GND
GND
P2/TIOB0
P27/NCS3
P26/NCS2
NCS1
NCS0
NWAIT
VDD_PROC
VDD_PROC
NWR0/NWR
NRD/NOE
TCK
TDO
TDI
TMS
GND
GND
P25/MCKO
P24/BMS
P23
MCKI
VDD_PROC
WDOVF
NRST
GND
NWR1/NUB
P22/RXD1
P29/A21/CS6
VDD_PROC
VDD_PROC
P30/A22/CS5
P31/A23/CS4
D0
D1
D2
D3
D4
GND
D5
D6
D7
D8
D9
D10
D11
VDD_PROC
D12
D13
D14
D15
P0/TCLK0
P1/TIOA0
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
6-8
5
D12
D13
D14
D15
TCLK0
TIOA0
1
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
6
TIOB0
IRQ0
TIOB2
TIOA2
TCLK2
TIOB1
TIOA1
TCLK1
IRQ2
IRQ1
TXD1
SCK1
P19
P18
P17
P16
RXD0
TXD0
SCK0
P12/FIQ
AT91M40400 VDD
U12
6
R20
10K
RXD[1..0]
TXD[1..0]
SCK[1..0]
TIOB[2..0]
TIOA[2..0]
TCLK[2..0]
Thursday, August 20, 1998
Date:
7
Document Number
ARM EOI-0042 (AT91PROC.SCH)
AT91M40400 in TQFP package
Size
B
Title
Sheet
RXD[1..0]
TXD[1..0]
SCK[1..0]
TIOB[2..0]
TIOA[2..0]
TCLK[2..0]
Timer & UART - Can be I/O as well
90 Fulbourn Road
Cherry Hinton
Cambridge
CB1 4JN
(c) ARM Ltd.
IRQ[2..0]
P12/FIQ
NRST
P25/MCKO
AT91CLK
TMS
TDI
TDO
TCK
8
7
8
of
Note : Interrupt lines can be used as I/O
IRQ[2..0]
P12/FIQ
NRST
P25/MCKO
AT91CLK
Clock, Reset & Interupts
TMS
TDI
TDO
TCK
JTAG signals
7
8
Rev
B
D
C
B
A
Appendix B - Schematics
Figure 6-7. AT91R40807 in TQFP Package
AT91EB40 Evaluation Board User Guide
D
C
B
A
1
RXD[1..0]
TXD_ONB[1..0]
RXD[1..0]
TXD_ONB[1..0]
Serial I/O from
AT91
2
Print on PCB the position
of 10K resistor i.e. A-C and B-C
A
C
B
LK4
1
2
3
3
VDD
SMLINK(10K)
10K Resistor factory fitted
in position C-B.
GND
VDD
Test Point
TP15
TP
+
1
2
3
4
5
6
7
8
9
10
C1AN
C47
0.1u
TANT
C1AP
C1AP
VAP
C1AN
C2AP
C2AN
VAN
TXD_SB
RXD_SB
RXD1
1
3
+
4
VDD
4
C2AN
C48
0.1u
TANT
C2AP
+
MAX3223CAP
20
19
18
17
16
15
14
13
12
11
GND
C49
0.1u
TANT
VAP
FRCOFF
EN
VCC
C1+
GND
V+
T1OUT
C1R1IN
C2+
R1OUT
C2FRCON
VT1IN
T2OUT
T2IN
R2IN
R2OUT
INV
U13
VDD
2
GND
AT91EB40 Evaluation Board User Guide
+
GND
C50
0.1u
TANT
VAN
VDD
VDD
GND
TXD_SA
RXD_SA
RXD0
VDD
TXD_ONB0
TXD_ONB1
+
1
5
0.1u
TANT
C51
5
6
C43
22pF
C39
22pF
1
6
2
7
3
8
4
9
5
C53
22pF
Print on PCB Serial A
Tuesday, July 14, 1998
7
Document Number
ARM EOI-0042 (RS232.SCH)
Date:
Serial Interface
Size
B
Title
90 FULBOURN ROAD
CHERRY HINTON
CAMBRIDGE
CB1 4JN
(c) ARM LTD.
Sheet
8
8
of
8
Rev
B
The Shell of both D type connectors
should be connected to the chassis plane
Print on PCB Serial B
DB9 PLUG
J6
8
Serial Port A is used for connection
to the host PC using a standard, straight
through cable - 9 way D type plug to 9
way D type socket.
DB9 SOCKET
J5
7
Place capacitors as close as possible
to the connector.
C46
22pF
1
6
2
7
3
8
4
9
5
DCD
DSR
TXD_SA
RTS
RXD_SA
CTS
DTR
C45
10nF
C42
22pF
C41
22pF
GND
C54
10nF
GND
TXD_SB
RXD_SB
C52
22pF
C44
22pF
C40
22pF
Place capacitors as close as possible
to the connector.
6
D
C
B
A
Appendix B - Schematics
Figure 6-8. Serial Interface
6-9
Appendix B - Schematics
6-10
AT91EB40 Evaluation Board User Guide
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