DC Injection Elimination using Model Capacitor and Modified

DC Injection Elimination using Model Capacitor and Modified Resonant
Controller in Unipolar Switched H-Bridge Transformerless PV Inverters
Anjali Varghese C a , T.Alwarsamy b *
Research Scholar , EEE Department, Anna University , Chennai, Tamil Nadu , India,
Liaison Officer, Directorate of Technical Education, Chennai-600025,India
The necessity of efficient topologies for photovoltaic (PV) inverters is a concern presently. With the advent of transformerless inverters,
the size, volume and cost of PV inverters can be decreased. Efficiency can be increased nearly by 2% by avoiding the galvanic connection.
With no galvanic isolation comes the problem of DC injection which pauses serious problems like core saturation of distribution
transformers and cable corrosion and has to be limited as per IEEE standards. A series capacitor in the output of the inverter can limit DC.
This paper presents a modified Proportional + Resonant (P+R) controller which has better stability and sensitivity than previous systems.
The controller is used in conjunction with model capacitor in the output of the inverter avoiding real capacitor overcoming drawbacks of
voltage drops and reverse polarity effects. Moreover the proposed control strategy is applied in a unipolar switched H Bridge inverter. A
comparison of the DC injection with and without the controller is presented for unipolar pulse width modulated (PWM) inverters.
Keywords: Proportional + Resonant controller, Unipolar Pulse Width Modulation (PWM),DC injection, Common Mode Voltage, Differential Mode
Voltage, Parasitic Capacitance, Total Harmonic Distortion (THD)
However the galvanic connection between the PV
system and the utility causes certain issues like DC
injection from PV system to the utility. This DC injection,
according to Berba et al, can be classified as common mode
and differential mode DC current injection [1]-[7].
Common mode DC injection is established due to the
parasitic capacitance that is formed between the PV array
and ground. This in turn produces ground leakage current
between inverter output and DC stage. A finite DC
component is thereby injected to the inverter output
through this connection. Ground leakage current can be
prevented by maintaining the common mode voltage
constant. This can also be prevented by using various
topologies and pulse width modulation (PWM) techniques.
Differential mode DC injection is produced due to the
asymmetrical operation of inverter switches and also due to
offset errors produced by sensors and transducers. Also a
differential mode voltage component is generated within
common mode component which is discussed in section II
and is avoided using equal value filter inductors. DC
Since the commercially available solar cells have
efficiency between 16-20%, the power electronic interface
that connects it to the utility should be extremely efficient
and dependable.
IEEE has limited DC injection to 0.5% of rated output
current for single unit of PV inverter system. Due to the
proliferation of distributed generation, the DC components
may add up and these regulations do not mention the
cumulative effect of different converters connected to grid.
Based on galvanic isolation, photovoltaic (PV) inverters
can be classified as inverters with line frequency
transformers and high frequency transformers. Line
frequency transformers make the whole system bulky and
less efficient. High frequency transformers have more than
one power stages and increase the system complexity. Need
for a transformerless inverter is imminent in this regard. A
transformerless inverter reduces the cost, size, weight and
volume and increases the efficiency of the whole system.
* Corresponding author. E-mail: [email protected]
capacitance is absent the topology as well as modulation
strategies can be effectively modified to eliminate DC
The common mode voltage existing between R and Y
terminals of the line is obtained as in [9] where VCM_RY
and VDM_RY are the common mode and differential mode
voltage between lines R and Y respectively. VRN and VYN
are the output voltages of the inverter with respect to the
negative terminal N of the DC bus reference. VCM_RY and
VDM_RY are defined as
injection can be eliminated by using series capacitors, DC
link sensors and particular topologies using DC decoupling
during freewheeling modes in inverter operation.
The series capacitance is modelled along with the P+R
controller thereby avoiding use of expensive AC capacitors
and additional circuitry for reverse polarity effects. Ideal
P+R controller used in earlier system produces undamped
output and gives saturation problems of the inverter [8],
This paper proposes a non- ideal P+R controller to be
used in conjunction with model capacitor to achieve better
stability and sensitivity and avoid saturation problems. Also
equal value filter inductors are used in the inverter output to
limit the differential mode component inherent in the
common mode model.
= V RN − VYN
VCM _ RY =
Fig. 2. Common mode voltage model
With reference to fig. 1 and also under the influence of
parasitic capacitance, a model of common mode voltage is
shown in fig. 3.
Fig. 1. Main circuit diagram
The organisation of the paper is as follows: Section II
contains modelling of common mode voltage and analysis
of unipolar PWM techniques. Section III gives the detailed
derivation of the controller employed to eliminate
differential mode DC injection. Section IV gives the
experimental analysis and Section V summarizes the
conclusion obtained from the experiments.
Common mode voltage model and unipolar PWM
Fig. 3. Model of effective common mode voltage
2.1. Common mode voltage model
VCM_ EFF is the combination of common mode voltage
between lines and the common mode voltage produced by
the differential mode voltage which is influenced by the
filter inductance imbalances depicted as Vry. CLG and Lg
can be avoided for grid frequency. Effective common mode
voltage can be defined as
VCM _ EFF = VCM _ RY + Vry
As presented in the introduction, the galvanic
connection between PV inverter and the grid pauses the
problem of DC injection. This section models the
equivalent common mode DC voltage considering both
differential mode and common mode voltage.
Fig. 2 shows a single phase inverter connected to the
output of PV array through a DC link capacitor. LR and LY
are line inductors respectively and Lg is the inductor on the
grid side. Parasitic capacitance can exist between PV panel
and frame, represented as CPV, between line and ground, as
CLG and between transformer windings, CW.
For PV inverters with galvanic isolation , the stray
capacitance between transformer windings offer impedance
to DC current and therefore the DC injection is not much
influenced by topology or PWM technique used in
inverters. But in transformerless inverters since winding
Vry =
This voltage can be made zero if LR=LY. The inverter
has been designed with equal output inductors. In this
paper, the DC injection measured and shown is the total
DC component in the output of the inverter [10]-[12].
2.2. Unipolar PWM
Stationary proportional integral (PI) controller often
produces steady state error in tracking a sinusoidal
reference. Synchronous PI reduces steady state errors but
its implementation is complex. P+R controller offers an
additional integrator and is much simpler to implement.
The controller avoids the use of a real time capacitor and
uses a model of capacitor in its feedback loop. Gain of the
controller is given by
In a Unipolar PWM switching, both sinusoidal and
mirrored sinusoidal signals are compared with triangular
wave to generate pulses such that normal sinusoidal
reference is used for one leg and mirrored for the other.
There are two zero output voltage stages and hence we
obtain a three level output. The switching ripple in the
current is twice the switching frequency thereby filter
requirements are minimized. Efficiency of up to 98% is
obtained due to reduced losses considering the zero output
voltage stages. This switching scheme is chosen because of
the many advantages as against the drawback of leakage
current [13], [14].
In mode1, S1,S4 are ON , VRN = VDC , VYN = 0 and VRY
= VRN - VYN =VDC and in mode 2, S2,S3 are ON, VRN= 0 ,
VYN = VDC and VRY = -V DC , in mode 3, S1,S3 are ON ,
VRN= V DC , VYN = VDC and VRY =0 and in mode 4, S2,S4
are ON , VRN= 0, VYN = 0 and VRY =0. In unipolar PWM
technique, the output voltage swings from 0 to +VDC, +VDC
to 0 and then from 0 to -VDC producing a three level output.
K iω c s
s + 2ω c s + ω 2
KCsG PR (s )
LCs + RCs + KCsG PR (s ) + 1
G PR (s ) = K p +
I ref
Design of controllers
The component used to block DC is the capacitor. In
case of half bridge inverters, one of the DC link capacitor is
always in the conducting path and blocks DC.
An AC capacitor can block dc injection but amount to
large amount of series voltage drop based on the output
currents of highly rated inverter. In order to prevent reverse
polarity effects on the polarised capacitor, complex DC
voltage control methods have to be used. Electrolytic
capacitors produce small amounts of AC voltage ripple.
Since these capacitors are polarised, they may not be able
to withstand reverse voltages. Non-polarised capacitors
available are of low capacitances that may cause voltage
Fig. 4. Linear model of inverter
A simple linear model (fig4) of an H Bridge inverter can
be obtained by considering that the DC link voltage is
constant, a large DC link capacitance can make the voltage
constant, and also the switching frequency should be
considerably large.
The P+R controller is based on the internal model
principle. According to the principle, the models of the
reference and disturbance are included in the feedback
loop. This ensures a very good tracking of the reference in
the stationary frame and rejection of disturbances.
Fig. 5. (a) Bode plot of Io/Iref with and without capacitor, (b) Bode plot (c)
Step response of ideal and non-ideal PR controller d)Step response of
Io /Iref for different values of capacitors
where GPR(s) denotes the P+R controller transfer
function , Kp is a constant of proportionality and Ki is a
constant of integration, K is the overall controller gain,
L=LR+LY, ω is the resonant frequency and ωc is the cut off
frequency such that ωc << ω.
Fig 5a shows the effect of capacitor in system response.
It can be seen that by adding capacitance the magnitude
plot gives a zero response to zero frequency. The proposed
controller is a non ideal P+R controller other than that used
previously. The ideal P+R controller is un-damped and has
lesser sensitivity due to the very narrow bandwidth. Due to
the infinite gain, the inverter output is almost saturated in
an ideal P+R which can be seen in fig5b, c. With the non
ideal P+R controller, the overall system is under-damped
and has better sensitivity because of the adjustable
bandwidth which takes care of small variations in
frequency. By introducing ωc, into the controller design, the
bandwidth becomes adjustable and as can be observed in
fig 5b, c is more sensitive to frequency variations.
Fig5d shows, as the capacitance increases the dynamic
response becomes slow. So too small a value of capacitance
causes fundamental voltage drop. So a choice has to be
made between achievement of a good dynamic response
and limited fundamental frequency voltage drop. The
controller gives a finite gain and prevents inverter from
saturation. Thus this type of controller brings about zero
steady state error and better rejection of selected noise as
compared to PI controller. This controller has been
designed for 50Hz frequency[15]-[17].
Fig. 6.(a) Circuit Diagram with modelled capacitor and (b) controller
block diagram.
Fig. 6 shows the simulation circuits. A DC offset is
provided in the sinusoidal reference current, which is
effectively eliminated by properly tuning the P+R
controller. The PWM delay in the output current is taken
care of by time delay introduced in the feedback loop
which ensures a sinusoidal error signal given as input to the
controller. The overall gain is so fixed as to take care of the
stability of the system.
4.1.Unipolar without controller
It can be observed through fast Fourier transform (FFT)
analysis that DC component present is above the IEEE
limits as can be seen in fig 7. The utility voltage used is
311Vrms and DC link voltage of 450V.The filter inductors
used are 0.1H each and resistor value is 2Ω.
Implementation and analysis
To validate and analyse the quality of output for
unipolar PWM with and without the controller, simulations
were performed in MATLAB/Simulink
transformerless inverters which can be avoided by choosing
appropriate control strategy, PWM techniques and topology
of inverter. This paper shows that the modified
proportional + resonant controller along with non real
capacitor and equal value inductors can be used to reduce
DC Injection. The modified non ideal P+R controller has
better sensitivity and gives a finite gain compared to the
ideal P+R controller. A unipolar PWM, in spite of having a
varying common mode voltage, gives a good response to
the DC blocking capacitor and non – ideal P+R controller.
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(b) FFT Analysis of Output current
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sensitive to frequency variations
Fig. 8. Unipolar Output with controller (a) Output current and voltage (b)
FFT Analysis of Output current
DC component
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