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Materials Today: Proceedings 2 (2015) 4272 – 4279
nanoFIS 2014 - Functional Integrated nanoSystems
The phonsistor - a novel VO2 based nanoscale thermal-electronic
device and its application in thermal-electronic logic circuits
(TELC)
J. Mizseia,*, M. C. Beina, J. Lappalainenb, L. Juhásza, B. Plesza
a
Budapest University of Technology and Economics, Department of Electron Devices, H-1521 Budapest, Hungary
b
University of Oulu, Department of Electrical Engineering, P.O. Box 4500, FIN-90014, Oulu, Finland
Abstract
The continuous development of electronics has been characterized by Moore’s law. Although the current CMOS integrated circuit
development is driven by a lot of innovations, there are still some limits determined by unavoidable physical effects. There are
many new ideas for building atomic or molecular scale devices for the information technology, but there is still a gap between
CMOS technology and novel devices. The recently proposed thermal-electronic device (phonsistor) and the CMOS compatible
thermal-electronic logic circuit (TELC) may help to fill this gap. The operation is based on the semiconductor-metal transition
(SMT) effect shown by certain materials, for example VO2. The switches can be excited by electronic and thermal signals as well,
thus two different physical parameters are available for representing the logic states. A proof of concept for the device operation
has been demonstrated, and device scaling and integration issues will be discussed too.
2014 Elsevier
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2015 The ©
Authors.
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This is an open access article under the CC BY-NC-ND license
Selection and peer-review under responsibility of Conference Committee of nanoFIS 2014 - Functional Integrated nanoSystems.
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Selection and peer-review under responsibility of Conference Committee of nanoFIS 2014 - Functional Integrated nanoSystems.
Keywords: nanoelectronics; phonsistor; thermal-electronic; vanadium-dioxide; MIT; SMT
1. Introduction
Until now, the continuous development of electronics has been characterized by Moore’s law. The scale down
resulted in the nanosized CMOS devices and integrated circuits, pushing the “red brick wall” towards the lower
dimensions. Although the current CMOS integrated circuit development is driven by a lot of innovations, there are
still some limits determined by unavoidable physical effects such as tunneling of charge carriers through thin
* Corresponding author. Tel.: +36-1-463-2715; fax: +36-1-463-2973.
E-mail address: mizsei@eet.bme.hu
2214-7853 © 2015 The Authors. Published by Elsevier Ltd. This is an open access article under the CC BY-NC-ND license
(http://creativecommons.org/licenses/by-nc-nd/4.0/).
Selection and peer-review under responsibility of Conference Committee of nanoFIS 2014 - Functional Integrated nanoSystems.
doi:10.1016/j.matpr.2015.09.013
J. Mizsei et al. / Materials Today: Proceedings 2 (2015) 4272 – 4279
4273
insulating regions, depletion layers at both side of p-n junctions and statistical irregularities in the number of dopant
atoms.
On the other hand, there are many new ideas for building atomic or molecular scale devices for the information
technology. However, there is still a gap between the up-to-date “top-down” CMOS technology and the “bottom-up”
devices, i.e. molecular electronics, nanotubes, single electron transistors. A new functional thermal-electronic device
(phonsistor; a portmanteau of “phonon transistor”) and the CMOS compatible thermal-electronic logic circuit
(TELC) [1, 2] may help to fill this gap. The operation of these functional devices is based on the semiconductor-metal
transition (SMT) effect shown by certain materials, for example VO2. This effect allows an electric resistance change
in three to four orders of magnitude induced by thermal or electrical excitation [3].
The phonsistor is made up of only bulk type semiconductor domains, consisting of significantly less regions,
interfaces, and providing advanced functionality compared to a monolithic MOSFET (there are no differently doped
regions, p-n junctions at all). This way, the single switches can be processed in steps that are technologically less
demanding and fewer in number. The switches in the thermal-electronic logic circuit (TELC) can be excited by
electronic and thermal signals as well, thus two different physical parameters are available for representing the
different logic states. This is similar to neurons in the nervous system, where information is transmitted by different
mechanisms for short and long distances and allows the realization of more complex logical connections as well as
modeling of data processing in nervous systems.
Due to its simple structure and process technology, the TELC can be built as real 3D structure and can be made
compatible with current CMOS technology enabling a smooth transition between the two integrated circuit concepts.
With its extended logical functionality, TELC represents a higher level of integration that can be achieved with
currently available technology.
If scaled down to nanosize, the heat is distributed not only by diffusion, as it is characteristic for macroscopic
structures. Quantum and hot electron effects enable the device to operate faster than current CMOS switches.
2. The idea of the thermal-electronic logic circuit
Most of electron devices are temperature sensitive. The forward voltage of silicon diodes (p-n junctions) decrease
about 2 mV/K at a constant forward current. The early idea for thermal-electronic logic circuit (TELC) contained p-n
junctions and control resistors (see Fig. 1.). Either of input resistors is heated up, the output voltages decrease (NOR
logic function).
Fig. 1. Early idea for thermal-electronic logic circuit (TELC) using p-n junctions and heating resistors
The properties of this kind of thermal-electronic logic circuit depend on thermal properties of the structure and
electrical properties of the components. This simple system is not suitable for practical realization of logic networks,
as the power gain and the slope of the transfer function is low. However, this may be overcome with devices having
different voltage vs. temperature characteristics.
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3. The semiconductor-metal transition
Some metal oxides, such as vanadium dioxide (VO2) exhibit reversible temperature-driven phase transition [4]
followed by several physical phenomena, including change of optical and electronic properties [5, 8]. From electronic
point of view, this is usually mentioned as semiconductor-metal transition (SMT, traditionally mentioned as metalinsulator transition, MIT). Below the transition temperature of 68 °C, VO2 behaves as a semiconductor with
monoclinic crystal structure and band gap of about 1 eV, whereas for temperatures higher than 68 °C it transforms
abruptly to metallic state with tetragonal rutile structure. In VO2 thin films this transition can be triggered by
thermal [5-7], electrical (charge injection or Joule heating) [6-8] or optical excitation (photon excitation) [9, 10], and
even by external pressure or strain [10]. The SMT induces extremely fast and abrupt changes in the electronic and
optical properties of the material: The electrical resistivity increases by 3 to 5 orders of magnitude (depending on the
crystalline quality of the deposited films [12], stoichiometry and doping [12]), while the optical reflectivity markedly
decreases [9, 10]. An activation time as short as 100 fs has been reported for the optically driven SMT transition [9,
10], and the electronically induced transition occurs within nanoseconds [6-8, 14].
The SMT resistor itself has thyristor-like characteristics due to the self-heating effect. At certain voltage and current
the power dissipation is enough to heat up the system above the phase transition temperature resulting in quick drop
of resistance. Thus, the SMT resistor may have two stable operating points, i.e. a high current and low voltage (low
resistance metallic) “on” state, and a low current and high voltage (high resistance semiconductor) “off” state (see
Fig. 2.).
Fig. 2. Thyristor-like behavior of a physical VO2 bulk resistor in series with a 100 : resistor
4. The phonsistor concept
A new thermal-electronic device is planned by integrating a heating resistor and an SMT device. The operation of
this device is similar to the bipolar transistor. Joule heat is generated in the heated resistor (see Fig. 3, shaded area).
The heat (phonons) is transported towards the SMT resistor by diffusion similar to the diffusion of minority carriers
in the base of a bipolar transistor. The switch-on voltage and hold-on current of the SMT resistor can be decreased by
temperature increase, controlled by the power dissipated on the attached heating resistor and the thermal properties of
the surrounding materials. This thermally coupled device will be hereinafter referred to as phonsistor (patent pending).
The operation of devices with characteristic size in the nanometer range could be somewhat different. As the
thickness of layer “A” (Fig. 3) is less than the mean free path of electrons, input current flows by ballistic transport
resulting in heat-generation at the metal contact and in the SMT resistor material, where hot electrons loose their
energy. This effect promises even shorter switching time for the case of scaled-down devices.
The phonsistor is a bulk type device, like the bipolar transistor, but it does not contain depletion layers. The number
of interfaces is fewer compared to MOS devices and the two terminals of the input can be placed extremely near to
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each other, producing the control heat by tunnel current. Besides the fewer regions, a further benefit compared to a
MOS transistor is that phonsistor consists only of near intrinsic regions, thus statistical irregularities caused by the
number of dopant atoms are avoided. The SMT effect is demonstrated on 20 nm [15] and 10 nm thin films [16] with
1 ns time constant, therefore the lower limit of scaling down is expected to be about these values.
Fig. 3. The phonsistor concept. (a) The simplest phonsistor consisting of a heating resistor “A” and an SMT resistor “B” thermally coupled. (b)
Joule heat of the resistor “A” used for “switching on” the resistor “B” made from SMT material. (c) Scaled-down version (heating resistor
thickness lower than the mean free path for electrons) with hot electrons injected directly into the SMT material by ballistic transport and
thermalizing there (see shaded domains). Tunnel junction or other type of junctions (p-n, metal-semiconductor) may be used forhot electron
injection, too.
5. The SMT-based thermal-electronic logic circuit (TELC) concept
Logic gates may be built using one or more heat sources (conventional or SMT resistors) as inputs, thermally
coupled with SMT resistors as outputs. This structure shows the following novelties compared to an electronic-only
logic gate:
x an SMT resistor can be used as input and output as well (bidirectional port);
x ports can be connected thermally and/or electrically meaning complex possibilities and also serious challenges in
circuit design;
x SMT resistors at the input of the gates can “remember” their logic state due to self-heating caused thyristor-like
characteristics;
x geometry and material selection determines the thermal coupling between the ports enabling relatively simple
structures to implement complex logical functions.
Some simple logic gates based on the above presented concept can be summarized as follows (see Fig. 4):
1. if the thermal coupling is strong, then any of the “A”-“C” excited phonon emitters produces enough heat to
switch on the “O” SMT resistor(s): parallel “OR” logic function;
2. if the thermal coupling is weak, then more than one phonon emitters (“a” and “b”) must be excited in the same
time to produce enough heat to switch on the SMT resistor(s): parallel “AND” logic function;
3. complex logic functions can be realized by different thermal coupling between the input resistors and output
SMT resistors;
4. if one or more input are excited for shorter time or with lower input signal than the necessary to switch on
(subthreshold signal), but these inputs get another subthreshold excitations within the thermal time constant,
then the output SMT resistor(s) may switch on: “sequential AND” logic function for a single input, but
complex sequential/parallel logic function(s) for two or more inputs.
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Fig. 4. Thermal-electronic logic gates. Each square represents a resistor. “O” resistors are of SMT material, inputs may be SMT or ohmic
resistors. The geometry and the thermal conductivity of the applied insulators (effective distance) influence the strength of thermal coupling, thus
different logic functions can be realized. (a) OR gate: O=A+B+C; (b) AND gate: O=a×c; (c) Complex AND-OR gate: O=(a×c)+B. Lth represents
the thermal diffusion length at the given operating frequency.
The thermal-electric logic circuit (TELC) consists of a lot of phonsistors. Some of them can be thermally coupled
to each other (Fig. 5.a), but the output voltage of a voltage-source and pull-up resistor (“P”) powered SMT resistor
can be treated as electric signal, too (Fig. 5.b). This electrical signal can be transferred for longer distances through
metallic lines.
Fig. 5. Thermal-electric gates with thermal (a) and electrical (b) outputs/propagation lines for electrical and thermal coupling.
The possibility of using two different signals gives high flexibility to this kind of system. Thermal signals, for
example, may propagate in different directions, but only for short distances, i.e. about for the thermal diffusion length.
However, the thermal signal may propagate and regenerate itself along a longer thermal transmission line (Fig. 5.a)
constructed from SMT resistors near to each other. Further input (and output) terminals can be built in along the
thermal transmission line (“X”), and the thermally generated logic “one” (the “hot” state) propagates in all directions
along the thermal transmission line.
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6. Considerations of physical realization
The thermal-electronic logic circuit (TELC) can be realized by thin film technologies compatible with conventional
silicon integrated circuits. The proposed vertical arrangement (see cross section on the Fig. 6) includes a substrate
(30) with conventional CMOS integrated circuits, and vertical resistors (34-39) embedded into heat and electric
insulator (33), together with thermal and/or electrical conductor columns (31-32). The thermally “grounded” (31) heat
conductor (copper metallization or a bundle of carbon nanotubes) separates thermally the elements of the system,
while the thermally “floating” heat conductor (32) results in good thermal coupling between (36, 38) and (39). If the
(38) resistor is an output, than “OR” function is realized for the (36, 37, 39) inputs, while “AND” function is valid for
the (34-35) inputs.
This kind of arrangement seems to be compatible with metallization technology of VLSI integrated circuits
(damascene technology), and it can increase overall function density (as a real 3-dimensional system). However, the
vertical and lateral heat and current flow paths should be analysed very precisely.
33
31
34
35
37
36
38
32
39
30
Fig. 6. Vertical arrangement for thermal-electric logic circuit (TELC)
As the thermal time constants go down with shrinking of the physical dimensions (scale-down), their value can be
comparable with the electrical time constants (10-9-10-10 seconds) if integrated with nanosized “classical” electronics.
The thermal-electric logic circuit could be realized separately or together with commercially used silicon VLSI
(CMOS) integrated circuits. Electrical and thermal coupling, infrared or visible radiation can be used for interfacing
with TELC.
The system contains less interfaces, compared to the conventional VLSI circuits, thus the scale down procedure is
easier, and more effective. The tunnel effect may limit the scaling down of phonsistor in 10-20 nm linear size and
complex logic gates in 50 nm characteristic size.
As it has been discussed above, the CMOS compatible TELC could improve the capabilities of the conventional
integrated circuits. The TELC could play an important role in the core of microprocessors, as its scaling down
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possibility is one order of magnitude higher, than in the case of CMOS. The most critical, high speed computing jobs
may be performed by this thermal-electric logic, while the conventional CMOS part of the chip takes care of timing
and connection with the other parts of the complex digital system.
7. Experimental results
An experimental model TELC system has been realized by metallization and VO2 thin film deposited by laser
ablation onto an insulator substrate. The substrate was cut into chips, which were mounted onto standard TO headers
and contacted with wire bonding (Fig. 7.). Outer rings of the metallization were shorted, and used as common ground
electrodes. The internal circular areas (dots) serve as inputs and outputs of the circuit. There are 9 thermally coupled
devices forming a TELC (see Fig. 7). This arrangement, i.e. the ring shaped electrodes as grounds, helps to separate
the electrical control of different gates from each other, as the whole chip is covered with the VO2 layer.
Fig. 7. Thermal electronic logic gate model system mounted onto a TO header, the measuring circuit and the demonstration of OR and AND
operation. V1 and V2 are input voltages, V3 is the output signal and V4 is the power (clock) signal.
During testing some of the gates were connected to current limited power supplies through pull up resistors. Gate
voltages (1-4) have been monitored and plotted by a four-channel oscilloscope. The gates G1, G2, G3 were used to
demonstrate the NOR operation. G3 is treated as output, while G1 and G2 as are inputs. As it can be seen (Fig. 7,
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bottom-left), any of the input gates switches itself and the output on. Simultaneous high state on the gates results in
shorter response time.
The NAND operation is demonstrated on the very same gates but with shorter heating pulses. Lower supply
voltages would result in similar change in behavior. In these cases the power of the Joule-heat produced by one gate
alone is not enough to switch on the device (Fig. 7, bottom-right). G3 is only switched on when both of G1 and G2
heats it. After switching on G3 sticks in high state due to self-heating and can only be reset by switching the power
supply off (V4 is for clock signal). Note the interaction of input gates: When they’re excited parallel they heat up the
output and themselves, too.
8. Conclusion
The TELC and its building blocks (phonsistors) are consisting of extremely simple structures (resistors with
common bottom electrodes and only two interfaces). They are subject to less physical limiting factors considering the
scaling down. Phonsistors are expected to operate down to (at least) 10 nm characteristic linear size. Their realization
could be compatible with the recent IC technology. The realization of highly integrated TELC would need very exact
and very sophisticated electro-thermal-logic simulation and new design principles to be developed. Successful
integration would result in various possibilities of interaction with other part of systems or the ambient (electrical or
thermal coupling to CMOS, possibility of optical coupling); improved technological flexibility (horizontal, vertical or
mixed realization) and increased design flexibility, due to the reversibility of signal paths and the promise of the
implementation of brain-like operation.
Acknowledgements
The research was partially supported by the project No. NN 110867 of the Hungarian Scientific Research Fund
(OTKA).
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