1
DC bus imbalance in a three phase four wire grid
connected inverter
Anirban Ghoshal, Vinod John
Abstract—DC bus imbalance in a split capacitor based
rectifier or inverter system is a widely studied issue. In this
paper the DC bus imbalance problem has been studied
for a three phase four wire grid connected inverter where
the midpoint of the split capacitor is connected to the
neutral of grid. The problem has been analysed from
common mode point of view and subsequently a low
frequency common mode model of the entire system has
been obtained. The same model helps to find a suitable
corrective action. Obtained experimental results confirm
the correctness of the theoretical understandings.
Index Terms—DC bus balancing, FEC.
I. I NTRODUCTION
T present three phase inverters find wide range
of grid connected applications such as Front end
converter (FEC) to drives and distributed generating
systems, Active filter, Uninterrupted power supply (UPS)
etc. IGBT based three phase two level bridge converter
has become the standard topology for these applications.
In few cases provision for a fourth wire is a necessity.
This requirement is met either by a fourth leg in the
inverter or by using the midpoint of DC bus capacitors.
Generally such requirement arises to cater single phase
loads or to provide earth fault protection or in a transformerless application. Here in this paper the problem
of DC bus imbalance is addressed for a three phase
four wire grid connected inverter where the fourth wire
connects the midpoint of DC bus capacitors to the neutral
point of grid. DC bus imbalance in a split capacitor
converter is a widely studied issue [1]–[4]. Generally
two precision resistors are used to divide the bus voltage
equally between the two capacitor. But because of offset
present in the sensed current and voltages, the neutral or
the wire connected to the midpoint of DC bus capacitor
carries a ‘DC’ current which causes one of the bus
voltage to rise and the other to decrease resulting in DC
bus imbalance [1]–[5]. Finally one of the bus voltage
gets clamped to the peak of phase voltage. Present
literatures show that the corrective action can be taken
in two ways. First one is by adding a feed-forward or
compensating term to the modulating signal [3]–[5] to
inject a ‘DC’ current into the system and the second
A
Fig. 1.
Inverter with LCL filter
one is by generating a current reference which is to be
tracked by the current controller such that the voltage
imbalance is forced to zero [2], [5]. Here in this work a
low frequency common mode model of the entire system
has been developed to understand the imbalance issue.
The similarity of this analysis with the existing approach
has been pointed out. Further the same common mode
model has been used to derive a suitable controller to
mitigate the problem.
II. DC BUS
IMBALANCE PROBLEM
The structure of a 3 phase 4 wire LCL filter based grid
connected inverter is shown in Fig. 1. The midpoint of
the DC bus is connected to the neutral point of the grid.
The problem to be looked into here is unequal voltage
distribution in the DC bus or voltage imbalance between
top (positive) DC bus and bottom (negative) DC bus.
The resistance Rd in the DC bus side are the voltage
balancing resistors. Here Rd = 25 kΩ, 25 W att.
DC bus capacitances, Cd , are of 3300 µF, 500 V . The
requirement here is to keep the total bus voltage at a
specified voltage Vdc (1) and the difference between top
(PO) and bottom (ON) DC bus voltage,∆v , should be
‘zero’ (2). Under these conditions the bus voltage would
be equally distributed in the two capacitors (3).
vP O + vON = vdc
(1)
∆v = vP O − vON = 0
(2)
vdc
(3)
vP O = vN O =
2
The voltage imbalance problem is generally analysed
by using KCL at the DC bus side. The same dynamic
equation can easily be achieved by doing a common
mode analysis.
2
III. M ODELLING
OF
AC
SIDE
If duty ratio at any instant is di , then average pole
voltage on AC side can be written as shown in (9).
vi = di vP O − (1−di ) vON ,
Fig. 2.
i = R, Y, B
vi = di (vP O + vON ) − vON
⇒
Common mode equivalent circuit of DC bus
Here
(9)
From (1) and (2) vP O and vON can be written as
vdc + ∆v
2
vdc − ∆v
=
2
A. From common mode analysis
vP O =
As the midpoint of the DC bus is connected to the
neutral and hence earthed, so it is at earth potential.
Therefore the common mode voltage at DC bus side is
vON
vP O − vON
∆v
vP O + vN O
=
=
2
2
2
vcom1 =
∆v = 2vcom1
⇒
(10)
Now for sine triangle PWM technique duty ratio di is
related to modulating signal mi by (11).
(4)
di = 0.5 + 0.5 mi
(5)
(11)
Again, mi can be composed of a DC part and an AC part
From common mode point of view both ‘P’ and ‘N’ are
at same potential. Therefore the DC bus side common
mode equivalent circuit can be represented as shown in
Fig. 2. From Fig. 2, neutral current in can be related to
vcom1 as shown in (6).
2Cd
vcom1
d
= in
vcom1 +
Rd
dt
2
(6)
Fig. 3.
i.e. mi = mdci + maci . Therefore using this relationship
along with (9), (10), and (11), average pole voltage can
be expressed as shown in (12).
B. From KCL
Applying KCL at point ‘O’ in fig. 1 gives
iP O +
⇒
⇒
Cd
Cd
vP O
vON
= iON +
+ in
Rd
Rd
(7)
d
∆v
∆v +
= in
dt
Rd
(12)
Common mode voltage at the terminals of inverter which
is average of the three pole voltages can be expressed
by (13). Further simplification shows that common mode
voltage at the AC terminals of inverter can be represented
by (14).
d
(vP O − vON )
(vP O − vON ) +
= in
dt
Rd
Cd
vdc
vdc ∆v
+
+ maci
2
2
2
vdc
vdc
vi = (mdci
+ vcom1 ) + maci
2
2
vi = mdci
⇒
dvP O
vP O
dvON
vON
+
= Cd
+
+ in
dt
Rd
dt
Rd
⇒
Low frequency common mode model of inverter
(8)
Equations (6) and (8) show that if in is DC then at
steady state ∆v = Rd in . Hence if a direct current flows
in the neutral wire then the two DC buses would not
remain equal. Also it can be concluded that the voltage
imbalance can be treated as a low frequency common
mode issue.
vcom2 =
⇒
1
vRO + vY O + vBO
= Σvi
3
3
vdc
+ vcom1
vcom2 = mdc
2
(13)
(14)
Here the assumption is that the injected DC offset in
all phases are equal. The low frequency common mode
model of inverter at the AC terminal is represented by
(14). The equivalent circuit is shown in Fig. 3.
3
∆v = 30 V , as seen in Fig. 7a. When the corrective
action was activated the voltages were brought to 150 V
as set by the reference (Fig. 7b). Fig. 7c shows the
charging of DC bus to the reference of 300 V with the
corrective action.
Fig. 4.
Low frequency common mode model of entire system
IV. L OW FREQUENCY
EQUIVALENT MODEL AND
IMBALANCE MITIGATION
The AC terminals, R,Y and B (Fig. 1), are at same
potential from common mode point of view. Hence the 3
phases of LCL filter can be reduced to a single equivalent
circuit. Combining this with low frequency common
mode equivalent circuit of inverter, an equivalent circuit
for the entire system can be obtained. Fig. 4 represents
the low frequency common mode equivalent circuit of
the total system. From this equivalent circuit it becomes
clear that the ‘DC’ current flowing in neutral wire can
be controlled by regulating ‘mdc ’ to achieve vcom1 = 0.
This will ensure that the DC bus voltage is equally
distributed in the two capacitors. Following section discusses the design of a suitable controller to mitigate DC
bus imbalance problem.
V. C ONTROLLER
DESIGN
Let us assume that the 3 phase 4 wire inverter with
LCL filter is being used as a DSTATCOM. The main
control strategy with the DC bus imbalance correction is
shown in Fig. 5. Here in this paper controller design part
for the imbalance correction is discussed. The objective
∆v
here is to make vcom1 =
= 0. So the reference
2
value for difference between two capacitor voltages is
set at ∆v ∗ = 0. As the two DC bus voltages are sensed
so ∆v can be calculated easily. The error between the
reference and the measured value is passed through a PI
controller to obtain the compensating current reference.
The current controller used here for controlling the
fundamental current is a PR controller. This will act as
a proportional controller for this compensating current
reference which is DC in nature. The closed loop control
block diagram is shown in Fig. 6.
VI. E XPERIMENTAL
(a)
(b)
(c)
Fig. 7. DC bus imbalance and corrective control action. (a)DC bus
charging without unbalance correction. Scale: X-axis: 100ms/div and
Y-axis: 500mV/div (1V ≡ 90V ); (b)Unbalance correction. Scale:
X-axis: 50ms/div and Y-axis: 500mV/div (1V ≡ 90V ); (c)DC bus
charging with unbalance correction. Scale: X-axis: 100ms/div and
Y-axis: 500mV/div (1V ≡ 90V ).
RESULT
During experiment initially each half of DC bus was
pre-charged closed to a voltage of 100 V . Then a
command was initiated to boost it to a total of 300 V .
Without corrective action the DC bus settled with a
VII. C ONCLUSION
In this paper the DC bus imbalance problem present
in a 3 phase 4 wire grid connected inverter has been
investigated. The problem has been analysed by making
4
Fig. 5.
Total system diagram along with control blocks
Fig. 6.
Closed loop control block diagram for DC bus imbalance correction
5
a low frequency common mode equivalent circuit of the
entire system. A suitable controller has been designed to
mitigate the problem. The experimental results obtained
confirms the theoretical understandings.
R EFERENCES
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Conf. of IEEE Ind. Electronics (IECON), Taipei, Taiwan, Nov
2007.
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[4] Y. K. Lo, T. H. Song, and H. J. Chiu, “Analysis and elimination
of voltage imbalance between the split capacitor in half-bridge
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pp. 1175–1177, Oct 2002.
[5] R. Ghosh and G. Narayanan, “Control of three-phase, four-wire
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