5
4
3
2
1
D
D
TMS320C6678 EVM Board for TI
Product name : DSPM-8301E
C
C
Rev. A101-1
PCB PN : 19C2830100
Project Code :
B
PCB Thickness : 62 mils(1.6mm)
12 Layers
A
DISCLAIMER: THIS CIRCUIT DESIGN IS
PROVIDED AS REFERENCE ONLY,
WITHOUT WARRANTY EXPRESSED OR
IMPLIED. THE USER IS ENCOURAGED
TO PERFORM ALL DUE DILIGENCE WITH
RESPECT TO DESIGN AND ANALYSIS.
Copyright (C) 2010 Texas Instruments Incorporated.
All rights reserved. This document is proprietary to TI
and is intended solely for use by TI and its customers.
This document is not to be reproduced, distributed, or
disclosed to other parties in its entirety or in part
without the express written consent of TI.
TOP
0.5 oz
L2_GND
0.5 oz
L3
0.5 oz
L4_PWR
0.5 oz
L5
0.5 oz
L6_GND
0.5 oz
L7_GND
0.5 oz
L8
0.5 oz
L9_PWR
0.5 oz
L10
0.5 oz
L11_GND
0.5 oz
BOT
0.5 oz
3mils
p.p
4mils
core
7mils
p.p
6mils
core
B
4.5mils p.p
core
4mils
TI Information - Selective Disclosure
Texas Instruments
20450 Century Blvd
Germantown, MD 20874
USA
4.5mils p.p
6mils
core
7mils
p.p
4mils
core
3mils
p.p
A
Designed for TI by ADVANTECH
Title
COVER PAGE
Size
C
Date:
5
4
3
2
Document Number
Rev
A101-1
DSPM-8301E
Tuesday, March 08, 2011
Sheet
1
1
of
40
5
4
3
2
1
TITLE & TABLE OF CONTENTS
Page
D
Description
Page
Description
01
COVER PAGE
31
FPGA_XC3S200AN_B
02
TITLE & TABLE OF CONTENTS
32
FPGA_XC3S200AN_C
03
BLOCK DIAGRAM_AMC
33
Power ucd9222
04
POWER SEQUENCE
34
Power_1.2V/1.8V/2.5V/0.75V
05
POWER CONSUMPTION
35
Power_VCC5 / VCC3V3_AUX
06
POWER DISTRIBUTION
36
Power VCC1V5
07
CLOCK DIAGRAM
37
History_0
08
FPGA_BLOCK
38
09
BUS Management Map
39
10
AMC GF
11
MMC
12
DSP_SERDES_PORTS
13
DSP_DDR3
14
DSP_EMIF
15
DSP_JTAG_EMU_TSIP
16
DSP_MISC
17
DSP_CLOCK_Smart Reflex
18
DSP_POWERA
19
DSP_POWERB
20
DSP_POWERC
21
DSP_GND
22
CLOCK_GEN1
23
CLOCK GEN2
24
DDR3
25
DDR3_ECC
26
USB-JTAG
27
Gigabit Ethernet PHY
28
RJ45
29
Connectors for HyperLink & Debug
30
FPGA_XC3S200AN_A
D
C
C
B
A
B
A
Designed for TI by ADVANTECH
Title
TITLE & TABLE OF CONTENTS
Size
C
Date:
5
4
3
2
Document Number
Rev
A101-1
DSPM-8301E
Tuesday, March 08, 2011
Sheet
1
2
of
40
5
4
3
2
1
BLOCK DIAGRAM_AMC
AMC Board
AMC_State
MMC JTAG
SPI EEPROM
SYSPG_D1 LED
FPGA_DONE LED
JTAG
User controlled LED - 4
1. 64M X 16 / 512MB
2. 128M X 16 / 1GB
ROM_SPI
MMC
XC3S200AN
(XILINX)
CDCE62005
CLK_SPI2
CLK_SPI3
CLK#2
Sequence
Control
JTAG & EMU[0:1]
CH-A
USB-JTAG
FT2232HL
CH-B
DSP_UART
UART
EEPROM
PIN
PIN
Port mapping
2
1
Power Control
Power
RAM
DSP
FPGA PHY
Others
PWR CONN
RS232
MAX3221EAE
PIN
Port mapping
Port mapping
PIN
Port mapping
PIN
01
GND
41
EMIFCE2Z
EMIFA21
03
SDA
43
EMIFBE0z
46
EMIFA22
05
SCL
45
EMIFBE1z
EMIFA03
48
EMIFA23
07
EMIFD0
47
EMIFOEz
EMIFA04
50
GPIO00
09
EMIFD1
49
EMIFWEz
12
EMIFA05
52
GPIO01
11
EMIFD2
51
EMIFRnW
14
EMIFA06
54
GPIO02
13
EMIFD3
53
EMIFWAIT1
16
EMIFA07
56
GPIO03
15
EMIFD4
55
TIMI0
18
EMIFA08
58
GPIO04
17
EMIFD5
57
TIMO0
20
EMIFA09
60
GPIO05
19
EMIFD6
59
TIMI1
22
EMIFA10
62
GPIO06
21
EMIFD7
61
TIMO1
24
EMIFA11
64
GPIO07
23
EMIFD8
63
SSPMISO
26
EMIFA12
66
GPIO08
25
EMIFD9
65
SSPMOSI
28
EMIFA13
68
GPIO09
27
EMIFD10
67
SSPCS1
30
EMIFA14
70
GPIO10
29
EMIFD11
69
SSPCK
32
EMIFA15
72
GPIO11
31
EMIFD12
71
UARTTXD
34
EMIFA16
74
GPIO12
33
EMIFD13
73
UARTRXD
36
EMIFA17
76
GPIO13
35
EMIFD14
75
UARTRTS
38
EMIFA18
78
GPIO14
37
EMIFD15
77
UARTCTS
Title
39
EMIFCE1Z
79
GND
Size
02
EMIFA00
42
EMIFA20
04
EMIFA01
44
06
EMIFA02
08
10
80
40
EMIFA19
80
GPIO15
4
TSIP_CLK0
11
SRIO_4
TCLKB
TSIP_CLK1
12
TSIP0 [0..3]
100MHz
13
TSIP1 [0..3]
SGMII
14
FCLKA
00
01
15
02
16
03
04
PCI-E_1
05
PCI-E_2
B
Alternate I2C link
TCLKC
TSIP_FS0
TCLKD
TSIP_FS1
17
06
18
07
19
08
SRIO_1
09
SRIO_2
10
SRIO_3
20
A
Designed for TI by ADVANTECH
BLOCK DIAGRAM_AMC
79
3
Port mapping
TCLKA
C
Date:
5
C
AMC Port mapping
B
A
POWER 12V
128k-byte
Miscellaneous I/O 80 Pin conn. Signal
Port mapping
TSIPx2
Pin-Header 3x1
2.54mm
DSP_SGMII_P1 & MDIO
PIN
Level-Shifter
DSP_I2C
DSP_UART
JTAG & EMU[0:1]
DSP_SGMII_P1 & MDIO
SWITCH
(TS3L301)
DSP_I2C(1.8V)
DSP_UART(3.3V)
DSP_SPI(1.8V)
EMIF16(1.8V)
GPIO[0:15](1.8V)
USB
TSIPx2
M24M01-HRMN6TP
EMU[2:17]
ENET PHY
Mini-USB
SRIOx4
NU Resistors
EMU[2:17]
MAC1
JTAG&EMU[0:1] MDIO
60-Pin EMU CONN.
Miscellaneous I/O conn.
PCIEx2
PCIEx2
I2C
BM_GPIO(0~15) /
PCIESSEN / User define
Power Control
D
SGMIIx1
MAC0
TSIPx2
DIP SW
MMC
MMC_LED1
MMC_LED2
SRIOx4
GPIO
IPMB-L
(MSP430)
EMIF
SPI
88E1111-B2
C
Hyper Link
DSP
TMS320C6678
GPIO[0:15]
DIP_SWITCH
CDCE62005
RJ45
DDR3
JTAG
+V3.3_MP
AMC_State
EMIF
HyperLink
50Gbps
DDR3-1333
w/ ECC
DSP_GPIO
NAND FLASH
(512Mb 64M X8)
NAND512R3A2D
ZA6E
to FPGA
NOR 128M-bit
N25Q128A21BSF40F #0
SPI
DSP_SPI#1
FPGA
iPass+HD
SPI Flash
DEBUG_LED
CLK#1
HyperLink CONN.
1. 1Gb X 16
2. 1Gb X 8
DDR3 -1333
128k-bit
AT25128B
MUX
JTAG
D
MUX
FPGA JTAG
DDR3(ECC)
1
from MMC
2
Document Number
Rev
A101-1
DSPM-8301E
Tuesday, March 08, 2011
Sheet
1
3
of
40
5
4
3
Power Sequence
S0
VCC3V3_MP
MMC
S1
Other
FT2232H XC3S200AN
VCC3V3_AUX
XC3S200AN
VCC1V8_AUX
XC3S200AN
VCC1V2
S3
T0
1ms
S4
Description
S2 plane power stable to S3 enable signal assertion
88E1111
S5
PMBUS &
UCD9222_ENA1
S6
CVDD
DSP TMS320C6678
S7
UCD9222_VID2 &
UCD9222_ENA2
S8
VCC1V0
DSP TMS320C6678
S9
T=5mS
T=5mS
T=5mS
VCC1V8_EN
S10
C
D
VCC12
S2
Time
1
VCC3V3_MP_AMC
D
Label
2
DSP TMS320C6678
S11
S12
DDR3
DSP TMS320C6678
C
T=5mS
DDR3 SDRAM
VCC1V5
VCC0V75_EN
DDR3
DSP TMS320C6678
S15
T=5mS
DDR3 Vref
VCC0V75
VCC2V5_EN
S16
VCC2V5
88E1111
S17
S18
T=5mS
VCC1V8
VCC1V5_EN
S13
S14
Power Sequence
VCC5_EN
XDS560V2 Mazzenine Board
VCC5
T=0mS
RESET#
including peripherals.
B
T=5mS
POR#
B
Reset Sequence
T=5mS
RESETFULL#
by DSP chip
RESETSTAT#
REFCLKP&N
by REFCLK2_PD#
CLOCK2_PLL_LOCK
CLK Sequence
DDRCLKP&N
by REFCLK3_PD#
DSP
TMS320C6678
VCC1V8
VCC1V0 Scaled/(CVDD)
VCC1V0 Fixed/(CVDD1)
VCC1V8/ (DVDD18)
1.5V/(DDR3_IO)
0.75V/(DDR3_Vref)
0ms<t<100us
0ms<t<100ms
VCC_1V0 scaled
VCC_1V0 Fixed
DSP
TMS320C6678
0.75V (DSP)
0ms<t<100us
1.5V/(DDR3_IO)
0.75V/(DDR3_Vref)
VCC_1V0 Fixed
1.5V/(DDR3_IO)
0.75V/(DDR3_Vref)
1.5V (DSP)
When power down
VCC1V8
VCC1V8
A
0ms<t<100us
0ms<t<100us
1.0V_fixed
VCC_1V0 scaled
0ms<t<100us
3.3V / 1.8V/ 1.2V
VDD
CLOCK3_PLL_LOCK
XILINX_XC3S200AN
A
VDD
Designed for TI by ADVANTECH
88E1111 (PHY)
Ther is no specific power-up nor
power-down sequence.
2.5V/ 1.2V
When power on
1.2V_AUX (VCCINT)
1.8V_AUX (VCC1V8_AUX)
3.3V_AUX (VCCAUX)
1.0V_scaled
XILINX_XC3S200AN
Ther is no specific power-up nor
power-down sequence.
88E1111
Title
Power Sequence
2.5V
1.2V
Size
C
Date:
5
4
3
2
Document Number
Rev
A101-1
DSPM-8301E
Tuesday, March 08, 2011
Sheet
1
4
of
40
5
4
3
2
1
POWER CONSUMPTION
D
D
C
C
B
B
A
A
Designed for TI by ADVANTECH
Title
POWER CONSUMPTION
Size
C
Date:
5
4
3
2
Document Number
Rev
A101-1
DSPM-8301E
Tuesday, March 08, 2011
Sheet
1
5
of
40
5
4
3
2
1
POWER DISTRIBUTION
AMC Gold Finger
D
3.3V_MP
165uA
VCC3V3_MP_AMC @ 165uA
D
Efficiency=80%
VCC12
3.04A
1.4A
PM_BUS
SmartReflex
CVDD @ 8A
UCD9222 +
UCD7242
VCC1V0 @ 5A
UCD9222_ENA [ 1..2]
XILINX_XC3S200AN
1.2V_AUX/ 0.125A (VCCINT)
3.3V_AUX/ 0.024A (VCCAUX)
DSP
TMS320C6678
DC Jack
VCC1V0 / 8A Scaled/(CVDD)
VCC1V0 / 5A Fixed/(CVDD1)
VCC1V8 / 0.33A (DVDD18)
1.5V / 0.85A (DDR3_IO)
0.75V/(DDR3_Vref)
Efficiency=90%
2.585
C
0.79A
C
VCC3V3_AUX @1.2A
TPS54620
DDR3
1.5V / 1.2A (DDR3_VDD)
0.75V / 0.25A (DDR3_Vref)
TPS73701DCQ
VCC1V2 @0.375A
88E1111 (PHY)
2.5V / 0.21A
1.2V / 0.25A
FT2232H(USB-JTAG)
TPS73701DCQ
3.3V / 0.21A
VCC1V8_AUX @0.3A
RS232
3.3V
TPS73701DCQ
VCC1V8_EN1
B
VCC1V8 @0.5A
B
FLASH
1.8V
TPS73701DCQ
VCC2V5_EN
VCC2V5 @0.21A
SPI NOR FLASH
1.8V
Efficiency=90%
0.33A
XDS560V2
Mazzenine Board
2.35A
TPS54620
5.0V / 1A
3.3V / 0.3A
VCC1V5 @2.1A
VCC1V5_EN
VCC0V75_EN
TPS51200
(3.3 Control)
VCC0V75 @0.25A
A
A
Efficiency=80%
0.52A
TPS54231
VCC_5V_EN
VCC5 @1A
Designed for TI by ADVANTECH
Title
POWER DISTRIBUTION
Size
C
Date:
5
4
3
2
Document Number
Rev
A101-1
DSPM-8301E
Tuesday, March 08, 2011
Sheet
1
6
of
40
5
4
3
2
1
NU
AC-coupling
capacitors
CLOCK DIAGRAM
100MHz
PCIe_CLKP/N (AMC)
AC-coupling
capacitors
100.00MHz
D
U0
CDCE62005
PRI_REF
PCIe_CLKP/N
DSP
TMS320C6678
D
X'TAL
312.50MHz
U2
312.50MHz
SRIO_SGMII_CLKP/N
U3
100.00MHz
PA_SS_CLKP/N
FT2232HL
12MHZ
MCM_CLKP/N
For HyperLink
U1
U4
U0
X'TAL
100.00MHz
88E1111
25MHZ
U1
X'TAL
CDCE62005
25MHZ
C
U2
66.667MHz
DDR_CLKP/N
U3
100MHz
CORE_CLKP/N
C
U4
XILINX
XC3S200AN
TSIP CLOCK
TSIP0_CLKA
TDM_CLKA +/TDM_CLKB +/-
+
TSIP0_CLKB
TSIP1_CLKA
TSIP1_CLKB
B
B
TSIP Frame Sync
100MHz
PCIe_CLKP/N (AMC)
TSIP0_FSA
TDM_CLKC +/TDM_CLKD +/-
+
TSIP0_FSB
-
TSIP1_FSA
TSIP1_FSB
AMC Gold Finger
A
A
Designed for TI by ADVANTECH
Title
CLOCK DIAGRAM
Size
C
Date:
5
4
3
2
Document Number
Rev
A101-1
DSPM-8301E
Tuesday, March 08, 2011
Sheet
1
7
of
40
5
4
3
TI MMC
TI_MSP430F5435IPN
MMC
Control
SPI_MMC_CS#
SPI_MMC_MISO
SPI_MMC_SCK
SPI_MMC_MOSI
PIN HEADER
+V3.3
+V3.3
MMC_DETECT#
MMC_RESETSTAT#
MMC_POR#
MMC_WARM_RST#
1
PM BUS
TMS320C6678 EVM (AMC)
XILINX_XC3S200AN-4FTG256C
FPGA_BLOCK
D
2
UCD9222
Control
PMBUS_ALT#
PMBUS_CTL
PMBUS_CLK
PMBUS_DAT
Alert
Control
Clk
Data
PGUCD9222
UCD9222_RST
UCD9222_PG1
UCD9222_ENA1
UCD9222_PG2
UCD9222_ENA2
PG
RESET
PG1
ENA1
PG2
ENA2
UCD9222_VID2
UCD9222_VID2
D
TI UCD9222
+V3.3
VCC2V5_PGOOD
VCC0V75_PGOOD
VCC3V3_AUX_PGOOD
VCC5_PGOOD
VCC1V5_PGOOD
Power Group
+V1.8
Power
Sequences
Control
TI_TPS54620RGY x3
TI_TPS73701DRBT x4
TI_TPS54231D x1
C
VCC2V5_EN
VCC0V75_EN
VCC1V8_EN1
VCC5_EN
VCC1V5_EN
PCIESSEN
User Switch
DSP
Default : TBD
Default : TBD
+V1.8
Boot & Device
configurations
GPIO[0:3] GPIO[8:11]
GPIO[4:7] GPIO[12:15]
BM_GPIO[0 : 15]
+V1.8 DSP_GPIO[0 : 15]
Test Connector 80-pin
(Female)
C
TIMI0
+V3.3
SPI_CLK_CS#[1..2]
CLOCK Group
SPI_CLK_CK[1..2]
TI_CDCE62005 #1
TI_CDCE62005 #2
SPI_CLK_MOSI[1..2]
GPIO[0:15]
TIMI[0]
+V1.8
CLOCK
Configurations
DSP_POR#
DSP_RESETFULL#
DSP_RESET#
DSP_PACLKSEL
DSP_LRRESETNMIEN#
DSP_CORESEL[0..3]#
DSP_NMI#
DSP_LRESET#
DSP_BOOTCOMPLETE
DSP_HOUT
DSP_SYSCLKOUT
DSP
RESET &
Interrupts
Control
SPI_CLK_MISO[1..2]
REFCLK1_PD#[1..2]
PLL_LOCK[1..2]
POR#
RESETFULL#
RESET#
PACLKSEL
LRRESETNMIEN#
CORESEL[0:3]
NMI#
LRESET#
BOOTCOMPLETE
HOUT
SYSCLKOUT
DSP
TMS320C6678
SPI_FPGA_CS1
DSP
SPI_FPGA_MISO
SPI_FPGA_SCK
SPI_FPGA_MOSI
SPI
MARVELL
B
PHY_INT#
PHY_RST#
PHY
Control
SPI ROM
ATMEL
AT25128B
B
+V3.3
88E1111-B2
+V1.8
DSP_TDM_FS[0:1]A/B
TDM CLK
DSP_TDM_CLK[0:1]A/B TDM_CLK[0:1] A/B
+V3.3
CS#
SPI_FPGA_CS#
MISO
SPI_FPGA_MISO
CLK
SPI_FPGA_SCK
MOSI
SPI_FPGA_MOSI
TDM_FS[0:1] A/B
DSP
LVDS
AMC_TDM_CLKA/B[p/n]
AMC_TDM_CLKC/D[p/n]
FPGA
Storage
AMC Edge Connector
(Golden Finger)
+V3.3
FPGA_JTAG_TCK
+V3.3
COLD RESET
WARM RESET
A
RESET
FPGA
JTAG
FULL RESET
TRGRSTZ
60-pin emulation
BSC_JTAG_TCK
BSC_JTAG_TDO
FPGA_JTAG_TDI
FPGA_JTAG_TDO
Buffer
BSC_JTAG_TDI
FPGA_JTAG_TMS
BSC_JTAG_TMS
FPGA_JTAG_RST#
BSC_JTAG_RST#
Designed for TI by ADVANTECH
Title
+V1.8
FPGA_BLOCK
(Female)
Size
B
Date:
5
A
4
3
2
Document Number
Rev
A101-1
DSPM-8301E
Tuesday, March 08, 2011
Sheet
1
8
of
40
5
4
3
2
1
Management Map
EMU_DETz
D
MDC
ENET PHY MDI/O
(88E1111) JTAG
MDC
MDI/O
+V2.5
Level Shifter
PCA9306DCUT
MDC
MDI/O
SEL
MDC
MDI/O
+V1.8
JTAG
+V1.8
EMU CONN.
JTAG
High-Speed
SWITCH
(TS3L301)
JTAG
EMU_DET PIN
+V1.8
D
JTAG
Level Shifter
+V1.8
JTAG
DSP
TMS320C6678
( 0xA0h )
I2C
I2C
UART
UART
+V1.8
DSP_RESETSTAT#
Level Shifter
SN74AVC4T245
EEPROM
(24AA1025)
(128KB)
+V3.3
USB-JTAG
FT2232HL
UART
+V3.3
Mini-USB
Console port
(Jumper Option)
RS232
MAX3221EAE
SPI (CS1z)
RESETZ#
POR#
RESETFULLZ#
C
USB
RS232
(Pin-Header 3x1)
80-pin Header
C
MSP430 (MMC)
NU Resistors
SPI1
JTAG
The NU resistors on these connections to the MSP430 are for debug use only
and will be used only with the shunts removed from pins 1 and 2 of CN7
Power Sequences Control
GPIO
PMBus
0-ohm
FPGA
(XILINX_XC3S200AN)
SmartReflex
(UCD9222)
JTAG
JTAG and
Boundary Scan
CN10
JTAG
CDCE62005
SPI2
TDO
TDI
DSP_RESETSTAT#
SPI3
TMS/TCK/TRSTn
CDCE62005
SPI
JTAG_EN# Buffer1
BS_EN#_1
Buffer2
B
B
WARM_RESET_AMC#
AMC_DETECT#
FP_POR_IN_AMC#
MMC_RESETSTAT#
MMC
(MSP430)
EEPROM
(AT25128B)
(128kb)
TDI
TDO
FPGA
XC3S200AN
JTAG
Buffer2
JTAG
IPMB-L
TDO
TDI
MMC_ENABLE_N
UCD9222
Level Shifter
PCA9306DCUT
PHY (88E1111)
JTAG
I2C
JTAG
TDI
NU Resistors
A
TDO
Buffer2
A
AMC Gold Finger
Designed for TI by ADVANTECH
MMC_PS_N0
Title
MMC_PS_N1
Management Map
Size
C
Date:
5
4
3
2
Document Number
Rev
A101-1
DSPM-8301E
Tuesday, March 08, 2011
Sheet
1
9
of
40
5
4
3
2
OVP: ~12.7V+0.6V = ~13.3V
FAN1
Front panel and ESD Strip
1
2
3
1
VCC12
DC_IN1
5%
R937
JACK_3H
10M
TRIP2
TRIP3
2
3
2
C525
1uF
16V
D
R931
100K
5%
R932
100K
5%
D
ESD1
R935
1K
5%
AMC-ESD-B
1
VCC12
2
1
R934
100K
5%
G
Q11
2N7002
300mA/60v
S
3
TRIP1
1
4
VCC12
C466
10uF
16V
5%
1
TRIP1
R930
1uF
25V
100K
5%
1
10M
D12
BZX84-C12
12.7V
3
R936
C516
1000pF
50V
Q12
MMBT3904LT1
200mA
C549
0.1uF
50V
R933
100K
5%
2
5%
D
C552
C550
0.1uF
50V
Q10
AO3401
4.2A/30V
3
G
NL/0
WB_3V_2.0mm
3
5%
S
R157
NL/0
2
D
R158
1
3
2
C526
1uF
16V
AMC1
IN
IN
(12)
(12)
AMC0_SGMII0_RX_DP
AMC0_SGMII0_RX_DN
(11)
MMC_GA1
AMC0_SGMII0_TX_DP
AMC0_SGMII0_TX_DN
OUT
OUT
AMC0_SGMII0_RX_DP
AMC0_SGMII0_RX_DN
MMC_GA1
IN
C
(11)
MMC_GA2
(11)
MMC_ENABLE_N
AMCC_P4_PCIe_TX1P
AMCC_P4_PCIe_TX1N
(12)
(12)
IN
IN
OUT
C301
C302
AMCC_P4_PCIe_RX1P
AMCC_P4_PCIe_RX1N
AMCC_P5_PCIe_TX2P
AMCC_P5_PCIe_TX2N
B
IN
IN
MMC_GA2
IN
OUT
OUT
C326
C369
AMCC_P5_PCIe_RX2P
AMCC_P5_PCIe_RX2N
OUT
OUT
(11)
SMB_SCL_IPMBL
OUT
BI
(30)
(30)
TDM_CLKA_P
TDM_CLKA_N
OUT
OUT
(30)
(30)
TDM_CLKB_P
TDM_CLKB_N
OUT
OUT
(17)
(17)
MMC_PS_N1
PCIE_REF_CLK_P
PCIE_REF_CLK_N
1
D3
ASD500V
100mA
2
AMCC_P4_PCIe_TX1P_C
(12)
AMCC_P4_PCIe_TX1N_C
(12)
AMCC_P4_PCIe_RX1P
AMCC_P4_PCIe_RX1N
0.1uF 16V
0.1uF 16V
(12)
(12)
SMB_SDA_IPMBL
MMC_ENABLE_N
0.1uF 16V
0.1uF 16V
AMCC_P5_PCIe_TX2P_C
(12)
AMCC_P5_PCIe_TX2N_C
(12)
AMCC_P5_PCIe_RX2P
AMCC_P5_PCIe_RX2N
SMB_SCL_IPMBL
SMB_SDA_IPMBL
(11)
TDM_CLKA_P
TDM_CLKA_N
TDM_CLKB_P
TDM_CLKB_N
OUT
OUT
MMC_PS_N0
VCC1V8
VCC3V3_AUX
R339
100K
1%
C355
0.1uF
16V
(16,29)
DSP_SCL
DSP_SDA
VCC1V8
TDM_CLKD_P
TDM_CLKD_N
TDM_CLKC_P
TDM_CLKC_N
R160
R161
NL/0
NL/0
OUT
OUT
TDM_CLKD_P
TDM_CLKD_N
(30)
(30)
OUT
OUT
TDM_CLKC_P
TDM_CLKC_N
(30)
(30)
VCC3V3_AUX
DSP_SDA_AMC
DSP_SCL_AMC
20
18
17
16
15
14
13
12
AMCC_P13_TDM1_TX2
AMCC_P13_TDM1_TX0
AMCC_P12_TDM0_TX3
AMCC_P12_TDM0_TX1
B1
B2
B3
B4
B5
B6
B7
B8
AMCC_P12_TDM0_TX2
AMCC_P12_TDM0_TX0
AMCC_P11_SRIO4_TXP
AMCC_P11_SRIO4_TXN
IN
IN
AMCC_P11_SRIO4_RXP
AMCC_P11_SRIO4_RXN
AMCC_P10_SRIO3_TXP
AMCC_P10_SRIO3_TXN
AMCC_P10_SRIO3_RXP
AMCC_P10_SRIO3_RXN
OUT
OUT
IN
IN
OUT
OUT
AMCC_P9_SRIO2_TXP
AMCC_P9_SRIO2_TXN
AMCC_P8_SRIO1_TXP
AMCC_P8_SRIO1_TXN
AMCC_P8_SRIO1_RXP
AMCC_P8_SRIO1_RXN
OUT
OUT
AMCC_P11_SRIO4_RXP
AMCC_P11_SRIO4_RXN
(12)
(12)
(12)
(12)
AMCC_P10_SRIO3_RXP
AMCC_P10_SRIO3_RXN
(12)
(12)
OUT
OUT
IN
IN
(12)
(12)
AMCC_P10_SRIO3_TXP
AMCC_P10_SRIO3_TXN
IN
IN
AMCC_P9_SRIO2_RXP
AMCC_P9_SRIO2_RXN
AMCC_P11_SRIO4_TXP
AMCC_P11_SRIO4_TXN
AMCC_P9_SRIO2_TXP
AMCC_P9_SRIO2_TXN
(12)
(12)
AMCC_P9_SRIO2_RXP
AMCC_P9_SRIO2_RXN
(12)
(12)
AMCC_P8_SRIO1_TXP
AMCC_P8_SRIO1_TXN
(12)
(12)
AMCC_P8_SRIO1_RXP
AMCC_P8_SRIO1_RXN
(12)
(12)
R180
10K
R964
10K
1
2
3
(16,29) 4
GND
VREF1
SCL1
SDA1
EN
VREF2
SCL2
SDA2
8
7
6
5
C411
0.1uF
16V
C
DSP_SCL_AMC
DSP_SDA_AMC
TI_PCA9306DCUT
R90
2K
1%
R175
2K
1%
VCC3V3_AUX
VCC1V8_AUX
C128
0.1uF
16V
R958
C160
0.1uF
16V
AMCC_P13_TDM1_TX3
AMCC_P13_TDM1_TX1
U245
DSP_SCL
DSP_SDA
IN
BI
4.7K
2
AMC0_SGMII0_TX_DP
AMC0_SGMII0_TX_DN
19
(12)
(12)
MMC_GA0
170
169
168
167
166
165
164
163
162
161
160
159
158
157
156
155
154
153
152
151
150
149
148
147
146
145
144
143
142
141
140
139
138
137
136
135
134
133
132
131
130
129
128
127
126
125
124
123
122
121
120
119
118
117
116
115
114
113
112
111
110
109
108
107
106
105
104
103
102
101
100
99
98
97
96
95
94
93
92
91
90
89
88
87
86
VCCA
IN
GND_56
TDI
TDO
TRST
TMS
TCK
GND_55
Tx20+
Tx20GND_54
Rx20+
Rx20GND_53
Tx19+
Tx19GND_52
Rx19+
Rx19GND_51
Tx18+
Tx18GND_50
Rx18+
Rx18GND_49
Tx17+
Tx17GND_48
Rx17+
Rx17GND_47
TCLKD+
TCLKDGND_46
TCLKC+
TCLKCGND_45
Tx15+
Tx15GND_44
Rx15+
Rx15GND_43
Tx14+
Tx14GND_42
Rx14+
Rx14GND_41
Tx13+
Tx13GND_40
Rx13+
Rx13GND_39
Tx12+
Tx12GND_38
Rx12+
Rx12GND_37
Tx11+
Tx11GND_36
Rx11+
Rx11GND_35
Tx10+
Tx10GND_34
Rx10+
Rx10GND_33
Tx9+
Tx9GND_32
Rx9+
Rx9GND_31
Tx8+
Tx8GND_30
Rx8+
Rx8GND_29
VCCB
MMC_GA0
Management Power
GND_1
PWR_12V_1
PS1
MP
GA0
RSRVD6
GND_2
RSRVD8
PWR_12V_2
GND_3
Tx0+
Tx0GND_4
Rx0+
Rx0GND_5
GA1
PWR_12V_3
GND_6
Tx1+
Tx1GND_7
Rx1+
Rx1GND_8
GA2
PWR_12V_4
GND_9
Tx2+
Tx2GND_10
Rx2+
Rx2GND_11
Tx3+
Tx3GND_12
Rx3+
Rx3GND_13
ENABLE
PWR_12V_5
GND_14
Tx4+
Tx4GND_15
Rx4+
Rx4GND_16
Tx5+
Tx5GND_17
Rx5+
Rx5GND_18
SCL_L
PWR_12V_6
GND_19
Tx6+
Tx6GND_20
Rx6+
Rx6GND_21
Tx7+
Tx7GND_22
Rx7+
Rx7GND_23
SDA_L
PWR_12V_7
GND_24
TCLKA+
TCLKAGND_25
TCLKB+
TCLKBGND_26
FCLKA+
FCLKAGND_27
PS0
PWR_12V_8
GND_28
GND
VCC3V3_MP_AMC
(11)
11
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
MMC_PS_N1
VCC1V8
TSIP1_TX3_R
TSIP1_TX1_R
OE
A1
A2
A3
A4
A5
A6
A7
A8
10
1
3
4
5
6
7
8
9
TSIP1_TX2_R
TSIP1_TX0_R
TSIP0_TX3_R
TSIP0_TX1_R
TSIP0_TX2_R
TSIP0_TX0_R
U13
TI_TXS0108EPWR
R124
R150
R151
R152
R122
R148
R149
R123
R119
R146
R147
R120
R105
R144
R145
R106
22
0
0
22
22
0
0
22
22
0
0
22
22
0
0
22
TSIP1_TX3
TSIP1_RX1
TSIP1_RX3
TSIP1_TX1
TSIP1_TX2
TSIP1_RX0
TSIP1_RX2
TSIP1_TX0
TSIP0_TX3
TSIP0_RX1
TSIP0_RX3
TSIP0_TX1
TSIP0_TX2
TSIP0_RX0
TSIP0_RX2
TSIP0_TX0
IN
OUT
OUT
IN
IN
OUT
OUT
IN
IN
OUT
OUT
IN
IN
OUT
OUT
IN
(15)
(15)
(15)
(15)
(15)
(15)
(15)
(15)
(15)
(15)
(15)
(15)
(15)
(15)
(15)
(15)
TSIP1_TX3
TSIP1_RX1
TSIP1_RX3
TSIP1_TX1
TSIP1_TX2
TSIP1_RX0
TSIP1_RX2
TSIP1_TX0
TSIP0_TX3
TSIP0_RX1
TSIP0_RX3
TSIP0_TX1
TSIP0_TX2
TSIP0_RX0
TSIP0_RX2
TSIP0_TX0
B
GF-AMC-B
A
A
Designed for TI by ADVANTECH
Title
AMC GF
Size
C
Date:
5
4
3
2
Document Number
Rev
A101-1
DSPM-8301E
Tuesday, March 08, 2011
Sheet
1
10
of
40
5
4
3
2
1
Power for MSP430
VCC3V3_MP
D
D10
2
RB751V40
1
200mA
VCC3V3_MP_AMC
D9
2
RB751V40
1
200mA
VCC3V3_AUX
D
C524
0.1uF
16V
VCC3V3_MP
MMC JTAG
MMC_TEST
MMC_TDO
MMC_TDI
MMC_TMS
MMC_TCK
C598
2200pF
50V
MMC1
C
1
Y1
2 32.768KHz_12.5pF
4
3
C8
22pF
50V
VCC3V3_MP
MMC_XTAL2
C6
0.1uF
16V
B1
120_100MHz
0.5A
MMC_XTAL1
MMC_XTAL2
VCC3V3_MP
(10)
(10)
(10)
MMC_GA0
MMC_GA1
MMC_GA2
OUT
OUT
OUT
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
P6.4/A4
P6.5/A5
P6.6/A6
P6.7/A7
P7.4/A12
P7.5/A13
P7.6/A14
P7.7/A15
P5.0/A8/VREF+/VeREF+
P5.1/A9/VREF-/VeREFAVCC
AVSS
P7.0/XIN
P7.1/XOUT
DVSS1
DVCC1
P1.0/TA0CLK/ACLK
P1.1/TA0.0
P1.2/TA0.1
P1.3/TA0.2
TI_MSP430F5435IPN
P1.4/TA0.3
P1.5/TA0.4
P1.6/SMCLK
P1.7
P2.0/TA1CLK/MCLK
P2.1/TA1.0
P2.2/TA1.1
P2.3/TA1.2
P2.4/RTCCLK
DVSS3
DVCC3
P2.5
P2.6/ACLK
P2.7/ADC12CLK/DMAE0
P3.0/UCB0STE/UCA0CLK
P3.1/UCB0SIMO/UCB0SDA
P3.2/UCB0SOMI/UCB0SCL
P3.3/UCB0CLK/UCA0STE
P3.4/UCA0TXD/UCA0SIMO
P3.5/UCA0RXD/UCA0SOMI
MMC_XTAL1
22pF
50V
(RED LED)
VCC3V3_MP
R3
330
R4
330
1
D1
R
2
MMC_LED1
KP-1608EC
B
2
MMC_LED2
19-215SUBC/S280/TR8
1
D2
C2
0.1uF
16V
C3
0.1uF
16V
C4
0.1uF
16V
MMC_RST_N
PH_7x2V_2.54mm
C5
C1
0.1uF
16V
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
VCC3V3_MP
TAP_MMC1
1
3
5
7
9
11
13
P6.3/A3
P6.2/A2
P6.1/A1
P6.0/A0
RST/NMI/SBWTDIO
PJ.3/TCK
PJ.2/TMS
PJ.1/TDI/TCLK
PJ.0/TDO
TEST/SBWTCLK
P5.3/XT2OUT
P5.2/XT2IN
DVSS4
DVCC4
P8.6/TA1.1
P8.5/TA1.0
P8.4/TA0.4
P8.3/TA0.3
P8.2/TA0.2
P8.1/TA0.1
2
4
6
8
10
12
14
VCC3V3_MP
MMC_TEST
MMC_TDO
MMC_TDI
MMC_TMS
MMC_TCK
MMC_RST_N
(BLUE LED)
C
P8.0/TA0.0
P7.3/TA1.2
P7.2/TB0OUTH/SVMOUT
P5.7/UCA1RXD/UCA1SOMI
P5.6/UCA1TXD/UCA1SIMO
P5.5/UCB1CLK/UCA1STE
P5.4/UCB1SOMI/UCB1SCL
P4.7/TB0CLK/SMCLK
P4.6/TB0.6
DVCC2
DVSS2
VCORE
P4.5/TB0.5
P4.4/TB0.4
P4.3/TB0.3
P4.2/TB0.2
P4.1/TB0.1
P4.0/TB0.0
P3.7/UCB1SIMO/UCB1SDA
P3.6/UCB1STE/UCA1CLK
60
59
58
57
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
R960
R961
R962
NL/0
NL/0
NL/0
C7
0.47uF
10V
OUT
IN
IN
(31)
(31)
(31)
MMC_SPI_MISO
MMC_SPI_MOSI
MMC_SPI_STE
VCC3V3_MP
MMC_SCK
R17
NL/0 MMC_HANDLE
R963
NL/0
IN
(31)
MMC_SPI_SCK
The NU resistors on these connections to the MSP430 are for debug use only
and will be used only with the shunts removed from pins 1 and 2 of CN7
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
B
R7
R6
MMC_GAPU
MMC_LED1
SPI I/F is for Advantech FPGA debugging.
MMC_MISO
MMC_MOSI
MMC_STE
TP7
NL/0
NL/0
IN
BI
MMC_LED2
OUT
IN
UART_FT_RX
UART_FT_TX
SMB_SCL_IPMBL
SMB_SDA_IPMBL
(10)
(10)
(16,26)
(16,26)
B
VCC3V3_MP
SMB_SCL_IPMBL
R2
33K
SMB_SDA_IPMBL
R1
33K
TP8
TP9
OUT
MMC_DETECT#
(30)
IN
IN
OUT
OUT
MMC_RESETSTAT#
MMC_BOOTCOMPLETE
MMC_POR_IN_AMC#
MMC_WR_AMC#
(30)
(30)
(30)
(30)
VCC3V3_MP
VCC3V3_MP
VCC3V3_MP
R10
8.2K
5%
SW2-P1
C
D
A
H2
H1
R12
100
1%
MMC_HANDLE
C10
0.01uF
16V
R11
NL/10K
1%
R14
3.3K
5%
R15
3.3K
5%
MMC_GA0
3
MMC_RST_N
R13
3.3K
5%
Q1
2N7002
300mA/60v
D
A
G
1
MMC_ENABLE_N
S
MMC_GA1
MMC_GA2
A
B
SW2
NL/MPU-101-127
MMC_GAPU
IN
MMC_ENABLE_N
(10)
2
R9
8.2K
5%
R16
10K
1%
R18
NL/0
R19
NL/0
Designed for TI by ADVANTECH
R20
NL/0
Title
MMC
Size
C
Date:
5
4
3
2
Document Number
Rev
A101-1
DSPM-8301E
Tuesday, March 08, 2011
Sheet
1
11
of
40
5
4
3
2
1
SRIO
Caution!
DSP1P
(10)
(10)
AMCC_P8_SRIO1_RXP
AMCC_P8_SRIO1_RXN
IN
IN
(10)
(10)
AMCC_P9_SRIO2_RXP
AMCC_P9_SRIO2_RXN
IN
IN
(10)
(10)
AMCC_P10_SRIO3_RXP
AMCC_P10_SRIO3_RXN
IN
IN
(10)
(10)
AMCC_P11_SRIO4_RXP
AMCC_P11_SRIO4_RXN
IN
IN
D
AMCC_P8_SRIO1_RXP
AMCC_P8_SRIO1_RXN
C164
C167
0.1uF 16V
0.1uF 16V
AMCC_P8_SRIO1_RXP_C
AMCC_P8_SRIO1_RXN_C
AJ12
AJ11
AMCC_P9_SRIO2_RXP
AMCC_P9_SRIO2_RXN
C165
C166
0.1uF 16V
0.1uF 16V
AMCC_P9_SRIO2_RXP_C
AMCC_P9_SRIO2_RXN_C
AH11
AH10
AMCC_P10_SRIO3_RXP
AMCC_P10_SRIO3_RXN
C168
C169
0.1uF 16V
0.1uF 16V
AMCC_P10_SRIO3_RXP_C
AMCC_P10_SRIO3_RXN_C
AH13
AH14
AMCC_P11_SRIO4_RXP
AMCC_P11_SRIO4_RXN
C170
C171
0.1uF 16V
0.1uF 16V
AMCC_P11_SRIO4_RXP_C
AMCC_P11_SRIO4_RXN_C
AJ14
AJ15
RIORXP0
RIORXN0
SERIAL RAPIDIO
SERDES
RIOTXP0
RIOTXN0
RIORXP1
RIORXN1
RIOTXP1
RIOTXN1
RIORXP2
RIORXN2
RIOTXP2
RIOTXN2
RIORXP3
RIORXN3
RIOTXP3
RIOTXN3
pinout_rev0_3_2_customer
AF11
AF10
AMCC_P8_SRIO1_TXP
AMCC_P8_SRIO1_TXN
AG12
AG11
AMCC_P9_SRIO2_TXP
AMCC_P9_SRIO2_TXN
AG14
AG15
AMCC_P10_SRIO3_TXP
AMCC_P10_SRIO3_TXN
AF13
AF14
AMCC_P11_SRIO4_TXP
AMCC_P11_SRIO4_TXN
OUT
OUT
AMCC_P8_SRIO1_TXP
AMCC_P8_SRIO1_TXN
(10)
(10)
OUT
OUT
AMCC_P9_SRIO2_TXP
AMCC_P9_SRIO2_TXN
(10)
(10)
OUT
OUT
AMCC_P10_SRIO3_TXP
AMCC_P10_SRIO3_TXN
(10)
(10)
OUT
OUT
AMCC_P11_SRIO4_TXP
AMCC_P11_SRIO4_TXN
(10)
(10)
"Place ALL SERDES DC-blocking
caps on top layer adjacent to the
DSP’s RX pins so that there are
no additional vias"
D
TI_TMS320C6678
SGMII
VCC1V8
VCC3V3_AUX
C327
0.1uF
16V
DSP1O
(10)
(10)
AMC0_SGMII0_RX_DP
AMC0_SGMII0_RX_DN
IN
IN
(27)
(27)
DSP_SGMII_RXP
DSP_SGMII_RXN
IN
IN
AMC0_SGMII0_RX_DP
AMC0_SGMII0_RX_DN
C172
C173
0.1uF 16V
0.1uF 16V
AMC0_SGMII0_RX_DP_C
AMC0_SGMII0_RX_DN_C
AJ17
AJ18
DSP_SGMII_RXP
DSP_SGMII_RXN
C465
C468
0.1uF 16V
0.1uF 16V
DSP_SGMII_RXP_C
DSP_SGMII_RXN_C
AH16
AH17
SGMII0RXP
SGMII0RXN
SGMII SERDES
SGMII1RXP
SGMII1RXN
SGMII0TXP
SGMII0TXN
SGMII1TXP
SGMII1TXN
AG17 AMC0_SGMII0_TX_DP
AG18 AMC0_SGMII0_TX_DN
AF16 DSP_SGMII_TXP
AF17 DSP_SGMII_TXN
OUT
OUT
AMC0_SGMII0_TX_DP
AMC0_SGMII0_TX_DN
(10)
(10)
OUT
OUT
DSP_SGMII_TXP
DSP_SGMII_TXN
(27)
(27)
R316
100K
1%
U244
DSP_MDC
DSP_MDIO
MDIO
pinout_rev0_3_2_customer
MDIO
MDCLK
G26 DSP_MDIO
H26 DSP_MDC
VCC1V8
TI_TMS320C6678
R85
10K
R957
10K
1
2
3
4
GND
VREF1
SCL1
SDA1
EN
VREF2
SCL2
SDA2
8
7
6
5
C401
0.1uF
16V
DSP_MDC_1
DSP_MDIO_1
DSP_MDC_1
DSP_MDIO_1
OUT
BI
TI_PCA9306DCUT
R82
2K
1%
R83
2K
1%
(27)
(27)
VCC2V5
C
C
PCIE
DSP1Q
AMCC_P4_PCIe_RX1P
AMCC_P4_PCIe_RX1N
IN
IN
AMCC_P4_PCIe_RX1P (10)
AMCC_P4_PCIe_RX1N (10)
C305
C306
0.1uF 16V
0.1uF 16V
AMCC_P4_PCIe_RX1P_C
AMCC_P4_PCIe_RX1N_C
AH8
AH7
AMCC_P5_PCIe_RX2P
AMCC_P5_PCIe_RX2N
IN
IN
AMCC_P5_PCIe_RX2P (10)
AMCC_P5_PCIe_RX2N (10)
C307
C308
0.1uF 16V
0.1uF 16V
AMCC_P5_PCIe_RX2P_C
AMCC_P5_PCIe_RX2N_C
AJ8
AJ9
PCIERXP0
PCIERXN0
PCIETXP0
PCIETXN0
PCIe SERDES
PCIERXP1
PCIERXN1
PCIETXP1
PCIETXN1
AF7 AMCC_P4_PCIe_TX1P
AF8 AMCC_P4_PCIe_TX1N
AG8 AMCC_P5_PCIe_TX2P
AG9 AMCC_P5_PCIe_TX2N
OUT
OUT
AMCC_P4_PCIe_TX1P
AMCC_P4_PCIe_TX1N
(10)
(10)
OUT
OUT
AMCC_P5_PCIe_TX2P
AMCC_P5_PCIe_TX2N
(10)
(10)
pinout_rev0_3_2_customer
TI_TMS320C6678
B
B
HyperLink
DSP1R
(29)
(29)
HyperLink_RXP0
HyperLink_RXN0
IN
IN
(29)
(29)
HyperLink_RXP1
HyperLink_RXN1
IN
IN
(29)
(29)
HyperLink_RXP2
HyperLink_RXN2
IN
IN
(29)
(29)
HyperLink_RXP3
HyperLink_RXN3
IN
IN
HyperLink_RXP0
HyperLink_RXN0
C505
C470
0.1uF 16V
0.1uF 16V
HyperLink_RXP0_C
HyperLink_RXN0_C
T2
U2
HyperLink_RXP1
HyperLink_RXN1
C512
C511
0.1uF 16V
0.1uF 16V
HyperLink_RXP1_C
HyperLink_RXN1_C
R1
T1
HyperLink_RXP2
HyperLink_RXN2
C14
C12
0.1uF 16V
0.1uF 16V
HyperLink_RXP2_C
HyperLink_RXN2_C
N1
M1
HyperLink_RXP3
HyperLink_RXN3
C20
C19
0.1uF 16V
0.1uF 16V
HyperLink_RXP3_C
HyperLink_RXN3_C
N2
P2
MCMRXP0
MCMRXN0
MCMTXP0
MCMTXN0
VUSR
SERDES
MCMRXP1
MCMRXN1
MCMTXP1
MCMTXN1
MCMRXP2
MCMRXN2
MCMTXP2
MCMTXN2
MCMRXP3
MCMRXN3
MCMTXP3
MCMTXN3
MCMREFCLKOUTP
MCMREFCLKOUTN
N5
M5
U4
T4
T5
R5
P4
N4
Y1
W1
OUT
OUT
HyperLink_TXP0
HyperLink_TXN0
(29)
(29)
OUT
OUT
HyperLink_TXP1
HyperLink_TXN1
(29)
(29)
OUT
OUT
HyperLink_TXP2
HyperLink_TXN2
(29)
(29)
OUT
OUT
HyperLink_TXP3
HyperLink_TXN3
(29)
(29)
HyperLink_REFCLKOUTP
HyperLink_REFCLKOUTN
“The HyperLink routes must
have a maximum of 2 vias and
no via stubs – top layer routing
recommended”
TP5
TP6
A
A
(29)
(29)
(29)
(29)
HyperLink_RXFLCLK
HyperLink_RXFLDAT
HyperLink_RXPMCLK
HyperLink_RXPMDAT
W3
W4
Y3
Y4
OUT
OUT
IN
IN
MCMRXFLCLK
MCMRXFLDAT
MCMRXPMCLK
MCMRXPMDAT
VUSR
SMBUS
MCMTXFLCLK
MCMTXFLDAT
MCMTXPMCLK
MCMTXPMDAT
AA1
AA3
AA2
AA4
IN
IN
OUT
OUT
HyperLink_TXFLCLK
HyperLink_TXFLDAT
HyperLink_TXPMCLK
HyperLink_TXPMDAT
(29)
(29)
(29)
(29)
pinout_rev0_3_2_customer
TI_TMS320C6678
Designed for TI by ADVANTECH
Title
DSP_SERDES_PORTS
Size
C
Date:
5
4
3
2
Document Number
Rev
A101-1
DSPM-8301E
Tuesday, March 08, 2011
Sheet
1
12
of
40
5
4
3
DSP1K
D
(24,25)
(24,25)
DSP0_DDR3_ECKP_0
DSP0_DDR3_ECKN_0
OUT
OUT
(24,25)
DSP0_DDR3_ECKE_0
OUT
(24,25)
DSP0_DDR3_ECS_0#
OUT
(24,25)
(24,25)
(24,25)
DSP0_DDR3_ECAS#
DSP0_DDR3_ERAS#
DSP0_DDR3_EWE#
(24,25)
(24,25)
(24,25)
C
OUT
OUT
OUT
DSP0_DDR3_EBA_0
DSP0_DDR3_EBA_1
DSP0_DDR3_EBA_2
(24)
(24)
(24)
(24)
(24)
(24)
(24)
(24)
(25)
(24)
(24)
(24)
(24)
(24)
(24)
(24)
(24)
(24)
(24)
(24)
(24)
(24)
(24)
(24)
(24)
(25)
(25)
OUT
OUT
OUT
DSP0_DDR3_EDM_0
DSP0_DDR3_EDM_1
DSP0_DDR3_EDM_2
DSP0_DDR3_EDM_3
DSP0_DDR3_EDM_4
DSP0_DDR3_EDM_5
DSP0_DDR3_EDM_6
DSP0_DDR3_EDM_7
DSP0_DDR3_EDM_8
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
DSP0_DDR3_EDQSP_0
DSP0_DDR3_EDQSN_0
DSP0_DDR3_EDQSP_1
DSP0_DDR3_EDQSN_1
DSP0_DDR3_EDQSP_2
DSP0_DDR3_EDQSN_2
DSP0_DDR3_EDQSP_3
DSP0_DDR3_EDQSN_3
DSP0_DDR3_EDQSP_4
DSP0_DDR3_EDQSN_4
DSP0_DDR3_EDQSP_5
DSP0_DDR3_EDQSN_5
DSP0_DDR3_EDQSP_6
DSP0_DDR3_EDQSN_6
DSP0_DDR3_EDQSP_7
DSP0_DDR3_EDQSN_7
DSP0_DDR3_EDQSP_8
DSP0_DDR3_EDQSN_8
(25) DSP0_DDR3_ECC[0..7]
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
BI
(24,25)DSP0_DDR3_EMRESETN
OUT
(24,25)
OUT
DSP0_DDR3_EODT_0
DSP0_DDR3_ECKP_0
DSP0_DDR3_ECKN_0
A12
B12
A16
B16
DSP0_DDR3_ECKE_0
D11
E18
C11
C12
DSP0_DDR3_ECS_0#
DSP0_DDR3_ECAS#
DSP0_DDR3_ERAS#
DSP0_DDR3_EWE#
D12
C10
E12
DSP0_DDR3_EBA_0
DSP0_DDR3_EBA_1
DSP0_DDR3_EBA_2
A13
B13
C13
DSP0_DDR3_EDM_0
DSP0_DDR3_EDM_1
DSP0_DDR3_EDM_2
DSP0_DDR3_EDM_3
DSP0_DDR3_EDM_4
DSP0_DDR3_EDM_5
DSP0_DDR3_EDM_6
DSP0_DDR3_EDM_7
DSP0_DDR3_EDM_8
E29
C27
A25
A22
A10
A8
B5
B2
A20
DSP0_DDR3_EDQSP_0
DSP0_DDR3_EDQSN_0
DSP0_DDR3_EDQSP_1
DSP0_DDR3_EDQSN_1
DSP0_DDR3_EDQSP_2
DSP0_DDR3_EDQSN_2
DSP0_DDR3_EDQSP_3
DSP0_DDR3_EDQSN_3
DSP0_DDR3_EDQSP_4
DSP0_DDR3_EDQSN_4
DSP0_DDR3_EDQSP_5
DSP0_DDR3_EDQSN_5
DSP0_DDR3_EDQSP_6
DSP0_DDR3_EDQSN_6
DSP0_DDR3_EDQSP_7
DSP0_DDR3_EDQSN_7
DSP0_DDR3_EDQSP_8
DSP0_DDR3_EDQSN_8
C28
C29
A27
B27
A24
B24
A21
B21
A9
B9
B6
A6
B3
A3
D1
C1
A19
B19
DSP0_DDR3_ECC0
DSP0_DDR3_ECC1
DSP0_DDR3_ECC2
DSP0_DDR3_ECC3
DSP0_DDR3_ECC4
DSP0_DDR3_ECC5
DSP0_DDR3_ECC6
DSP0_DDR3_ECC7
E19
C20
D19
B20
C19
C18
B18
A18
DSP0_DDR3_EMRESETN
E11
DSP0_DDR3_EODT_0
D13
E13
U1_DDRSLRATE0
U1_DDRSLRATE1
G27
H27
DSP_VREFSSTL
E14
G22
C114
0.1uF
16V
DDRCKE0
DDRCKE1
DDRCE0z
DDRCE1z
DDR3
CONTROLLER
DDRCASz
DDRRASz
DDRWEz
DDRBA0
DDRBA1
DDRBA2
DDRDQM0
DDRDQM1
DDRDQM2
DDRDQM3
DDRDQM4
DDRDQM5
DDRDQM6
DDRDQM7
DDRDQM8
DDRDQS0P
DDRDQS0N
DDRDQS1P
DDRDQS1N
DDRDQS2P
DDRDQS2N
DDRDQS3P
DDRDQS3N
DDRDQS4P
DDRDQS4N
DDRDQS5P
DDRDQS5N
DDRDQS6P
DDRDQS6N
DDRDQS7P
DDRDQS7N
DDRDQS8P
DDRDQS8N
DDRCB00
DDRCB01
DDRCB02
DDRCB03
DDRCB04
DDRCB05
DDRCB06
DDRCB07
DDRRESETz
DDRODT0
DDRODT1
DDRSLRATE0
DDRSLRATE1
VREFSSTL
PTV15
R58
45.3
1%
DDR3 Drive Stength:
70-ohm: 6mA
60-ohm: 7mA
50-ohm: 8mA
45-ohm: 9mA
40-ohm: 10mA
36-ohm: 11mA
B
DDRCLKOUTP0
DDRCLKOUTN0
DDRCLKOUTP1
DDRCLKOUTN1
pinout_rev0_3_2_customer
DSP0_DDR3_EA0
DSP0_DDR3_EA1
DSP0_DDR3_EA2
DSP0_DDR3_EA3
DSP0_DDR3_EA4
DSP0_DDR3_EA5
DSP0_DDR3_EA6
DSP0_DDR3_EA7
DSP0_DDR3_EA8
DSP0_DDR3_EA9
DSP0_DDR3_EA10
DSP0_DDR3_EA11
DSP0_DDR3_EA12
DSP0_DDR3_EA13
DSP0_DDR3_EA14
DSP0_DDR3_EA15
E28
D29
E27
D28
D27
B28
E26
F25
F24
E24
E25
D25
D26
C26
B26
A26
F23
F22
D24
E23
A23
B23
C24
E22
D21
F20
E21
F21
D22
C21
B22
C22
E10
D10
B10
D9
E9
C9
B8
E8
A7
D7
E7
C7
B7
E6
D6
C6
C5
A5
B4
A4
D4
E4
C4
C3
F4
D2
E2
C2
F2
F3
E1
F1
DSP0_DDR3_EDQ0
DSP0_DDR3_EDQ1
DSP0_DDR3_EDQ2
DSP0_DDR3_EDQ3
DSP0_DDR3_EDQ4
DSP0_DDR3_EDQ5
DSP0_DDR3_EDQ6
DSP0_DDR3_EDQ7
DSP0_DDR3_EDQ8
DSP0_DDR3_EDQ9
DSP0_DDR3_EDQ10
DSP0_DDR3_EDQ11
DSP0_DDR3_EDQ12
DSP0_DDR3_EDQ13
DSP0_DDR3_EDQ14
DSP0_DDR3_EDQ15
DSP0_DDR3_EDQ16
DSP0_DDR3_EDQ17
DSP0_DDR3_EDQ18
DSP0_DDR3_EDQ19
DSP0_DDR3_EDQ20
DSP0_DDR3_EDQ21
DSP0_DDR3_EDQ22
DSP0_DDR3_EDQ23
DSP0_DDR3_EDQ24
DSP0_DDR3_EDQ25
DSP0_DDR3_EDQ26
DSP0_DDR3_EDQ27
DSP0_DDR3_EDQ28
DSP0_DDR3_EDQ29
DSP0_DDR3_EDQ30
DSP0_DDR3_EDQ31
DSP0_DDR3_EDQ32
DSP0_DDR3_EDQ33
DSP0_DDR3_EDQ34
DSP0_DDR3_EDQ35
DSP0_DDR3_EDQ36
DSP0_DDR3_EDQ37
DSP0_DDR3_EDQ38
DSP0_DDR3_EDQ39
DSP0_DDR3_EDQ40
DSP0_DDR3_EDQ41
DSP0_DDR3_EDQ42
DSP0_DDR3_EDQ43
DSP0_DDR3_EDQ44
DSP0_DDR3_EDQ45
DSP0_DDR3_EDQ46
DSP0_DDR3_EDQ47
DSP0_DDR3_EDQ48
DSP0_DDR3_EDQ49
DSP0_DDR3_EDQ50
DSP0_DDR3_EDQ51
DSP0_DDR3_EDQ52
DSP0_DDR3_EDQ53
DSP0_DDR3_EDQ54
DSP0_DDR3_EDQ55
DSP0_DDR3_EDQ56
DSP0_DDR3_EDQ57
DSP0_DDR3_EDQ58
DSP0_DDR3_EDQ59
DSP0_DDR3_EDQ60
DSP0_DDR3_EDQ61
DSP0_DDR3_EDQ62
DSP0_DDR3_EDQ63
VCC1V5
R77
1K
1%
DSP_VREFSSTL
C59
0.1uF
16V
DDRD00
DDRD01
DDRD02
DDRD03
DDRD04
DDRD05
DDRD06
DDRD07
DDRD08
DDRD09
DDRD10
DDRD11
DDRD12
DDRD13
DDRD14
DDRD15
DDRD16
DDRD17
DDRD18
DDRD19
DDRD20
DDRD21
DDRD22
DDRD23
DDRD24
DDRD25
DDRD26
DDRD27
DDRD28
DDRD29
DDRD30
DDRD31
DDRD32
DDRD33
DDRD34
DDRD35
DDRD36
DDRD37
DDRD38
DDRD39
DDRD40
DDRD41
DDRD42
DDRD43
DDRD44
DDRD45
DDRD46
DDRD47
DDRD48
DDRD49
DDRD50
DDRD51
DDRD52
DDRD53
DDRD54
DDRD55
DDRD56
DDRD57
DDRD58
DDRD59
DDRD60
DDRD61
DDRD62
DDRD63
A14
B14
F14
F13
A15
C15
B15
D15
F15
E15
E16
D16
E17
C16
D17
C17
OUT
DSP0_DDR3_EA[0..15]
D
BI
DSP0_DDR3_EDQ[0..7]
BI
DSP0_DDR3_EDQ[8..15]
BI
DSP0_DDR3_EDQ[16..23]
BI
DSP0_DDR3_EDQ[24..31]
BI
DSP0_DDR3_EDQ[32..39]
DSP_VREFSSTL
(24,25)
(24)
(24)
(24)
(24)
DSP0_DDR3_EDQ[40..47]
(24)
BI
DSP0_DDR3_EDQ[48..55]
(24)
BI
DSP0_DDR3_EDQ[56..63]
(24)
R37
39.2
1%
DSP0_DDR3_ECKN_0
R38
39.2
1%
C31
0.1uF
16V
VCC1V5
VCC0V75
DSP0_DDR3_EA0
R41
39.2
1%
C33
0.01uF 16V
DSP0_DDR3_EA1
R42
39.2
1%
C34
0.1uF 16V
DSP0_DDR3_EA2
R43
39.2
1%
C35
0.01uF 16V
DSP0_DDR3_EA3
R44
39.2
1%
C36
0.1uF 16V
DSP0_DDR3_EA4
R45
39.2
1%
C37
0.01uF 16V
DSP0_DDR3_EA5
R46
39.2
1%
C38
0.1uF 16V
DSP0_DDR3_EA6
R47
39.2
1%
DSP0_DDR3_EA7
R48
39.2
1%
DSP0_DDR3_EA8
R49
39.2
1%
DSP0_DDR3_EA9
R50
39.2
1%
DSP0_DDR3_EA10
R51
39.2
1%
DSP0_DDR3_EA11
R52
39.2
1%
DSP0_DDR3_EA12
R53
39.2
1%
DSP0_DDR3_EA13
R54
39.2
1%
DSP0_DDR3_EA14
R55
39.2
1%
DSP0_DDR3_EA15
R86
39.2
1%
C
Place these resistors at the
end of the trace.
VCC0V75
DSP0_DDR3_EBA_0
R56
39.2
1%
C39
0.01uF 16V
DSP0_DDR3_EBA_1
R57
39.2
1%
C40
0.1uF 16V
DSP0_DDR3_EBA_2
R59
39.2
1%
C41
0.01uF 16V
DSP0_DDR3_EODT_0
R60
39.2
1%
C42
0.1uF 16V
DSP0_DDR3_EWE#
R61
39.2
1%
C43
0.01uF 16V
DSP0_DDR3_ERAS#
R62
39.2
1%
C44
0.1uF 16V
DSP0_DDR3_ECAS#
R63
39.2
1%
DSP0_DDR3_ECKE_0
R64
39.2
1%
DSP0_DDR3_ECS_0#
R65
39.2
1%
DSP0_DDR3_EMRESETN
R66
39.2
1%
B
VCC1V5
R70
10K
1%
U1_DDRSLRATE0
R78
1K
1%
DSP0_DDR3_ECKP_0
(24)
BI
R69
NL/10K
1%
OUT
1
(24,25)
TI_TMS320C6678
VCC1V5
C60
0.1uF
16V
DDRA00
DDRA01
DDRA02
DDRA03
DDRA04
DDRA05
DDRA06
DDRA07
DDRA08
DDRA09
DDRA10
DDRA11
DDRA12
DDRA13
DDRA14
DDRA15
2
U1_DDRSLRATE1
R71
10K
1%
R72
NL/10K
1%
A
A
Trace need 20 mil.
DDR3 Slew-Rate Setting (DDRSLRATE[1:0]):
00
10
01
11
Fastest
Fast
Slow
Slowest
Designed for TI by ADVANTECH
Title
DSP_DDR3
Size
C
Date:
5
4
3
2
Document Number
Rev
A101-1
DSPM-8301E
Tuesday, March 08, 2011
Sheet
1
13
of
40
5
4
3
2
1
D
D
NAND1
DSP1N
DSP_EMIFD0
DSP_EMIFD1
DSP_EMIFD2
DSP_EMIFD3
DSP_EMIFD4
DSP_EMIFD5
DSP_EMIFD6
DSP_EMIFD7
DSP_EMIFD8
DSP_EMIFD9
DSP_EMIFD10
DSP_EMIFD11
DSP_EMIFD12
DSP_EMIFD13
DSP_EMIFD14
DSP_EMIFD15
C
(29)
DSP_EMIFWAIT1
VCC1V8
DSP_EMIFD0
DSP_EMIFD1
DSP_EMIFD2
DSP_EMIFD3
DSP_EMIFD4
DSP_EMIFD5
DSP_EMIFD6
DSP_EMIFD7
DSP_EMIFD8
DSP_EMIFD9
DSP_EMIFD10
DSP_EMIFD11
DSP_EMIFD12
DSP_EMIFD13
DSP_EMIFD14
DSP_EMIFD15
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
DSP_EMIFWAIT0
DSP_EMIFWAIT1
IN
R183
Y27
(29)
AB29
(29)
AA29
(29)
Y26
(29)
AA27
(29)
AB27
(29)
AA26
(29)
AA25
(29)
Y25
(29)
AB25
(29)
AA24
(29)
Y24
(29)
AB23
(29)
AB24
(29)
AB26
(29)
AC25
(29)
T29
T28
EMIFD00
EMIFD01
EMIFD02
EMIFD03
EMIFD04
EMIFD05
EMIFD06
EMIFD07
EMIFD08
EMIFD09
EMIFD10
EMIFD11
EMIFD12
EMIFD13
EMIFD14
EMIFD15
EMIFWAIT0
EMIFWAIT1
EMIFA00
EMIFA01
EMIFA02
EMIFA03
EMIFA04
EMIFA05
EMIFA06
EMIFA07
EMIFA08
EMIFA09
EMIFA10
EMIFA11
EMIFA12
EMIFA13
EMIFA14
EMIFA15
EMIFA16
EMIFA17
EMIFA18
EMIFA19
EMIFA20
EMIFA21
EMIFA22
EMIFA23
T27
T24
U29
T25
U27
U28
U25
U24
V28
V29
V27
V26
V25
V24
W28
W27
W29
W26
W25
W24
W23
Y29
Y28
U23
DSP_EMIFA00
DSP_EMIFA01
DSP_EMIFA02
DSP_EMIFA03
DSP_EMIFA04
DSP_EMIFA05
DSP_EMIFA06
DSP_EMIFA07
DSP_EMIFA08
DSP_EMIFA09
DSP_EMIFA10
DSP_EMIFA11
DSP_EMIFA12
DSP_EMIFA13
DSP_EMIFA14
DSP_EMIFA15
DSP_EMIFA16
DSP_EMIFA17
DSP_EMIFA18
DSP_EMIFA19
DSP_EMIFA20
DSP_EMIFA21
DSP_EMIFA22
DSP_EMIFA23
P25
R27
R28
R25
R236
R248
R249
R24
R23
DSP_EMIFBE0Z
DSP_EMIFBE1Z
P24
R26
DSP_EMIFWEZ
DSP_EMIFOEZ
P26
DSP_EMIFRNW
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
DSP_EMIFA00
DSP_EMIFA01
DSP_EMIFA02
DSP_EMIFA03
DSP_EMIFA04
DSP_EMIFA05
DSP_EMIFA06
DSP_EMIFA07
DSP_EMIFA08
DSP_EMIFA09
DSP_EMIFA10
DSP_EMIFA11
DSP_EMIFA12
DSP_EMIFA13
DSP_EMIFA14
DSP_EMIFA15
DSP_EMIFA16
DSP_EMIFA17
DSP_EMIFA18
DSP_EMIFA19
DSP_EMIFA20
DSP_EMIFA21
DSP_EMIFA22
DSP_EMIFA23
(29)
(29)
(29)
(29)
(29)
(29)
(29)
(29)
(29)
(29)
(29)
(29)
(29)
(29)
(29)
(29)
(29)
(29)
(29)
(29)
(29)
(29)
(29)
(29)
(30)
EMIFCE0z
EMIFCE1z
EMIFCE2z
EMIFCE3z
EMIFBE0z
EMIFBE1z
EMIF16
pinout_rev0_3_2_customer
EMIFWEz
EMIFOEz
EMIFRnW
DSP_EMIFCE0Z
DSP_EMIFCE1Z
DSP_EMIFCE2Z
OUT
OUT
DSP_EMIFCE1Z
DSP_EMIFCE2Z
OUT
OUT
DSP_EMIFBE0Z
DSP_EMIFBE1Z
(29)
(29)
OUT
OUT
DSP_EMIFWEZ
DSP_EMIFOEZ
(29)
(29)
OUT
DSP_EMIFRNW
(29)
H4
J4
K4
K5
K6
J7
K7
J8
DSP_EMIFWEZ
C7
C3
DSP_EMIFOEZ
DSP_EMIFWAIT0
D4
C8
DSP_EMIFCE0Z
DSP_EMIFA12
C6
D5
DSP_EMIFA11
C4
IN
G3
G8
VCC1V8
4.7K
22
22
22
NAND_WP#
DSP_EMIFD0
DSP_EMIFD1
DSP_EMIFD2
DSP_EMIFD3
DSP_EMIFD4
DSP_EMIFD5
DSP_EMIFD6
DSP_EMIFD7
R134
4.7K
DSP_EMIFWAIT0
R135
4.7K
NAND_WP#
IO0
IO1
IO2
IO3
IO4
IO5
IO6
IO7
WE
WP
RE
R/B
CE
CLE
ALE
DNU1
DNU2
(29)
(29)
F7
K8
K3
C5
TI_TMS320C6678
VSS1
VSS2
VSS3
VSS4
NC1
NC2
NC3
NC4
NC5
NC6
NC7
NC8
NC9
NC10
NC11
NC12
NC13
NC14
NC15
NC16
NC17
NC18
NC19
NC20
NC21
NC22
NC23
NC24
NC25
NC26
NC27
NC28
NC29
NC30
NC31
NC32
NC33
NC34
NC35
NC36
NC37
NC38
VCC1
VCC2
VCC3
VCC4
NUMONYX_NAND512R3A2DZA6E
A1
A10
A2
A9
B1
B10
B9
D6
D7
D8
E3
E4
E5
E6
E7
E8
F3
F4
F5
F6
F8
G5
G6
G7
H3
H5
H6
H7
J3
J5
L1
L10
L2
L9
M1
M10
M2
M9
G4
D3
H8
J6
C
VCC1V8
C519
0.1uF
16V
C159
0.1uF
16V
C158
10uF
6.3V
B
B
A
A
Designed for TI by ADVANTECH
Title
DSP_EMIF
Size
C
Date:
5
4
3
2
Document Number
Rev
A101-1
DSPM-8301E
Tuesday, March 08, 2011
Sheet
1
14
of
40
5
4
3
2
1
JTAG & EMU
DSP_TRST#_R
XDS560V2 power connector
R905
4.7K
VCC5
(30)
VCC1V8
C555
8.2pF
50V
DSP_TMS
R893
4.7K
DSP_TDI
R895
4.7K
DSP_TCK
R896
4.7K
DSP_TDO
R897
4.7K
DSP_TRST#
R900
NL/4.75K
XDS560_IL
560V2_PWR1
1
2
3
4
5
6
7
8
IN
VCC3V3_AUX
C537
10uF
6.3V
C536
0.1uF
16V
C553
10uF
16V
(26)
EXT_EMU_DET0
R904
(26)
DSP1I
VCC1V8
P28
P29
P27
N29
R29
R226
R232
R233
N23
NL/0
N24
NL/0
1K 1% AH28
R234
R235
NL/0
0
AH19
AF19
TRSTz
TMS
TDI
TCK
TDO
JTAG/EMU/DFT
RSV03
RSV02
RSV01
RSV08
RSV09
C
pinout_rev0_3_2_customer
EMU00
EMU01
EMU02
EMU03
EMU04
EMU05
EMU06
EMU07
EMU08
EMU09
EMU10
EMU11
EMU12
EMU13
EMU14
EMU15
EMU16
EMU17
EMU18
AC29
AC28
AC27
AC26
AD29
AD28
AD27
AE29
AE28
AF29
AE27
AF28
AG29
AD26
AG28
AG27
AJ27
AF27
AH27
DSP_EMU_00
DSP_EMU_01
DSP_EMU_02
DSP_EMU_03
DSP_EMU_04
DSP_EMU_05
DSP_EMU_06
DSP_EMU_07
DSP_EMU_08
DSP_EMU_09
DSP_EMU_10
DSP_EMU_11
DSP_EMU_12
DSP_EMU_13
DSP_EMU_14
DSP_EMU_15
DSP_EMU_16
DSP_EMU_17
DSP_EMU_18
D
NL/10K
1%
BI
BI
DSP_EMU_00
DSP_EMU_01
(26)
EMU_TMS
(26)
(26)
EMU_TDI
OUT
OUT
(26)
EMU_TDO
IN
VCC1V8
(26)
EMU_TCK
OUT
EMU_EMU_00
OUT
TRGRSTZ
BI
R290
EMU_TMS
DSP_EMU_17
EMU_TDI
DSP_EMU_14
DSP_EMU_12
EMU_TDO
DSP_EMU_09
DSP_EMU_07
DSP_EMU_05
EMU_TCK
DSP_EMU_02
EMU_EMU_00
4.7K
R295
R279
R294
R280
R276
R293
R658
R271
R270
R268
R292
R266
R287(26)
TRGRSTZ
10
10
10
10
10
10
100 1%
10
10
10
10
10
10
DSP_TMS_R
DSP_EMU_17_R
DSP_TDI_R
DSP_EMU_14_R
DSP_EMU_12_R
DSP_TDO_R
DSP_TVD
DSP_EMU_09_R
DSP_EMU_07_R
DSP_EMU_05_R
EMU_TCK_R
DSP_EMU_02_R
DSP_EMU_00_R
B1
D1
A1
C1
B1
B2
B3
B4
B5
B6
B7
B8
B9
B10
B11
B12
B13
B14
B15
C1
C2
C3
C4
C5
C6
C7
C8
C9
C10
C11
C12
C13
C14
C15
DSP_EMU_18_R
DSP_TRST#_R
DSP_EMU_16_R
DSP_EMU_15_R
DSP_EMU_13_R
DSP_EMU_11_R
DSP_TCK_R
DSP_EMU_10_R
DSP_EMU_08_R
DSP_EMU_06_R
DSP_EMU_04_R
DSP_EMU_03_R
DSP_EMU_01_R
R282
R288
R278
R277
R275
R274
R291
R281
R272
R273
R269
R267
R286
DSP_EMU_18
EMU_TRST#
DSP_EMU_16
DSP_EMU_15
DSP_EMU_13
DSP_EMU_11
EMU_TCK_R
DSP_EMU_10
DSP_EMU_08
DSP_EMU_06
DSP_EMU_04
DSP_EMU_03
EMU_EMU_01
10
10
10
10
10
10
10
10
10
10
10
10
10
OUT
BI
EMU_TRST#
(26)
EMU_EMU_01
(26)
D1
D2
D3
D4
D5
D6
D7
D8
D9
D10
D11
D12
D13
D14
D15
PTH
H1
DSP_TRST#
DSP_TMS
DSP_TDI
DSP_TCK
DSP_TDO
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10
A11
A12
A13
A14
A15
1%
VCC1V8
IN
IN
IN
IN
OUT
1%
EXT_EMU_DET0
OUT
PH_4x2V_2.54mm
(30)
DSP_TRST#
DSP_TMS
DSP_TDI
DSP_TCK
DSP_TDO
4.75K
PTH
VCC3V3_AUX
R67
49.9
1%
(26)
(26)
(26)
(26)
(26)
R903
VCC3V3_AUX
H2
C551
0.1uF
16V
D
EMU_EMU_00
R901
4.75K
EMU_EMU_01
R902
4.75K
VCC1V8
EMU1
BB_30x2V_S1.27mm
C
TI_TMS320C6678
TSIP0, 1
DSP1T
B
(10)
(10)
(10)
(10)
TSIP0_RX0
TSIP0_RX1
TSIP0_RX2
TSIP0_RX3
(30)
(30)
DSP_TSIP0_FSA0
DSP_TSIP0_FSB0
AH26
AJ25
AD23
AD24
AC23
AH25
AC24
AE25
IN
IN
IN
IN
IN
IN
(30)
(30)
DSP_TSIP0_CLKA0
DSP_TSIP0_CLKB0
IN
IN
(10)
(10)
(10)
(10)
TSIP1_RX0
TSIP1_RX1
TSIP1_RX2
TSIP1_RX3
IN
IN
IN
IN
(30)
(30)
DSP_TSIP1_FSA1
DSP_TSIP1_FSB1
IN
IN
(30)
(30)
DSP_TSIP1_CLKA1
DSP_TSIP1_CLKB1
IN
IN
DSP_TSIP0_FSA0
DSP_TSIP0_FSB0
AJ26
AG26
DSP_TSIP0_CLKA0
DSP_TSIP0_CLKB0
AF25
AG25
AE22
AD21
AC21
AJ21
AH22
AJ20
AH21
AG21
DSP_TSIP1_FSA1
DSP_TSIP1_FSB1
AG23
AJ22
DSP_TSIP1_CLKA1
DSP_TSIP1_CLKB1
AJ23
AH23
TR00
TR01
TR02
TR03
TR04
TR05
TR06
TR07
TSIP0
TX00
TX01
TX02
TX03
TX04
TX05
TX06
TX07
AE24
AD25
AJ24
AG24
AH24
AF24
AE23
AF23
OUT
OUT
OUT
OUT
TSIP0_TX0
TSIP0_TX1
TSIP0_TX2
TSIP0_TX3
(10)
(10)
(10)
(10)
OUT
OUT
OUT
OUT
TSIP1_TX0
TSIP1_TX1
TSIP1_TX2
TSIP1_TX3
(10)
(10)
(10)
(10)
B
FSA0
FSB0
CLKA0
CLKB0
TR10
TR11
TR12
TR13
TR14
TR15
TR16
TR17
TSIP1
TX10
TX11
TX12
TX13
TX14
TX15
TX16
TX17
AF21
AD22
AC22
AE21
AG20
AE20
AH20
AF20
FSA1
FSB1
CLKA1
CLKB1
pinout_rev0_3_2_customer
TI_TMS320C6678
A
A
Designed for TI by ADVANTECH
Title
DSP_JTAG_EMU_TSIP
Size
C
Date:
5
4
3
2
Document Number
Rev
A101-1
DSPM-8301E
Tuesday, March 08, 2011
Sheet
1
15
of
40
5
4
3
2
I2C, TIMER0,1, SPI, UART
1
16M SPI NOR Flash
1M-bit I2C EEPROM
VCC1V8
VCC1V8
C303
0.1uF
16V
(10,29)
(29,31)
(29)
(29)
(29) D
DSP_SCL
DSP_SDA
DSP_TIMI0
DSP_TIMI1
DSP_TIMO0
DSP_TIMO1
IN
IN
OUT
OUT
R341
R347
DSP1M
AD3
SCL
AC4 (10,29)
SDA
L24
L26 TIMI0/PCIESSEN
L25 TIMI1
M26 TIMO0
TIMO1
DSP_SCL
DSP_SDA
OUT
BI
10
10
R185
4.7K
I2C
TIMER0
TIMER1
SPI UART
SPISCS0
SPISCS1
SPICLK
SPIDIN
SPIDOUT
UARTRTS
UARTCTS
UARTTXD
UARTRXD
R186
4.7K
pinout_rev0_3_2_customer
AG1 R337
AG2
AE1 R340
AD2
AB1 R363
10
AB2 R377
AB3 R378
AC1
AD1
10
10
10
10
DSP_SSPCS0
DSP_SSPCS1
DSP_SSPCK
DSP_SSPMISO
DSP_SSPMOSI
VCC1V8
R427
NL/0
SPI1
OUT
DSP_SSPCS1
(29,30)
IN
OUT
DSP_SSPMISO
DSP_SSPMOSI
(29,30)
(29,30)
VCC1V8
DSP_UARTRTS_V1P8
DSP_UARTCTS_V1P8
DSP_UARTTXD_V1P8
DSP_UARTRXD_V1P8
(30)
NOR_WP#
NOR_HD#
4.7K
DSP_SSPCS0
NOR_SSPCK
DSP_SSPMOSI
DSP_SSPMISO
R398
10
NOR_WP#
R163
4.7K
R162
2
1
7
16
15
8
9
10
IN
VCC
HOLD/DQ3
S
SCK
DQ0
DQ1
W/Vpp/DQ2
VSS
DU/NC8
DU/NC7
DU/NC6
DU/NC5
DU/NC4
DU/NC3
DU/NC2
DU/NC1
14
13
12
11
6
5
4
3
R428
NL/0
R429
NL/0
EEPROM1
STMicro_M24M01-HRMN6TP
1
2
3
4
R164
NL/0
R165
0
A0
A1
A2
VSS
VCC
WP
SCL
SDA
C304
0.1uF
16V
8
7
6
5
EEPROM_WP
DSP_SCL
DSP_SDA
R168
R169
4.7K
4.7K
D
R167
0
R179
4.7K
5%
NUMONYX_N25Q128A21BSF40F
IN
(30)
EEPROM_WP
VCC1V8
TI_TMS320C6678
DSP_SSPMISO
R166
4.7K
VCC1V8
B21
2200pF
700mA
1
GPIO
3
VCC1V8
U255
R369
33
R368
33
1
2
3
4
5
6
7
DSP1L
DSP_GPIO_00
DSP_GPIO_01
DSP_GPIO_02
DSP_GPIO_03
DSP_GPIO_04
DSP_GPIO_05
DSP_GPIO_06
DSP_GPIO_07
DSP_GPIO_08
DSP_GPIO_09
DSP_GPIO_10
DSP_GPIO_11
DSP_GPIO_12
DSP_GPIO_13
DSP_GPIO_14
DSP_GPIO_15
C
R938
R939
R940
R941
R942
R943
R944
R945
R946
R947
R948
R949
R950
R951
R952
R953
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
10
10
10
10
10
10
10
10
10
10
10
10
10
10
10
10
DSP_GPIO_R_00
(29,31)
DSP_GPIO_R_01
(29,31)
DSP_GPIO_R_02
(29,31)
DSP_GPIO_R_03
(29,31)
DSP_GPIO_R_04
(29,31)
DSP_GPIO_R_05
(29,31)
DSP_GPIO_R_06
(29,31)
DSP_GPIO_R_07
(29,31)
DSP_GPIO_R_08
(29,31)
DSP_GPIO_R_09
(29,31)
DSP_GPIO_R_10
(29,31)
DSP_GPIO_R_11
(29,31)
DSP_GPIO_R_12
(29,31)
DSP_GPIO_R_13
(29,31)
DSP_GPIO_R_14
(29,31)
DSP_GPIO_R_15
(29,31)
H25
J28
J29
J26
J25
J27
J24
K27
K28
K26
K29
L28
L29
K25
K24
L27
GPIO00/LENDIAN
GPIO01/BOOTMODE00
GPIO02/BOOTMODE01
GPIO03/BOOTMODE02
GPIO04/BOOTMODE03
GPIO05/BOOTMODE04
GPIO06/BOOTMODE05
GPIO07/BOOTMODE06
GPIO08/BOOTMODE07
GPIO09/BOOTMODE08
GPIO10/BOOTMODE09
GPIO11/BOOTMODE10
GPIO12/BOOTMODE11
GPIO13/BOOTMODE12
GPIO14/PCIESSMODE0
GPIO15/PCIESSMODE1
(29)
GPIO
PH_SSPCK
OUT
1OE
1A
1Y
2OE
2A
2Y
GND
VCC
4OE
4A
4Y
3OE
3A
3Y
14
13
12
11
10
9
8
2
DSP_SSPCK
NOR_SSPCK
R202
DSP_SSPCK
33
OUT
(30)
FPGA_SSPCK
TI_SN74ALVC125PWR
C
pinout_rev0_3_2_customer
VCC1V8
VCC3V3_AUX
TI_TMS320C6678
C368
0.1uF
16V
C367
0.1uF
16V
U24
TI_SN74AVC4T245PWR
16
15
14
13
12
11
10
9
DSP_UARTRTS_V1P8
DSP_UARTTXD_V1P8
DSP_UARTCTS_V1P8
DSP_UARTRXD_V1P8
VCCB
1OE
2OE
1B1
1B2
2B1
2B2
GND2
1
2
3
4
5
6
7
8
VCCA
1DIR
2DIR
1A1
1A2
2A1
2A2
GND1
DSP_UARTRTS
DSP_UARTTXD
DSP_UARTCTS
DSP_UARTRXD
OUT
OUT
IN
IN
(29)
(29)
(29)
(29)
DSP_UARTRTS
DSP_UARTTXD
DSP_UARTCTS
DSP_UARTRXD
Reset Control
COM_SEL1(2-4)
DSP1J
B
(30)
(30)
(30)
DSP_PORZ
DSP_RESETFULLZ
DSP_RESETZ
DSP_PORZ
DSP_RESETFULLZ
DSP_RESETZ
IN
IN
IN
(30)
DSP_PACLKSEL
IN
(30)
(30)
(30)
(30)
(30)
(30)
(30)
DSP_LRESETNMIENZ
DSP_CORESEL0
DSP_CORESEL1
DSP_CORESEL2
DSP_CORESEL3
DSP_NMIZ
DSP_LRESETZ
IN
IN
IN
IN
IN
IN
IN
AC20
N25
M29
DSP_PACLKSEL
AE4
DSP_LRESETNMIENZ
DSP_CORESEL0
DSP_CORESEL1
DSP_CORESEL2
DSP_CORESEL3
DSP_NMIZ
DSP_LRESETZ
M27
AF2
AD4
AE6
AE5
M25
N26
PORz
RESETFULLz
RESETz
N27
AE2
AD20
RESETSTATz
BOOTCOMPLETE
HOUT
DSP_RESETSTAT#
DSP_BOOTCOMPLETE
DSP_HOUT
OUT
OUT
OUT
DSP_RESETSTAT#
DSP_BOOTCOMPLETE
DSP_HOUT
(30)
(30)
(30)
B
MINIJUMPER_2_2.54mm
PACLKSEL
LRESETNMIENz
CORESEL0
CORESEL1
CORESEL2
CORESEL3
NMIz
LRESETz
COM_SEL1(1-3)
MINIJUMPER_2_2.54mm
DSP_UARTRXD
RESET/BOOT
UART_MAX_TX
COM_SEL1
(11,26)
UART_FT_TX
OUT
pinout_rev0_3_2_customer
1
3
5
UART_FT_TX
DSP_UARTTXD
UART_MAX_TX
TI_TMS320C6678
R187
R188
R200
IN
(11,26)
UART_FT_RX
R384
4.7K
JP-UART(1-3) & (2-4) : UART over USB Connector (Default)
JP-UART(3-5) & (4-6) : UART over 3-Pin Header J5
4.7K
4.7K
4.7K
Reserved
VCC3V3_AUX
COM1
3
2
1
DSP1S
A
UART_FT_RX
DSP_UARTRXD
UART_MAX_RX
PH_3x2V_S2.54mm
R203
4.7K
DSP_PORZ
DSP_RESETFULLZ
DSP_RESETZ
2
4
6
R342
R343
NL/0
NL/0
5%
5%
K22
J22
R344
R345
NL/0
NL/0
5%
5%
Y5
W5
RSV10
RSV11
RSV12
RSV13
R329
4.7K
R330
4.7K
C522
1uF
6.3V
C472
0.1uF
16V
RS232_RX
RS232_TX
PH_3x1V_2.54mm
pinout_rev0_3_2_customer
A
U249
RESERVED PINS
C154
C155
0.1uF 16V
0.1uF 16V
C156
0.1uF 16V
C157
0.1uF 16V
RS232_RX
TI_TMS320C6678
1
2
3
4
5
6
7
8
EN
C1+
V+
C1C2+
C2VRIN
FORCEOFF
VCC
GND
DOUT
FORCEON
DIN
INVALID
ROUT
16
15
14
13
12
11
10
9
RS232_TX
Designed for TI by ADVANTECH
UART_MAX_TX
UART_MAX_RX
TI_MAX3221ECPWR
Title
DSP_MISC
Size
C
Date:
5
4
3
2
Document Number
Rev
A101-1
DSPM-8301E
Tuesday, March 08, 2011
Sheet
1
16
of
40
5
4
3
2
1
DSP CLOCK
D
D
TP12
DSP1H
(23)
CORECLKP
CORECLKN
(23)
100.00MHz
(23)
(23)
DDRCLKP
DDRCLKN
IN
IN
(22)
PASSCLKP
PASSCLKN
IN
IN
66.667MHz
(22)
100.00MHz
(22)
SRIOSGMIICLKP
SRIOSGMIICLKN
(22)
312.5MHz
(22)
PCIECLKP
PCIECLKN
(22)
100.00MHz
(22)
(22)
HyperLink_CLKP
HyperLink_CLKN
312.5MHz
C494
C493
IN
IN
IN
IN
IN
IN
IN
IN
0.1uF 16V
0.1uF 16V
CORECLKP_C
CORECLKN_C
AG3
AG4
G29
H29
DDRCLKP
DDRCLKN
C496
C495
0.1uF 16V
0.1uF 16V
DDRCLKP_C
DDRCLKN_C
PASSCLKP
PASSCLKN
C498
C497
0.1uF 16V
0.1uF 16V
PASSCLKP_C
PASSCLKN_C
AJ5
AJ4
SRIOSGMIICLKP
SRIOSGMIICLKN
C500
C499
0.1uF 16V
0.1uF 16V
SRIOSGMIICLKP_C
SRIOSGMIICLKN_C
AG6
AJ6
PCIECLKP
PCIECLKN
C502
C501
0.1uF 16V
0.1uF 16V
PCIECLKP_C
PCIECLKN_C
AG5
AH5
HyperLink_CLKP
HyperLink_CLKN
C504
C503
0.1uF 16V
0.1uF 16V
HyperLink_CLKP_C
HyperLink_CLKN_C
W2
Y2
CORECLKP
CORECLKN
SYSCLKOUT
DDRCLKP
DDRCLKN
RSV20
RSV21
RSV22
PASSCLKP
PASSCLKN
RSV04
RSV05
SRIOSGMIICLKP
SRIOSGMIICLKN
RSV06
RSV07
PCIECLKP
PCIECLKN
RSV24
RSV25
MCMCLKP
MCMCLKN
RSV14
RSV15
RSV16
RSV17
PLL REFERENCE CLOCKS
AE3
DSP_SYSCLKOUT
AF3
G25
AF1
R360
R361
R362
NL/0
NL/0
NL/0
5%
5%
5%
AH2
AJ3
R358
R359
NL/0
NL/0
5%
5%
H28
G28
R356
R357
NL/0
NL/0
5%
5%
AH4
AH3
R354
R355
NL/0
NL/0
5%
5%
W6
AE12
AC9
AD19
R349
R346
R351
R352
NL/0
NL/0
NL/0
NL/0
5%
5%
5%
5%
OUT
(30)
DSP_SYSCLKOUT
pinout_rev0_3_2_customer
TI_TMS320C6678
(10)
(10)
PCIE_REF_CLK_P
PCIE_REF_CLK_N
IN
IN
C528
C527
NL/0.1uF
NL/0.1uF
16V
16V
PCIECLKP_C
PCIECLKN_C
C
C
“All DC-blocking capacitors to be placed near DSP to keep connecting routes short and minimize vias”
Smart Reflex
VCC1V8
R322
10K
1%
B
VCC1V8
R323
10K
1%
R320
10K
1%
C174
0.1uF
R321
10K
1%
VCNTL0
VCNTL1
VCNTL2
VCNTL3
SMART REFLEX
CONTROL
VCL
VD
M24
M23
DSP_VCL
DSP_VD
DSP_VIDA
DSP_VIDB
DSP_VIDC
DSP_VIDS
pinout_rev0_3_2_customer
VCCB
1OE
2OE
1B1
1B2
2B1
2B2
GND2
VCCA
1DIR
2DIR
1A1
1A2
2A1
2A2
GND1
VCC3V3_AUX
C175
0.1uF
U19
TI_SN74AVC4T245PWR
16
15
14
13
12
11
10
9
DSP1G
L23
K23
J23
H23
DSP_VIDA
DSP_VIDB
DSP_VIDC
DSP_VIDS
VCC3V3_AUX
1
2
3
4
5
6
7
8
R326
10K
1%
R327
10K
1%
R324
10K
1%
R325
10K
1%
B
UCD9222_VIDA
UCD9222_VIDB
UCD9222_VIDC
UCD9222_VIDS
OUT
OUT
OUT
OUT
(33)
(33)
(33)
(33)
UCD9222_VIDA
UCD9222_VIDB
UCD9222_VIDC
UCD9222_VIDS
TI_TMS320C6678
VCC1V8
IN
C521
0.1uF
16V
DSP_VCL
DSP_VD
VCC1V8
1
2
3
4
GND
VREF1
SCL1
SDA1
EN
VREF2
SCL2
SDA2
(30)
PCA9306_EN
R328
100K
U248
TI_PCA9306DCUT
8
7
6
5
C520
0.1uF
16V
DSP_VCL_1
DSP_VD_1
OUT
BI
R130
10K
R128
10K
R131
10K
R129
10K
DSP_VCL_1
DSP_VD_1
(30)
(30)
VCC3V3_AUX
A
A
Designed for TI by ADVANTECH
Title
DSP_CLOCK_Smart Reflex
Size
C
Date:
5
4
3
2
Document Number
Rev
A101-1
DSPM-8301E
Tuesday, March 08, 2011
Sheet
1
17
of
40
5
4
3
2
1
1.8V
VCC1V8
VCC1V8
DSP1D
AB7
N28
P23
T23
U26
V23
Y7
Y23
AB5
H24
AB19
D
R364
R365
NL/0
NL/0
DVDD18_1
DVDD18_2
DVDD18_3
DVDD18_4
DVDD18_5
DVDD18_6
DVDD18_7
DVDD18_8
DVDD18_9
DVDD18_10
DVDD18_11
AA21
AA20
1.8V I/O SUPPLY
AB21
AB28
AC3
AF26
AG22
AH1
AH29
AJ2
AJ28
AA6
AF5
D
VCC1V8
Place near to DSP
C176
100uF
6.3V
RESERVED PINS
RSV0A
RSV0B
H22
AC6
AD5
DVDD18_12
DVDD18_13
DVDD18_14
DVDD18_15
DVDD18_16
DVDD18_17
DVDD18_18
DVDD18_19
DVDD18_20
DVDD18_21
DVDD18_22
AVDDA1
AVDDA2
AVDDA3
C177
10uF
6.3V
C178
10uF
6.3V
C179
4.7uF
6.3V
1.8V PLL SUPPLY
pinout_rev0_3_2_customer
VCC1V8
TI_TMS320C6678
Place near to DSP pins
VCC1V8
C194
0.1uF
16V
B8
1
C198
0.01uF
16V
C199
560pF
50V
2
C197
0.1uF
16V
C184
0.1uF
16V
C185
0.1uF
16V
C183
0.01uF
16V
C182
0.01uF
16V
C195
0.01uF
16V
C180
1000pF
50V
C181
1000pF
50V
C191
560pF
50V
C192
560pF
50V
C193
560pF
50V
C196
1000pF
50V
3
C200
100uF
6.3V
2200pF
700mA
C201
4.7uF
6.3V
VCC1V8
Place near to DSP pins
B31
C
1
C203
0.01uF
16V
C186
560pF
50V
C204
560pF
50V
2
C202
0.1uF
16V
C
3
C187
560pF
50V
C188
560pF
50V
C189
560pF
50V
C190
560pF
50V
2200pF
700mA
B32
C205
0.1uF
16V
C206
0.01uF
16V
C207
560pF
50V
3
2
1
2200pF
700mA
1.5V
B
B
VCC1V5
VCC1V5
Place near to DSP
VCC1V5
VCC1V5
C556
100uF
6.3V
C557
100uF
6.3V
C558
10uF
6.3V
C559
10uF
6.3V
C226
4.7uF
6.3V
C227
4.7uF
6.3V
C216
0.1uF
16V
C217
0.1uF
16V
C225
0.01uF
16V
C564
0.01uF
16V
C565
0.01uF
16V
C213
560pF
50V
C214
560pF
50V
C215
560pF
50V
C218
0.1uF
16V
C219
0.1uF
16V
C560
0.1uF
16V
C561
0.1uF
16V
C562
0.1uF
16V
C563
0.1uF
16V
DSP1C
A2
A11
A17
A28
B1
B29
C14
C25
D5
D8
D20
D23
E3
F5
F7
F9
F11
DVDD15_1
DVDD15_2
DVDD15_3
DVDD15_4
DVDD15_5
DVDD15_6
DVDD15_7
DVDD15_8
DVDD15_9
DVDD15_10
DVDD15_11
DVDD15_12
DVDD15_13
DVDD15_14
DVDD15_15
DVDD15_16
DVDD15_17
1.5V DDR3
I/O SUPPLY
DVDD15_18
DVDD15_19
DVDD15_20
DVDD15_21
DVDD15_22
DVDD15_23
DVDD15_24
DVDD15_25
DVDD15_26
DVDD15_27
DVDD15_28
DVDD15_29
DVDD15_30
DVDD15_31
F17
F19
F26
F28
G2
G4
G8
G10
G12
G14
G16
G18
G20
G23
VCC1V5
Place near to DSP pins
C220
0.01uF
16V
C221
0.01uF
16V
C222
0.01uF
16V
C223
0.01uF
16V
C224
0.01uF
16V
pinout_rev0_3_2_customer
TI_TMS320C6678
VCC1V5
Place near to DSP pins
A
C208
560pF
50V
C209
560pF
50V
C210
560pF
50V
C211
560pF
50V
C212
560pF
50V
A
Designed for TI by ADVANTECH
Title
DSP_POWERA
Size
C
Date:
5
4
3
2
Document Number
Rev
A101-1
DSPM-8301E
Tuesday, March 08, 2011
Sheet
1
18
of
40
5
4
0.9V - 1.1V (Smart Reflex)
3
CVDD
1
CVDD
Place near to DSP
C566
100uF
6.3V
D
2
C567
100uF
6.3V
C568
100uF
6.3V
C569
100uF
6.3V
C264
47uF
6.3V
C265
47uF
6.3V
C266
47uF
6.3V
C570
10uF
6.3V
C571
10uF
6.3V
D
CVDD
CVDD
DSP1A
H7
H9
H11
H13
H15
H17
H19
H21
J10
J12
J16
J18
J20
K11
K17
K19
K21
L10
L12
L16
L18
M11
M13
M15
M17
M19
N8
N10
N12
N14
N16
N18
P9
P11
P13
P15
P17
P19
P21
R8
R10
C
CVDD_1
CVDD_2
CVDD_3
CVDD_4
CVDD_5
CVDD_6
CVDD_7
CVDD_8
CVDD_9
CVDD_10
CVDD_11
CVDD_12
CVDD_13
CVDD_14
CVDD_15
CVDD_16
CVDD_17
CVDD_18
CVDD_19
CVDD_20
CVDD_21
CVDD_22
CVDD_23
CVDD_24
CVDD_25
CVDD_26
CVDD_27
CVDD_28
CVDD_29
CVDD_30
CVDD_31
CVDD_32
CVDD_33
CVDD_34
CVDD_35
CVDD_36
CVDD_37
CVDD_38
CVDD_39
CVDD_40
CVDD_41
0.9V - 1.1V
SMARTREFLEX
CORE SUPPLY
CVDD_42
CVDD_43
CVDD_44
CVDD_45
CVDD_46
CVDD_47
CVDD_48
CVDD_49
CVDD_50
CVDD_51
CVDD_52
CVDD_53
CVDD_54
CVDD_55
CVDD_56
CVDD_57
CVDD_58
CVDD_59
CVDD_60
CVDD_61
CVDD_62
CVDD_63
CVDD_64
CVDD_65
CVDD_66
CVDD_67
CVDD_68
CVDD_69
CVDD_70
CVDD_71
CVDD_72
CVDD_73
CVDD_74
CVDD_75
CVDD_76
CVDD_77
CVDD_78
CVDD_79
CVDD_80
R18
R20
R22
T9
T11
T13
T15
T17
T19
T21
U8
U10
U18
U20
U22
V9
V11
V17
V19
V21
W8
W10
W18
W20
W22
Y9
Y11
Y13
Y15
Y17
Y19
Y21
AA8
AA10
AA12
AA14
AA16
AA18
AA22
Place near to DSP pins
C258
0.1uF
16V
C259
0.1uF
16V
C260
0.1uF
16V
C261
0.1uF
16V
C262
0.1uF
16V
C263
0.1uF
16V
C572
0.1uF
16V
C573
0.1uF
16V
C574
0.1uF
16V
C575
0.1uF
16V
C576
0.1uF
16V
C577
0.1uF
16V
C578
0.1uF
16V
C579
0.1uF
16V
C580
0.1uF
16V
C581
0.1uF
16V
C582
0.1uF
16V
C583
0.1uF
16V
C584
0.1uF
16V
C585
0.1uF
16V
C253
0.01uF
16V
C254
0.01uF
16V
C255
0.01uF
16V
C256
0.01uF
16V
C257
0.01uF
16V
C586
0.01uF
16V
C587
0.01uF
16V
C588
0.01uF
16V
C589
0.01uF
16V
C590
0.01uF
16V
C591
0.01uF
16V
C592
0.01uF
16V
C593
0.01uF
16V
C594
0.01uF
16V
C595
0.01uF
16V
C233
560pF
50V
C234
560pF
50V
C235
560pF
50V
C236
560pF
50V
C237
560pF
50V
C238
560pF
50V
C239
560pF
50V
C240
560pF
50V
C241
560pF
50V
C242
560pF
50V
C243
560pF
50V
C244
560pF
50V
C245
560pF
50V
C246
560pF
50V
C247
560pF
50V
CVDD
Place near to DSP pins
C248
0.01uF
16V
C249
0.01uF
16V
C250
0.01uF
16V
C251
0.01uF
16V
C252
0.01uF
16V
CVDD
Place near to DSP pins
C228
560pF
50V
C229
560pF
50V
C230
560pF
50V
C231
560pF
50V
C232
560pF
50V
C
pinout_rev0_3_2_customer
TI_TMS320C6678
VCC1V0
VCC1V0
Place near to DSP
C404
100uF
6.3V
B
C402
100uF
6.3V
C325
4.7uF
6.3V
B
VCC1V0
Place near to DSP pins
VCC1V0
VCC1V0
C277
0.01uF
16V
DSP1B
J8
J14
K7
K9
K13
K15
L8
L14
L20
L22
M9
M21
N20
CVDD1_1
CVDD1_2
CVDD1_3
CVDD1_4
CVDD1_5
CVDD1_6
CVDD1_7
CVDD1_8
CVDD1_9
CVDD1_10
CVDD1_11
CVDD1_12
CVDD1_13
1.0V CORE
MEMORY SUPPLY
CVDD1_14
CVDD1_15
CVDD1_16
CVDD1_17
CVDD1_18
CVDD1_19
CVDD1_20
CVDD1_21
CVDD1_22
CVDD1_23
CVDD1_24
CVDD1_25
N22
R12
R14
R16
U12
U14
U16
V13
V15
W12
W14
W16
C278
0.01uF
16V
C279
0.01uF
16V
C280
0.01uF
16V
C281
0.01uF
16V
C282
0.01uF
16V
VCC1V0
Place near to DSP pins
pinout_rev0_3_2_customer
C283
0.1uF
16V
TI_TMS320C6678
A
C284
0.1uF
16V
C285
0.1uF
16V
C286
0.1uF
16V
C596
0.1uF
16V
C597
0.1uF
16V
A
VCC1V0
Place near to DSP pins
C267
560pF
50V
C268
560pF
50V
C269
560pF
50V
C270
560pF
50V
C271
560pF
50V
C272
560pF
50V
C273
560pF
50V
C274
560pF
50V
C275
560pF
50V
C276
560pF
50V
Designed for TI by ADVANTECH
Title
DSP_POWERB
Size
C
Date:
5
4
3
2
Document Number
Rev
A101-1
DSPM-8301E
Tuesday, March 08, 2011
Sheet
1
19
of
40
5
4
3
2
1
1.0V & 1.5V for Serdes
VDDT1
VDDT2
DSP1E
M7
N6
P7
R6
T7
U6
V7
D
VDDR1
VDDT1_1
VDDT1_2
VDDT1_3
VDDT1_4
VDDT1_5
VDDT1_6
VDDT1_7
V5
VDDT2_1
VDDT2_2
VDDT2_3
VDDT2_4
VDDT2_5
VDDT2_6
VDDT2_7
VDDT2_8
VDDT2_9
VDDT2_10
VDDT2_11
VDDT2_12
VDDT2_13
VDDT2_14
VDDT2_15
VDDT2_16
VDDT2_17
VDDT2_18
pinout_rev0_3_2_customer
VDDR1
1.0V SERDES TERMINATION SUPPLY
1.5V SERDES REGULATOR SUPPLY
VDDR2
VDDR3
VDDR4
AB9
AB11
AB13
AB15
AC8
AC10
AC12
AC14
AC16
AC18
AD7
AD9
AD11
AD13
AD15
AD17
AE18
AB17
D
AE10
AE16
AE14
VDDR2
VDDR3
VDDR4
TI_TMS320C6678
C
C
Place near to DSP pins
B9
B10
C288
0.01uF
16V
C289
560pF
50V
C290
560pF
50V
C291
0.1uF
16V
C292
0.01uF
16V
C293
560pF
50V
C294
560pF
50V
2
C287
0.1uF
16V
3
2200pF
700mA
VCC1V0
1
VDDT1
C295
4.7uF
6.3V
C296
0.1uF
16V
C297
0.01uF
16V
C298
560pF
50V
C299
560pF
50V
3
VCC1V0
C300
4.7uF
6.3V
2200pF
700mA
2
1
VDDT2
B28
B27
C478
0.1uF
16V
C479
0.01uF
16V
C480
1000pF
50V
2
C477
560pF
50V
3
1
VDDR2
3
VCC1V5
VCC1V5
B
C481
560pF
50V
2200pF
700mA
C482
0.1uF
16V
C484
0.01uF
16V
C483
1000pF
50V
2
1
VDDR1
B
2200pF
700mA
B30
B29
C486
0.1uF
16V
C488
0.01uF
16V
C487
1000pF
50V
1
VDDR4
3
VCC1V5
VCC1V5
C489
560pF
50V
2200pF
700mA
C490
0.1uF
16V
C491
0.01uF
16V
C492
1000pF
50V
2
C485
560pF
50V
3
2
1
VDDR3
2200pF
700mA
A
A
Designed for TI by ADVANTECH
Title
DSP_POWERC
Size
C
Date:
5
4
3
2
Document Number
Rev
A101-1
DSPM-8301E
Tuesday, March 08, 2011
Sheet
1
20
of
40
VSS_83
VSS_84
VSS_85
VSS_86
VSS_87
VSS_88
VSS_89
VSS_90
VSS_91
VSS_92
VSS_93
VSS_94
VSS_95
VSS_96
VSS_97
VSS_98
VSS_99
VSS_100
VSS_101
VSS_102
VSS_103
VSS_104
VSS_105
VSS_106
VSS_107
VSS_108
VSS_109
VSS_110
VSS_111
VSS_112
VSS_113
VSS_114
VSS_115
VSS_116
VSS_117
VSS_118
VSS_119
VSS_120
VSS_121
VSS_122
VSS_123
VSS_124
VSS_125
VSS_126
VSS_127
VSS_128
VSS_129
VSS_130
VSS_131
VSS_132
VSS_133
VSS_134
VSS_135
VSS_136
VSS_137
VSS_138
VSS_139
VSS_140
VSS_141
VSS_142
VSS_143
VSS_144
VSS_145
VSS_146
VSS_147
VSS_148
VSS_149
VSS_150
VSS_151
VSS_152
VSS_153
VSS_154
VSS_155
VSS_156
VSS_157
VSS_158
VSS_159
VSS_160
VSS_161
VSS_162
VSS_163
VSS_164
VSS_1
VSS_2
VSS_3
VSS_4
VSS_5
VSS_6
VSS_7
VSS_8
VSS_9
VSS_10
VSS_11
VSS_12
VSS_13
VSS_14
VSS_15
VSS_16
VSS_17
VSS_18
VSS_19
VSS_20
VSS_21
VSS_22
VSS_23
VSS_24
VSS_25
VSS_26
VSS_27
VSS_28
VSS_29
VSS_30
VSS_31
VSS_32
VSS_33
VSS_34
VSS_35
VSS_36
VSS_37
VSS_38
VSS_39
VSS_40
VSS_41
VSS_42
VSS_43
VSS_44
VSS_45
VSS_46
VSS_47
VSS_48
VSS_49
VSS_50
VSS_51
VSS_52
VSS_53
VSS_54
VSS_55
VSS_56
VSS_57
VSS_58
VSS_59
VSS_60
VSS_61
VSS_62
VSS_63
VSS_64
VSS_65
VSS_66
VSS_67
VSS_68
VSS_69
VSS_70
VSS_71
VSS_72
VSS_73
VSS_74
VSS_75
VSS_76
VSS_77
VSS_78
VSS_79
VSS_80
VSS_81
VSS_82
C
V16
V18
V20
V22
W7
W9
W11
W13
W15
W17
W19
W21
Y8
Y10
Y12
Y14
Y16
Y18
Y20
Y22
AA5
AA7
AA9
AA11
AA13
AA15
AA17
AA19
AE8
AA23
AA28
AB4
AB8
AB10
AB12
AB14
AB16
AB18
AB20
AB22
AC5
AC7
AC2
AC11
B
TI_TMS320C6678
5
A1
A29
B11
B17
B25
C8
C23
D3
D14
D18
E5
E20
F6
F8
F10
F12
F16
F18
F27
F29
G1
G3
G5
G6
G7
G9
G11
G13
G15
G17
G19
G21
G24
H1
H2
H3
H4
H5
H6
H8
H10
H12
H14
H16
H18
H20
J1
J2
J3
J4
J5
J6
J7
J9
J11
J13
J15
J17
J19
J21
K1
K2
K3
K4
K5
K6
K8
K10
K12
K14
K16
K18
K20
Y6
L1
L2
L3
L4
L5
L6
L7
L9
DSP1F
L11
L13
L15
L17
L19
L21
M2
M3
M4
M6
M8
M10
M12
M14
M16
M18
M20
M22
M28
N3
N7
N9
N11
N13
N15
N17
N19
N21
P1
P3
P5
P6
P8
P10
P12
P14
P16
P18
P20
P22
R2
R3
R4
R7
R9
R11
R13
R15
R17
R19
R21
T3
T6
T8
T10
T12
T14
T16
T18
T20
T22
T26
U1
U3
U5
U7
U9
U11
U13
U15
U17
U19
U21
V1
V2
V3
V4
V6
V8
V10
V12
V14
5
4
VSS_165
VSS_166
VSS_167
VSS_168
VSS_169
VSS_170
VSS_171
VSS_172
VSS_173
VSS_174
VSS_175
VSS_176
VSS_177
VSS_178
VSS_179
VSS_180
VSS_181
VSS_182
VSS_183
VSS_184
VSS_185
VSS_186
VSS_187
VSS_188
VSS_189
VSS_190
VSS_191
VSS_192
VSS_193
VSS_194
VSS_195
VSS_196
VSS_197
VSS_198
VSS_199
VSS_200
VSS_201
VSS_202
VSS_203
VSS_204
VSS_205
VSS_206
VSS_207
VSS_208
4
3
POWER SUPPLY REFERENCE
pinout_rev0_3_2_customer
3
2
VSS_209
VSS_210
VSS_211
VSS_212
VSS_213
VSS_214
VSS_215
VSS_216
VSS_217
VSS_218
VSS_219
VSS_220
VSS_221
VSS_222
VSS_223
VSS_224
VSS_225
VSS_226
VSS_227
VSS_228
VSS_229
VSS_230
VSS_231
VSS_232
VSS_233
VSS_234
VSS_235
VSS_236
VSS_237
VSS_238
VSS_239
VSS_240
VSS_241
VSS_242
VSS_243
VSS_244
VSS_245
VSS_246
VSS_247
VSS_248
VSS_249
VSS_250
VSS_251
VSS_252
2
1
D
D
AC13
AC15
AC17
AC19
AD6
AD8
AD10
AD12
AD14
AD16
AD18
AE7
AE9
AE11
AE13
AE15
AE17
AE19
AE26
AF6
AF9
AF12
AF15
AF18
AF22
AF4
AG7
AG10
AG13
AG16
AG19
AH6
AH9
AH12
AH15
AH18
AJ1
AJ7
AJ10
AJ13
AJ16
AJ19
AJ29
C
AB6
B
A
A
Designed for TI by ADVANTECH
Title
Size
C
Date:
Document Number
DSP_GND
Tuesday, March 08, 2011
DSPM-8301E
Sheet
1
21
of
Rev
A101-1
40
5
4
3
2
1
CLOCK GEN1
D
D
VCCPLLA3C
VCC3V3_AUX
VCCPLLA3B
VCC3V3_AUX
VCCPLLA3A
VCC3V3_AUX
VCC_VCO3B
C339
0.1uF
16V
VCC_VCO3A
(31)
(31)
(31)
(31)
(31)
VCC3V3_AUX
REFCLK3_PD#
CLOCK3_SSPCS1
CLOCK3_SSPCK
CLOCK3_SSPSI
CLOCK3_SSPSO
VCC3V3_AUX
10K
IN
1%
REFCLK3_PD#
R367
10K
1%
31
12
14
CLOCK3_SSPCS1
CLOCK3_SSPCK
CLOCK3_SSPSI
CLOCK3_SSPSO
25
24
23
22
IN
IN
IN
OUT
R176
R177
33
30
10K
1%
1K 1%
1uF
1uF
6.3V
6.3V
4
38
C338
0.1uF
16V
U2P
U2N
U3P
U3N
TI_CDCE62005RGZT
U4P
U4N
SPI_LE
SPI_CLK
SPI_MOSI
SPI_MISO
AUXOUT
AUXIN
TEST_MODE
TESTOUTA
REG_CAP1
REG_CAP2
PLL_LOCK
27
28
PCIECLKP
PCIECLKN
19
20
HyperLink_CLKP
HyperLink_CLKN
16
17
SRIOSGMIICLKP
SRIOSGMIICLKN
9
10
PASSCLKP
PASSCLKN
(17)
OUT
OUT
PCIECLKP
PCIECLKN
OUT
OUT
HyperLink_CLKP
HyperLink_CLKN
(17)
(17)
OUT
OUT
SRIOSGMIICLKP
SRIOSGMIICLKN
(17)
(17)
OUT
OUT
PASSCLKP
PASSCLKN
(17)
100.00MHz
VCC3V3_AUX
1
C341
0.1uF
16V
C342
0.1uF
16V
C343
0.1uF
16V
C344
0.1uF
16V
312.5MHz
2200pF
700mA
VCC_VCO3A
C349
0.1uF
16V
VCC3V3_AUX
1
C350
1uF
6.3V
1
13
43
CLOCK3_PLL_LOCK
C351
0.1uF
16V
C352
1uF
6.3V
C359
0.1uF
16V
C360
1uF
6.3V
C
(17)
B18
OUT
2200pF
700mA
VCCPLLA3C
(17)
100.00MHz
VCC3V3_AUX
CLOCK3_PLL_LOCK
3
312.5MHz
6
7
37
B17
3
2
EXT_LFP
EXT_LFN
36
C337
0.1uF
16V
C347
0.1uF
16V
11
18
21
26
29
32
34
35
5
39
42
8
VCC_OUT1
VCC_OUT2
VCC_OUT3
VCC_OUT4
VCC_OUT5
VCC_OUT6
VCC_OUT7
VCC_VCO1
VCC_VCO2
VCC1_PLL1
VCC1_PLL2
VCC1_PLL3
47
1
U1P
U1N
GND_VCO
C361
C362
C346
0.1uF
16V
B16
U0P
U0N
PRIREF+
PRIREF-
REF_SEL
Power_Down
SYNC
C345
0.1uF
16V
B19
3
2200pF
700mA
VCC_VCO3B
C357
0.1uF
16V
VCC3V3_AUX
C358
1uF
6.3V
1
3
2
40
41
R174
SECREF+
SECREF-
2
45
46
2
0.1uF 16V
0.1uF 16V
C340
0.1uF
16V
2200pF
700mA
VCCPLLA3B
(31)
B20
VCC3V3_AUX
1
3
2
C354
C356
IN
IN
EPAD
Thermal_VIA1
Thermal_VIA2
Thermal_VIA3
Thermal_VIA4
Thermal_VIA5
Thermal_VIA6
Thermal_VIA7
Thermal_VIA8
Thermal_VIA9
Thermal_VIA10
Thermal_VIA11
Thermal_VIA12
Thermal_VIA13
Thermal_VIA14
Thermal_VIA15
Thermal_VIA16
Thermal_VIA17
Thermal_VIA18
Thermal_VIA19
Thermal_VIA20
Thermal_VIA21
Thermal_VIA22
Thermal_VIA23
Thermal_VIA24
Thermal_VIA25
REFCK_P
REFCK_N
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
3
2
C
(23)
(23)
VCC_IN_PRI
VCC_IN_SEC
VBB
CLK3
44
15
6.3V
48
1uF
VCC_AUXIN
VCC_AUXOUT
C348
2200pF
700mA
VCCPLLA3A
C363
0.1uF
16V
C364
1uF
6.3V
B
B
A
A
Designed for TI by ADVANTECH
Title
DSP_CLOCK_GEN1
Size
C
Date:
5
4
3
2
Document Number
Rev
A101-1
DSPM-8301E
Tuesday, March 08, 2011
Sheet
1
22
of
40
5
4
3
2
1
CLOCK GEN2
VCCPLLA2C
VCC3V3_AUX
VCCPLLA2B
VCC3V3_AUX
VCCPLLA2A
VCC3V3_AUX
VCC_VCO2B
C310
0.1uF
16V
VCC_VCO2A
CLOCK2_SSPCS1
CLOCK2_SSPCK
CLOCK2_SSPSI
CLOCK2_SSPSO
CLOCK2_SSPCS1
CLOCK2_SSPCK
CLOCK2_SSPSI
CLOCK2_SSPSO
IN
IN
IN
OUT
R173
R172
VCC3V3_AUX
33
30
1%
1%
1uF
1uF
25
24
23
22
6.3V
6.3V
4
38
REF_SEL
Power_Down
SYNC
U3P
U3N
TI_CDCE62005RGZT
U4P
U4N
SPI_LE
SPI_CLK
SPI_MOSI
SPI_MISO
C315
0.1uF
16V
C316
0.1uF
16V
OUT
OUT
16
17
DDRCLKP
DDRCLKN
9
10
AUXOUT
AUXIN
REG_CAP1
REG_CAP2
PLL_LOCK
(22)
100.00MHz
VCC3V3_AUX
1
C317
0.1uF
16V
C318
0.1uF
16V
C319
0.1uF
16V
D
B12
3
CORECLKP
CORECLKN
(17)
OUT
OUT
DDRCLKP
DDRCLKN
(17)
66.667MHz
OUT
OUT
CORECLKP
CORECLKN
(17)
100.00MHz
13
43
37
2200pF
700mA
VCC_VCO2A
C321
0.1uF
16V
VCC3V3_AUX
1
C322
1uF
6.3V
B13
VCC3V3_AUX
CLOCK2_PLL_LOCK
VCCPLLA2C
C323
0.1uF
16V
2200pF
700mA
C324
1uF
6.3V
1
B14
3
VCC_VCO2B
VCC3V3_AUX
1
3
VCCPLLA2B
NL/47pF 50V
25MHz_20pF
REFCLK2_XTALIN
3
(17)
6
7
C366
TEST_MODE
TESTOUTA
(22)
REFCK_P
REFCK_N
2
REFCK_P
REFCK_N
2
8
C309
0.1uF
16V
C314
0.1uF
16V
11
18
21
26
29
32
34
35
5
39
42
VCC_OUT2
VCC_OUT3
VCC_OUT4
VCC_OUT5
VCC_OUT6
VCC_OUT7
VCC_VCO1
VCC_VCO2
VCC1_PLL1
VCC1_PLL2
VCC1_PLL3
U2P
U2N
36
C
VCC_OUT1
EXT_LFP
EXT_LFN
GND_VCO
C333
C334
10K
1K
31
12
14
C313
0.1uF
16V
Y5
OUT
CLOCK2_PLL_LOCK
2200pF
700mA
C329
0.1uF
16V
C330
1uF
6.3V
2
NL/10K 1%
REFCLK2_PD#
R366
10K
1%
IN
C312
0.1uF
16V
19
20
2
(31)
(31)
(31)
(31)
R170
VCC3V3_AUX
REFCLK2_PD#
U1P
U1N
27
28
C331
0.1uF
16V
2200pF
700mA
C332
1uF
6.3V
(31)
B15
VCC3V3_AUX
1
3
2
(31)
C311
0.1uF
16V
B11
U0P
U0N
PRIREF+
PRIREF-
EPAD
Thermal_VIA1
Thermal_VIA2
Thermal_VIA3
Thermal_VIA4
Thermal_VIA5
Thermal_VIA6
Thermal_VIA7
Thermal_VIA8
Thermal_VIA9
Thermal_VIA10
Thermal_VIA11
Thermal_VIA12
Thermal_VIA13
Thermal_VIA14
Thermal_VIA15
Thermal_VIA16
Thermal_VIA17
Thermal_VIA18
Thermal_VIA19
Thermal_VIA20
Thermal_VIA21
Thermal_VIA22
Thermal_VIA23
Thermal_VIA24
Thermal_VIA25
40
41
SECREF+
SECREF-
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
3
2
45
46
VCC_IN_PRI
VCC_IN_SEC
VBB
CLK2
47
1
6.3V
44
15
1uF
48
C320
VCC_AUXIN
VCC_AUXOUT
D
2200pF
700mA
VCCPLLA2A
C335
0.1uF
16V
C
C336
1uF
6.3V
B
B
A
A
Designed for TI by ADVANTECH
Title
CLOCK GEN2
Size
C
Date:
5
4
3
2
Document Number
Rev
A101-1
DSPM-8301E
Tuesday, March 08, 2011
Sheet
1
23
of
40
5
4
3
2
1
VCC1V5
(13,24,25)DSP0_DDR3_EA[0..15]
DSP0_DDR3_EA0
DSP0_DDR3_EA1
DSP0_DDR3_EA2
DSP0_DDR3_EA3
DSP0_DDR3_EA4
DSP0_DDR3_EA5
DSP0_DDR3_EA6
DSP0_DDR3_EA7
DSP0_DDR3_EA8
DSP0_DDR3_EA9
DSP0_DDR3_EA10
DSP0_DDR3_EA11
DSP0_DDR3_EA12
DSP0_DDR3_EA13
D
(13,24,25)DSP0_DDR3_EBA_0
(13,24,25)DSP0_DDR3_EBA_1
(13,24,25)DSP0_DDR3_EBA_2
IN
IN
IN
(13,24,25)DSP0_DDR3_EWE#
(13,24,25)DSP0_DDR3_ECAS#
(13,24,25)DSP0_DDR3_ERAS#
(13,24,25)DSP0_DDR3_ECS_0#
IN
IN
IN
IN
(13)
(13)
(13)
(13)
DSP0_DDR3_EDQSP_0
DSP0_DDR3_EDQSN_0
DSP0_DDR3_EDQSP_1
DSP0_DDR3_EDQSN_1
IN
IN
IN
IN
(13)
(13)
DSP0_DDR3_EDM_0
DSP0_DDR3_EDM_1
IN
IN
(13,24,25)DSP0_DDR3_ECKP_0
(13,24,25)DSP0_DDR3_ECKN_0
(13,24,25)DSP0_DDR3_ECKE_0
IN
IN
IN
(13,24,25)DSP0_DDR3_EODT_0
IN
(13,24,25)DSP0_DDR3_EMRESETN
IN
R73
DSP0_DDR3_EBA_0
DSP0_DDR3_EBA_1
DSP0_DDR3_EBA_2
N3
P7
P3
N2
P8
P2
R8
R2
T8
R3
L7
R7
N7
T3
M2
N8
M3
DSP0_DDR3_EWE#
DSP0_DDR3_ECAS#
DSP0_DDR3_ERAS#
DSP0_DDR3_ECS_0#
L3
K3
J3
L2
DSP0_DDR3_EDQSP_0
DSP0_DDR3_EDQSN_0
DSP0_DDR3_EDQSP_1
DSP0_DDR3_EDQSN_1
F3
G3
C7
B7
DSP0_DDR3_EDM_0
DSP0_DDR3_EDM_1
E7
D3
DSP0_DDR3_ECKP_0
DSP0_DDR3_ECKN_0
DSP0_DDR3_ECKE_0
J7
K7
K9
DSP0_DDR3_EODT_0
K1
DSP0_DDR3_EMRESETN
T2
L8
240
A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10/AP
A11
A12/BC
A13
BA0
BA1
BA2
WE
CAS
RAS
CS
DQSL
DQSL
DQSU
DQSU
DML
DMU
CK
CK
CKE
ODT
C
IN
DSP0_DDR3_EA15
DSP0_DDR3_EA14
J1
J9
L1
L9
M7
T7
VDD_1
VDD_2
VDD_3
VDD_4
VDD_5
VDD_6
VDD_7
VDD_8
VDD_9
VDDQ_1
VDDQ_2
VDDQ_3
VDDQ_4
VDDQ_5
VDDQ_6
VDDQ_7
VDDQ_8
VDDQ_9
VREFCA
VREFDQ
DQL0
DQL1
DQL2
DQL3
DQL4
DQL5
DQL6
DQL7
DQU0
DQU1
DQU2
DQU3
DQU4
DQU5
DQU6
DQU7
RESET
ZQ
1%
(13,24,25)DSP0_DDR3_EA[0..15]
VCC1V5
U4
IN
NC_1
NC_2
NC_3
NC_4
NC_5
NC_6
VSS_1
VSS_2
VSS_3
VSS_4
VSS_5
VSS_6
VSS_7
VSS_8
VSS_9
VSS_10
VSS_11
VSS_12
VSSQ_1
VSSQ_2
VSSQ_3
VSSQ_4
VSSQ_5
VSSQ_6
VSSQ_7
VSSQ_8
VSSQ_9
(13,24,25)DSP0_DDR3_EA[0..15]
B2
D9
G7
K2
K8
N1
N9
R1
R9
A1
A8
C1
C9
D2
E9
F1
H2
H9
C51
0.1uF
16V
C162
M8
H1
E3
F7
F2
F8
H3
H8
G2
H7
D7
C3
C8
C2
A7
A2
B8
A3
C52
0.1uF
16V
C53
0.1uF
16V
C54
0.1uF
16V
C55
0.1uF
16V
U16
IN
DSP0_DDR3_EA0
DSP0_DDR3_EA1
DSP0_DDR3_EA2
DSP0_DDR3_EA3
DSP0_DDR3_EA4
DSP0_DDR3_EA5
DSP0_DDR3_EA6
DSP0_DDR3_EA7
DSP0_DDR3_EA8
DSP0_DDR3_EA9
DSP0_DDR3_EA10
DSP0_DDR3_EA11
DSP0_DDR3_EA12
DSP0_DDR3_EA13
C56
22uF
6.3V
0.1uF 16V
DSP_VREFSSTL
Trace need 20 mil.
IN
BI
DSP0_DDR3_EDQ0
DSP0_DDR3_EDQ1
DSP0_DDR3_EDQ2
DSP0_DDR3_EDQ3
DSP0_DDR3_EDQ4
DSP0_DDR3_EDQ5
DSP0_DDR3_EDQ6
DSP0_DDR3_EDQ7
DSP0_DDR3_EDQ8
DSP0_DDR3_EDQ9
DSP0_DDR3_EDQ10
DSP0_DDR3_EDQ11
DSP0_DDR3_EDQ12
DSP0_DDR3_EDQ13
DSP0_DDR3_EDQ14
DSP0_DDR3_EDQ15
DSP0_DDR3_EDQ[0..7]
BI
A9
B3
E1
G8
J2
J8
M1
M9
P1
P9
T1
T9
B1
B9
D1
D8
E2
E8
F9
G1
G9
(13,24,25)
DSP_VREFSSTL
DSP0_DDR3_EDQ[8..15]
(13)
(13)
(13,24,25)DSP0_DDR3_EBA_0
(13,24,25)DSP0_DDR3_EBA_1
(13,24,25)DSP0_DDR3_EBA_2
IN
IN
IN
(13,24,25)DSP0_DDR3_EWE#
(13,24,25)DSP0_DDR3_ECAS#
(13,24,25)DSP0_DDR3_ERAS#
(13,24,25)DSP0_DDR3_ECS_0#
IN
IN
IN
IN
(13)
(13)
(13)
(13)
DSP0_DDR3_EDQSP_4
DSP0_DDR3_EDQSN_4
DSP0_DDR3_EDQSP_5
DSP0_DDR3_EDQSN_5
IN
IN
IN
IN
(13)
(13)
DSP0_DDR3_EDM_4
DSP0_DDR3_EDM_5
IN
IN
(13,24,25)DSP0_DDR3_ECKP_0
(13,24,25)DSP0_DDR3_ECKN_0
(13,24,25)DSP0_DDR3_ECKE_0
IN
IN
IN
(13,24,25)DSP0_DDR3_EODT_0
IN
(13,24,25)DSP0_DDR3_EMRESETN
IN
DSP0_DDR3_EBA_0
DSP0_DDR3_EBA_1
DSP0_DDR3_EBA_2
N3
P7
P3
N2
P8
P2
R8
R2
T8
R3
L7
R7
N7
T3
M2
N8
M3
DSP0_DDR3_EWE#
DSP0_DDR3_ECAS#
DSP0_DDR3_ERAS#
DSP0_DDR3_ECS_0#
L3
K3
J3
L2
DSP0_DDR3_EDQSP_4
DSP0_DDR3_EDQSN_4
DSP0_DDR3_EDQSP_5
DSP0_DDR3_EDQSN_5
F3
G3
C7
B7
DSP0_DDR3_EDM_4
DSP0_DDR3_EDM_5
E7
D3
DSP0_DDR3_ECKP_0
DSP0_DDR3_ECKN_0
DSP0_DDR3_ECKE_0
J7
K7
K9
DSP0_DDR3_EODT_0
K1
DSP0_DDR3_EMRESETN
T2
L8
R132
(13,24,25)DSP0_DDR3_EA[0..15]
BA0
BA1
BA2
WE
CAS
RAS
CS
DQSL
DQSL
DQSU
DQSU
DML
DMU
CK
CK
CKE
ODT
IN
DSP0_DDR3_EA15
DSP0_DDR3_EA14
J1
J9
L1
L9
M7
T7
VDD_1
VDD_2
VDD_3
VDD_4
VDD_5
VDD_6
VDD_7
VDD_8
VDD_9
VDDQ_1
VDDQ_2
VDDQ_3
VDDQ_4
VDDQ_5
VDDQ_6
VDDQ_7
VDDQ_8
VDDQ_9
VREFCA
VREFDQ
DQL0
DQL1
DQL2
DQL3
DQL4
DQL5
DQL6
DQL7
DQU0
DQU1
DQU2
DQU3
DQU4
DQU5
DQU6
DQU7
RESET
ZQ
1% 240
* Data bits can be swapped within
the byte lane to ease routing.
* Address/Command/Control/Clock
routing must be Fly-By in byte order
0, 1, 2, 3 ECC, 4, 5, 6, 7.
SAMSUNG_K4B1G1646E-HCH9
A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10/AP
A11
A12/BC
A13
NC_1
NC_2
NC_3
NC_4
NC_5
NC_6
VSS_1
VSS_2
VSS_3
VSS_4
VSS_5
VSS_6
VSS_7
VSS_8
VSS_9
VSS_10
VSS_11
VSS_12
VSSQ_1
VSSQ_2
VSSQ_3
VSSQ_4
VSSQ_5
VSSQ_6
VSSQ_7
VSSQ_8
VSSQ_9
B2
D9
G7
K2
K8
N1
N9
R1
R9
A1
A8
C1
C9
D2
E9
F1
H2
H9
M8
H1
E3
F7
F2
F8
H3
H8
G2
H7
D7
C3
C8
C2
A7
A2
B8
A3
C88
0.1uF
16V
C85
0.1uF
16V
C86
0.1uF
16V
C90
0.1uF
16V
C89
0.1uF
16V
D
C328
0.1uF 16V
DSP_VREFSSTL
DSP0_DDR3_EDQ32
DSP0_DDR3_EDQ33
DSP0_DDR3_EDQ34
DSP0_DDR3_EDQ35
DSP0_DDR3_EDQ36
DSP0_DDR3_EDQ37
DSP0_DDR3_EDQ38
DSP0_DDR3_EDQ39
DSP0_DDR3_EDQ40
DSP0_DDR3_EDQ41
DSP0_DDR3_EDQ42
DSP0_DDR3_EDQ43
DSP0_DDR3_EDQ44
DSP0_DDR3_EDQ45
DSP0_DDR3_EDQ46
DSP0_DDR3_EDQ47
Trace need 20 mil.
IN
(13,24,25)
DSP_VREFSSTL
BI
DSP0_DDR3_EDQ[32..39] (13)
BI
DSP0_DDR3_EDQ[40..47] (13)
A9
B3
E1
G8
J2
J8
M1
M9
P1
P9
T1
T9
B1
B9
D1
D8
E2
E8
F9
G1
G9
C
SAMSUNG_K4B1G1646E-HCH9
VCC1V5
(13,24,25)DSP0_DDR3_EA[0..15]
DSP0_DDR3_EA0
DSP0_DDR3_EA1
DSP0_DDR3_EA2
DSP0_DDR3_EA3
DSP0_DDR3_EA4
DSP0_DDR3_EA5
DSP0_DDR3_EA6
DSP0_DDR3_EA7
DSP0_DDR3_EA8
DSP0_DDR3_EA9
DSP0_DDR3_EA10
DSP0_DDR3_EA11
DSP0_DDR3_EA12
DSP0_DDR3_EA13
B
(13,24,25)DSP0_DDR3_EBA_0
(13,24,25)DSP0_DDR3_EBA_1
(13,24,25)DSP0_DDR3_EBA_2
DSP0_DDR3_EBA_0
DSP0_DDR3_EBA_1
DSP0_DDR3_EBA_2
IN
IN
IN
(13,24,25)DSP0_DDR3_EWE#
(13,24,25)DSP0_DDR3_ECAS#
(13,24,25)DSP0_DDR3_ERAS#
(13,24,25)DSP0_DDR3_ECS_0#
IN
IN
IN
IN
(13)
(13)
(13)
(13)
DSP0_DDR3_EDQSP_2
DSP0_DDR3_EDQSN_2
DSP0_DDR3_EDQSP_3
DSP0_DDR3_EDQSN_3
IN
IN
IN
IN
(13)
(13)
DSP0_DDR3_EDM_2
DSP0_DDR3_EDM_3
IN
IN
(13,24,25)DSP0_DDR3_ECKP_0
(13,24,25)DSP0_DDR3_ECKN_0
(13,24,25)DSP0_DDR3_ECKE_0
IN
IN
IN
(13,24,25)DSP0_DDR3_EODT_0
IN
(13,24,25)DSP0_DDR3_EMRESETN
IN
R76
N3
P7
P3
N2
P8
P2
R8
R2
T8
R3
L7
R7
N7
T3
M2
N8
M3
DSP0_DDR3_EWE#
DSP0_DDR3_ECAS#
DSP0_DDR3_ERAS#
DSP0_DDR3_ECS_0#
L3
K3
J3
L2
DSP0_DDR3_EDQSP_2
DSP0_DDR3_EDQSN_2
DSP0_DDR3_EDQSP_3
DSP0_DDR3_EDQSN_3
F3
G3
C7
B7
DSP0_DDR3_EDM_2
DSP0_DDR3_EDM_3
E7
D3
DSP0_DDR3_ECKP_0
DSP0_DDR3_ECKN_0
DSP0_DDR3_ECKE_0
J7
K7
K9
DSP0_DDR3_EODT_0
K1
DSP0_DDR3_EMRESETN
T2
L8
240
A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10/AP
A11
A12/BC
A13
BA0
BA1
BA2
WE
CAS
RAS
CS
DQSL
DQSL
DQSU
DQSU
DML
DMU
CK
CK
CKE
ODT
A
IN
DSP0_DDR3_EA15
DSP0_DDR3_EA14
J1
J9
L1
L9
M7
T7
VDD_1
VDD_2
VDD_3
VDD_4
VDD_5
VDD_6
VDD_7
VDD_8
VDD_9
VDDQ_1
VDDQ_2
VDDQ_3
VDDQ_4
VDDQ_5
VDDQ_6
VDDQ_7
VDDQ_8
VDDQ_9
VREFCA
VREFDQ
DQL0
DQL1
DQL2
DQL3
DQL4
DQL5
DQL6
DQL7
DQU0
DQU1
DQU2
DQU3
DQU4
DQU5
DQU6
DQU7
RESET
ZQ
1%
(13,24,25)DSP0_DDR3_EA[0..15]
VCC1V5
U5
IN
NC_1
NC_2
NC_3
NC_4
NC_5
NC_6
VSS_1
VSS_2
VSS_3
VSS_4
VSS_5
VSS_6
VSS_7
VSS_8
VSS_9
VSS_10
VSS_11
VSS_12
VSSQ_1
VSSQ_2
VSSQ_3
VSSQ_4
VSSQ_5
VSSQ_6
VSSQ_7
VSSQ_8
VSSQ_9
(13,24,25)DSP0_DDR3_EA[0..15]
B2
D9
G7
K2
K8
N1
N9
R1
R9
A1
A8
C1
C9
D2
E9
F1
H2
H9
C65
0.1uF
16V
C163
C67
0.1uF
16V
C68
0.1uF
16V
C69
0.1uF
16V
U17
IN
DSP0_DDR3_EA0
DSP0_DDR3_EA1
DSP0_DDR3_EA2
DSP0_DDR3_EA3
DSP0_DDR3_EA4
DSP0_DDR3_EA5
DSP0_DDR3_EA6
DSP0_DDR3_EA7
DSP0_DDR3_EA8
DSP0_DDR3_EA9
DSP0_DDR3_EA10
DSP0_DDR3_EA11
DSP0_DDR3_EA12
DSP0_DDR3_EA13
C70
22uF
6.3V
0.1uF 16V
(13,24,25)DSP0_DDR3_EBA_0
(13,24,25)DSP0_DDR3_EBA_1
(13,24,25)DSP0_DDR3_EBA_2
Trace need 20 mil.
DSP_VREFSSTL
M8
H1
E3
F7
F2
F8
H3
H8
G2
H7
D7
C3
C8
C2
A7
A2
B8
A3
C66
0.1uF
16V
DSP0_DDR3_EDQ16
DSP0_DDR3_EDQ17
DSP0_DDR3_EDQ18
DSP0_DDR3_EDQ19
DSP0_DDR3_EDQ20
DSP0_DDR3_EDQ21
DSP0_DDR3_EDQ22
DSP0_DDR3_EDQ23
DSP0_DDR3_EDQ24
DSP0_DDR3_EDQ25
DSP0_DDR3_EDQ26
DSP0_DDR3_EDQ27
DSP0_DDR3_EDQ28
DSP0_DDR3_EDQ29
DSP0_DDR3_EDQ30
DSP0_DDR3_EDQ31
BI
BI
DSP0_DDR3_EDQ[16..23] (13)
DSP0_DDR3_EDQ[24..31] (13)
A9
B3
E1
G8
J2
J8
M1
M9
P1
P9
T1
T9
B1
B9
D1
D8
E2
E8
F9
G1
G9
DSP0_DDR3_EBA_0
DSP0_DDR3_EBA_1
DSP0_DDR3_EBA_2
IN
IN
IN
(13,24,25)DSP0_DDR3_EWE#
(13,24,25)DSP0_DDR3_ECAS#
(13,24,25)DSP0_DDR3_ERAS#
(13,24,25)DSP0_DDR3_ECS_0#
IN
IN
IN
IN
(13)
(13)
(13)
(13)
DSP0_DDR3_EDQSP_6
DSP0_DDR3_EDQSN_6
DSP0_DDR3_EDQSP_7
DSP0_DDR3_EDQSN_7
IN
IN
IN
IN
(13)
(13)
DSP0_DDR3_EDM_6
DSP0_DDR3_EDM_7
IN
IN
(13,24,25)DSP0_DDR3_ECKP_0
(13,24,25)DSP0_DDR3_ECKN_0
(13,24,25)DSP0_DDR3_ECKE_0
IN
IN
IN
(13,24,25)DSP0_DDR3_EODT_0
IN
(13,24,25)DSP0_DDR3_EMRESETN
IN
N3
P7
P3
N2
P8
P2
R8
R2
T8
R3
L7
R7
N7
T3
M2
N8
M3
DSP0_DDR3_EWE#
DSP0_DDR3_ECAS#
DSP0_DDR3_ERAS#
DSP0_DDR3_ECS_0#
L3
K3
J3
L2
DSP0_DDR3_EDQSP_6
DSP0_DDR3_EDQSN_6
DSP0_DDR3_EDQSP_7
DSP0_DDR3_EDQSN_7
F3
G3
C7
B7
DSP0_DDR3_EDM_6
DSP0_DDR3_EDM_7
E7
D3
DSP0_DDR3_ECKP_0
DSP0_DDR3_ECKN_0
DSP0_DDR3_ECKE_0
J7
K7
K9
DSP0_DDR3_EODT_0
K1
DSP0_DDR3_EMRESETN
T2
L8
R133
(13,24,25)DSP0_DDR3_EA[0..15]
IN
A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10/AP
A11
A12/BC
A13
BA0
BA1
BA2
WE
CAS
RAS
CS
DQSL
DQSL
DQSU
DQSU
DML
DMU
CK
CK
CKE
ODT
DSP0_DDR3_EA15
DSP0_DDR3_EA14
J1
J9
L1
L9
M7
T7
VDD_1
VDD_2
VDD_3
VDD_4
VDD_5
VDD_6
VDD_7
VDD_8
VDD_9
VDDQ_1
VDDQ_2
VDDQ_3
VDDQ_4
VDDQ_5
VDDQ_6
VDDQ_7
VDDQ_8
VDDQ_9
VREFCA
VREFDQ
DQL0
DQL1
DQL2
DQL3
DQL4
DQL5
DQL6
DQL7
DQU0
DQU1
DQU2
DQU3
DQU4
DQU5
DQU6
DQU7
RESET
ZQ
1% 240
SAMSUNG_K4B1G1646E-HCH9
NC_1
NC_2
NC_3
NC_4
NC_5
NC_6
VSS_1
VSS_2
VSS_3
VSS_4
VSS_5
VSS_6
VSS_7
VSS_8
VSS_9
VSS_10
VSS_11
VSS_12
VSSQ_1
VSSQ_2
VSSQ_3
VSSQ_4
VSSQ_5
VSSQ_6
VSSQ_7
VSSQ_8
VSSQ_9
B2
D9
G7
K2
K8
N1
N9
R1
R9
A1
A8
C1
C9
D2
E9
F1
H2
H9
M8
H1
E3
F7
F2
F8
H3
H8
G2
H7
D7
C3
C8
C2
A7
A2
B8
A3
C103
0.1uF
16V
C104
0.1uF
16V
C100
0.1uF
16V
DSP_VREFSSTL
DSP0_DDR3_EDQ48
DSP0_DDR3_EDQ49
DSP0_DDR3_EDQ50
DSP0_DDR3_EDQ51
DSP0_DDR3_EDQ52
DSP0_DDR3_EDQ53
DSP0_DDR3_EDQ54
DSP0_DDR3_EDQ55
DSP0_DDR3_EDQ56
DSP0_DDR3_EDQ57
DSP0_DDR3_EDQ58
DSP0_DDR3_EDQ59
DSP0_DDR3_EDQ60
DSP0_DDR3_EDQ61
DSP0_DDR3_EDQ62
DSP0_DDR3_EDQ63
A9
B3
E1
G8
J2
J8
M1
M9
P1
P9
T1
T9
B1
B9
D1
D8
E2
E8
F9
G1
G9
Trace need 20 mil.
BI
DSP0_DDR3_EDQ[48..55] (13)
BI
DSP0_DDR3_EDQ[56..63] (13)
Designed for TI by ADVANTECH
Title
DDR3
Date:
2
C101
22uF
6.3V
A
C
3
C102
0.1uF
16V
0.1uF 16V
SAMSUNG_K4B1G1646E-HCH9
4
C105
0.1uF
16V
B
C353
Size
5
C87
22uF
6.3V
Document Number
Rev
A101-1
DSPM-8301E
Tuesday, March 08, 2011
Sheet
1
24
of
40
5
4
D
3
2
1
D
CO-LAYOUT
ECC Populated for 2Gb size.
VCC1V5
(13,24,25)DSP0_DDR3_EA[0..15]
U256
DSP0_DDR3_EA0
DSP0_DDR3_EA1
DSP0_DDR3_EA2
DSP0_DDR3_EA3
DSP0_DDR3_EA4
DSP0_DDR3_EA5
DSP0_DDR3_EA6
DSP0_DDR3_EA7
DSP0_DDR3_EA8
DSP0_DDR3_EA9
DSP0_DDR3_EA10
DSP0_DDR3_EA11
DSP0_DDR3_EA12
DSP0_DDR3_EA13
K3
L7
L3
K2
L8
L2
M8
M2
N8
M3
H7
M7
K7
N3
DSP0_DDR3_EBA_0
DSP0_DDR3_EBA_1
DSP0_DDR3_EBA_2
J2
K8
J3
DSP0_DDR3_EWE#
DSP0_DDR3_ECAS#
DSP0_DDR3_ERAS#
DSP0_DDR3_ECS_0#
H3
G3
F3
H2
DSP0_DDR3_EDQSP_8
DSP0_DDR3_EDQSN_8
C3
D3
DSP0_DDR3_EDM_8
ECC_NU
B7
A7
DSP0_DDR3_ECKP_0
DSP0_DDR3_ECKN_0
DSP0_DDR3_ECKE_0
F7
G7
G9
C
DSP0_DDR3_EODT_0
G1
DSP0_DDR3_EMRESETN
N2
ECC_ZQ
H8
DSP0_DDR3_EA15
DSP0_DDR3_EA14
A3
F1
F9
H1
H9
J7
N7
A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10/AP
A11
A12/BC
A13
BA0
BA1
BA2
WE
CAS
RAS
CS
DQS
DQS
VDD0
VDD1
VDD2
VDD3
VDD4
VDD5
VDD6
VDD7
VDD8
VDDQ1
VDDQ2
VDDQ3
VDDQ4
VREFCA
VREFDQ
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
A2
A9
D7
G2
G8
K1
K9
M1
M9
B9
C1
E2
E9
ODT
RESET
ZQ
NC0
NC1
NC2
NC3
NC4
NC5
NC6
VSS0
VSS1
VSS2
VSS3
VSS4
VSS5
VSS6
VSS7
VSS8
VSS9
VSS10
VSS11
VSSQ1
VSSQ2
VSSQ3
VSSQ4
VSSQ5
DSP0_DDR3_EA0
DSP0_DDR3_EA1
DSP0_DDR3_EA2
DSP0_DDR3_EA3
DSP0_DDR3_EA4
DSP0_DDR3_EA5
DSP0_DDR3_EA6
DSP0_DDR3_EA7
DSP0_DDR3_EA8
DSP0_DDR3_EA9
DSP0_DDR3_EA10
DSP0_DDR3_EA11
DSP0_DDR3_EA12
DSP0_DDR3_EA13
VCC1V5
J8
E1
DSP_VREFSSTL
B3
C7
C2
C8
E3
E8
D2
E7
DSP0_DDR3_ECC0
DSP0_DDR3_ECC1
DSP0_DDR3_ECC2
DSP0_DDR3_ECC3
DSP0_DDR3_ECC4
DSP0_DDR3_ECC5
DSP0_DDR3_ECC6
DSP0_DDR3_ECC7
DM/TDQS
NU/TDOS
CK
CK
CKE
U8
IN
A1
A8
B1
D8
F2
F8
J1
J9
L1
L9
N1
N9
B2
B8
C9
D1
D9
(13,24)
(13,24)
(13,24)
DSP0_DDR3_EBA_0
DSP0_DDR3_EBA_1
DSP0_DDR3_EBA_2
IN
IN
IN
(13,24)
(13,24)
(13,24)
(13,24)
DSP0_DDR3_EWE#
DSP0_DDR3_ECAS#
DSP0_DDR3_ERAS#
DSP0_DDR3_ECS_0#
IN
IN
IN
IN
(13)
(13)
DSP0_DDR3_EDQSP_8
DSP0_DDR3_EDQSN_8
(13)
DSP0_DDR3_EDM_8
IN
(13,24)
(13,24)
(13,24)
DSP0_DDR3_ECKP_0
DSP0_DDR3_ECKN_0
DSP0_DDR3_ECKE_0
IN
IN
IN
IN
IN
VCC1V5
(13,24)
DSP0_DDR3_EODT_0
IN
(13,24)
DSP0_DDR3_EMRESETN
IN
R87
(13,24,25)DSP0_DDR3_EA[0..15]
IN
N3
P7
P3
N2
P8
P2
R8
R2
T8
R3
L7
R7
N7
T3
DSP0_DDR3_EBA_0
DSP0_DDR3_EBA_1
DSP0_DDR3_EBA_2
M2
N8
M3
DSP0_DDR3_EWE#
DSP0_DDR3_ECAS#
DSP0_DDR3_ERAS#
DSP0_DDR3_ECS_0#
L3
K3
J3
L2
DSP0_DDR3_EDQSP_8
DSP0_DDR3_EDQSN_8
R390
4.7K
R389
4.7K
F3
G3
C7
B7
DSP0_DDR3_EDM_8
R387
4.7K
E7
D3
DSP0_DDR3_ECKP_0
DSP0_DDR3_ECKN_0
DSP0_DDR3_ECKE_0
J7
K7
K9
DSP0_DDR3_EODT_0
K1
DSP0_DDR3_EMRESETN
T2
240
1%
ECC_ZQ
DSP0_DDR3_EA15
DSP0_DDR3_EA14
L8
J1
J9
L1
L9
M7
T7
A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10/AP
A11
A12/BC
A13
BA0
BA1
BA2
WE
CAS
RAS
CS
DQSL
DQSL
DQSU
DQSU
DML
DMU
CK
CK
CKE
ODT
VDD_1
VDD_2
VDD_3
VDD_4
VDD_5
VDD_6
VDD_7
VDD_8
VDD_9
VDDQ_1
VDDQ_2
VDDQ_3
VDDQ_4
VDDQ_5
VDDQ_6
VDDQ_7
VDDQ_8
VDDQ_9
VREFCA
VREFDQ
DQL0
DQL1
DQL2
DQL3
DQL4
DQL5
DQL6
DQL7
DQU0
DQU1
DQU2
DQU3
DQU4
DQU5
DQU6
DQU7
RESET
ZQ
NC_1
NC_2
NC_3
NC_4
NC_5
NC_6
NL/SAMSUNG_K4B1G0846E-HCH9
VSS_1
VSS_2
VSS_3
VSS_4
VSS_5
VSS_6
VSS_7
VSS_8
VSS_9
VSS_10
VSS_11
VSS_12
VSSQ_1
VSSQ_2
VSSQ_3
VSSQ_4
VSSQ_5
VSSQ_6
VSSQ_7
VSSQ_8
VSSQ_9
B2
D9
G7
K2
K8
N1
N9
R1
R9
A1
A8
C1
C9
D2
E9
F1
H2
H9
C107
0.1uF
16V
C113
M8
H1
C108
0.1uF
16V
C109
0.1uF
16V
C110
0.1uF
16V
C111
0.1uF
16V
C112
22uF
6.3V
0.1uF
16V
Trace need 20 mil.
DSP_VREFSSTL
E3
DSP0_DDR3_ECC0
F7
DSP0_DDR3_ECC1
F2
DSP0_DDR3_ECC2
F8
DSP0_DDR3_ECC3
H3
DSP0_DDR3_ECC4
H8
DSP0_DDR3_ECC5
G2
DSP0_DDR3_ECC6
H7
DSP0_DDR3_ECC7
D7 ECC_NU R348
4.7K
C3
R353
4.7K
C8
R379
4.7K
C2
R382
4.7K
A7
R380
4.7K
A2
R381
4.7K
B8
R388
4.7K
A3
R383
4.7K
IN
BI
(13,24)
DSP_VREFSSTL
DSP0_DDR3_ECC[0..7]
(13)
C
A9
B3
E1
G8
J2
J8
M1
M9
P1
P9
T1
T9
B1
B9
D1
D8
E2
E8
F9
G1
G9
SAMSUNG_K4B1G1646E-HCH9
B
B
A
A
Designed for TI by ADVANTECH
Title
DDR3_ECC
Size
C
Date:
5
4
3
2
Document Number
Rev
A101-1
DSPM-8301E
Tuesday, March 08, 2011
Sheet
1
25
of
40
5
4
3
2
1
B4
0.5A
120_100MHz
VPLL
VCC3V3_AUX
C115
0.01uF
16V
D
VCC1V8_AUX
C116
0.1uF
16V
VCC3V3_AUX
C117
0.1uF
16V
B5
0.5A
120_100MHz
C118
0.1uF
16V
C119
0.1uF
16V
C120
0.1uF
16V
R94
5
GND_2
D4
PGB1010603
D5
PGB1010603
VCC5_VBUS
7
USB_DP
8
6
12.1K 1%
R95
4.7K
R138
10K
14
DP
ACBUS0
ACBUS1
ACBUS2
ACBUS3
ACBUS4
ACBUS5
ACBUS6
ACBUS7
REF
RESET
1%
63
(26)
62
GND_USB
VCC3V3_AUX
DM
61
EECS
EECLK
BCBUS0
BCBUS1
BCBUS2
BCBUS3
BCBUS4
BCBUS5
BCBUS6
BCBUS7
EEDATA
C
C132
0.1uF
16V
R956
4.7K
8
7
6
5
VCC
NC
ORG
GND
CS
SK
DI
DO
1
2
3
4
C130
33pF
50V
C131
33pF
50V
2
OSCI
Y2
12MHz_20pF
R102
2.2K
3
13
U12
ATMEL_AT93C46DN-SH-T
R103
10K
BDBUS0
BDBUS1
BDBUS2
BDBUS3
BDBUS4
BDBUS5
BDBUS6
BDBUS7
OSCO
TEST
VCC3V3_AUX
VCC3V3_AUX
26
27
28
29
30
32
33
34
R96
4.7K
R97
4.7K
2
19
VCCA
10
1
3
4
5
6
7
8
9
4.7K
VCC1V8
1V8_TCK
1V8_TDI
1V8_TDO
1V8_TMS
1V8_TRST#
1V8_EMU_00
1V8_EMU_01
TI_TXS0108EPWR
11
4
6
R100
22
FT_EMU0
8
R101
22
FT_EMU1
5
9
10
C
U11C
TI_SN74LVC00APWR
UART_FT_RX
UART_FT_TX
R204
OUT
IN
(11,16)
(11,16)
UART_FT_RX
UART_FT_TX
4.7K
VCC3V3_AUX
TP10
TP11
C135
0.1uF
16V
GND_1
GND_2
GND_3
GND_4
GND_5
GND_6
GND_7
GND_8
U11A
TI_SN74LVC00APWR
1
3
R104
2
4.7K
U254
FOR EMI
(15)
B6
0.5A
120_100MHz
B
B1
B2
B3
B4
B5
B6
B7
B8
R955
OE
A1
A2
A3
A4
A5
A6
A7
A8
U11B
TI_SN74LVC00APWR
13
60
36
R171
1K
20
18
17
16
15
14
13
12
R98
4.7K
U11D
TI_SN74LVC00APWR
12
48
52
53
54
55
57
58
59
38
39
40
41
43
44
45
46
FT_TDK
FT_TDI
FT_TDO
FT_TMS
FT_TRST#
FT_EMU0
FT_EMU1
VCC3V3_AUX
1
5
11
15
25
35
47
51
FTDI_FT2232HL
10
AGND
PWREN
SUSPEND
22
22
22
22
22
VCCB
20
31
42
56
12
37
64
VREGOUT
R88
R89
R91
R92
R93
GND
90 OHM DIFF. IMPEDANCE CONTROL
4
GND_1
ADBUS0
ADBUS1
ADBUS2
ADBUS3
ADBUS4
ADBUS5
ADBUS6
ADBUS7
FT_TDK_R
FT_TDI_R
FT_TDO_R
FT_TMS_R
FT_TRST#_R
GPIOL1
GPIOL2
GPIOL3
11
Mini-AB
3
USB_DM
U10
16
17
18
19
21
22
23
24
14
6
7
8
9
PTH_1
PTH_2
PTH_3
PTH_4
2
DATA-
NPH_1
NPH_2
49
VREGIN
0.1uF
16V
10
11
MINIUSB_5H
50
R137
0
5%
DATA+
VCC1V8_AUX
C125
0.1uF
16V
7
GND_USB
C129
D
C124
0.1uF
16V
VCCIO_1
VCCIO_2
VCCIO_3
VCCIO_4
VPHY
VPLL
4
9
U9
VCC5_VBUS
1
C123
0.1uF
16V
VPLL
VPHY
(26)
+5V
C122
0.1uF
16V
VCC3V3_AUX
C127
0.1uF
16V
VCORE_1
VCORE_2
VCORE_3
C126
0.01uF
16V
USB1
C121
0.1uF
16V
VPHY
VCC3V3_AUX
(15)
(15)
(15)
(15)
(15)
(26)
GND_USB
EXT_EMU_DET0
EMU_TCK
EMU_TDI
EMU_TDO
EMU_TMS
EMU_TRST#
EMU_EMU_00
EMU_EMU_01
24
IN
48
47
42
41
35
34
29
28
IN
IN
OUT
IN
IN
BI
BI
1V8_TCK
1V8_TDI
1V8_TDO
1V8_TMS
1V8_TRST#
1V8_EMU_00
1V8_EMU_01
45
44
39
38
32
31
26
25
46
43
40
37
33
30
SEL
NC
0B1
1B1
2B1
3B1
4B1
5B1
6B1
7B1
A0
A1
A2
A3
A4
A5
A6
A7
(15)
(15)
0B2
1B2
2B2
3B2
4B2
5B2
6B2
7B2
GND17
GND16
GND15
GND14
GND13
GND12
VDD1
VDD2
VDD3
VDD4
VDD5
GND1
GND2
GND3
GND4
GND5
GND6
GND7
GND8
GND9
GND10
GND11
14
2
4
8
10
15
17
21
23
OUT
OUT
IN
OUT
OUT
BI
BI
1
6
12
19
36
3
5
7
9
11
13
16
18
20
22
27
(15)
(15)
(15)
(15)
(15)
(15)
(15)
DSP_TCK
DSP_TDI
DSP_TDO
DSP_TMS
DSP_TRST#
DSP_EMU_00
DSP_EMU_01
B
VCC3V3_AUX
C133
0.1uF
16V
C134
0.1uF
16V
C396
10uF
6.3V
TI_TS3L301DGG
Switch for JTAG emulation
EXT_EMU_DET = 0 --> External / Mezzanine Emulator
EXT_EMU_DET = 1 --> On board emulation
A
A
Designed for TI by ADVANTECH
Title
USB-JTAG
Size
C
Date:
5
4
3
2
Document Number
Rev
A101-1
DSPM-8301E
Tuesday, March 08, 2011
Sheet
1
26
of
40
4
3
R121
(12)
DSP_MDC_1
DSP_MDIO_1
PHY_INT#
VCC2V5
(31)
IN
BI
OUT
4.7K
GTX_CLK
TX_CLK
TX_EN
TX_ER
TXD0
TXD1
TXD2
TXD3
TXD4
TXD5
TXD6
TXD7
P1_COL_PD
L3
M1
L1
(12)
R764
E2
D1
E1
F2
F1
G2
G3
H2
H1
H3
J1
J2
C1
B1
D2
B2
D3
C3
B3
C4
A1
A2
C5
B5
B6
10K
1%
TP4
C
P1_CONFIG0
P1_CONFIG1
P1_CONFIG2
P1_CONFIG3
P1_CONFIG4
P1_CONFIG5
P1_CONFIG6
P1_CLKSEL
G1
K7
C6
C7
D7
E3
E7
F3
J3
J7
M3
M4
M7
M8
N5
B7
AVDD_1
AVDD_2
AVDD_3
AVDD_4
AVDD_5
AVDD_6
K9
L2
B4
C2
K1
R763
GTX_CLK
TX_CLK
TX_EN
TX_ER
TXD0
TXD1
TXD2
TXD3
TXD4
TXD5
TXD6
TXD7
RX_CLK
RX_DV
RX_ER
RXD0
RXD1
RXD2
RXD3
RXD4
RXD5
RXD6
RXD7
CRS
COL
MDI3+
MDI3MDI2+
MDI2MDI1+
MDI1MDI0+
MDI0S_IN+
S_INS_OUT+
S_OUTS_CLK+
S_CLK-
88E1111-BAB
LED_LINK10
LED_LINK100
LED_LINK1000
LED_DUPLEX
LED_RX
LED_TX
MARVELL_88E1111-B2-BAB1C000
TDI
TMS
TCK
TRST
TDO
MDC
MDIO
INT
125CLK
CONFIG0
CONFIG1
CONFIG2
CONFIG3
CONFIG4
CONFIG5
CONFIG6
SEL_FREQ
HSDAC+
HSDACRSET
RESET
COMA
XTAL1
XTAL2
NC_1
NC_2
D4
G6
J5
J6
K4
K5
K6
L5
L6
D5
D6
E4
E5
E6
F4
F5
F6
G4
G5
H4
H5
H6
J4
VSS_1
VSS_2
VSS_3
VSS_4
VSS_5
VSS_6
VSS_7
VSS_8
VSS_9
VSS_10
VSS_11
VSS_12
VSS_13
VSS_14
VSS_15
VSS_16
VSS_17
VSS_18
VSS_19
VSS_20
VSS_21
VSS_22
VSS_23
PHY Strap Options: see below
K2
D8
E9
F8
G7
F9
G9
G8
H8
VCC1V2
N8
N9
N6
N7
N3
N4
N1
N2
MDI3_P
MDI3_N
MDI2_P
MDI2_N
MDI1_P
MDI1_N
MDI0_P
MDI0_N
A3
A4
A7
A8
A5
A6
DSP_SGMII_TXP_C
C136
DSP_SGMII_TXN_C
C137
DSP_SGMII_RXP
DSP_SGMII_RXN
R391
4.99K 1%
R392
4.99K 1%
MDI3_P
MDI3_N
MDI2_P
MDI2_N
MDI1_P
MDI1_N
MDI0_P
MDI0_N
BI
BI
BI
BI
BI
BI
BI
BI
0.1uF 16V
0.1uF 16V
(28)
(28)
(28)
(28)
(28)
(28)
(28)
(28)
DSP_SGMII_TXP
DSP_SGMII_TXN
P1_CONFIG2
L7
L8
L9
M9
K8
R762
R773
0
VCC2V5
R778
0
LED_LINK10
R774
0
LED_LINK1000
R775
0
R779
0
LED_DUPLEX
R776
0
LED_TX
R777
0
111
P1_CONFIG5
D
10K
1%
VCC2V5
110
P1_CONFIG1
100
IN
IN
OUT
OUT
DSP_SGMII_TXP
DSP_SGMII_TXN
DSP_SGMII_RXP
DSP_SGMII_RXN
P1_CONFIG4
(12)
(12)
(12)
(12)
100
P1_CONFIG3
011
P1_CONFIG0
C8
B8
A9
E8
C9
D9
P1_CLKSEL
NL/10K
1%
001
LED_LINK10
LED_LINK100
LED_LINK1000
LED_DUPLEX
LED_RX
LED_TX
R431
0
R432
22
OUT
OUT
LED_LINK100
LED_LINK1000
(28)
(28)
OUT
LED_RX
(28)
IN
IN
IN
IN
OUT
P1_CONFIG6
000
(32)
(32,33)
(32)
(30,32,33)
(32)
PHY_JTAG_TDI
PHY_9222_JTAG_TMS
PHY_JTAG_TCK
FPGA_JTAG_RST#
PHY_JTAG_TDO
M5
M6
C
M2
P1_RSET
R125
K3
L4
R_P1_LAN_RST#
R126
H9
J9
PHY_P1_XTAL1
PHY_P1_XTAL2
4.99K
1%
0
PHY_RST#
IN
PHY_RST#
(31)
R393
4.99K
1%
VSSC
4.7K
NL/4.7K
4.7K
4.7K
4.7K
4.7K
4.7K
4.7K
4.7K
4.7K
4.7K
4.7K
1
H7
R107
R108
R109
R110
R111
R112
R113
R114
R115
R116
R117
R118
VDDO_1
VDDO_2
VDDO_3
D
AVCC2V5
VDDOX_1
VDDOX_2
VDDOH_1
VDDOH_2
VDDOH_3
PHY1
B9
F7
J8
VCC2V5
2
DVDD_1
DVDD_2
DVDD_3
DVDD_4
DVDD_5
DVDD_6
DVDD_7
DVDD_8
5
PHY_P1_XTAL1_R
R127
0
PHY_P1_XTAL1
Y3
25MHz_20pF
PHY_P1_XTAL2
C138
27pF
50V
Pin to Constant Mapping
88E1111 Device Pin to Configuration Bit Mapping
B
Pin
CONFIG0
CONFIG1
CONFIG2
CONFIG3
CONFIG4
CONFIG5
CONFIG6
Bit[2]
PHYADR[2]
ENA_PAUSE
ANEG[3]
ANEG[0]
HWCFG_MODE[2]
DIS_FC
SEL_TWSI
Bit[1]
PHYADR[1]
PHYADR[4]
ANEG[2]
ENA_XC
HWCFG_MODE[1]
DIS_SLEEP
INT_POL
Pin
A
LED Pin
Connection
001
100
111
011
CONFIG0
CONFIG1
CONFIG2
CONFIG3
CONFIG4
CONFIG5
CONFIG6
100
110
000
Pin
Bit[0]
Bit[2:0]
B
VDDO
LED_LINK10
LED_LINK100
LED_LINK1000
LED_DUPLEX
LED_RX
LED_TX
VSS
PHYADR[0]
PHYADR[3]
ANEG[1]
DIS_125
HWCFG_MODE[0]
HWCFG_MODE[3]
75/50 OHM
CONFIG Pin Connection
PHY Address = 0x01
Hardware
Configuration
Bit Setting
LED_TX
LED_LINK1000
VDDO
LED_DUPLEX
LED_LINK1000
LED_LINK10
VSS
C139
27pF
50V
111
110
101
100
011
010
001
000
AVCC2V5
VCC2V5
B7
0.5A
120_100MHz
C140
0.01uF
16V
C141
0.1uF
16V
C142
4.7uF
6.3V
C149
0.1uF
16V
C150
4.7uF
6.3V
C143
0.01uF
16V
C144
0.1uF
16V
C146
0.1uF
16V
C145
4.7uF
6.3V
C147
4.7uF
6.3V
VCC1V2
PHY Configuration
C148
0.01uF
16V
C151
0.01uF
16V
C152
0.1uF
16V
C153
4.7uF
6.3V
PHY Address bit[2:0] 001
A
Enable Pause ,PHY Address bit[4:3] = 00
Auto-Neg advertise all capabilities ,prefer Master
Enable MDI crossover, disable 125CLK
Designed for TI by ADVANTECH
SGMII without Clock with SGMII Auto-Neg to copper
Disable fiber /copper Auto-detect, Disable sleep
Select MDIO interface, INT signal active high, 50 ohm SERDES
Title
Gigabit Ethernet PHY
Size
C
Date:
5
4
3
2
Document Number
Rev
A101-1
DSPM-8301E
Tuesday, March 08, 2011
Sheet
1
27
of
40
5
4
3
2
RJ-45
1
P1_TCT
B2
0.5A
120_100MHz
VCC2V5
C23
0.1uF
16V
C25
0.1uF
16V
C26
0.1uF
16V
C27
0.1uF
16V
C28
0.1uF
16V
D
D
C21
0.1uF
16V
C22
0.1uF
16V
P1_RC_P00
P1_RC_P01
C24
470pF
50V
LAN1
R26
49.9
1%
R27
49.9
1%
R28
49.9
1%
(27)
R29
49.9
1%
LED_RX
LED_RX
IN
R30
100
LAN_ACT
13
G
14
VCC2V5
11
MDI0_P
BI
(27)
MDI0_P
MDI0_N
BI
(27)
MDI0_N
P1_TCT
12
1
TX1+
10
TX12
4
MDI1_P
BI
(27)
MDI1_P
MDI1_N
BI
(27)
MDI1_N
P1_TCT
6
3
TX2+
5
TX26
3
MDI2_P
BI
(27)
MDI2_P
MDI2_N
BI
(27)
MDI2_N
P1_TCT
1
4
TX3+
2
TX35
8
C
MDI3_P
BI
(27)
MDI3_P
MDI3_N
BI
(27)
MDI3_N
P1_TCT
P1_RC_P03
R32
49.9
1%
R33
49.9
1%
R34
(27)
49.9
(27)
1%
LED_LINK100
LED_LINK1000
IN
IN
LED_LINK100
LED_LINK1000
7
TX4+
9
TX48
16
VCC2V5
R31
49.9
1%
7
G
R35
R36
100
100
O
17
15
C
H1
H2
H3
H4
75R
1000pF 2kV
SHIELD GND
P1_RC_P02
GND_LAN
RJ45_W/XFMR&LED
C29
0.1uF
16V
C30
0.1uF
16V
FOR EMI
B3
0.5A
120_100MHz
GND_LAN
B
B
Heatsink Holes
BRK1
SOCKET841_CSBGA841
H1
H2
1
1
H35-NPTH
H35-NPTH
3
6
On board
FM1
4
FM2
NL/Fiducial
NL/Fiducial
5
2
1
H4
H3
FM3
1
1
H35-NPTH
H35-NPTH
FM4
NL/Fiducial
NL/Fiducial
A
A
Designed for TI by ADVANTECH
Title
RJ45
Size
C
Date:
5
4
3
2
Document Number
Rev
A101-1
DSPM-8301E
Tuesday, March 08, 2011
Sheet
1
28
of
40
5
4
3
2
1
IPASS+HD for HyperLink Bus connection
D
D
Hyperlink1
iPass Plus HD 1x1 Assy
HyperLink_RXPMCLK
HyperLink_RXFLDAT
OUT
IN
D1
D2
D3
D4
D5
D6
D7
D8
D9
HyperLink_RXPMCLK
HyperLink_RXFLDAT
HyperLink_TXP0
HyperLink_TXN0
(12)
(12)
HyperLink_TXP0
HyperLink_TXN0
IN
IN
(12)
(12)
HyperLink_TXP2
HyperLink_TXN2
IN
IN
(12)
(12)
HyperLink_RXPMDAT
HyperLink_TXFLDAT
OUT
IN
HyperLink_TXP2
HyperLink_TXN2
HyperLink_RXP0
HyperLink_RXN0
OUT
OUT
(12)
(12)
HyperLink_RXP2
HyperLink_RXN2
OUT
OUT
B1
B2
B3
B4
B5
B6
B7
B8
B9
HyperLink_RXPMDAT
HyperLink_TXFLDAT
HyperLink_RXP0
HyperLink_RXN0
HyperLink_RXP2
HyperLink_RXN2
sideband4
sideband2
GND_C3
Txp1
Txn1
GND_C6
Txp3
Txn3
GND_C9
sideband3
sideband1
GND_B3
Rxp0
Rxn0
GND_B6
Rxp2
Rxn2
GND_B9
sideband7
sideband0
GND_A3
Rxp1
Rxn1
GND_A6
Rxp3
Rxn3
GND_A9
H1
H2
(12)
(12)
sideband5
sideband6
GND_D3
Txp0
Txn0
GND_D6
Txp2
Txn2
GND_D9
NPTH1
NPTH2
(12)
(12)
C1
C2
C3
C4
C5
C6
C7
C8
C9
HyperLink_TXPMDAT
HyperLink_TXPMCLK
A1
A2
A3
A4
A5
A6
A7
A8
A9
HyperLink_TXFLCLK
HyperLink_RXFLCLK
HyperLink_TXP1
HyperLink_TXN1
HyperLink_TXP3
HyperLink_TXN3
HyperLink_RXP1
HyperLink_RXN1
HyperLink_RXP3
HyperLink_RXN3
IN
IN
HyperLink_TXPMDAT
HyperLink_TXPMCLK
(12)
(12)
IN
IN
HyperLink_TXP1
HyperLink_TXN1
(12)
(12)
IN
IN
HyperLink_TXP3
HyperLink_TXN3
(12)
(12)
OUT
IN
HyperLink_TXFLCLK
HyperLink_RXFLCLK
(12)
(12)
OUT
OUT
HyperLink_RXP1
HyperLink_RXN1
(12)
(12)
OUT
OUT
HyperLink_RXP3
HyperLink_RXN3
(12)
(12)
IPASS+HD_36H
C
C
Pin Header for debug
the interfaces on the 80-pin header are all
1.8V LVCMOS except for the UART which
is 3.3V LVCMOS
H2
TEST_PH1
(14)
(14)
(14)
(14)
(14)
(14)
(14)
(14)
(14)
(14)
(14)
(14)
(14)
(14)
(14)
(14)
(14)
(14)
(14)
(14)
(14)
(14)
(14)
(14)
B
DSP_EMIFA00
DSP_EMIFA01
DSP_EMIFA02
DSP_EMIFA03
DSP_EMIFA04
DSP_EMIFA05
DSP_EMIFA06
DSP_EMIFA07
DSP_EMIFA08
DSP_EMIFA09
DSP_EMIFA10
DSP_EMIFA11
DSP_EMIFA12
DSP_EMIFA13
DSP_EMIFA14
DSP_EMIFA15
DSP_EMIFA16
DSP_EMIFA17
DSP_EMIFA18
DSP_EMIFA19
DSP_EMIFA20
DSP_EMIFA21
DSP_EMIFA22
DSP_EMIFA23
DSP_GPIO_00
DSP_GPIO_01
DSP_GPIO_02
DSP_GPIO_03
DSP_GPIO_04
DSP_GPIO_05
DSP_GPIO_06
DSP_GPIO_07
DSP_GPIO_08
DSP_GPIO_09
DSP_GPIO_10
DSP_GPIO_11
DSP_GPIO_12
DSP_GPIO_13
DSP_GPIO_14
DSP_GPIO_15
DSP_EMIFA00
DSP_EMIFA01
DSP_EMIFA02
DSP_EMIFA03
DSP_EMIFA04
DSP_EMIFA05
DSP_EMIFA06
DSP_EMIFA07
DSP_EMIFA08
DSP_EMIFA09
DSP_EMIFA10
DSP_EMIFA11
DSP_EMIFA12
DSP_EMIFA13
DSP_EMIFA14
DSP_EMIFA15
DSP_EMIFA16
DSP_EMIFA17
DSP_EMIFA18
DSP_EMIFA19
DSP_EMIFA20
DSP_EMIFA21
DSP_EMIFA22
DSP_EMIFA23
DSP_GPIO_00
DSP_GPIO_01
DSP_GPIO_02
DSP_GPIO_03
DSP_GPIO_04
DSP_GPIO_05
DSP_GPIO_06
DSP_GPIO_07
DSP_GPIO_08
DSP_GPIO_09
DSP_GPIO_10
DSP_GPIO_11
DSP_GPIO_12
DSP_GPIO_13
DSP_GPIO_14
DSP_GPIO_15
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
1
3
5
7
9
11
13
15
17
19
21
23
25
27
29
31
33
35
37
39
41
43
45
47
49
51
53
55
57
59
61
63
65
67
69
71
73
75
77
79
DSP_SDA
DSP_SCL
DSP_EMIFD0
DSP_EMIFD1
DSP_EMIFD2
DSP_EMIFD3
DSP_EMIFD4
DSP_EMIFD5
DSP_EMIFD6
DSP_EMIFD7
DSP_EMIFD8
DSP_EMIFD9
DSP_EMIFD10
DSP_EMIFD11
DSP_EMIFD12
DSP_EMIFD13
DSP_EMIFD14
DSP_EMIFD15
DSP_EMIFCE1Z
DSP_EMIFCE2Z
DSP_EMIFBE0Z
DSP_EMIFBE1Z
DSP_EMIFOEZ
DSP_EMIFWEZ
DSP_EMIFRNW
DSP_EMIFWAIT1
DSP_TIMI0
DSP_TIMO0
DSP_TIMI1
DSP_TIMO1
R399
10 5%
DSP_SSPMOSI
DSP_SSPCS1
PH_SSPCK
DSP_UARTTXD
DSP_UARTRXD
DSP_UARTRTS
DSP_UARTCTS
BI
IN
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
IN
IN
IN
IN
IN
IN
IN
OUT
OUT
IN
OUT
IN
DSP_SSPMISO
OUT
IN
IN
IN
IN
OUT
IN
OUT
DSP_SDA
DSP_SCL
DSP_EMIFD0
DSP_EMIFD1
DSP_EMIFD2
DSP_EMIFD3
DSP_EMIFD4
DSP_EMIFD5
DSP_EMIFD6
DSP_EMIFD7
DSP_EMIFD8
DSP_EMIFD9
DSP_EMIFD10
DSP_EMIFD11
DSP_EMIFD12
DSP_EMIFD13
DSP_EMIFD14
DSP_EMIFD15
DSP_EMIFCE1Z
DSP_EMIFCE2Z
DSP_EMIFBE0Z
DSP_EMIFBE1Z
DSP_EMIFOEZ
DSP_EMIFWEZ
DSP_EMIFRNW
DSP_EMIFWAIT1
DSP_TIMI0
DSP_TIMO0
DSP_TIMI1
DSP_TIMO1
DSP_SSPMISO
DSP_SSPMOSI
DSP_SSPCS1
PH_SSPCK
DSP_UARTTXD
DSP_UARTRXD
DSP_UARTRTS
DSP_UARTCTS
(10,16)
(10,16)
(14)
(14)
(14)
(14)
(14)
(14)
(14)
(14)
(14)
(14)
(14)
(14)
(14)
(14)
(14)
(14)
(14)
(14)
(14)
(14)
(14)
(14)
(14)
(14)
(16,31)
(16)
(16)
(16)
(16,30)
(16,30)
(16,30)
(16)
(16)
(16)
(16)
(16)
B
A
H1
A
(16,31)
(16,31)
(16,31)
(16,31)
(16,31)
(16,31)
(16,31)
(16,31)
(16,31)
(16,31)
(16,31)
(16,31)
(16,31)
(16,31)
(16,31)
(16,31)
2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
42
44
46
48
50
52
54
56
58
60
62
64
66
68
70
72
74
76
78
80
PH(F)_40x2V_S1.27mm
DSP_UART(3.3V)
Designed for TI by ADVANTECH
Title
Connectors for HyperLink & Debug
Size
C
Date:
5
4
3
2
Document Number
Rev
A101-1
DSPM-8301E
Tuesday, March 08, 2011
Sheet
1
29
of
40
5
4
3
2
TDM_CLKA_P
TDM_CLKB_P
TDM_CLKC_P
TDM_CLKD_P
D
R228
R317
R318
R319
1
TDM_CLKA_N
TDM_CLKB_N
TDM_CLKC_N
TDM_CLKD_N
100
100
100
100
D
Place near to FPGA
VCC3V3_FPGA
MMC
VCL/VDA Eable
POWER SEQUENCE
C
POWER UCD9222
(11)
(11)
(11)
(11)
(11)
(17)
MMC_DETECT#
MMC_RESETSTAT#
MMC_POR_IN_AMC#
MMC_WR_AMC#
MMC_BOOTCOMPLETE
PCA9306_EN
IN
OUT
IN
IN
OUT
OUT
(35)
(34)
(35)
(34)
(36)
VCC5_PGOOD
VCC2V5_PGOOD
VCC3V3_AUX_PGOOD
VCC0V75_PGOOD
VCC1V5_PGOOD
IN
IN
IN
IN
IN
(36)
VCC1V5_EN
OUT
(34)
(34)
(34)
(35)
(33)
(33)
(33)
(33)
(33)
(33)
(33)
VCC1V8_EN1
VCC0V75_EN
VCC2V5_EN
VCC_5V_EN
UCD9222_PG2
UCD9222_ENA2
UCD9222_PG1
UCD9222_ENA1
PGUCD9222
UCD9222_RST#
PMBUS_CLK
PMBUS_DAT
PMBUS_ALT
PMBUS_CTL
OUT
OUT
OUT
OUT
IN
OUT
IN
OUT
IN
OUT
OUT
BI
IN
OUT
(33)
(33)
MMC_DETECT#
MMC_RESETSTAT#
MMC_POR_IN_AMC#
MMC_WR_AMC#
MMC_BOOTCOMPLETE
PCA9306_EN
VCC5_PGOOD
VCC2V5_PGOOD
VCC3V3_AUX_PGOOD
VCC0V75_PGOOD
VCC1V5_PGOOD
FPGA_JTAG_RST#
VCC1V8_EN1
VCC0V75_EN
VCC2V5_EN
VCC_5V_EN
UCD9222_PG2
UCD9222_ENA2
UCD9222_PG1
UCD9222_ENA1
PGUCD9222
UCD9222_RST#
PMBUS_CLK R153
PMBUS_DAT R154
PMBUS_ALT R155
PMBUS_CTL R156
DSP_VCL_FPGA
DSP_VD_FPGA
SYS_PGOOD
AMC TDM CLOCK
(10)
(10)
1K
1K
1K
1K
PMBUS_CLK_R
PMBUS_DAT_R
PMBUS_ALT_R
PMBUS_CTL_R
FULL_RESET
WARM_RESET
Cold_RESET
FPGA_JTAG_RST#
IN
TDM_CLKA_N
TDM_CLKA_P
IN
IN
TDM_CLKC_N
TDM_CLKC_P
TDM_CLKD_N
IN
TDM_CLKD_P
IN
(10)
(10)
IN
IN
(10)
(10)
IN
IN
R159
VCC3V3_FPGA
B33
120_100MHz
FPGA1A
TP15
0
(33) 0
0
0
TDM_CLKB_N
TDM_CLKB_P
(10)
(10)
10K
R79
R80
R81
R84
TP16
VCC1V5_EN
Switches RESET
(27,32,33)
R201
0
5%
2A
C600
0.1uF
B
C599
0.1uF
C546
0.1uF
C384
0.1uF
N14
N13
P15
R15
N16
P16
M14
M13
K13
L13
M16
M15
L16
L14
J13
J12
K14
K15
J16
K16
H14
J14
H16
H15
F16
G16
G14
H13
F15
E16
F14
G13
F13
E14
D15
D16
D14
E13
C15
C16
K12
K11
J11
J10
H11
H10
G11
G12
F11
F12
R16
E15
H12
J15
N15
IO_L01N_1/LDC2
IO_L01P_1/HDC
IO_L02N_1/LDC0
IO_L02P_1/LDC1
IO_L03N_1/A1
IO_L03P_1/A0
IO_L05N_1/VREF_1_1
IO_L05P_1
IO_L06N_1/A3
IO_L06P_1/A2
IO_L07N_1/A5
IO_L07P_1/A4
IO_L08N_1/A7
IO_L08P_1/A6
IO_L10N_1/A9
IO_L10P_1/A8
IO_L11N_1/RHCLK1
IO_L11P_1/RHCLK0
IO_L12N_1/TRDY1/RHCLK3
IO_L12P_1/RHCLK2
IO_L14N_1/RHCLK5
IO_L14P_1/RHCLK4
IO_L15N_1/RHCLK7
IO_L15P_1/IRDY1/RHCLK6
IO_L16N_1/A11
IO_L16P_1/A10
IO_L17N_1/A13
IO_L17P_1/A12
IO_L18N_1/A15
IO_L18P_1/A14
IO_L19N_1/A17
IO_L19P_1/A16
IO_L20N_1/A19
IO_L20P_1/A18
IO_L22N_1/A21
IO_L22P_1/A20
IO_L23N_1/A23
IO_L23P_1/A22
IO_L24N_1/A25
IO_L24P_1/A24
IP_L04N_1/VREF_1_2
IP_L04P_1
IP_L09N_1
IP_L09P_1/VREF_1_3
IP_L13N_1
IP_L13P_1
IP_L21N_1
IP_L21P_1/VREF_1_4
IP_L25N_1
IP_L25P_1/VREF_1_5
SUSPEND
VCCO_1_1
VCCO_1_2
VCCO_1_3
VCCO_1_4
Bank1
IO_L01N_0
IO_L01P_0
IO_L02N_0
IO_L02P_0/VREF_0_1
IO_L03N_0
IO_L03P_0
IO_L04N_0
IO_L04P_0
IO_L05N_0
IO_L05P_0
IO_L06N_0/VREF_0_2
IO_L06P_0
IO_L07N_0
IO_L07P_0
IO_L08N_0
IO_L08P_0
IO_L09N_0/GCLK5
IO_L09P_0/GCLK4
IO_L10N_0/GCLK7
IO_L10P_0/GCLK6
IO_L11N_0/GCLK9
IO_L11P_0/GCLK8
IO_L12N_0/GCLK11
IO_L12P_0/GCLK10
IO_L13N_0
IO_L13P_0
IO_L14N_0/VREF_0_3
IO_L14P_0
IO_L15N_0
IO_L15P_0
IO_L16N_0
IO_L16P_0
IO_L17N_0
IO_L17P_0
IO_L18N_0
IO_L18P_0
IO_L19N_0
IO_L19P_0
IO_L20N_0/PUDC
IO_L20P_0/VREF_0_4
IP_0_1
IP_0_2
IP_0_3
IP_0_4
IP_0_5
IP_0_6
IP_0_7/VREF_0_5
VCCO_0_1
VCCO_0_2
VCCO_0_3
VCCO_0_4
Bank0
C13
D13
B14
B15
D11
C12
A13
A14
A12
B12
E10
D10
A11
C11
A10
B10
D9
C10
A9
C9
D8
C8
B8
A8
C7
A7
E7
F8
B6
A6
C6
D7
C5
A5
B4
A4
B3
A3
D5
C4
D6
D12
E6
F7
F9
F10
E9
B5
B9
B13
E8
DSP_RESETSTAT#
TRGRSTZ
EEPROM_WP
NOR_WP#
IN
IN
OUT
OUT
DSP_RESETSTAT#
TRGRSTZ
EEPROM_WP
NOR_WP#
(16)
(15)
(16)
(16)
IN
IN
OUT
IN
DSP_SSPCS1
FPGA_SSPCK
DSP_SSPMISO
DSP_SSPMOSI
(16,29)
(16)
(16,29)
(16,29)
DSP
60 PIN Header
EEPROM
NOR FLASH
TP13
TP14
DSP_SSPCS1
R400
10
DSP_SSPMISO
DSP_SSPMOSI
DSP_PACLKSEL
DSP_LRESETNMIENZ
DSP_CORESEL0
DSP_CORESEL1
DSP_CORESEL2
DSP_CORESEL3
DSP_NMIZ
DSP_LRESETZ
DSP_HOUT
DSP_BOOTCOMPLETE
DSP_SYSCLKOUT
VCC1V8_PGOOD
R99
DSP_PORZ
DSP_RESETFULLZ
DSP_RESETZ
(16)
DSP_PACLKSEL
(16)
DSP_LRESETNMIENZ
(16)
DSP_CORESEL0
(16)
DSP_CORESEL1
(16)
DSP_CORESEL2
(16)
DSP_CORESEL3
(16)
DSP_NMIZ
(16)
DSP_LRESETZ
IN
DSP_HOUT
IN
DSP_BOOTCOMPLETE
IN
DSP_SYSCLKOUT
1K 1%
VCC1V8
(16)
OUT
DSP_PORZ
(16)
OUT
DSP_RESETFULLZ
(16)
DSP_RESETZ
OUT
OUT
NAND_WP#
(15)
OUT
DSP_TSIP0_CLKA0
(15)
OUT
DSP_TSIP0_CLKB0
(15)
OUT
DSP_TSIP1_CLKA1
(15)
OUT
DSP_TSIP1_CLKB1
OUT
DSP_TSIP0_FSA0
DSP_TSIP0_FSB0
OUT
OUT
DSP_TSIP1_FSA1
OUT
DSP_TSIP1_FSB1
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
DSP_TSIP0_CLKA0
DSP_TSIP0_CLKB0
DSP_TSIP1_CLKA1
DSP_TSIP1_CLKB1
DSP_TSIP0_FSA0
DSP_TSIP0_FSB0
DSP_TSIP1_FSA1
DSP_TSIP1_FSB1
FPGA_PUDC
XDS560_IL
OUT
C533
0.1uF
C532
0.1uF
120_100MHz
DSP TMS320C6678
C
(16)
(16)
(17)
DSP RESETS
(14)
(15)
(15)
(15)
(15)
DSP TSIP_CLK/FS
(15)
XDS560_IL
B34
C383
0.1uF
16V
DSP SPI
2A
VCC1V8_AUX
C531
0.1uF
VCC1V8_AUX
B
XILINX_XC3S200AN-4FTG256C
R181
10K
1%
FPGA_PUDC
IN
BI
VCC3V3_FPGA
SW7-P1
1
HDK632AR-ST
Cold_RESET
C9
0.01uF
16V
RST_WARM1
HDK632AR-ST
3
4
A
R74
8.2K
5%
R68
100
VCC3V3_FPGA
FULL_RESET
WARM_RESET
C11
0.01uF
16V
3
4
SW8-P1
RST_FULL1
HDK632AR-ST
3
4
SYS_PGOOD
R139
8.2K
5%
R140
100
FULL_RESET
C13
0.01uF
16V
R184
330
5%
High active
PUDC:
User I/O Pull-Up Control. When
Low during configuration, enables
pull-up resistors in all I/O pins to
respective I/O bank VCCO input.
0: Pull-ups during configuration
1: No pull-ups
SYSPG_D1
B
1
R8
100
RST_COLD1
2
SW1-P1
R5
8.2K
5%
VCC3V3_FPGA
WARM_RESET
2
Cold_RESET
R182
NL/10K
1%
(17)
(17)
DSP_VCL_1
DSP_VD_1
1
DSP_VCL_1
DSP_VD_1
NL/0
NL/0
2
R394
R395
DSP_VCL_FPGA
DSP_VD_FPGA
1
PMBUS_CLK
PMBUS_DAT
NL/0
NL/0
2
R409
R410
19-215SUBC/S280/TR8
A
Designed for TI by ADVANTECH
Title
FPGA_XC3S200AN_A
Size
C
Date:
5
4
3
2
Document Number
Rev
A101-1
DSPM-8301E
Tuesday, March 08, 2011
Sheet
1
30
of
40
5
4
3
2
1
Boot Configuration
BOOT STRAP CONFIGURATION
default value : TBD
VCC1V8_AUX
VCC3V3_FPGA
VCC3V3_FPGA
VCC3V3_FPGA
VCC3V3_FPGA
R209
R210
R213
R215
10K
10K
10K
10K
BM_GPIO_00
BM_GPIO_01
BM_GPIO_02
BM_GPIO_03
SW3
ESD104EZ
1
ON
2
3
4
R284
R265
R296
R264
10K
10K
10K
10K
BM_GPIO_04
BM_GPIO_05
BM_GPIO_06
BM_GPIO_07
SW4
ESD104EZ
1
ON
2
3
4
8
7
6
5
R285
R289
R283
R297
100
100
100
100
R301
R299
R304
R298
10K
10K
10K
10K
BM_GPIO_08
BM_GPIO_09
BM_GPIO_10
BM_GPIO_11
SW5
ESD104EZ
ON
1
2
3
4
8
7
6
5
R302
R303
R300
R305
100
100
100
100
R309
R308
R312
R306
10K
10K
10K
10K
BM_GPIO_12
BM_GPIO_13
BM_GPIO_14
BM_GPIO_15
SW6
ESD104EZ
1
ON
2
3
4
8
7
6
5
R310
R311
R307
R313
100
100
100
100
R408
R407
10K
10K
PCIESSEN
User_define
1
2
4
3
R403
R402
100
100
D
R923
1K
R191
330
R192
330
R193
NL/330
FPGA_INIT#
FPGA_M0
FPGA_M1
FPGA_M2
R924
NL/0
R197
NL/0
R198
NL/0
R199
0
8
7
6
5
R211
R212
R214
R216
100
100
100
100
ON
FPGA1B
C
For BOOT MODE
SWITCH
DSP_GPIO_00
DSP_GPIO_01
DSP_GPIO_02
DSP_GPIO_03
DSP_GPIO_04
DSP_GPIO_05
DSP_GPIO_06
DSP_GPIO_07
DSP_GPIO_08
DSP_GPIO_09
DSP_GPIO_10
DSP_GPIO_11
DSP_GPIO_12
DSP_GPIO_13
DSP_GPIO_14
DSP_GPIO_15
DSP GPIO
TO FPGA
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
PCIESSEN
User_define
(16,29)
DSP_TIMI0
OUT
DSP_TIMI0
B
VCC1V8_AUX
B35
2A
120_100MHz
C439
0.1uF
C436
0.1uF
C390
0.1uF
C389
0.1uF
Bank3
Bank2
IO_L01N_2/M0
IO_L01P_2/M1
IO_L02N_2/CSO
IO_L02P_2/M2
IO_L03N_2/VS2
IO_L03P_2/RDWR
IO_L04N_2/VS0
IO_L04P_2/VS1
IO_L05N_2
IO_L05P_2
IO_L06N_2/D6
IO_L06P_2/D7
IO_L07N_2
IO_L07P_2
IO_L08N_2/D4
IO_L08P_2/D5
IO_L09N_2/GCLK13
IO_L09P_2/GCLK12
IO_L10N_2/GCLK15
IO_L10P_2/GCLK14
IO_L11N_2/GCLK1
IO_L11P_2/GCLK0
IO_L12N_2/GCLK3
IO_L12P_2/GCLK2
IO_L13N_2
IO_L13P_2
IO_L14N_2/MOSI/CSI
IO_L14P_2
IO_L15N_2/DOUT
IO_L15P_2/AWAKE
IO_L16N_2
IO_L16P_2
IO_L17N_2/D3
IO_L17P_2/INIT
IO_L18N_2/D1
IO_L18P_2/D2
IO_L19N_2
IO_L19P_2
IO_L20N_2/CCLK
IO_L20P_2/D0/DIN/MISO
IP_2_1
IP_2_2
IP_2_3/VREF_2_1
IP_2_4/VREF_2_2
IP_2_5/VREF_2_3
IP_2_6/VREF_2_4
IP_2_7/VREF_2_5
IP_2_8/VREF_2_6
VCCO_2_1
VCCO_2_2
VCCO_2_3
VCCO_2_4
P4
N4
T2
R2
T3
R3
P5
N6
R5
T4
T6
T5
P6
N7
N8
P7
T7
R7
T8
P8
P9
N9
T9
R9
M10
N10
P10
T10
R11
T11
N11
P11
P12
T12
R13
T13
P13
N12
R14
T14
L7
L8
L9
L10
M7
M8
M11
N5
M9
R4
R8
R12
FPGA_M0
FPGA_M1
FPGA_M2
FPGA_VS2
R423
10K
FPGA_VS0
FPGA_VS1
R422
R421
10K
10K
CLOCK2_PLL_LOCK
CLOCK3_PLL_LOCK
IN
OUT
R397
10
R401
OUT
OUT
OUT
IN
OUT
10
MAIN_48MHZ_CLK_R
MMC_SPI_SCK
MMC_SPI_STE
MMC_SPI_MISO
MMC_SPI_MOSI
OUT
OUT
IN
OUT
OUT
OUT
OUT
OUT
DEBUG_LED_0
DEBUG_LED_1
CLOCK2_PLL_LOCK
IN
CLOCK3_PLL_LOCK
IN
PHY_INT#
(27)
PHY_RST#
(27)
CLOCK2_SSPCS1
OUT
OUT
CLOCK2_SSPCK
OUT
CLOCK2_SSPSI
IN
CLOCK2_SSPSO
OUT
REFCLK2_PD#
(22)
CLOCK3_SSPCS1
(22)
CLOCK3_SSPCK
(22)
CLOCK3_SSPSI
(22)
CLOCK3_SSPSO
(22)
REFCLK3_PD#
MMC_SPI_SCK
MMC_SPI_STE
MMC_SPI_MISO
MMC_SPI_MOSI
UCD9222_VID2A
UCD9222_VID2B
UCD9222_VID2C
UCD9222_VID2S
(11)
(11)
(11)
(11)
(33)
(33)
(33)
(33)
(23)
(22)
PHY 88E1111
(23)
(23)
(23)
(23)
(23)
CLOCK GEN
DEBUG_LED_2
DEBUG_LED_3
FPGA_SPI_CS#
FPGA_SPI_SI
R396
10 FPGA_SPI_SCK
FPGA_SPI_SO
MMC SPI
C530
0.1uF
GPIO0
GPIO1
GPIO2
GPIO3
GPIO4
GPIO5
GPIO6
GPIO7
GPIO8
GPIO9
GPIO10
GPIO11
GPIO12
GPIO13
GPIO14
GPIO15
LENDIAN
BOOTMODE00
BOOTMODE01
BOOTMODE02
BOOTMODE03
BOOTMODE04
BOOTMODE05
BOOTMODE06
BOOTMODE07
BOOTMODE08
BOOTMODE09
BOOTMODE10
BOOTMODE11
BOOTMODE12
PCIESSMODE0
PCIESSMODE1
BM_GPIO
13 12 11
0 0 0
0 0 1
0 1 0
0 1 1
1 0 0
1 0 1
1 1 0
1 1 1
DEBUG_LED
330
FPGA_D1
19-215SUBC/S280/TR8
1
2
DEBUG_LED_0
R205
VCC3V3_FPGA
R206
330 1
R207
FPGA_D3
19-215SUBC/S280/TR8
2
DEBUG_LED_2
330 1
R189
4.7K
4.7K
4.7K
4.7K
FPGA_SPI_CS#
FPGA_SPI_SO
FPGA_SPI_WP#
5%
5%
5%
B
1
2
3
4
CS
SO
WP
GND
VCC
HOLD
SCK
SI
8
7
6
5
VCC3V3_FPGA
VCC3V3_FPGA
FPGA_D2
19-215SUBC/S280/TR8
2
DEBUG_LED_1
C
The device configuration fields
GPIO[10:4] are used to configure the
boot peripheral and, therefore, the bit
definitions depend on the boot mode.
Device
Configuration
Field
INPUT
CLK (MHz)
50.00
66.67
80.00
100.00
156.25
250.00
312.50
122.88
00b
01b
10b
CorePac System PLL Configuration
PA driven from core clk
PA driver from PA clk
B
Description
PCIe in End-point mode
PCIe in Legacy End-point mode(no support for MSI)
PCIe in Legacy Root complex mode
PCIESSEN
R190
4.7K
Input
Description
0
Initial state of the power domain and the clock
domain for PCIE subsystem is disabled
1
Initial state of the power domain and the clock
domain for PCIE subsystem is enabled
FPGA_SPI_HD#
FPGA_SPI_SCK
FPGA_SPI_SI
ATMEL_AT25128B-SSHL-B
A
PA driven from core clk
PA driver from PA clk
PCIe Mode selection(PCIESSMODE[1:0])
U26
R194
R195
R196
NOTE
VCC3V3_FPGA
C440
0.1uF
VCC3V3_FPGA
VCC3V3_FPGA
BOOT
Device
EMIF16
sRIO
SMGII
SGMII
PCIe
I2C
SPI
HyperLink
BM_GPIO [15:14] INPUT
C387
0.1uF
VCC3V3_AUX
A
B
B
R208
FPGA_D4
19-215SUBC/S280/TR8
2
DEBUG_LED_3
330 1
B
B24
120_100MHz
0.5A
Y7
4
2
C382
0.1uF
16V
VCC
GND
OUT
OE
3
1
MAIN_48MHZ_CLK
R178
33
Designed for TI by ADVANTECH
MAIN_48MHZ_CLK_R
48MHz_15pF
3.3V
Title
FPGA_XC3S200AN_B
Size
C
Date:
5
4
3
D
Device Configuration
XILINX_XC3S200AN-4FTG256C
VCC3V3_FPGA
Primary Function
Pull Up
Pull Down
Little Endian Big Endian
Boot Device
Boot Device
Boot Device
Device Cfg
Device Cfg
Device Cfg
Device Cfg
Device Cfg
Device Cfg
Device Cfg
PLL Multiplier/I2C
PLL Multiplier/I2C
PLL Multiplier/I2C
Endpt/RootComplex
Endpt/RootComplex
PLL Settings
UCD9222
VCC1V0 VID CTRL
FPGA EEPROM
B36
2A
120_100MHz
C435
0.1uF
BM_GPIO0
BM_GPIO1
BM_GPIO2
BM_GPIO3
BM_GPIO4
BM_GPIO5
BM_GPIO6
BM_GPIO7
BM_GPIO8
BM_GPIO9
BM_GPIO10
BM_GPIO11
BM_GPIO12
BM_GPIO13
BM_GPIO14
BM_GPIO15
BM_GPIO
[10:4]
FPGA_INIT#
C388
0.1uF
Boot Mode
BM_GPIO
3 2 1
0 0 0
0 0 1
0 1 0
0 1 1
1 0 0
1 0 1
1 1 0
1 1 1
ESD102EZ
C1
C2 IO_L01N_3
D3 IO_L01P_3
D4 IO_L02N_3
E1 IO_L02P_3
D1 IO_L03N_3
E2 IO_L03P_3
E3 IO_L05N_3
G4 IO_L05P_3
F3 IO_L07N_3
G1 IO_L07P_3
F1 IO_L08N_3/VREF_3_1
H4 IO_L08P_3
G3 IO_L09N_3
H5 IO_L09P_3
H6 IO_L10N_3
H1 IO_L10P_3
(16,29)IO_L11N_3/LHCLK1
G2
(16,29)IO_L11P_3/LHCLK0
J3
(16,29)
H3 IO_L12N_3/IRDY2/LHCLK3
(16,29)IO_L12P_3/LHCLK2
J1
(16,29)
J2 IO_L14N_3/LHCLK5
(16,29)IO_L14P_3/LHCLK4
K1
(16,29)IO_L15N_3/LHCLK7
K3
(16,29)IO_L15P_3/TRDY2/LHCLK6
L2
(16,29)IO_L16N_3
L1
(16,29)
J6 IO_L16P_3/VREF_3_2
(16,29)IO_L17N_3
J4
(16,29)IO_L17P_3
L3
(16,29)
K4 IO_L18N_3
(16,29)IO_L18P_3
L4
(16,29)
M3 IO_L19N_3
(16,29)IO_L19P_3
N1
M1 IO_L20N_3
P1 IO_L20P_3
N2 IO_L22N_3
P2 IO_L22P_3
R1 IO_L23N_3
M4 IO_L23P_3
N3 IO_L24N_3
F4 IO_L24P_3
E4 IP_L04N_3/VREF_3_3
G5 IP_L04P_3
G6 IP_L06N_3/VREF_3_4
J7 IP_L06P_3
H7 IP_L13N_3
K6 IP_L13P_3
K5 IP_L21N_3
L6 IP_L21P_3
L5 IP_L25N_3/VREF_3_5
D2 IP_L25P_3
H2 VCCO_3_1
J5 VCCO_3_2
M2 VCCO_3_3
VCCO_3_4
DSP
Boot Device
SW9
BM_GPIO_00
BM_GPIO_01
BM_GPIO_02
BM_GPIO_03
BM_GPIO_04
BM_GPIO_05
BM_GPIO_06
BM_GPIO_07
BM_GPIO_08
BM_GPIO_09
BM_GPIO_10
BM_GPIO_11
BM_GPIO_12
BM_GPIO_13
BM_GPIO_14
BM_GPIO_15
DIP Switch
2
Document Number
Rev
A101-1
DSPM-8301E
Tuesday, March 08, 2011
Sheet
1
31
of
40
5
4
3
BSC_JTAG_TCK
BSC_JTAG_TMS
BSC_JTAG_TDI
BSC_EN#
FPGA JTAG
BSC_JTAG_RST#
R370
R413
R414
R247
4.7K
4.7K
4.7K
4.7K
R315
4.7K
C15
0.1uF
16V
2
1
VCC3V3_AUX
VCC3V3_FPGA
VCC3V3_FPGA
TAP_FPGA1
1
2
3
4
5
6
7
8
VCC3V3_FPGA
R965
22
R966
22
D
R217
1K
BSC_JTAG_TCK
BSC_JTAG_RST#
BSC_JTAG_TDO
BSC_JTAG_TDI
BSC_JTAG_TMS
BSC_EN#
R218
4.7K
FPGA_DONE
PH_8x1V_2.54mm
FPGA_PROG
Q13
2N7002DW-7-F
BSC_EN#
S1
D1
6
R968
2
G1
G2
5
JTAG_EN#
3
D2
S2
4
4.7K
R220
NL/100K
VCC3V3_AUX
D11
NL/KP-1608SGD
2
VCC3V3_AUX
4.7K
1
G
R969
R219
NL/330
1
D
BSC_EN#_1
<Characteristic>
During Configuration :
Must be High to allow
configuration to start.
Always enabling :
C
JTAG_EN#
FPGA_JTAG_TDO
BSC_JTAG_TDO
FPGA_JTAG_TCK
33
R371
BSC_JTAG_TMS
(27,30,33)
FPGA_JTAG_RST#
OUT
BSC_EN#_1
(33)
(33)
9222_JTAG_TDO
9222_JTAG_TDI
(27)
PHY_JTAG_TDI
(27)
IN
OUT
OUT
PHY_JTAG_TCK
OUT
R436
0
R435
0
R412
33
BSC_JTAG_TDO
BSC_JTAG_TCK
BSC_JTAG_TMS
FPGA_JTAG_TMS
1
2
3
4
5
6
7
8
9
10
1
2
3
4
5
6
7
8
9
10
U6
TI_SN74ALVC244PWR
20
1OE
VCC 19
1A1
2OE 18
2Y4
1Y1 17
1A2
2A4 16
2Y3
1Y2 15
1A3
2A3 14
2Y2
1Y3 13
1A4
2A2 12
2Y1
1Y4 11
GND
2A1
C365
U7
TI_SN74ALVC244PWR
20
1OE
VCC 19
1A1
2OE 18
2Y4
1Y1 17
1A2
2A4 16
2Y3
1Y2 15
1A3
2A3 14
2Y2
1Y3 13
1A4
2A2 12
2Y1
1Y4 11
GND
2A1
C603
BSC_JTAG_RST# --> FPGA_JTAG_RST#.
BSC_JTAG_TCK
--> FPGA_JTAG_TCK
0.1uF
16V
VCC3V3_AUX
BSC_JTAG_TDI
FPGA_JTAG_TDI
JTAG port (CN10) is only for FPGA debug
and programming.
BSC_JTAG_TCK
FPGA_JTAG_TMS
BSC_JTAG_RST#
BSC_JTAG_TDO
BSC_JTAG_TDI
BSC_JTAG_TMS
0.1uF
16V
IN
33
BSC_JTAG_TCK
BSC_JTAG_TMS
(27)
PHY_JTAG_TDO
R372
OUT
9222_JTAG_TCK
PHY_9222_JTAG_TMS
OUT
(33)
(27,33)
For boundary scan by pass test
B
FPGA_JTAG_TDI
R424
NL/0
PHY_JTAG_TDI
R425
NL/0
R426
9222_JTAG_TDI
NL/0
--> FPGA_JTAG_TDI
<-- FPGA_JTAG_TDO
--> FPGA_JTAG_TMS
When BSC_EN# = 0:
JTAG port (CN10) is a boundary scan feature.
The sequence is FPGA, 88E1111, then UCD9222.
BSC_JTAG_TCK
--> FPGA_JTAG_TCK
VCC3V3_AUX
BSC_EN#_1
BSC_JTAG_TDI
FPGA_JTAG_TDI
FPGA_JTAG_TDO
C
When BSC_EN# = 1:
9222_JTAG_TDO
BSC_JTAG_TCK
--> 9222_JTAG_TCK
BSC_JTAG_TMS
BSC_JTAG_TCK
BSC_JTAG_TDO
FPGA_JTAG_TDO
PHY_JTAG_TDO
9222_JTAG_TDO
-->
-->
-->
-->
-->
-->
PHY_9222_JTAG_TMS
PHY_JTAG_TCK
FPGA_JTAG_TDI
PHY_JTAG_TDI
9222_JTAG_TDI
BSC_JTAG_TDI
B
FPGA1C
FPGA_DONE
FPGA_PROG
FPGA_JTAG_TCK
FPGA_JTAG_TDI
FPGA_JTAG_TDO
FPGA_JTAG_TMS
R430
R967
VCC3V3_FPGA
C419
0.1uF
16V
C418
0.1uF
16V
C417
0.1uF
16V
C425
0.1uF
16V
C413
0.1uF
16V
C412
0.1uF
16V
C400
0.1uF
16V
C391
0.1uF
16V
C534
0.1uF
16V
C476
0.1uF
16V
C475
0.1uF
16V
C535
0.1uF
16V
C416
0.1uF
16V
C415
0.1uF
16V
C414
0.1uF
16V
C394
0.1uF
16V
VCC1V2_FPGA
A
T15
A2
0
22
A15
B1
B16
B2
E11
F5
L12
M6
G7
G9
H8
J9
K8
K10
DONE
PROG
TCK
TDI
TDO
TMS
VCCAUX_1
VCCAUX_2
VCCAUX_3
VCCAUX_4
VCCINT_1
VCCINT_2
VCCINT_3
VCCINT_4
VCCINT_5
VCCINT_6
GND_1
GND_2
GND_3
GND_4
GND_5
GND_6
GND_7
GND_8
GND_9
GND_10
GND_11
GND_12
GND_13
GND_14
GND_15
GND_16
GND_17
GND_18
GND_19
GND_20
GND_21
GND_22
GND_23
GND_24
GND_25
GND_26
GND_27
GND_28
A1
A16
B7
B11
C3
C14
E5
E12
F2
F6
G8
G10
G15
H9
J8
K2
K7
K9
L11
L15
M5
M12
P3
P14
R6
R10
T1
T16
VCC3V3_AUX
VCC3V3_FPGA
B25
VCC1V2
VCC1V2_FPGA
120_100MHz
2A
B26
C385
10uF
6.3V
120_100MHz
2A
C386
0.1uF
16V
C392
10uF
6.3V
C393
0.1uF
16V
A
XILINX_XC3S200AN-4FTG256C
Designed for TI by ADVANTECH
Title
FPGA_XC3S200AN_C
Size
C
Date:
5
4
3
2
Document Number
Rev
A101-1
DSPM-8301E
Tuesday, March 08, 2011
Sheet
1
32
of
40
5
4
3
CVDD / VCC1V0
2
UCD9222_PG1
UCD9222_PG2
R418
R419
10K
10K
1%
1%
1
VCC3V3_AUX
PMBus Address Bins
PMBus Address PMBus RESISTANCE ( K ohm )
C441
4.7uF
6.3V
VCC12
41
C442
0.1uF
16V
34
33
R250
10.2K
1%
C444
35
1uF
6.3V
UCD_VIN
C518
1000pF
50V
EAP1
The component need
next to UCD9222
EAN1
EAP2
R261
R252
1.5K
1%
750
R405
C448
100pF
50V
C445
0.1uF
16V
TEMP1
4
1
45
46
2
48
V33FB
V33A
V33DIO
BPCAP
VinMon
IinMon
Vtrack
Temp1/AuxADC1
Temp2/AuxADC2
750
560pF
NL/2K
50V
1%
C467
R415
560pF
NL/2K
50V
1%
37
38
39
40
1%
EAp1
EAn1
EAp2
EAn2
C
PMBUS Address
=>78 (6*12+6)
IN
IN
OUT
IN
IN
R433
R434
(30)
PGUCD9222
C602
PMBUS1
1
2
3
4
5
6
(30)
(30)
(30)
(30)
0.1uF 16V
PMBUS_CLK
PMBUS_DAT
PMBUS_ALT
PMBUS_CTL
IN
BI
OUT
IN
R257
R258
VCC3V3_AUX
PMBUS_CLK
PMBUS_DAT
PMBUS_ALT
PMBUS_CTL
OUT
R255
R256
VCC3V3_AUX
VCC3V3_AUX
VCC3V3_AUX
(30)
0
22
R253
R254
R262
VCC3V3_AUX
UCD9222_RST#
IN
27
29
28
30
31
100K
100K
10K
1%
1%
1%
44
43
PGUCD9222
2K
2K
17
1%
1%
10
11
19
20
PMBUS_CLK
PMBUS_DAT
PMBUS_ALT
PMBUS_CTL
100K 1%
1M 1%
R259
5
10K
JTAG_TCK
JTAG_TDI/SYNC_IN
JTAG_TDO/SYNC_OUT
JTAG_TMS
JTAG_TRST
PMBus_ADDR0
PMBus_ADDR1
PowerGood
PMBUS_CLK
PMBUS_DATA
PMBUS_ALERT
PMBUS_CNTRL
RESET
1%
UCD9222_RST#
R376
OUT
UCD9222_PG1
10K
1%
(30)
lsenes-1A
FF-2A
PWM-2A
UCD9222_PG2
OUT
UCD9222_ENA2
R417
100
lsenes-2A
16
18
21
7
22
23
24
9
IN
IN
IN
IN
IN
UCD9222_ENA1
(30)
IN
UCD9222_ENA2
(30)
0.01uF
16V
4.99K 1%
R404
UCD9222_PG2
C447
R373
10K
1%
(30)
0.01uF
16V
4.99K 1%
(17)
UCD9222_VIDA
(17)
UCD9222_VIDB
(17)
UCD9222_VIDC
(17)
UCD9222_VIDS
IN
UCD9222_VID2A
IN
UCD9222_VID2B
IN
UCD9222_VID2C
IN
UCD9222_VID2S
36
47
32
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
AGND2
AGND3
DGND3
PowerPad
Thermal_VIA1
Thermal_VIA2
Thermal_VIA3
Thermal_VIA4
Thermal_VIA5
Thermal_VIA6
Thermal_VIA7
Thermal_VIA8
Thermal_VIA9
Thermal_VIA10
Thermal_VIA11
Thermal_VIA12
Thermal_VIA13
Thermal_VIA14
Thermal_VIA15
Thermal_VIA16
Thermal_VIA17
Thermal_VIA18
Thermal_VIA19
Thermal_VIA20
Thermal_VIA21
Thermal_VIA22
Thermal_VIA23
Thermal_VIA24
Thermal_VIA25
EAN2
(32)
9222_JTAG_TCK
(32)
9222_JTAG_TDI
(32)
9222_JTAG_TDO
(27,32)
PHY_9222_JTAG_TMS
(27,30,32) FPGA_JTAG_RST#
8
14
15
26
3 CS2A
VID1A
VID1B
VID1C
VID1S
VID2A
VID2B
VID2C
VID2S
ADC_REF
FF-1A
PWM-1A
UCD9222_PG1
UCD9222_ENA1
R416
100
C443
R251
FLT2A
DPWM2A
PG2
ENA2
CS2A
1%
C446
R246
6
12
13
25
42 CS1A
FLT1A
DPWM1A
PG1
ENA1
CS1A
-205
178
154
133
115
100
86.6
75
64.9
56.2
48.7
42.2
--
OPEN
11
10
9
8
7
6
5
4
3
2
1
0
SHORT
U32
VCC3V3_AUX
D
The component need
next to UCD9222
(31)
(31)
(31)
(31)
DSP
D
UCD9222
10 ohm
CVDD
10 ohm
GND
10 ohm
VCC1V0
10 ohm
GND
EAP1
EAN1
750 ohm
EAP2
EAN2
750 ohm
C
EAp1
560 pF
EAn1
EAp2
560 pF
EAn2
TI_UCD9222RGZR
PH_6x1V_2.54mm
Corresponding "EA" Pins MUST be routed as differential
signals and connected next to DSP for specific rails
Series resistors on EA nets to be placed at the load for proper voltage feedback.
Each 22uF Cin cap needs to tightly coupled to Vin and PGND of the UCD7242.
VCC12
VCC12
+++output capacitor Calculation for VCC1V0+++
R331
VCC3V3_AUX
1
10K SRE_AB
1%
FF-2A
2
9
10
10
5%
5%
CVDD
EAP2
EAN2
R411
R406
10
10
5%
5%
VCC1V0
B
27
29
28
19
TMON
VIN_3
VIN_4
NC-VIN_2
PWM-2A
VIN_1
VIN_2
NC-VIN_1
U34
C= 5 / ( 10m * 8 * 750k )
C=83.3uF
30
32
31
(VPPQ=10mV)
R338
R260
C450
22uF
16V
TEMP1
C449
22uF
16V
B
EAP1
EAN1
PWM_B
PWM_A
SRE_B
SRE_A
FLT_B
FLT_A
26
PWM-1A
25
SRE_AB
18
FF-1A
TI_UCD7242RSJT
C473
330uF
6.3V
C474
330uF
6.3V
10
12
11
SWA
PGND_1
PGND_2
NC-PGND_1
8
A
PGND_3
PGND_4
NC-PGND_2
+++output capacitor Calculation for VCC1V0+++
lsenes-1A
24
C452
0.22uF
DSP Vcore @8A
25V
23
14
L6
0.47uH
17.5A
CVDD
C460
330uF
6.3V
15
17
16
C469
330uF
6.3V
C471
330uF
6.3V
C459
220uF
4V
C458
220uF
4V
C461
47uF
6.3V
C462
47uF
6.3V
R263
1K
1%
(VPPQ=10mV)
C= 8 / ( 10m * 8 * 750k )
C= 133.3uF
VGG
C456
330uF
6.3V
BSW_A
SWB
20
5
C457
220uF
4V
BSW_B
BP3
C455
220uF
4V
13
BST_A
VGG_DIS
C454
47uF
6.3V
17.5A
IMON_A
BST_B
testmode
C453
47uF
6.3V
0.47uH
IMON_B
6
4
L5
VCC1V0
R420
1K
1%
3
25V
22
0.22uF
AGND
C451
21
7
lsenes-2A
1.0V@ 5A
A
+++Inductor Calculation for VCC1V0+++
C463
1uF
16V
+++Inductor Calculation for CVDD+++
C464
4.7uF
16V
Designed for TI by ADVANTECH
L= ( 12 - 1 ) / 5 * (1/12) / 750K
L= ( 11 / 5 ) * ( 0.083 / 750K )
L= 0.243 uH
L= ( 12 - 1 ) / ( 8 ) * (1/12) / 750K
L= ( 11 / 8 ) * ( 0.083 / 750K )
L= 0.152 uH
Title
Power ucd9222
Size
C
Date:
5
4
3
2
Document Number
Rev
A101-1
DSPM-8301E
Tuesday, March 08, 2011
Sheet
1
33
of
40
5
4
3
2
1
VCC1V8_AUX
VCC1V2
1.2V @0.38A
2
6
7
VCC1V2
3
R221
0
5%
R21
VCC3V3_AUX
10K
1%
R223
10K
1%
C507
10uF
6.3V
8
VCC3V3_AUX
C506
0.1uF
16V
C397
10uF
6.3V
C548
0.1uF
16V
R25
10K
1%
5
VIN
NC1
NC2
NC3
FB
VOUT
GND
EPAD
1
VOUT
EN
FB
EN
R1
VCC3V3_AUX
2
6
7
5
C547
0.1uF
16V
VIN
EN
VOUT
FB
1
C509
10uF
6.3V
R225
39.2K
1%
C
R1
VCC2V5_EN
R2
8
VCC3V3_AUX
C398
10uF
6.3V
C554
0.1uF
16V
5
1
2
3
1%
VCC
5
4
(30)
R75
10K
1%
VCC2V5_PGOOD
GND
VOUT
FB
EN
VCC1V8_EN1
IN
VCC3V3_AUX
1K
VIN
VCC1V8
3
R385
28K
1%
R1
R386
56.2K
1%
R2
C517
10uF
6.3V
C523
0.1uF
16V
R141
10K
1%
OUT
Vout=(R1+R2)/R2*1.204
1.805V =(28k+56.2k)/56.2k*1.205
(30)
VCC2V5_PGOOD
U251
TI_SN74LVC1G07DBVR
B
1
4
9
Vout=(R1+R2)/R2*1.204
2.50V =(39.2k+36.5k)/36.5k*1.204
R142
1.8V@0.5A
Q5
TI_TPS73701DRBT
R227
36.5K
1%
2
6
7
IN
R22
10K
1%
VCC2V5
R2
C508
0.1uF
16V
NC1
NC2
NC3
VCC2V5_EN
R224
56.2K
1%
D
VCC1V8
GND
EPAD
(30)
R1
C515
0.1uF
16V
VCC2V5
3
4
9
C399
10uF
6.3V
NC1
NC2
NC3
8
VCC3V3_AUX
GND
EPAD
C
R222
28K
1%
C514
10uF
6.3V
Vout=(R1+R2)/R2*1.204
1.805V =(28k+56.2k)/56.2k*1.205
2.5V @0.21A
Q4
TI_TPS73701DRBT
VCC1V8_AUX
3
R2
Vout=(R1+R2)/R2*1.204
1.204V = (0+10k)/10k*1.204
VCC2V5
1
4
9
VIN
4
9
D
5
C513
0.1uF
16V
NC1
NC2
NC3
C395
10uF
6.3V
GND
EPAD
8
VCC3V3_AUX
1.8V_AUX @0.3A
Q3
TI_TPS73701DRBT
2
6
7
Q2
TI_TPS73701DRBT
B
VCC0V75
R229
VCC1V5
C405
10uF
6.3V
VCC3V3_AUX
1K
1%
C406
0.1uF
16V
R231
1K
1%
C403
0.01uF
16V
U27
TI_TPS51200DRCT
1
2
3
VCC0V75
C407
10uF
6.3V
C408
10uF
6.3V
C409
10uF
6.3V
4
5
REFIN
VLDOIN
VIN
PGOOD
VO
GND
PGND
VOSNS
EN
REFOUT
C510
0.1uF
16V
10
9
VCC0V75_PGOOD
OUT
VCC0V75_PGOOD
(30)
8
7
VCC0V75_EN
IN
VCC0V75_EN
(30)
6
A
EPAD
VIA1
VIA2
VIA3
VIA4
VIA5
A
R230
10K
1%
11
12
13
14
15
16
C410
0.1uF
16V
R23
10K
1%
Designed for TI by ADVANTECH
0.75V @0.25A
Title
Power_1.2V/1.8V/2.5V/0.75V
Size
C
Date:
5
4
3
2
Document Number
Rev
A101-1
DSPM-8301E
Tuesday, March 08, 2011
Sheet
1
34
of
40
5
4
3
2
1
VCC3V3_AUX
Assume 90% Pe,
Iin = ( 3.3V * 2.58A ) / 90% / 12V = 788mA
12V@0.79A
U36
TI_TPS54620RGY
100K
1
2
3
4
5
6
7
VCC12
C543
10uF
16V
VCC12
C538
0.1uF
16V
RT/CLK
GND1
GND2
PVIN1
PVIN2
VIN
VSENSE
PWRGD
BOOT
PH2
PH1
EN
SS/TR
COMP
14
13
12
11
10
9
8
VCC3V3_AUX_PGOOD
0.1uF 16V
L8
3.3uH
6A
VCC3V3_AUX_EN
C431
D
OUT
(30)
VCC3V3_AUX_PGOOD
VCC3V3_AUX
C432
100uF
6.3V
R333
1.69K
1%
15
C544
10uF
16V
R350
10K
1%
1%
B165
2A
120_100MHz
EPAD
R332
D
C545
0.1uF
16V
3.3V_AUX @2.585A
VCC3V3_AUX
R334
31.6K
1%
R1
R335
10K
1%
R2
VCC12
C438
0.01uF
16V
C437
8200pF
50V
R374
31.6K
1%
VCC3V3_AUX_EN
R336
10K
1%
Vout=0.8 V*(R1/R2+1)
3.3=0.8 V*(10k/3.1k+1)
(Over all tolerance is 5% ,DC tolerance is 2.5% )
+++output capacitor Calculation+++
+++Inductor Calculation+++
(KIND=0.3)
L = ((Vin(max) - Vout)/Iout * Kind)) * (Vout/(Vin(max) * Fsw))
Cout=(2*delta(Iout))/(Fsw*delta(Vout))
L = ((12.6 - 3.3)/2.58 * Kind) * (3.3 / (12.7 * 1MHz))
Cout=(2*2.58)/(1MHz*0.0825)
L = ((9.3/2.58 * 0.3) * (3.3 / (12.7M))
Cout=(5.16)/(82500)
L = (9.3/0.774) * (0.26M)
Cout=63uF
L = 3.12uH
Reference Capacitor=100uF
Reference Inductor 3.3uH
C
C
VCC5
Assume 80% Pe,
Iin = ( 5V * 1A ) / 80% / 12V = 520mA
5V @1A
12V@0.52A
C420
0.1uF
16V
120_100MHz
C423
10uF
16V
B
(30)
C426
0.01uF
16V
VCC_5V_EN
U29
1
2
3
4
2A
R237
NL/332K
1%
IN
8
7
6
5
BOOT
PH
VIN
GND
EN
COMP
SS
VSENSE
1
B158
VCC12
D7
B340A
3A
C424
1200pF
50V
TI_TPS54231D
C428
0.01uF
16V
R143
VCC5
1K
1%
1
2
3
VCC
5
4
R136
10K
1%
VCC5_PGOOD
GND
VCC5_PGOOD
(30)
R238
10K
1%
R1
C427
56pF
50V
B
R241
1.87K
1%
+++output capacitor Calculation+++
OUT
VCC5
C422
100uF
6.3V
R239
22.6K
1%
Vout=0.8 V*(R1/R2+1)
5=0.8 V*(10k/1.87k+1)
A
2.8A
VCC_5V_EN
R240
68.1K
1%
VCC3V3_AUX
22uH
2
L2
Cout=1/( 2 * 3.14 * 5 * 25K)
Cout=1.3 uf
Reference Capacitor=100uF
R2
+++Inductor Calculation+++
(KIND=0.3)
L = ((Vin(max) - Vout)/Iout * Kind)) * (Vout/(Vin(max) * Fsw))
L = ((12.6 - 5)/1 * Kind) * (5 / (12.7 * 570K))
L = ((7.6/ 0.3) * (5 / (7239K))
L = (25.3) * (0.69M)
L = 17.5uH
Reference Inductor 22uH
U253
TI_SN74LVC1G07DBVR
A
Designed for TI by ADVANTECH
Title
Power_VCC5 / VCC3V3_AUX
Size
C
Date:
5
4
3
2
Document Number
Rev
A101-1
DSPM-8301E
Tuesday, March 08, 2011
Sheet
1
35
of
40
5
4
3
2
1
VCC1V5
VCC3V3_AUX
Assume 90% Pe,
Iin = ( 1.5V * 2.12A ) / 90% / 12V = 295mA
120_100MHz
100K
1%
1
2
3
4
5
6
7
2A
C542
0.1uF
16V
C541
10uF
16V
C540
10uF
16V
VCC12
C529
0.1uF
16V
D
U30
TI_TPS54620RGY
RT/CLK
GND1
GND2
PVIN1
PVIN2
VIN
VSENSE
EPAD
B164
R242
15
12V@0.3A
VCC12
1.5V @2.12A
R314
10K
1%
D
PWRGD
BOOT
PH2
PH1
EN
SS/TR
COMP
14
13
12
11
10
9
8
VCC1V5_PGOOD
0.1uF 16V
L3
3.3uH
C429
OUT
R244
1.69K
1%
VCC1V5_PGOOD
(30)
6A
VCC1V5_EN
VCC1V5
C430
100uF
6.3V
C539
100uF
6.3V
R243
9.09K
1%
R1
C433
0.01uF
16V
IN
C434
8200pF
50V
R245
10K
1%
(30)
VCC1V5_EN
R375
10K
1%
R2
Vout=0.8 V*(R1/R2+1)
1.52=0.8 V*(9.09k/10k+1)
C
C
(Over all tolerance is 5% ,DC tolerance is 2.5%)
+++output capacitor Calculation+++
Cout=(2*delta(Iout))/(Fsw*delta(Vout))
Cout=(2*2.12)/(1MHz*0.0375)
Cout=(4.24)/(37500)
Cout=113uF
Reference Capacitor=100uF*2=200uF
+++Inductor Calculation+++
(KIND=0.3)
L = ((Vin(max) - Vout)/Iout * Kind)) * (Vout/(Vin(max) * Fsw))
L = ((12.6 - 1.5)/2.12 * Kind) * (1.5 / (12.7M))
L = ((11.1/2.12 * 0.3) * (1.5 / (12.7M))
L = (11.1/0.636) * (0.12M)
L = 2.09uH
Reference Inductor 3.3uH
B
B
A
A
Designed for TI by ADVANTECH
Title
Power VCC1V5
Size
C
Date:
5
4
3
2
Document Number
Rev
A101-1
DSPM-8301E
Tuesday, March 08, 2011
Sheet
1
36
of
40