LECTURE SUPPLEMENT #05
Bipolar Junction Transistor
Models And Biasing Circuits
Dr. John Choma
Professor of Electrical Engineering
University of Southern California
Ming Hsieh Department of Electrical Engineering
University Park: Mail Code: 0271
Los Angeles, California 90089–0271
213–740–4692 [USC Office]
213–740–7581 [USC Fax]
818–384–1552 [Cell]
johnc@usc.edu
PRELUDE:
In this chapter, we develop the circuit level models and study the associated volt-ampere
characteristics of the bipolar junction transistor. Although these models are not definitively derived, the physical properties on which they are premised are discussed in a largely qualitative
fashion that exploits many of the arguments set forth in the preceding chapter on semiconductor
PN junction diodes. The models and their engineering implications are then used to forge practical network topologies and corresponding design guidelines for bipolar technology biasing circuits.
September 2009/January 2011
Lecture Supplement #05
BJT Models & Biasing
J. Choma
3.1.0. INTRODUCTION
The successful realization of reliable and reproducible analog signal processing networks boasting predictable I/O performance measures relies strongly on the availability of
meaningful and mathematically tractable circuit level models for the device technologies utilized
in these networks. The electrical properties that these models are called upon to emulate include
both the static and dynamic volt-ampere characteristics of the devices, as well as the impact exerted on these characteristics by device operating temperature. The formulation and application
of accurate models capable of relating observable electrical performance to pertinent physical
phenomenology comprise daunting challenges in light of the complexities of semiconductor device physics and the vagarious nature of device processing. While the use of supremely accurate
device models can be relegated to definitive computer-aided circuit investigations, the models
exploited by circuit designers in pre-computer design-oriented analyses must nonetheless be
sufficiently comprehensive to convey an insightful understanding of the performance attributes
and limitations of the device technologies and circuit topologies of interest. In this chapter, we
focus our attention on the silicon monolithic bipolar junction transistor (BJT). Our circuit level
ruminations are directed toward understanding BJT performance limitations at high signal
frequencies and efficient and reliable BJT biasing for linear signal processing applications.
E
−
Ve
− Vb +
+ +
−
− Ve +
C
Vc
E
Emitter
(N+)
B
E
+
Ve
+ Vb −
− −
+ Vc −
Base
(P)
Collector
(N)
C
Xw
B
+
(a).
Xe
Xb
Xc
E
Emitter
(P+)
Base
(N)
Collector
(P)
C
Vc
Xw
− Vc +
+ Ve −
B
C
B
(b).
Figure (3.1). (a). Schematic symbol and simplified cross section of the NPN bipolar junction transistor
(BJT). (b). Schematic symbol and simplified physical abstraction of the PNP BJT. The
cross section diagrams are not drawn to scale.
BJTs are available in two flavors. We display the schematic symbol and simplified
cross section abstraction of the NPN bipolar junction transistor, which is the principle type utilized in the signal flow paths of broadband analog networks, in Figure (3.1a), and we diagram its
PNP transistor counterpart in Figure (3.1b). In each of these devices, a bipolar junction transisMing Hsieh Department of Electrical Engineering
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Lecture Supplement #05
BJT Models & Biasing
J. Choma
tor is seen as an amalgam of two PN junction diodes, which suggests immediately that the time
devoted to studying the PN junction diode in the preceding chapter pays dividends in the process
of forging an understanding of BJT operation. As is evident in the figure at hand, one of the two
diodes implicit to a BJT is formed by the emitter and base semiconductor volumes, while the
other is fashioned by the collector and base regions.
In each of the transistors depicted in Figure (3.1), the emitter region is very heavily
doped to an impurity concentration approaching the solid solubility limit of silicon; that is, the
doping concentration is very near to the maximum that can be received by silicon. The average
dopant concentration of the base layer is typically five to six orders of a magnitude less than that
of the emitter, while the collector is doped to an impurity concentration that is one or two orders
of a magnitude less than that of the base. For minimal geometry transistors intended for high frequency circuit applications, the emitter length, Xe, is generally under a micron, the base width,
Xb, is two-tenths of a micron or smaller, and the collector length, Xc, is often as large as tens of
microns. On the other hand, the feature thickness, Xw, of the transistor is generally under a micron, and the thickness, say Wb (dimension perpendicular to the page face), which is a designable
geometric parameter in integrated circuit design, is at least as large as Xw. In monolithic
technologies, the geometric parameter, Wb, is commonly referred to as the emitter finger length.
The PN junction diode studied in the preceding chapter is a two-terminal element for
which only a single current and a single voltage are available to define its volt-ampere properties.
In contrast, the BJT is fundamentally a three-terminal device (actually four terminals in its
monolithic embodiment) for which two independent voltages and two independent currents are
required for a satisfying characterization of its observable electrical behavior. In the NPN structure of Figure (3.1a), one of the two independent current variables is the emitter current, Ie,
which is displayed as a positive current flowing out of the transistor. Positive collector current
and base current, Ic and Ib, respectively, flow into the device. On the other hand, the PNP unit
shows positive emitter current as flowing into the transistor and positive collector and base currents flowing out of the device. In both cases, Kirchhoff happily radiates
Ie = I c + Ib ,
(3-1)
which affirms that only two of the three transistor terminal currents are independent electrical
variables.
The diagrams in Figure (3.1) also delineate an internal base-emitter junction voltage,
Ve, and an internal base-collector junction voltage, Vc. Both of these voltages are interpreted as
positive variables when the potential on the p-side of the applicable junction is larger than the
potential on the n-side. The resultant internal collector to emitter voltage, Vb, of the NPN transistor is
Vb = Ve − Vc .
(3-2)
An identical voltage relationship applies for the emitter to collector voltage of the PNP device.
3.2.0. EBERS-MOLL MODEL
To first order, the static volt-ampere characteristics of either an NPN or a PNP bipolar
junction transistor abide by the Ebers-Moll relationships[1],
I c = I cc − I rr − I bc
(3-3)
,
I b = I be + I bc
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BJT Models & Biasing
which by (3-1) implies an emitter current, Ie, of
I e = I cc − I rr + I be .
In (3-3), current Icc is given by
(
Ve n f VT
I cc = Ae J s e
)
(
Ve n f VT
− 1 = Is e
J. Choma
(3-4)
)
−1 ,
(3-5)
where
Ae = Wb X w
(3-6)
is the injection area of the base-emitter junction. Like the injection area of a PN junction diode,
Ae is the cross section area pierced by mobile charge carriers that are motivated to penetrate the
junction interface between the emitter and base volumes. Continuing with (3-5), Js is the saturation current density of the transistor, Is = AeJs is the corresponding saturation current, nf is the
injection coefficient of the base-emitter junction, and
kT j
VT =
(3-7)
q
is the familiar Boltzmann voltage, with Tj representing the absolute temperature of the base-emitter junction. The saturation current density, Js in (3-5), and hence the effective saturation current, Is, is strongly affected by the operating temperature of the junction. As witnessed in
conjunction with PN junction diodes, the numerical value of Js nominally doubles to quadruples
for each ten degree centigrade rise in operating temperature.
The current component, Icc, in (3-3), (3-4), and (3-5) is known as the forward transport
current of the BJT. When the base-emitter junction of an NPN device is suitably forward biased
(Ve > 0), electrons from the emitter are injected into the base region. In tandem with this electron transport, holes are similarly injected from the base to the emitter. However, the junction
current manifested by injected holes is significantly smaller than is the junction current arising
from injected electrons because the emitter region is doped to a concentration that is far larger
than the impurity concentration to which the base volume is doped. The phrase, “suitably forward biased,” is taken to mean that in addition to the requirement of a positive junction voltage,
Ve must be at least as large as the turn on or threshold voltage, Veon, of the base-emitter junction.
We recall that for a junction of p-type and n-type silicon semiconductors, this threshold voltage
is of the order of 700 mV.
Our tacit study of (3-3) and (3-4) confirms that Icc is a component of collector current Ic
and emitter current Ie, but it does not contribute to base current Ib. We can therefore logically
attribute the forward transport current of an NPN transistor to those electrons that are injected
into the base region from the emitter site and thence swept from the base into the collector.
Since those electrons manifesting current Icc through their injection into the base are swept out of
the base and into the collector, no net charge perturbation is evidenced in the base. Accordingly,
the physical mechanisms contributing to the establishment of the forward transport current, Icc,
do not influence the measurable base current, Ib.
The transport from emitter to collector of injected minority carriers in the base is rendered plausible and likely by the relatively low impurity concentration and narrowness of the
base region. In particular, low base region doping tends to bound the level to which base region
holes can recombine with injected electrons therein. There simply are insufficient numbers of
free base region holes to recombine with a large percentage of injected electrons. Such global
transport is further encouraged by the built-in potential developed at the base collector junction,
which effectively acts as an intrinsic junction reverse bias. This potential gives rise to an intrinMing Hsieh Department of Electrical Engineering
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BJT Models & Biasing
J. Choma
sic field, directed from the collector to the base, which attracts minority carriers (electrons in an
NPN device) within the narrow confines of the base volume. An additional reverse bias (Vc < 0)
imposed by external means across the base-collector junction serves to further promote the likelihood of emitter to collector charge transport through the base.
Although the recombination of injected electrons with base region holes in an NPN
transistor is discouraged because of the relatively low dopant concentration in, and narrowness
of, the base, a small percentage of these injected minority carriers nevertheless succumb to
recombination. The current arising from this recombination mechanism, which contributes directly to only the observable emitter and base currents of the subject transistor, is Ibe, which is
given by
I
AJ
I
V n V
V n V
I be = cc = e s e e f T − 1 = s e e f T − 1 .
(3-8)
βf
βf
βf
(
)
(
)
In this relationship, βf, the forward short circuit (meaning Vc = 0) base to collector current
transfer ratio, is generally of the order of one hundred (greater than 100 in BJTs fabricated as a
silicon-germanium heterostructure). In effect, the forward recombination current, Ibe, reflects
those injected carriers that are “lost” in the base in the sense of reducing the number of injected
carriers available for ultimate transport into the collector. For example, the implication of βf =
100 is that 99% of electrons injected into the base from the emitter escape a recombination fate
and are successfully transported to the collector. The fact that the form of (3-8) mirrors the static
volt-ampere relationship of a traditional diode is hardly surprising in that the emitter and base
volumes shown in Figure (3.1) coalesce to form a classic PN junction diode. The effective
saturation current of this intrinsic diode is Is/βf.
Returning to (3-3) and (3-4), the current component, Irr, is given by
)
(
)
(
I rr = Ae J s eVc nrVT − 1 = I s eVc nrVT − 1 ,
(3-9)
while current Ibc is
AJ
I
I
I bc = rr = e s eVc nrVT − 1 = s eVc nrVT − 1 .
(3-10)
βr
βr
βr
With Vc ≥ Vcon, the threshold voltage of the base-collector junction diode, majority carriers in the
collector region are injected into the base region where they become minority carriers.
Recombination in this so-called reverse direction is more probable than in the formerly considered forward direction because the base region is doped to a higher impurity concentration than
is the collector. Current Ibc is a measure of this reverse recombination phenomena. Parameter βr
is the reverse short circuit (meaning Ve = 0) base to emitter current transfer ratio. Owing to
the likelihood of enhanced recombination in reverse operation, βr is substantially smaller than is
its forward counterpart, βf. The current, Irr, represents the effects of collector-injected minority
carriers that are swept from the base into the emitter by the built-in potential at the base-emitter
junction or by an imposed reverse bias therein. In (3-9) and (3-10), nr is the injection coefficient
of the base-collector PN junction. Generally, nr and nf in (3-5) and (3-9) are taken as identical
constants that are only slightly larger than unity.
(
)
(
)
Similar statements can be advanced for the current components, Icc, Irr, Ibe, and Ibc, of a
PNP bipolar junction transistor. In the PNP device case, Icc and Irr are measures of injected holes
that are transported from emitter to collector and from collector to emitter, respectively. As with
NPN devices, Ibe represents the recombination current, which in the PNP case is attributed to
base region electrons that recombine with holes injected from the emitter. On the other hand, Ibc
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BJT Models & Biasing
J. Choma
is the recombination current arising from base region electrons that recombine with holes injected from the collector.
It is worth our underscoring that each of the four current components in the Ebers-Moll
model of a bipolar junction transistor is directly proportional to the saturation current density, Js.
Recall that Js increases dramatically with the operating temperature of the base-emitter junction.
Thus, all three transistor currents −emitter current Ie, collector current Ic, and base current Ib− are
vulnerable to device temperature increases if the base-emitter and base-collector junction potentials, Ve and Vc, respectively, are held fast over temperature. The flip side of this argument is that
acceptable temperature stability in bipolar networks mandates designs for which Ve and/or Vc are
allowed to decrease to compensate for the increased current ramifications of junction temperature increases.
Additionally, it should be noted that all of the Ebers-Moll current components are directly proportional to the base-emitter junction area, Ae, just as the current flowing through a PN
junction diode is proportional to its injection area. This circumstance means that for fixed values
of the junction potentials, Ve and Vc, the emitter, base, and collector currents scale linearly with
base-emitter junction area. Assume, for example, that the second of two identical transistors has
a junction area that is K-times that of the first transistor and that both transistors are excited by
equivalent base-emitter and base-collector junction potentials. Both transistors therefore exhibit
the same current densities despite the fact that the second transistor conducts emitter, base, and
collector currents that are respectively K-times larger than the corresponding currents of the first
device. Since the internal self-heating caused by current conduction is intimately related to current density, as opposed to actual current level, the proper scaling of monolithic transistors can
circumvent performance problems that may be incurred by excessive on-chip thermal gradients.
In short, fat transistors are needed when large currents must be conducted, just as thick wires are
required to power high current appliances, such as microwave ovens and electric clothes dryers.
Base
+
Ib
+
Collector
Base
Vb
Ib
Ve
Ve
Ie
−
Ibc +
+
−
Ibe
Ic
−
+
DBC
Ic
DBE
Icc
Irr Vb
Ie
−
Collector
−
Emitter
Emitter
(a).
Ic
Ib
−
−
Vb
Ve
Ve
+
Ibc −
Ie
+
+
Ibe
Ic
+
−
DBC
Base
−
Ib
Base
Collector
DBE
Icc
Ie
Emitter
Collector
Irr Vb
+
Emitter
(b).
Figure (3.2). (a). Ebers-Moll model of the NPN bipolar junction transistor. (b). Ebers-Moll model
of the PNP bipolar junction transistor.
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BJT Models & Biasing
J. Choma
3.2.1. EBERS-MOLL MODEL INTERPRETATION
In consideration of the fact that both the base-emitter and base-collector junctions of a
BJT are PN junction diodes, the circuit level interpretation of (3-3) and (3-4) are the NPN and
PNP model topologies offered in Figure (3.2). In these topologies, diode DBE represents the
base-emitter junction diode, while DBC identifies the base-collector junction diode. A trivial
model modification, which derives from (3-8) and (3-10) appears in Figure (3.3). In particular,
(3-8) shows that the forward transport current, Icc, can be written as Icc = βfIbe. The forward
transport component, Icc, of the collector current can therefore be represented as a current controlled current source controlled by the forward base recombination current, Ibe, which is conducted by diode DBE. Analogously, (3-10) implies Irr = βrIbc, thereby suggesting that the reverse transport component, Irr, of the collector current can be represented as a current controlled
current source controlled by the reverse component of the base recombination current, Ibc, which
is the current flowing through diode DBC.
Base
+
Ib
+
Collector
Base
Vb
Ib
Ve
Ve
Ie
−
Ibc +
+
−
Ibe
Ic
−
+
DBC
Ic
DBE
βf Ibe
βr Ibc Vb
Ie
−
Collector
−
Emitter
Emitter
(a).
Ic
Ib
Ibc −
−
−
Vb
Ve
Ve
+
Ib
Ie
+
+
Ibe
Ic
+
−
DBC
Base
−
Base
Collector
DBE
βf Ibe
Ie
Emitter
Collector
βr Ibc Vb
+
Emitter
(b).
Figure (3.3). (a). Alternative Ebers-Moll model of the NPN bipolar junction transistor.
Alternative Ebers-Moll model of the PNP bipolar junction transistor.
(b).
It is instructive to study the Ebers-Moll equations for the two special cases of Ve = 0
and Vc = 0. For example, with Vc = 0, (3-9) and (3-10) give Irr = 0 and Ibc = 0, whence by (3-3)
and (3-4),
I b = I be
I c = I cc = β f I be = β f I b
I e = I cc + I be =
( β f + 1) Ibe
.
=
(3-11)
( β f + 1) I b
Equation (3-11) gives rise to the circuit interpretation we submit in Figure (3.4a), where the voltage, Ve, of the indicated battery is presumed larger than the threshold voltage of the base-emitter
PN junction in order to support measurable emitter and base currents in the transistor. This
model underscores the logic of referring to parameter βf as a short circuit (Vc = 0) base to
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BJT Models & Biasing
J. Choma
collector current transfer ratio in that the ratio, Ic/Ib, of collector to base currents in the subject
circuit is clearly βfIbe/Ibe = βf. we note a resultant ratio of collector current to emitter current of
βf Ibe
βr Ibc
Ibe
Ibc
+
+
Ve
Vc
(βf +1)Ibe
−
(βr +1)Ibc
−
(a).
(b).
Figure (3.4). (a). An NPN bipolar junction transistor operated with a forward biased base-emitter junction and a short circuited
base-collector junction. Voltage Ve is presumed to be at
least as large as the threshold voltage of the base-emitter diode. (b). An NPN bipolar junction transistor operated with
a forward biased base-collector junction and a short circuited base-emitter junction. Voltage Vc is at least as large
as the threshold voltage of the base-collector diode.
βf
Ic
=
αf ,
(3-12)
I e V =0
βf +1
c
where parameter αf is commonly referred to as the short circuit emitter to collector current
transfer ratio. This parameter is a measure of the extent of forward recombination in that (3-12)
makes clear that the amount of emitter current that is not observed as collector current and is
therefore “lost” in recombination, is (1−αf)Ie. For large βf and therefore for αf approaching
unity, forward recombination in the base is minimal.
On the other hand, with Ve = 0, Icc in (3-5) and Ibe in (3-8) are null and resultantly,
I b = I bc
(3-13)
I c = − I rr − I bc = − ( βr + 1) I bc = − ( βr + 1) I b .
I e = − I rr = − βr I bc = − βr I b
The last result begets the circuit level representation in Figure (3.4b) in which the voltage, Vc, applied from the base to the collector is presumed to be at least as large as Vcon, the threshold voltage of the base-collector diode. In the circuit diagram at hand, parameter βr is recognized as the
magnitude of the base to emitter current transfer ratio. The indicated positive value of the applied voltage Vc serves to inject carriers from the collector to the emitter. Many of these injected
carriers recombine with holes in the base, while others are transported to the emitter to manifest
the current, −βrIb. The resultant ratio of emitter current to collector current is
Ie
βr
=
αr .
(3-14)
I c V =0
βr + 1
e
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Since βr is of the order of one, at least half of the aforementioned injected carrier population is
lost to recombination within the base volume. In (3-4), parameter αr is the short circuit collector
to emitter current transfer ratio.
3.2.1.1. Forward Active Operation
A bipolar junction transistor is said to operate in its forward active, or linear active, regime when its base-emitter junction voltage exceeds the threshold potential (Ve ≥ Veon) of the
base-emitter junction and its base-collector voltage is non-positive (Vc ≤ 0); that is the basecollector junction operates at either zero bias or is reverse biased by external means. The transistors in almost all bipolar technology circuits that are designed to operate as acceptable
approximations of linear networks are biased in this operating domain. For Ve ≥ Veon and Vc ≤ 0,
it is instructive to cast the collector current, Ic, in (3-3) as
I c = β f I be − ( βr + 1) I bc = β f I b − β f + βr + 1 I bc .
(3-15)
(
)
Recalling (3-10),
)
)
⎛ β f + βr + 1 ⎞
V nV
V nV
Ic = β f Ib − ⎜
⎟ Ae J s e c r T − 1 = β f I b − I co e c r T − 1 , (3-16)
βr
⎝
⎠
(
(
where
⎛ β f + βr + 1 ⎞
(3-17)
I co ⎜
⎟ Ae J s
β
r
⎝
⎠
is termed the collector leakage current. Specifically, Ico is the collector current fashioned by an
open circuited base (Ib = 0) and a base-collector junction that is strongly reverse biased (Vc <<
0). This current is small since it derives from the minority carrier injection across the basecollector junction that strong reverse junction biasing promotes.
There are at least two interesting aspects to (3-16). First, for Vc ≤ 0,
Ic
≈ β f I b + I co ≈ β f I b ,
(3-18)
Vc ≤0
Base
Ib
Ve
+
−
Ic
+ Vc ≤ 0 −
Ibe
+
Collector
Base
Ib
−
DBE
βf Ib Vb
Ie
−
Ve
+
Ic
− Vc ≤ 0 +
Ibe
−
DBE
βf Ib Vb
Ie
Emitter
(a).
Collector
+
Emitter
(b).
Figure (3.5). (a). Approximate equivalent circuit of an NPN BJT for the case in which the base-emitter junction voltage, Ve, is at least as large as the threshold voltage, Veon, of the junction,
and the base-collector junction voltage, Vc, is negative or no larger than zero. (b).
Approximate equivalent circuit of a PNP BJT for the case in which Ve is at least as large
as the threshold voltage of the junction, and Vc is negative or no larger than zero.
which suggests that to the extent that parameter βf is a constant and Ico << βfIb, the collector current of a BJT operated in the forward active region is directly proportional to its base current;
that is, the BJT emulates input base current to output collector current linearity. To this end, the
BJT might be modeled for Vc ≤ 0 by the simple equivalent circuits postured in Figure (3.5).
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BJT Models & Biasing
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Moreover, since βf is a transistor metric that is significantly greater than one, the linearity between base and collector currents that is inferred by (3-18) establishes a vehicle for the realization of I/O gain from an input base port to an output collector port. A second point pertinent to
(3-18) is that for Vc ≤ 0, current Ibc in (3-10) is essentially zero, which means that the forward
recombination current, Ibe, dominantly determines the observed base current, Ib. Accordingly,
(3-8) and (3-10) combine to yield
Ic
(
Ve n f VT
≈ β f I b ≈ β f I be = I cc = Ae J s e
Vc ≤0
)
(
Ve n f VT
− 1 = Is e
)
−1 .
(3-19)
The last result is interesting in that it shows that in the forward active region, the collector current of a BJT is determined almost exclusively by the base-emitter junction voltage, Ve.
Actually, since Ic ≈ Icc ≈ βfIbe, Ib ≈ Ibe, and Ie ≈ Icc + Ibe = (βf +1)Ibe for Vc ≤ 0, all three transistor
currents, as opposed to the collector current alone, are determined almost exclusively by voltage
Ve. This state of affairs is cause for jubilation since a design scenario in which all three transistor
currents are predicated on a single device voltage is decidedly easier to embrace analytically than
is a situation in which said currents are fixed by a suitable combination of two transistor voltages. It is important to understand that the transistor currents are independent of base-collector
junction voltage only if the base collector junction is not forward biased. From (3-2), this
requirement translates to an internal collector-emitter voltage (or emitter-collector voltage in
PNP units), Vb, that must equal or exceed the base-emitter junction voltage Ve. In short, forward
linear active BJT operation requires Vb ≥ Ve ≥ Veon.
3.2.1.2. Reverse Active Operation
A bipolar junction transistor operating in its reverse active regime is the converse of
forward active transistor operation; that is, the base-collector junction potential exceeds threshold
potential (Vc ≥ Vcon), while its base-emitter voltage is non-positive (Ve ≤ 0). Transistors embedded in linear signal processing networks rarely operate as reverse active devices. Indeed, device
operation in this domain is invariably the result of errors either in biasing or in topological layout. With Vc ≥ Vcon and Ve ≤ 0, (3-3), (3-4), and (3-8) deliver
⎛ β f + βr + 1 ⎞
V n V
V nV
I e = − βr I b + ⎜
⎟ Ae J s e e f T − 1 = − βr I b + I eo e e r T − 1 , (3-20)
⎜
⎟
βf
⎝
⎠
where
⎛ β f + βr + 1 ⎞
I eo ⎜
(3-21)
⎟ Ae J s
⎜
⎟
β
f
⎝
⎠
is termed the emitter leakage current. In particular, Ieo is the emitter current that results from an
open circuited base (Ib = 0) and a base-emitter junction that is strongly reverse biased (Ve << 0).
By comparison with (3-17), Ieo is smaller than the collector leakage current, Ico, in that parameter
βf is much larger than parameter βr.
(
)
(
)
With voltage Ve ≤ 0, current Ibe in (3-8) becomes entirely negligible, whence the base
current, Ib, in reverse active mode is largely determined by the reverse recombination current, Ibc.
Accordingly, the emitter current in (3-20) is set by the base-collector voltage, Vc, and is essentially independent of the base-emitter voltage, Ve. But since Ib ≈ Ibc and Ic = Ie − Ib ≈ −(βr +
1)Ibc with Ve ≤ 0, all currents in a reverse active transistor are approximately fixed by only voltage Vc. Moreover, the pertinent magnitude of the collector current to base current ratio is seen to
Ming Hsieh Department of Electrical Engineering
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BJT Models & Biasing
J. Choma
be (βr +1), which is far less than the base to collector transfer ratio, βf, evidenced in forward
mode. The fact that the collector current to base current ratio is a measure of the achievable gain
in a bipolar stage is reason enough to steer clear of reverse active operation in favor of forward
active operation.
3.2.1.3. Saturation
A BJT operates in saturation when both its base-emitter and base-collector junctions are
forward biased. In the saturation regime, the base of a transistor is injected with mobile charge
carriers from both the emitter and the collector, and all transistor currents are resultantly influenced by both of the junction voltages, Ve and Vc. Using (3-3), the collector to base current ratio
in saturation is
β f − ( βr + 1) ( I bc I be )
I − ( βr + 1) I bc
Ic
(3-22)
= cc
=
.
Ib
I be + I bc
1 + ( I bc I be )
Since the recombination currents, Ibe and Ibc, are each positive in saturation, the collector current
to base current ratio in (3-22) is clearly smaller than the gain metric, βf. In a word, the collector
current to base current ratio always falls below the short circuit current gain, βf, when a transistor
operates in its saturation domain. Aside from the dependence of all transistor currents on both
transistor junction voltages, the degradation in I/O gain measure is ample reason to avoid saturation like the proverbial plague in linear BJT signal processing networks. Another reason to avoid
saturation is poor frequency response since a significant amount of time is likely to be required
to displace the enormous density of charge injected into the base. Additionally, and as is discussed shortly, saturation incurs current flow in the substrate body of a monolithic transistor,
which can cause potentially damaging substrate heating and other deleterious effects.
Finally, the intrinsic collector-emitter voltage in (3-2) is the difference of two positive
junction voltages when the subject transistor enters its saturation regime. Because of the doping
disparity between the emitter and collector volumes, this difference is always positive. It is normally designated as the collector-emitter saturation voltage, Vcesat, which is dependent on
transistor currents and is typically in the range of 50 mV to 300 mV. We can determine the
collector-emitter saturation voltage by solving (3-22) for the recombination current ratio, Ibc/Ibe.
Denoting this ratio by Xce,
β f − ( Ic Ib )
I
(3-23)
X ce bc =
,
I be
1 + βr + ( I c I b )
which is zero if (Ic/Ib) = βf. This disclosure is synergistic with engineering expectations in that
(Ic/Ib) = βf in only the forward active regime of operation where the reverse recombination current, Ibc, approaches zero. Since (Ic/Ib) < βf in saturation positive Xce is indicative of device
saturation. The result at hand, coupled with (3-3) and (3-8), delivers
(1 + X ce ) Ae J s Ve n f VT
(3-24)
I b = (1 + X ce ) I be =
e
−1 ,
βf
(
)
whence a base-emitter junction voltage of
β f Ib
⎡
⎤
Ve = n f VT ln ⎢1 +
(3-25)
⎥.
+
1
X
A
J
(
)
ce
e
s
⎣
⎦
It is interesting that operation in the saturation domain, where Xce > 0, reduces the base-emitter
junction voltage from the level evidenced for a similar base current conducted by a transistor in
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its forward active domain. This effect is reasonable in light of the fact that in saturation, the base
current is partitioned between base-emitter and base-collector recombination components while
in the active domain, the base current is almost exclusively determined by base-emitter
recombination phenomena.
Returning to (3-23), (3-3) and (3-10) yield
⎛ 1 + X ce ⎞
(1 + X ce ) Ae J s Vc nrVT
(3-26)
−1 ,
Ib = ⎜
e
⎟ I bc =
X ce βr
⎝ X ce ⎠
which establishes a base-collector junction voltage of
⎡
X ce βr I b ⎤
Vc = nrVT ln ⎢1 +
(3-27)
⎥.
+
1
X
A
J
(
)
ce
e
s
⎣
⎦
Recalling (3-2) and assuming Xce > 0, the collector-emitter saturation voltage, Vcesat, in an NPN
unit (or emitter to collector saturation voltage, Vecsat, in a PNP transistor) is
n
⎧⎡
β f Ib
⎤ f ⎫
⎪ ⎢1 +
⎪
(1 + X ce ) Ae J s ⎥⎦ ⎪⎪
⎪⎪ ⎣
Vcesat = Ve − Vc = VT ln ⎨
, X ce > 0 .
(3-28)
nr ⎬
⎪⎡
X ce βr I b ⎤ ⎪
⎪ ⎢1 +
(1 + X ce ) Ae J s ⎥⎦ ⎪⎭⎪
⎩⎪ ⎣
Using (3-23), it is a simple matter to confirm that gain parameter βf is always larger than the
product, Xceβr, and indeed, it is never equal to Xceβr. It follows that the collector-emitter saturation voltage in (3-28) is always a nonzero and positive voltage. For the case of identical junction
injection coefficients, say nf = nr = n, the small transistor saturation current, AeJs, simplifies (328) to
⎛ βf ⎞
(3-29)
Vcesat = Ve − Vc ≈ nVT ln ⎜
⎟ , X ce > 0 ,
X
β
⎝ ce r ⎠
which suggests that the saturation voltage is nominally dependent on only the current ratio, (Ic/Ib)
(because of parameter Xce), and not on the individual transistor currents, Ic or Ib.
(
)
3.2.1.4. Cutoff
There is nothing fundamentally wrong with asserting that a transistor is cutoff when
any one of its three currents is zero. Historically, however, a transistor is said to be in cutoff
when its emitter current, Ie is zero. You are asked to investigate this useless operating case in
Problem #3.3.
EXAMPLE #3.1:
In an integrated circuit realized in bipolar transistor technology, PN junction diodes are
realized as appropriate connections of bipolar junction transistors. Three plausible
realizations appear in Figure (3.6). For each of these “diodes,” determine the volt-ampere characteristic equations, Id -versus- Vd, and give expressions for their effective
saturation currents. Assume that the junction injection coefficients of the transistor are
identical and equal to n.
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SOLUTION #3.1:
(1).
In the interconnection of Figure (3.6a), the base and collector terminals are connected together, thereby constraining base-collector junction voltage Vc to zero and rendering voltage
Vd equal to the base-emitter junction voltage, Ve. With Vc = 0, Ibc and Irr in (3-3) are null and
thus, (3-3) and (3-8) provide
Id
+
Id
−
+
Vd
Vd
Vd
−
Id
(a).
(b).
+
−
(c).
Figure (3.6). (a). A diode formed by short circuiting the base to the collector
of an NPN BJT. (b). A diode formed by short circuiting the base
to the emitter of a PNP BJT. (c). A diode formed by short
circuiting the collector to the emitter of an NPN BJT.
(
)
I d = I b + I c = I be + I cc = β f + 1 I be .
(E1-1)
Using (3-8) once again, it follows that the volt-ampere characteristic of the subject diode
interconnection is
⎛ βf +1⎞
V nV
Id = ⎜
⎟A J e d T − 1 ,
(E1-2)
⎜ βf ⎟ e s
⎝
⎠
whereupon the effective saturation current, say Io, is seen to be
⎛ βf +1⎞
AJ
Io = ⎜
⎟ Ae J s = e s .
(E1-3)
⎜ βf ⎟
αf
⎝
⎠
)
(
(2).
In Figure (3.6b), the base and emitter terminals are tied together, thereby constraining baseemitter junction voltage Ve to zero and rendering voltage Vd equal to base-collector junction
voltage Vc. With Ve = 0, Ibe and Icc in (3-3) are zero and thus, (3-3) and (3-10) yield
I d = − I c = I bc + I rr = ( βr + 1) I bc .
(E1-4)
Using (3-10) the volt-ampere characteristic of the subject diode interconnection is
⎛ β +1⎞
V nV
Id = ⎜ r
(E1-5)
⎟ Ae J s e d T − 1 ,
⎝ βr ⎠
)
(
and the saturation current follows as
⎛ β +1⎞
Ae J s
.
Io = ⎜ r
⎟ Ae J s =
αr
⎝ βr ⎠
(3).
(E1-6)
In Figure (3.6c), the collector and emitter terminals are interconnected, thereby rendering Vd
= Ve = Vc. Accordingly, (3-3), (3-8) and (3-10) combine to give
I d = I b = I be + I bc ,
(E1-7)
and the volt-ampere characteristic of the subject diode interconnection is
⎛ 1
1 ⎞
V nV
Id = ⎜
+
⎟ Ae J s e d T − 1 .
(E1-8)
⎜ βf
⎟
β
r⎠
⎝
Clearly, the corresponding saturation current, Io, is
(
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)
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⎛ 1
1 ⎞
Io = ⎜
+
⎟ Ae J s .
⎜ βf
βr ⎟⎠
⎝
(E1-9)
COMMENTS: The only diode interconnection of the three considered topologies that precludes a forward biased base-collector junction is the configuration of Figure (3.6a). As is demonstrated subsequently, a forward biased basecollector junction can be detrimental in monolithic bipolar technology circuits and consequently, the diode configuration of Figure (3.6a) is rightfully deemed the most efficacious of the three considered interconnections.
EXAMPLE #3.2:
A PNP bipolar junction transistor has a forward short circuit current gain, βf, of 100
amps/amp, a reverse short circuit current gain, βr, of 1.0 amp/amp, a base-emitter junction injection coefficient, nf, of 1.025, and a base-collector junction injection coefficient,
nr, of 1.0. When operated at room temperature (27 °C) in a particular circuit, the collector current, Ic, is measured to be 2 mA, while the base current is determined to be 200
μA. Calculate the emitter-collector saturation voltage, Vecsat. Assume a room temperature saturation current, Is, of 2 fA.
SOLUTION #3.2:
(1).
Since Ic/Ib in this example is 2 mA/200μA = 10, which is obviously smaller than βf, the subject transistor is saturated. For the quoted parameters and Ic/Ib = 10, equation (3-23), which
is applicable for NPN and PNP units alike, delivers a recombination current ratio, Xce =
Ibc/Ibe of Xce = 7.50.
(2).
At a junction temperature of Tj = 27 °C, the Boltzmann voltage, VT, is VT = 25.89 mV. With
Xce = 7.50, (3-28) resultantly delivers an emitter-collector saturation voltage of Vecsat = 85.05
mV.
COMMENTS: As confirmed above, the emitter-collector saturation voltage is a small,
positive number. It should be understood that the measured value of this
metric is somewhat larger owing to ohmic resistances in the collector and
emitter leads of the transistor. These resistances are addressed shortly.
The fact that Xce is 7.50 indicates that the reverse recombination current
precipitated by base region mobile carriers and collector-injected carriers
is 7.5-times larger than the forward recombination current attributed to
base region and emitter-injected carriers. In general, Xce > 1 is the norm
in that the base region doping concentration is larger than the collector
impurity concentration, which in turn is several orders of magnitude
smaller than the impurity concentration in the emitter volume.
3.2.2. ENHANCEMENTS TO THE EBERS-MOLL MODEL
Despite its better than half century age, the Ebers-Moll model remains a viable design
tool for manually estimating bipolar circuit performance. Viability notwithstanding, numerous
enhancements to the model demonstrably improve its accuracy, particularly for scaled, minimal
geometry, monolithic bipolar devices. A definitive discussion of all of the modeling improvements postured in the archival literature in the better than five decades since the original publicaMing Hsieh Department of Electrical Engineering
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tion of the seminal Ebers and Moll paper is beyond the scope of this chapter. However, four specific modeling enhancements are potentially vital for a realistic design-oriented analyses of
monolithic circuits that exploit state of the art bipolar devices in linear network applications.
These improvements entail corrections for the transport current in the face of high emitter-base
carrier injection, adjustments to the transport current necessitated by base conductivity modulation, parasitic resistances in the base, emitter, and collector, and incorporation of high frequency
effects on the I/O transfer characteristics. The enhancements in the subsections that follow pertain only to the linear forward active regime of BJT operation (Ve ≥ Veon and Vc ≤ 0) since the focus of this chapter, and indeed the majority of this text, is circuit analysis that underpins the design and realization of linear active networks.
3.2.2.1. High Injection Phenomena
The Ebers-Moll model implicitly presumes a low injection condition. For forward active operating circumstances, low injection operation is tantamount to a concentration of injected
carriers from the emitter to the base that is significantly smaller than the background impurity
concentration in the base volume. As this injected charge level rises toward the level of the base
dopant concentration, a high injection condition is initiated, which manifests impaired carrier
mobility due to the traffic jam of minority carriers that accumulate in the base. The upshot of degraded carrier mobility is an increased likelihood of carrier recombination, thereby giving rise to
diminished charge transport into the collector region and hence, a reduced collector current. For
the large geometry transistors prevailing some four or five decades ago and for most present day
discrete component transistors, the low injection presumption is appropriate. But low injection
presuppositions become progressively more dubious as transistor geometries shrink to the submicron scale that is commonplace in the monolithic state of the art. The Gummel-Poon model of a
BJT accounts for these high injection effects by supplanting the transport current, Icc, in (3-5)
with a corrected transport current, Ict, which is given by[2]
I cc
I cc
I ct ≈
=
,
(3-30)
I cc
I cc
1+
1+
I kf
Ae J kf
where Ikf is termed the forward knee current of the bipolar device, and Jkf is the corresponding
forward knee current density[3]. The knee current parameter is a measure of the onset of high
injection phenomena in the sense that Icc << Ikf is indicative of low injection conditions. When
Icc, which remains stipulated by (3-5), is, in fact, significantly smaller than Ikf, Ict collapses to the
transport current predicted by Ebers and Moll.
Base
Ib
Ve
+
−
Ic
+ Vc ≤ 0 −
Ibe
+
DBE
Ict
Ie
Collector
Vb
−
Emitter
Figure (3.7). Linear forward active region model of an NPN
BJT with a correction adopted for high injection
effects on carrier transport. The current, Ict, is
given by (3-30). The indicated junction voltage,
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Ve, must be at least as large as the threshold voltage, Veon, of the base-emitter junction.
We can gain a fundamental understanding of the impact of high injection phenomena
on bipolar transistor performance by examining the model in Figure (3.7), which depicts the corrected form of the large signal bipolar model. Only an NPN model is drawn since the PNP
model is little more than its NPN counterpart with the current directions and voltage polarities
reversed. The model clearly establishes a collector current, Ic, of[4]
I cc
I c = I ct =
.
(3-31)
I cc
1+
Ae J kf
At low injection levels,
V n V
I c = I ct ≈ I cc ≈ Ae J s e e f T ,
(3-32)
where the unity term in the parenthesized quantity on the right hand side of (3-5) is ignored in
deference to the requirement that Ve be at least as large as the base-emitter junction threshold
potential, Veon. This threshold voltage is typically more than 25-times the effective thermal voltage, nfVT, which certainly justifies the neglect of the unity term in comparison to the exponential
term. On the other hand, at high levels of carrier injection and correspondingly large forward
transport currents, Icc, (3-31) approaches
I c = I ct ≈
Ve 2n f VT
Ae J kf I cc ≈ Ae J kf J s e
.
(3-33)
Note that while the natural logarithm of the low injection collector current in (3-32) rises linearly
with Ve/nfVT, the logarithm of the high injection collector current in (3-33) rises linearly with
Ve/2nfVT. In effect, the forward base-emitter junction voltage to collector current transconductance, for which a measure is the derivative, dIc/dVe, is reduced by the onset of high injection
phenomena.
A related high injection phenomenological effect is an attenuation of the static current
transfer ratio, Ic/Ib. Recalling (3-3) and (3-8), the Ebers-Moll, or low injection, BJT model predicts Ic/Ib ≈ βf in the linear domain. But noting that Icc = βfIb in this regime, (3-31) predicts
Ic
βf
≈
.
(3-34)
Ib
I cc
1+
Ae J kf
In general, this transfer relationship is traditionally symbolized as hFE, which is commonly referred to as the DC beta, or static beta of a transistor. Thus, at this stage of the model development,
Ic
βf
βf
hFE ≈
=
.
(3-35)
Ib
I cc
I cc
1+
1+
Ae J kf
I kf
As is demonstrated in discussions surrounding the design of suitable biasing networks for bipolar
technology circuits, hFE is a troublesome parameter largely because of its direct dependence on
parameter βf. In particular, the numerical value of βf suffers a variance of at least three -to- one
owing to process uncertainties surrounding the implementation of a stereotypical submicron base
width. The problem stems from the fact that βf is inversely dependent on the base width, whose
control at submicron dimensions proves to be a daunting fabrication challenge. The lesson we
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should learn here is that bipolar circuit design should be accomplished to ensure that critical
performance metrics are not directly dependent on the highly vagarious parameter, hFE.
3.2.2.2. Base Conductivity Modulation
The large signal BJT model in Figure (3.7) represents the collector-emitter port as an
ideal controlled current source, Ict, that is independent of the internal collector-emitter voltage,
Vb, and thus independent of the base-collector junction voltage, Vc. But it is intuitively evident
that the transport of emitter-injected charge through the base and on into the collector is promoted by increased reverse bias across the base-collector PN junction. Equivalently, such
charge transport is encouraged by increasing the internal collector-emitter voltage, Vb. This
assertion stems from (3-2), which suggests that as Vb rises, voltage Ve, the forward biasing potential across the intrinsic base-emitter PN junction, changes only modestly from its threshold, or
turn on, level. Thus, most of the increase afforded to voltage Vb is mirrored by an increase in
(−Vc).
The enhanced transport current promoted by increases in voltage Vb is known as the
Early effect[5]. Two engineering reasons can be proffered to explain this transport current
phenomenon. First, an increased Vb results in increased reverse bias across the base-collector
junction, as noted above. This boost in reverse bias establishes stronger electric fields in the
depletion layer surrounding the base-collector junction and in turn, these robust fields exert
progressively more compelling attractive forces on the mobile carriers that are injected into the
base volume from the emitter region. Such attractive forces serve to inhibit recombination between emitter-injected and base region carriers, thereby facilitating forward charge carrier transport through the base and hence, increased collector current. Second, the increased reverse bias
at the base-collector junction widens the junction depletion layer therein. The immediate result
of such widening is a commensurate narrowing of the neutral base width, which further decreases the likelihood of recombination of injected carriers with majority carriers in the base.
Stated quite simply, the charge neutral base volume where recombination is most likely to occur
is reduced. Collectively, the two reasons articulated herewith argue that the increased basecollector reverse bias increases the conductivity of the neutral base so that charge transport
through the entire base is correspondingly promoted.
A physically sound model for the foregoing base conductivity modulation, or Early effect, proves too cumbersome for manual estimates of static BJT performance. Instead, an
empirical representation of the form,
⎛
V ⎞
I cc ⎜ 1 + b ⎟
⎜
Vaf ⎟⎠
⎛
V ⎞
⎝
(3-36)
Ic =
= I ct ⎜ 1 + b ⎟ ,
⎟
⎜
V
I cc
af
⎝
⎠
1+
I kf
is adopted for circuit level modeling, where Ict is given by (3-31) and voltage Vaf is an
experimentally discerned Early voltage parameter, whose value for minimal geometry transistors is typically in the mid to high tens of volts. The resultant electrical model for the NPN device is shown in Figure (3.8), where it can be seen that the appended parenthesized term on the
right hand side of (3-36) establishes a current-dependent resistance. This resistance, whose value
is inversely proportional to current Ict, is in shunt with the controlled source, Ict.
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We must now update the static current gain of the transistor to the slightly more
complicated form,
⎛
⎛
V ⎞
V ⎞
β f ⎜1 + b ⎟
β f ⎜1 + b ⎟
⎜
⎜
Vaf ⎟⎠
Vaf ⎠⎟
Ic
⎝
⎝
(3-37)
hFE ≈
=
.
Ib
I cc
I cc
1+
1+
Ae J kf
I kf
Base
Ib
Ve
Ic
+ Vc ≤ 0 −
+
−
+
DBE
Ict
Ie
Collector
Vaf
Ict Vb
−
Emitter
Figure (3.8). Linear forward active region model of an NPN BJT
with an account made of both high injection and base
conductivity modulation (Early effect) phenomena.
Observe that the behavioral expression for the Early effect in (3-36) and in the current gain
expression of (3-37) somewhat (but certainly incompletely) mitigates the deleterious impact of
high injection phenomena. This observation explains why circuit designers interested in only a
quick first order estimate of static BJT performance commonly opt for invoking only the EbersMoll model.
3.2.2.3. Parasitic Resistances
The model in Figure (3.8) highlights only intrinsic transistor action in that the voltages
appearing at the terminals of the transistor are internal base-emitter junction voltage, Ve, internal
base-collector junction voltage, Vc, and internal collector-emitter voltage, Vb. In physically
realizable structures, these internal voltages couple electrically to the accessible external terminals of the device through series resistances derived from the charge neutral regions of the
collector, emitter, and base volumes. At the collector, a resistance, rc, appears as depicted in the
revised model of Figure (3.9), in which both NPN and PNP models are offered in the interest of
analytical completeness. Because of the length of the collector region and its low impurity
concentration, rc is a relatively large resistance. For minimal geometry devices destined for
broadband circuit applications, rc is in the range of mid tens of ohms to as much as low hundreds
of ohms. In contrast, the extremely high impurity concentration of the emitter, together with its
short length, promotes a series emitter resistance, re, that is very small, particularly for silicongermanium heterostructures. Typically, re is a few tenths of ohms to a few ohms. Both rc and re
scale inversely with the base-emitter junction area, Ae, and since both are physical ohmic resistances, both contribute thermal noise to the total integrated output noise generated by the transistor.
The base resistance, rb, like emitter resistance re and collector resistance rc, is an ohmic
element that generates thermal noise and scales inversely with the base-emitter junction area.
Owing to the inherently two-dimensional nature of the volt-ampere characteristics in the base region and emitter crowding, rb, is current dependent[6],[7]. The phrase, “emitter crowding,” refers
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to an inability to establish uniformly constant voltage bias across the width of the base-emitter
junction of a monolithic device. A commonly invoked empirical expression for the base resistance of a bipolar device subjected to emitter crowding is
r − Rbm
(3-38)
rb = Rbm + bb
,
1 + ( I c I rb )
Base
Ib
rb
rc
+ Vc ≤ 0 −
+
Ve
+
−
Vbe
+
Ict Vb
−
DBE
Ibe
Ic
+
Collector
Vaf
Ict
Vce
Ie
re
−
Base
−
Ib
(a).
rb
rc
− Vc ≤ 0 +
−
Ve
Veb
−
+
−
Ict Vb
+
DBE
Ibe
Ic
−
Emitter
Collector
Vaf
Ict
Vec
Ie
re
+
+
Emitter
(b).
Figure (3.9). (a). The NPN BJT model of Figure (3.8) embellished by the incorporation
of series resistances rc, re, and rb in the collector, emitter, and base leads,
respectively. For most modeling circumstances, resistances rc and re can
be ignored. (b). The PNP model counterpart to the NPN model in (a).
where Ic is the collector current, Irb is an experimentally deduced constant that scales with baseemitter junction area, Rbm is the minimum base resistance (typically tens of ohms as extrapolated
from high current measurements), and rbb is the zero bias (meaning Ic = 0) value of the measured
base resistance. For minimal geometry transistors, current parameter Irb is generally of the order
of one-half the transistor forward knee current, Ikf, while resistance rbb can be as large as a few
hundred ohms. Figure (3.10) displays a plot of the normalized base resistance, rb/rbb, versus the
normalized collector current, Ic/Irb, for various resistor ratios, rbb/Rbm. Notice that a better than
two factor between the actual base resistance, rb, and its zero current value, rbb, is possible for
even reasonable values of collector current. Because large base resistance generally reflects
worst case operating conditions, in the senses of incurring reduced I/O voltage gain, compromised bandwidth, and increased thermal noise contribution to the net integrated output noise of a
transistor, designers typically adopt the conservative worst case design stance of presuming a
base resistance equaling its zero current value.
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Norm. Base Resistance, (r b /r bb )
r bb /R bm = 2
r bb /R bm = 4
0.8
0.6
0.4
r bb /R bm = 20
r bb /R bm = 10
0.2
0
0
0.2
0.4
0.6
0.8
1
1.2
1.4
1.6
1.8
2
Norm. Collector Current, (I c /I rb )
Figure (3.10). The dependence of the internal base resistance, rb, on the collector current flowing in
a bipolar junction transistor.
3.2.2.4. Transistor Capacitances
An accurate assessment of the impact of high signal frequencies on transistor
characteristics is a daunting challenge requiring careful consideration of charge storage and related memory effects that prevail within the semiconductor body of a bipolar junction transistor.
At the circuit level, at least three capacitances must be incorporated into the transistor model to
bracket the effects that high signal frequencies exert on observable BJT circuit performance.
These capacitances are the base-emitter capacitance, Cπ, the base-collector junction depletion
capacitance, Cμ, and the substrate depletion capacitance, Cs, as depicted in the high frequency
NPN BJT model set forth in Figure (3.11). An analogous model prevails for the PNP device,
wherein all current directions, all voltage polarities, and all diode interconnections are reversed.
Base
Ib
rbb
+
Ve
Vbe
Cμ
+
−
DBE
rc
+
−
Vc ≤ 0
Cπ
+
Ict Vb
Ibe
−
−
Vaf
Vsc
DSC
Ict
+
Ic
+
Collector
Cs
Vce
Ie
re
−
Substrate
−
Emitter
Figure (3.11). High frequency model of the NPN BJT. The high frequency model of a PNP BJT is
topologically similar, with the provisos that the connections of both diodes are reversed, all
voltage polarities are reversed, and the directions of all currents are reversed.
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As in the case of a forward biased PN junction diode, the shunt interconnection of two
capacitances model the high frequency effects at the base-emitter junction of a BJT operated in
the linear active mode of transistor operation, where Ve ≥ Veon and Vc ≤ 0. The dominant component of these two capacitances is the base-emitter diffusion capacitance, Cbe. It is reminiscent
of the diffusion component of net PN junction diode capacitance in that it models the effects of
charge stored temporarily in the volume prior to its transport through or recombination in the
base volume. This diffusion component, Cbe, of base-emitter junction capacitance is expressible
as
(3-39)
Cbe = τ fe g m ,
where τfe is the average time required to transport minority carriers through the base region and
gm is the forward transconductance of the BJT. Parameter τfe is naturally affected by the average mobility of the minority carriers in the base. Since minority carrier mobility diminishes with
the increasing carrier concentration that necessarily underpins forward transport current in a BJT,
τfe can be expected to increase with progressively larger transport currents. In effect, increased
device capacitances, and thus potentially impaired circuit response speeds, can be expected when
BJTs are compelled to conduct relatively large collector currents. The degradation of transport
time induced by pronounced carrier concentrations in the base is somewhat mitigated by the imposed base-collector junction reverse bias, which exerts an attractive force on carriers injected
into the base from the emitter. Accordingly, a plausible semi-empirical relationship for the
effective minority carrier transport time, τfe, in (3-39) is
Ic ⎞
⎛
+
1
⎜
I kf ⎟
⎟,
τ fe = τ fo ⎜
(3-40)
⎜ 1 + Vb ⎟
⎜
Vaf ⎟⎠
⎝
where τfo is the low current (small Ic), Vc = 0 value of the minority carrier transport time in the
base of a BJT. Observe that the expression in question allows τfe to increase with progressive increases in the collector current, Ic, which is given by (3-31). On the other hand, (3-40) permits
τfe to decrease with increasing Vb, which relates implicitly to the magnitude of reverse bias to
which the base-collector junction is subjected. A small, but nonetheless important engineering
lesson surfaces herewith. In particular, increasing Vb reduces τfe, and hence device capacitance
Cbe, thereby promoting the possibility of improved circuit response speeds. But Vb increases
only if a suitably larger voltage, Vce, biases the collector-emitter terminals of a transistor. In turn
and for a given collector current, increased Vce increases the power dissipated in a BJT, thereby
encouraging the philosophical stance that the price paid for improved circuit response speeds or
bandwidth is likely increased circuit power dissipation.
Continuing with (3-40), parameter τfo is typically in the range of tens to hundreds of
picoseconds for minimal geometry transistors. For silicon-germanium heterostructure BJTs, τfo
can be as small as only a few tenths of a picosecond. Since parameter τfo is nominally proportional to the square of base width Xb in Figure (3.1), a progressive narrowing of the base region
yields dramatic dividends insofar as a reduction of base-emitter diffusion capacitance, Cbe, is
concerned. There are, however, limits to the base region narrowness that can be tolerated. In
particular, too narrow a base promotes a voltage breakdown condition known as punch through,
wherein the reverse bias imposed at the base-collector junction allows the base side boundary of
the base-collector depletion layer to encroach on the base-side boundary of the base-emitter
depletion layer.
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Finally, the transconductance metric in (3-39) is, using (3-36),
⎞⎛
∂I c
Ic ⎛
Ic
V ⎞
⎜1 −
⎟⎜1 + b ⎟ .
gm =
(3-41)
n f VT ⎜
Vaf ⎠⎟
∂Ve
2 I cc I kf ⎟ ⎜⎝
⎝
⎠
Assuming that voltage Vb is much smaller than the Early voltage, Vaf, as is often the case in welldesigned, high performance BJT networks, (3-36) combines with (3-41) to deliver
I c ⎛ 2 + I cc I kf ⎞
⎜
⎟.
gm ≈
(3-42)
2n f VT ⎜ 1 + I cc I kf ⎟
⎝
⎠
The last result portrays the forward transconductance as increasing linearly with collector current
Ic with a slope, dgm/dIc, of roughly 1/nfVT at low injection levels where Icc << Ikf. Under high
injection conditions, transconductance gm continues to increase with Ic, but at a slope, dgm/dIc,
that is a factor of two smaller than evidenced at low current levels. Another electronics lesson
surfaces for here for us. Specifically, transconductance gm is a measure of attainable I/O gain in
a BJT network. Increased gain potential accrues with increased gm, which obviously mandates
enhanced collector current. But the aforementioned slopes suggest that diminishing gain returns
accrue as currents approach levels commensurate with high injection operating conditions.
Although the base-emitter junction is forward biased in the linear active mode of BJT
operation, a narrow depletion layer nonetheless prevails at this PN junction. Accordingly, the
second component of the net base-emitter junction capacitance is a depletion capacitance, Cje,
which is associated with the transition region of the depletion layer. Under forward biased
circumstances, this capacitance, which is analogous to the depletion component of capacitance
prevailing in a forward biased PN junction diode, is given approximately by
C jeo
C je ≈
,
(3-43)
me
⎛
V ⎞
⎜⎜ 1 − eon ⎟⎟
V je ⎠
⎝
where Cjeo is the zero bias (meaning Ve = 0) value of the junction depletion capacitance, Vje is the
built-in potential of the base-emitter junction, and me is the grading coefficient of the subject
junction. The potential, Vje, is typically in the range of 800 mV to 900 mV, and parameter me is
usually close to 0.5. It is understood that capacitance Cjeo scales linearly with the base-emitter
junction area, Ae. In summary, the net base-emitter junction capacitance, Cπ, as delineated in
Figure (3.11), is, recalling (3-39), (3-40), (3-41), and (3-43),
⎞
⎛
C jeo
I ⎞ I ⎛
Ic
⎟ +
(3-44)
.
Cπ = Cbe + C je ≈ τ fo ⎜ 1 + c ⎟ c ⎜ 1 −
me
⎜
⎟ n f VT ⎜
⎟
I
2
I
I
kf
cc
kf
⎛
⎝
⎠
V ⎞
⎝
⎠
⎜⎜ 1 − eon ⎟⎟
V je ⎠
⎝
Since the base-collector junction of a BJT is reverse biased under linear active operating circumstances, the capacitance, Cμ, in Figure (3.11) is exclusively a depletion capacitance.
Accordingly, it is given by the familiar mathematical form,
C jco
Cμ =
.
(3-45)
mc
⎛
⎞
V
⎜⎜ 1 − c ⎟⎟
V jc ⎠
⎝
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In (3-35), Cjco is the zero bias (meaning Vc = 0) value of the base-collector junction depletion
capacitance, Vjc is the built in potential of the base-collector junction (of the order of 700 mV to
800 mV), and mc is the grading coefficient of the junction. Typically, 1/3 ≤ mc ≤ 1/2. Capacitance Cjco, like Cjeo, scales linearly with the base-emitter junction area.
Substrate Collector
Base
Emitter
Intrinsic
Transistor
N+ Collector Contact
N+ Type
Emitter
P-Type
Base
N-Type
Collector
P+ Substrate Contact
P+ Substrate Contact
Silicon Dioxide
N+ Buried Layer
P-Type Substrate
Figure (3.12). Simplified cross section representation of a monolithic NPN bipolar junction transistor.
The diagram is not drawn to scale. The section of the diagram enclosed by the dotted
rectangle is known as the intrinsic transistor. It corresponds to the cross section abstraction
appearing in Figure (3.1a).
In an attempt to facilitate our comprehension of the engineering significance of the substrate diode, DSC, and its associated substrate capacitance, Cs, it is necessary for us to digress to
the cross section diagram of a monolithic transistor. To this end, a simplified cross section of an
NPN monolithic BJT is abstracted in Figure (3.12). The vertical part of the diagram enclosed by
the dotted rectangle lying directly under the emitter terminal and consisting of the n+-emitter, the
p-type base, and the n-type collector is the intrinsic transistor and corresponds to the simplified
BJT structure we provided in Figure (3.1a). Since all terminal contacts are necessarily formed at
the surface of the structure, the collector metal contact is incident with a heavily doped diffused
or implanted collector contact to reduce the parasitic series resistance associated with the collector. A further reduction in this series resistance is fomented by assuring that this n+-collector
contact is deep enough to coalesce with the n+ buried layer that abuts the lightly doped intrinsic
collector region. The entire structure rests atop a lightly doped p-type substrate to which electrical accessibility is provided at the surface through dual p+-substrate contacts. Aside from allowing an electrical contact to the substrate foundation of the NPN transistor, these deep substrate
contacts create a mechanism to isolate the subject NPN device from adjacent on chip transistors.
The isolation proves effective if the substrate terminal at the transistor surface is incident with
the most negative potential afforded by the circuit in which the NPN transistor is electrically
embedded, thereby ensuring nominally non-conductive, reverse biased PN junctions around the
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periphery of the NPN unit. In effect, the reverse bias at the collector-substrate junctions renders
the NPN transistor a virtual electrical island in a sea of potentially many other active and passive
devices that are incorporated on the chip in question. Electrical contact is similarly made to the
p-type base by doping the base region adjacent to the emitter region sidewalls at a level that is
higher than the impurity concentration of the intrinsic base immediately below the emitter. In
addition to mitigating work function phenomena between metal contact and semiconductor and
reducing the series base resistance, this doping gradient minimizes carrier injection from the
emitter to the base along the emitter sidewalls, thereby rendering the simplistic diagram in Figure
(3.1a) reasonably reflective of the transistor action implied by the cross section under present
consideration.
Our study of the diagram in Figure (3.12) reveals that in addition to realizing the desired vertical NPN transistor, a parasitic PNP device, QP, is forged with the p-type substrate, the
n-type collector and the p-type base. While a parasitic PNP transistor is unquestionably formed,
questions can be raised as to whether its emitter is the NPN substrate or the base region of the
desired NPN unit. These questions can be answered only when the nature of the electrical
connection made to the substrate contact is clarified.
Collector
Collector
Base
Base
QP
Emitter
QP
Substrate
Emitter
(a).
Substrate
(b).
Figure (3.13). (a). Behavioral representation of a monolithic NPN transistor for the case in which
the substrate is biased to a potential that is larger than the potential applied to the
collector of the NPN device. (b). Behavioral representation of a monolithic NPN
transistor for the case in which the substrate is returned to the most negative circuit
potential afforded by the circuit into which the NPN transistor is embedded.
To the foregoing end, consider the atypical case in which the substrate is not connected
to the most negative of available circuit potentials and instead supports a voltage with respect to
ground that is larger than the voltage developed at the collector of the NPN transistor. Because
the substrate-collector junction is forward biased, the substrate can rationally be viewed as the
emitter of parasitic transistor QP, and the resultant circuit level abstraction becomes the structure
we show in Figure (3.13a). The forward bias across the substrate-collector junction allows holes
from the substrate to be injected into the NPN collector region, particularly in the substratecollector junction neighborhood lying to the right of the buried layer. Given that the base-collector junction of the NPN device is reverse biased for linear forward active operation, the basecollector junction of QP is correspondingly reverse biased. Traditional transistor action through
the PNP device is therefore fostered, which means that the base current conducted by the vertical
NPN device is perturbed by the collector current of the parasitic PNP transistor. Assuming that
the DC beta of QP is greater than one, the immediate impact of this enhanced NPN base current
is a reduction of the available current transfer ratio, hFE, for the NPN unit. Obviously, the power
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dissipation of the overall structure increases because the substrate now conducts the current that
is demanded by the emitter of transistor QP.
When, as is virtually mandated in linear signal processing applications, the substrate is
connected to the most negative circuit potential, the substrate-collector PN junction is reverse
biased. Accordingly, the substrate is precluded from serving as a PNP transistor emitter that
injects holes into the NPN collector, or equivalently, the PNP base. Instead, the substrate acts as
the collector region of transistor QP, thereby permitting the base of the NPN structure to be
delineated as the emitter of QP, as shown in Figure (3.13b). The routine reverse biasing of the
base-collector junction of the NPN transistor operated in its forward active mode imposes a reverse bias across the base-emitter junction of transistor QP. Consequently, QP conducts only
negligible leakage current and therefore exerts minimal impact on the operation of the target
NPN device at low signal frequencies. At high signal frequencies, the base-collector depletion
capacitance of QP can be absorbed into capacitance Cμ of the NPN transistor. Moreover, the reverse biased PN junction diode observed at the QP base-emitter junction shunts the reverse biased diode evidenced at the NPN base-collector junction. The reversed biased substrate-collector junction can be modeled as a shunt interconnection of a reverse biased diode, DSC, and the
depletion capacitance, Cs, associated with the substrate-collector junction. The foregoing capacitance item assumes its usual depletion capacitance form,
Cso
Cs =
,
(3-46)
ms
⎛
V ⎞
⎜⎜ 1 − sc ⎟⎟
V js ⎠
⎝
where Vsc is the reverse biased, and therefore negative, voltage established across the substratecollector junction, Vjs is the built in potential of said junction, ms is the grading coefficient of the
subject junction, and Cso is the Vsc = 0 value of the substrate-collector depletion capacitance. For
a properly biased, minimal geometry, high speed NPN transistor, Vjs is in the range of 550 mV to
700 mV, ms is of the order of a third, and Cso is typically a few femtofarads to tens of femtofarads.
The base-collector junction of the NPN transistor is forward biased when the device enters its saturation regime. Correspondingly, the base-emitter junction of the parasitic PNP device
in Figure (3.13b) mirrors this forward biasing, which, along with the imposed reverse bias at the
substrate-collector junction, forces QP to conduct and actually to function in its forward active
domain. The result is a degraded short circuit current gain in the NPN transistor, whose base
must now supply current to the PNP emitter. Aside from degraded current gain, the power
dissipation of the entire structure increases and undesirable heating of the substrate is incurred
because of the collector current manifested in transistor QP. These observations support our earlier contention that BJT operation in saturation must be avoided at all reasonable engineering
costs.
3.3.0. SMALL SIGNAL MODEL
In order for a bipolar junction transistor to respond in a nominally linear fashion to applied input signal excitation, it must be biased in its forward active domain. As we have previously asserted, the prerequisites cultivating operation in this domain are that (1) the base-emitter
junction voltage, Ve, be at least as large as the junction threshold voltage, Veon, and (2) the basecollector junction voltage, Vc, be negative or at most zero. The latter requirement is equivalent to
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stipulating that the internal collector-emitter (or emitter-collector in PNP devices) voltage, Vb, be
equal to or greater than the base-emitter junction voltage, Ve. For monolithic devices, an additional necessity is that the substrate terminal be returned to the most negative potential available
in the circuit into which the transistor is embedded. These biasing constraints establish a quiescent, or zero signal, collector current, say IcQ, and corresponding base and emitter quiescent currents, IbQ and IeQ, respectively, which are given by
I bQ = I cQ hFE
,
(3-47)
I eQ = I bQ + I cQ = ( hFE + 1) I bQ = ( hFE + 1) I cQ hFE = I cQ αFE
(
)
where hFE is given by (3-37) and
I cQ
hFE
αFE =
I eQ
hFE + 1
(3-48)
is nearly unity because hFE is typically much larger than one. The three quiescent BJT currents
correlate closely with a Q-point base-emitter terminal voltage VbeQ and correspond loosely to a
Q-point collector-emitter terminal voltage, VceQ, which, as inferred by Figure (3.11), satisfy the
KVL constraints,
VbeQ = I bQ rbb + VeQ + I eQ re
(3-49)
.
VceQ = I cQ rc + VbQ + I eQ re
Since VeQ > Veon and all transistor currents are nonzero and positive in the forward active regime,
VbeQ > VeQ > Veon. In actual practice, the Q-point base current and series emitter resistance are so
small that VbeQ is very nearly equal to VeQ. Moreover, the requirement that VcQ, the Q-point
value of the base-collector junction voltage, not exceed zero gives rise to the static operating
constraint, VceQ ≥ VbeQ.
rbb
rc
Cμ
Base
V
+
−
Collector
rπ
I
Cπ
gmV
re
ro
Cs
Substrate
Emitter
Figure (3.14). Approximate small signal model of either an NPN or a PNP bipolar junction transistor. The model presumes that the transistor undergoing study is
biased for linear operation in its forward active domain, which in turn
presupposes that the substrate terminal is incident with the signal ground
of the circuit into which the subject transistor is embedded. Subject to the
absence of relevant model information, resistances rc and re are routinely
taken to be zero.
In the forward active domain, the small signal model of either an NPN or a PNP bipolar
junction transistor is the structure depicted in Figure (3.14). The subject model is offered with
two caveats. First, it is presumed that the model is typically exploited to arrive at conservative
estimates of bipolar circuit performance. Thus, the current-dependent resistance, rb in (3-38), is
supplanted by the maximum anticipated base resistance, rbb, which simplifies relevant circuit
analyses in that resistance rbb is current invariant. Second, the substrate is presumed connected
to the most negative of available circuit potentials. This means that the substrate-collector PN
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junction diode, DSC in Figure (3.11), can be ignored for small signal analyses since it is reverse
biased and therefore conducts only minutely small leakage currents. Since the substrate is connected purposefully to a suitable constant potential that is either circuit ground or a static voltage
lying below circuit ground, the substrate lies at signal ground potential in that no signal is supported at the substrate terminal. As witnessed in the small signal model of a PN junction diode,
the BJT model at hand is capable of establishing only the appropriate interrelationships among
the signal components of all transistor voltage and current variables. It cannot predict Q-point
voltages and currents and indeed, the parameters of the small signal model rely a priori on the
numerical values of these Q-point currents and voltages.
In the model of Figure (3.14), rbb, re, and rc, are physical resistances that account for
voltage drops incurred by currents flowing in the charge neutral regions of the base, emitter, and
collector, respectively. On the other hand, the resistance, rπ, is a mathematical artifact arising
from a linear representation of the volt-ampere characteristics indigenous to the base-emitter
junction diode. In particular, if the forward base recombination current, Ibe, in (3-8) is approximated by only the linear terms in its Taylor series expansion about the transistor operating point
established in part by Ve = VeQ,
∂I
I be ≈ I beQ + be Ve − VeQ .
(3-50)
∂Ve Q
(
)
With reference to Figure (3.14), (Ve − VeQ) in this relationship is the signal-induced change, V,
across the internal base-emitter junction terminals and (Ibe − IbeQ) is the corresponding signal induced change, I, in the forward recombination current. Accordingly, resistance rπ in the subject
model derives from
I beQ
∂I be
Ae J s Ve n f VT
1
≈
e
(3-51)
=
.
∂Ve Q
n f VT
rπ
n f VT β f
Q
Given that current IbeQ closely approximates the quiescent transistor base current, IbQ, in the linear forward region of operation, (3-47) combines with (3-51) to deliver
n f VT
n f VT
hFE n f VT
(3-52)
rπ ≈
≈
=
.
I beQ
I bQ
I cQ
We see that he small signal resistance, rπ, is vulnerable to the gain metric, hFE, whose observed
value suffers significant variance due to processing uncertainties. Additionally, the inverse
dependence of rπ on Q-point collector current, along with the direct dependence of Boltzmann
voltage VT on absolute temperature, renders it dependent on junction temperature Tj unless we
design the circuit to ensure a quiescent collector current proportional to absolute junction
temperature. The latter condition is commonly referred to as a proportional to absolute temperature design, or PTAT design.
Like rπ, the Early resistance, ro, in Figure (3.14) is also a mathematical artifact. But in
contrast to rπ, which derives from a consideration of the volt-ampere characteristics of the baseemitter junction, ro pertains to a coefficient in the linearized Taylor series expansion of the function that relates transistor collector current to internal collector-emitter voltage, Vb. From (3-36)
and (3-5), which collectively advance a collector current dependence on both base-emitter junction voltage, Ve, and intrinsic collector-emitter voltage, Vb, the pertinent two-variable Taylor series expansion for the collector current, Ic, is
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∂I c
∂I c
Ve − VeQ +
Vb − VbQ .
(3-53)
∂Ve Q
∂Vb Q
The coefficient of (Ve − VeQ) on the right hand side of this relationship is the Q-point value of the
transconductance, gm, introduced in (3-40); that is,
⎞⎛
I cQ ⎛
I cQ
V ⎞
∂I c
⎜1 −
⎟ ⎜ 1 + bQ ⎟ .
=
gm (3-54)
∂Ve Q
n f VT ⎜
Vaf ⎟⎠
2 I ccQ I kf ⎟ ⎝⎜
⎝
⎠
On the other hand, the coefficient of (Vb − VbQ) produces an expression for the Early resistance
ro. In particular, (3-36) yields
I cQ
1
∂I c
I
= ct
=
,
(3-55)
ro
∂Vb Q
Vaf
VbQ + Vaf
I c ≈ I cQ +
(
)
(
)
Q
whence
ro =
VbQ + Vaf
.
I cQ
(3-56)
In most cases, voltage VbQ in (3-54) and (3-56) can be supplanted by the Q-point collector-emitter voltage, VceQ, since the quiescent voltage drops in both the collector resistance, rc, and the
emitter resistance, re, are generally small enough to warrant their tacit neglect. Accordingly,
⎞⎛
⎞
I cQ ⎛
I cQ
V
⎜1 −
⎟ ⎜ 1 + ceQ ⎟
gm ≈
n f VT ⎜
Vaf ⎟⎠
2 I ccQ I kf ⎟ ⎜⎝
⎝
⎠
.
(3-57)
VceQ + Vaf
ro ≈
I cQ
Clearly, resistance ro in (3-57) is large for very small collector bias currents, IcQ. With
reference to the small signal model of Figure (3.14), it follows that at low signal frequencies
where all device capacitances can be ignored, the collector-emitter port of a BJT emulates an
ideal voltage controlled current source (VCCS) for low level biasing. However and despite this
low frequency VCCS nature of the collector-emitter port, the transistor does not behave as an
ideal transconductance element because of the finite input impedance evidenced between the
base and emitter terminals. This situation confers the possibility of representing the collectoremitter output port as a current controlled current source (CCCS) that is controlled by the signal
recombination current, I, flowing as shown through resistance rπ. Since the model at hand verifies V = rπI,
gmV = gm rπ I βac I ,
(3-58)
where, by (3-57) and (3-52), the so-called signal beta, or AC beta, βac, of a bipolar junction
transistor is
⎛
⎞⎛
I cQ
V ⎞
⎟ ⎜ 1 + bQ ⎟ .
βac = gm rπ = hFE ⎜ 1 −
(3-59)
⎜
Vaf ⎟⎠
2 I ccQ I kf ⎟ ⎜⎝
⎝
⎠
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rbb
Base
V
J. Choma
rc
Cμ
+
−
Collector
rπ
I
Cπ
βac I
re
ro
Cs
Substrate
Emitter
Figure (3.15). Alternative small signal model of the BJT. Note herein that in contrast
to the small signal model in Figure (3.14), the collector-emitter port contains the current controlled current source, βacI, whose controlling current, I, is conducted by the model resistance, rπ.
Figure (3.15) depicts the alternative CCCS model, for which prudence dictates our underscoring
that current I is not the base current at all signal frequencies. In particular, the net signal base
current must supply current to the branch represented by resistance rπ, and the currents conducted by the branches comprised of capacitances, Cπ and Cμ. In short, current I in the βacI
generator is always only the current that flows through the resistance, rπ.
EXAMPLE #3.3:
The diode-connected transistor in Figure (3.6a) operates in a circuit that allows the silicon technology transistor to conduct a quiescent collector current, IcQ, of 4 mA. A room
temperature (27 °C) characterization of the transistor at hand reveals a maximum base
resistance, rbb, of 140 Ω, a nominal series collector resistance, rc, of 20 Ω, and a nominal
emitter resistance, re, of 0.9 Ω. Moreover, the DC beta, hFE, of the considered device is
found to be at least 120 amps/amp, the knee current, Ikf, is 12 mA, the Early voltage, Vaf,
is 45 volts, and the saturation current, Is, is 10 fA. Use these numerical data to compute
the low frequency small signal parameters of the transistor. Exploit these parameters to
determine the low frequency, small signal terminal resistance, say rd, of the diode-connected structure. Assume a base-emitter junction injection coefficient of nf = 1.
SOLUTION #3.3:
(1).
In the diode interconnection of Figure (3.6a), the measurable quiescent collector-emitter
voltage, Vd, of the transistor is identical to the quiescent base-emitter voltage, say VbeQ. In
silicon, positive VbeQ, and hence voltage Vd, is rarely larger than 800 mV. Owing to the voltages dropped across the internal collector and emitter resistances, the internal Q-point
collector-emitter voltage, VbQ, in Figure (3.9a) must therefore be smaller than 800 mV, which
assuredly is a voltage level that is significantly smaller than the forward Early voltage, Vaf =
45 volts. It follows that the collector current in (3-36) is essentially the net transport current,
Ict. Setting IcQ = Ict in (3-30), the Q-point Ebers-Moll transport current, IccQ, can therefore be
determined. Unfortunately, a quadratic relationship must be solved to arrive at IccQ. The
relevant fruit of this annoying exercise is
⎡
I cQ ⎛
4I kf ⎞ ⎤
⎜1 + 1 +
⎟ ⎥ = 7.07 mA .
I ccQ = I cQ ⎢1 +
(E3-1)
2I kf ⎜
I cQ ⎟ ⎥
⎢⎣
⎝
⎠⎦
(2).
With nf = 1, Is = 10 fA, IccQ = 7.07 mA, and, recalling (3-7), VT = 25.89 mV for a junction
temperature of Tj = 300.16 °K, (3-5) gives a Q-point voltage, VeQ, developed across the
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intrinsic base-emitter junction diode of VeQ = 706.36 mV. Now, for IcQ = 4 mA and hFE =
120 amps/amp, the Q-point base current, IbQ, is IbQ = IcQ/hFE = 33.33 μA, while the Q-point
emitter current, IeQ, is IeQ = (hFE+1)IbQ = 4.03 mA. These currents, the computed internal
base-emitter junction voltage of VeQ = 706.36 mV, the given base resistance of rbb = 140 Ω,
and the emitter resistance of re = 0.9 Ω imply, via (3-49), a quiescent base-emitter terminal
voltage, VbeQ, of
VbeQ = I bQ rbb + VeQ + I eQ re = 714.66 mV ,
(E3-2)
which is only slightly more than 8 mV above its intrinsic junction voltage counterpart. Since
VbeQ is identical to voltage Vd in Figure (3.6a), the internal collector-emitter voltage, VbQ, at
the quiescent operating point of the diode-connected transistor is
VbQ = Vd − I cQ rc − I eQ re = 631.03 mV .
(E3-3)
Note that voltage VbQ is more than 71-times smaller than the forward Early voltage, Vaf, of
the transistor, which assuredly validates our previously invoked approximation of IcQ ≈ Ict in
(3-30).
(3).
The foregoing calculations set the table for evaluating the small signal parameters of the
considered BJT. Using (3-52), the small signal base-emitter junction resistance, rπ, is rπ =
776.66 Ω. From (3-54) the forward transconductance, gm, is 122.66 mS, and since βac =
gmrπ, the AC beta of the transistor is βac = 95.26 amps/amp. Finally, VbQ = 631.03 mV, Vaf =
45 V, and IcQ = 4 mA in (3-56) yield an Early resistance, ro, of ro = 11.41 KΩ.
I
rbb
Ix
V
+
Vx
−
Ix
+
−
rπ
I
rc
βac I
ro
Ix − (βac+1)I
re
Ix − I
+
Vx
Ix
−
Ix
Figure (3.16). Low frequency, small signal model of the diode connected transistor in Figure
(3.6a). The effective, or small signal terminal resistance, rd, of the diode
connection is determined via the “ohmmeter” method, which entails a calculation of the voltage to current ratio, Vx/Ix.
(4).
If we lean on Figure (3.15), we can posture Figure (3.16) as the low frequency, small signal
model of the diode-connected transistor in Figure (3.6a). All of the device capacitances in
the model of Figure (3.15) are tacitly ignored because of the present exclusive interest on
only low frequency diode characteristics. The desired small signal terminal resistance, rd,
derives from the “ohmmeter” voltage to current ratio, Vx/Ix. An analysis of the structure at
hand provides
Vx = ( rbb + rπ ) I + re I x
(E3-4)
and
(E3-5)
Vx = rc ( I x − I ) + ro ⎡⎣ I x − ( βac + 1) I ⎤⎦ + re I x .
Upon elimination of current I in these two relationships, the terminal resistance, rd, of the diode is readily shown to be
rd =
( ro + rc ) ( rbb + rπ )
Vx
= re +
= 10.43 ohms .
βac ro
Ix
1+
ro + rc + rbb + rπ
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Since ro is a large resistance, (E3-6) can be approximated as
V
r +r
rd = x ≈ re + bb π = 10.42 ohms ,
Ix
βac + 1
which differs insignificantly from the “exact” result in (E3-6).
(E3-7)
COMMENTS: The computed small signal diode resistance of 10.43 ohms is comparable
to the resistance presented to a circuit by a traditional PN junction diode.
This resistance is small because of the large forward transconductance,
and hence large AC beta, afforded by a BJT operated at reasonable biasing
levels. In stark contrast, the resistance presented by a diode-connected,
deep submicron technology MOSFET is ultimately shown to be considerably larger owing to the relatively small forward transconductance typically
afforded by a MOS technology transistor.
The approximate diode resistance stemming from the tacit neglect of the
Early resistance is worthy of further exploration. To this end, the pertinent
small signal model is offered in Figure (3.17), wherein the removal of
resistance ro postures the controlled current source, βacI, as an ideal current
generator that projects infinitely large resistance in the collector circuit of
the transistor. The series interconnection of the internal collector resistance, rc, with this infinite resistance current source renders rc
inconsequential, regardless of its value. Moreover, since the resistance, re,
is in series with the port at which the mathematical ohmmeter is applied to
evaluate the diode resistance, the resistance, (rbb + rπ) evidenced in the
base circuit, is necessarily referred to the emitter. In turn, the emitter conducts a signal current that is larger than the signal current in the base by a
factor of (βac + 1). Accordingly, it is reasonable to expect, as is confirmed
by (E3-7), that the effective resistance seen in series with re is the resistance observed in the base, scaled by a factor of the base current -to- emitter current ratio, 1/(βac + 1).
I
rbb
Ix
V
+
Vx
−
Ix
+
−
rπ
I
rc
Ix − I
βac I
+
Vx
re
Ix
−
Ix = (βac+1)I
Figure (3.17). The equivalent circuit in Figure (3.16) with the Early resistance, ro, tacitly ignored.
3.3.1. UNITY GAIN FREQUENCY
Sophisticated communication and data processing systems require significantly large
signal bandwidths to process and transmit perpetually increasing amounts of audio, video, or
digitized information. It is only natural that engineers tasked with the realization of these high
performance systems insist on being provided with convenient circuit level metrics that quantify
the high frequency capabilities of the active devices considered for deployment in circuit cells
that can interact to establish the desirable system performance. The most common, but not
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necessarily the most illuminating, of these metrics is the short circuit, unity gain frequency, fT,
which is commonly referenced as simply the unity gain frequency.
In order facilitate our understanding of the engineering implications of metric fT, we
consider the test bipolar cell in Figure (3.18a). In this structure, the transistor, whose emitter is
incident with electrical ground, is biased in its linear regime by the quiescent base current, IbQ,
and the static voltage source, VceQ. In the interest of analytical simplicity, both the static current
source and the static voltage source are treated as ideal sources of energy. In particular, neither
an impedance is placed across IbQ, nor is a series impedance utilized in conjunction with voltage
VceQ. Transistor operation in its forward active domain relies on selecting voltage VceQ to ensure
that it exceeds the quiescent base-emitter voltage, VbeQ. In turn, VbeQ is presumably rendered
sufficiently large by current IbQ to achieve turn on of the base-emitter diode intrinsic to the subject transistor. A small amplitude, sinusoidal, test signal current, Ibs, is applied in shunt with the
aforementioned source of static base current. The combined action of IbQ and Ibs incurs a net
collector current comprised of the superposition of a Q-point current component, IcQ, and a signal
component, Ics, as we highlight in Figure (3.18a). Similarly, a Q-point current, IeQ, superimposes
with a signal current, Ies, in the emitter lead of the transistor.
rbb
+VceQ
IcQ + Ics
rc
Cμ
V
+
−
Ibs
rπ
Cπ
gmV
Vbe −
IbQ
Cs
Ics
+
Ibs
ro
re
IeQ + Ies
Ies
(a).
(b).
rbb
Ibs
Cμ
V
+
−
rπ
I
Cπ
gmV
Ics
Ies
(c).
Figure (3.18). (a). Test circuit used in the measurement of the unity gain frequency, fT, of the transistor
undergoing evaluation. (b). High frequency model of the test structure in (a). (c). The
model in (b) simplified by ignoring the collector resistance, rc, and the emitter resistance, re.
Using the model of Figure (3.14), the small signal equivalent circuit of the test structure
in question is the network shown in Figure (3.18b). Since IbQ in Figure (3.18a) is a current
source of constant (static) value, it does not appear in the small signal model. In effect, IbQ is replaced by an open circuit to reflect the fact that IbQ embraces no signal fluctuations and therefore
offers zero signal current value. Similarly, the collector in the equivalent circuit is shown
grounded to the emitter because VceQ is a constant, and therefore zero signal, voltage source. In
short, the supply voltage, VceQ, is supplanted by a short circuit to mirror its zero signal status.
Because IbQ and VceQ are necessarily set to zero for small signal analysis purposes, the only current flowing in the collector of the equivalent circuit is the signal constituent, Ics, of the net
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collector current. Similarly, the signal emitter current, Ies, is the lone current flowing in the emitter lead of the model.
If we ignore tacitly the series collector resistance, rc, and the series emitter resistance,
re, we can collapse the model in Figure (3.18b) to the simplified topology we show in Figure
(3.18c). Observe that setting rc to zero short circuits the substrate capacitance, Cs, while setting
both rc and re to zero imposes a short circuit across the Early resistance, ro. Moreover, ignoring
resistances rc and re allows the inherently three-pole structure in Figure (3.18b) to be emulated
by the simple single pole, or single time constant, circuit in Figure (3.18c). To the latter end,
note that the short circuit imposed at the collector port effectively connects capacitance Cμ in
parallel with capacitance Cπ.
Obviously, the frequency response of the I/O current transfer function, Ics/Ibs, can be extracted from the measurement test cell in Figure (3.18a). Indeed, this transfer function, which is
denoted herewith as β(jω), can be determined straightforwardly from the simplified model given
in Figure (3.18c). In particular, the model produces
V
I bs =
+ jω Cπ + C μ V
rπ
(3-60)
,
(
)
I cs = g mV − jωC μV
whence
(
)
)
βac 1 − jωC μ gm
g m − jωC μ
I cs
=
=
,
(3-61)
1
I bs
+
+
1
jωr
C
C
π
π
μ
+ jω Cπ + C μ
rπ
where (3-59) has been used. This result confirms the anticipated low frequency, short circuit
current gain of βac. It also projects a right half plane zero at a frequency of gm/Cμ, which is
invariably extremely large owing to the relatively small base-collector depletion capacitance, Cμ,
and the generally substantial forward transconductance, gm, of a small geometry BJT biased in its
forward active domain. Indeed, the frequency, gm/Cμ, is so large as to cast aspersions on the
validity of the simplified high frequency model we have used to generate (3-61). Consequently,
we can successfully argue the validity of approximating the last result by the expression,
I
βac
β(jω) cs ≈
,
(3-62)
I bs
1 + jω ωβ
β(jω) (
)
where the so-called beta cutoff frequency,
1
ωβ =
,
rπ Cπ + C μ
(
(
(3-63)
)
is recognized as the resultant 3-dB bandwidth of the short circuit, small signal current gain,
β(jω). The unity gain frequency can now be extrapolated as the gain-bandwidth product, βacωβ,
as suggested by the asymptotic frequency response plot given in Figure (3.19). This assertion
derives from the fact that at high test signal frequencies, (3-62) becomes
βac ωβ
β(jω) ω>> ω ≈
,
(3-64)
β
jω
from which it is apparent that the magnitude of the current gain degrades to one at a radial frequency, ωT, corresponding to frequency fT, of
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βacωβ
gm
ωT
≈
=
.
2π
2π
2π Cπ + C μ
(
(3-65)
)
β(jω) (in dB)
βac (dB)
op
Sl
3 dB
e=
d
20
−
d
B/
ec
0
ωβ
ωT
ω
Figure (3.19). Asymptotic approximation of the frequency response of
the short circuit, grounded emitter, current gain of a
bipolar junction transistor.
EXAMPLE #3.4:
At room temperature operating conditions, the high frequency silicon technology
transistor in Figure (3.18a) is biased at a collector current, IcQ, of 800 μA and a collector-emitter voltage, VceQ, of 2 volts. The transistor has a maximum base resistance, rbb,
of 360 Ω, a series collector resistance, rc, of 60 Ω, and a series emitter resistance, re, of
1.5 Ω. The short circuit current gain, βf, of the device is 140 amps/amp, the knee current, Ikf, is 10 mA, the Early voltage, Vaf, is 25 volts, and the saturation current, Is, is 6 fA.
For the base-collector junction, the high frequency parameters are Cjco = 5 fF, mc = 1/3,
and Vjc = 660 mV, while for the base-emitter junction, Cjeo = 1.5 fF, me = 1/2, and Vje =
920 mV. Moreover, the low current, short circuit transit time, τfo, for base region minority carriers is τfo = 2.5 pSEC. The base-emitter junction injection coefficient, nf, can be
taken as nf = 1. Use these numerical data to compute the short circuit unity gain frequency, fT, at the specified operating point.
SOLUTION #3.4:
(1).
Equation (E3-1) in the preceding example defines the quiescent transport current, IccQ, in
terms of the Q-point collector current, IcQ. For IcQ = 800 μA and Ikf = 10 mA, this relationship provides
⎡
I cQ ⎛
4I kf ⎞ ⎤
⎜1 + 1 +
⎟ ⎥ = 1.06 mA .
I ccQ = I cQ ⎢1 +
(E4-1)
2I kf ⎜
I cQ ⎟ ⎥
⎢⎣
⎝
⎠⎦
With nf = 1, Is = 6 fA, and, recalling (3-7), VT = 25.89 mV for a junction temperature of Tj =
300.16 °K, (3-5) gives a Q-point voltage, VeQ, developed across the intrinsic base-emitter
junction of VeQ = 670.47 mV.
(2).
Since parameter βf, to which the static beta, hFE, is directly proportional is large, the
quiescent base current, IbQ = IcQ/hFE, is correspondingly small. Thus, the Q-point emitter
current, IeQ, is virtually identical to its collector counterpart, IcQ. Taking IeQ ≈ IcQ, it follows
from Figure (3.11) that the internal collector-emitter voltage, VbQ, is, with VceQ = 2 volts, rc =
60 Ω, and re = 1.5 Ω,
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VbQ ≈ VceQ − I cQ rc − I cQ re = 1.95 V .
J. Choma
(E4-2)
In the interest of completeness, hFE can now be evaluated with the assistance of (3-37). In
particular, for VbQ = 1.95 volts, and βf = 140, hFE = 113.85 amps/amp.
(3).
The forward transconductance, gm, computes from (3-41). For the given and calculated variables,
⎞⎛
I cQ ⎛
V ⎞
Ic
⎜1 −
⎟ ⎜ 1 + bQ ⎟ = 29.22 m .
gm =
(E4-3)
n f VT ⎜
Vaf ⎟⎠
2 I ccQ I kf ⎟ ⎜⎝
⎝
⎠
(4).
Recalling (3-40), the effective value, τfe, of the minority carrier transit time is
I cQ ⎞
⎛
⎜1+
⎟
I kf ⎟
⎜
τ fe = τ fo
= 2.505 pSEC
(E4-4)
⎜
VbQ ⎟
⎜1 +
⎟
⎜
⎟
V
af
⎝
⎠
for τfo = 2.50 pSEC. It follows by (3-39) that the base-emitter diffusion capacitance, Cbe, is,
for gm = 29.22 mS and τfe = 2.505 pSEC,
Cbe = τ fe gm = 73.19 fF .
(E4-5)
(5).
The remaining device capacitances derive from (3-43) and (3-45). In the former of these two
relationships, the base-emitter junction threshold potential, Veon, can be taken as 700 mV, despite the fact that the computed value of the base-emitter junction voltage, VeQ, is about 30
mV smaller. Equation (3-43) is, after all, only an approximation of the deletion capacitance
evidenced at the forward biased junction. Additionally, capacitance Cjeo is so small that the
depletion component of the net base-emitter junction capacitance is doubtlessly
inconsequential to the present exercise. Accordingly, with Cjeo = 1.5 fF, Vje = 920 mV, Veon
= 700 mV, and me = 1/2,
C jeo
C je ≈
= 3.07 fF .
(E4-6)
me
⎛
⎞
V
⎜ 1 − eon ⎟
⎜
V je ⎟⎠
⎝
For capacitance Cμ in (3-45), the intrinsic base-collector junction voltage, VcQ, must first be
computed. Appealing to Figure (3.11),
VcQ = VeQ − VbQ = − 1.28 volts .
(E4-7)
Thus, (3-45) yields
C jco
Cμ =
= 3.49 fF ,
m
⎛
VcQ ⎞ c
⎜1 −
⎟
⎜
⎟
V
jc
⎝
⎠
where Cjco = 5 fF, Vjc = 660 mV, and mc = 1/3.
(6).
(E4-8)
Recalling that capacitance Cπ is simply the sum of capacitances Cbe in (E4-5) and Cje in (E46), (3-65) finally delivers
gm
gm
fT =
=
= 58.32 GHz .
(E4-9)
2π Cπ + C μ
2π τ fe gm + C je + C μ
(
)
(
)
Those who may be concerned by the tacit neglect of the right half plane zero in (3-61) can
verify that for the stipulated operating point conditions, gm/Cμ ≈ 1,332 GHz, which is almost
23-times larger than fT in (E4-9).
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COMMENTS: The procedure underlying the numerical evaluation of the unity gain frequency of a BJT is obviously computationally intensive. In order to allay
any trepidation on your part that may ensue from this computational intensity, the procedure is documented herewith merely to demonstrate the utility of all of the modeling relationships derived to this point. In practice,
and as the reader will be relieved to learn, operating point printouts
accompanying SPICE simulations of BJT circuits include a numerical
delineation of fT for user-defined transistor operating points.
The critical issue at hand is the practical utility of the unity gain frequency
metric. In brief, its principle value is to serve as a measure of comparison
among devices proposed for utilization in broadband analog or high-speed
digital circuit applications. The rationale surrounding this contention is
that transistors exemplifying very large values of fT for a specified quiescent operating point can generally be expected to perform more admirably
at high signal frequencies than can presumably competitive devices exuding smaller values of the unity gain metric. For example, a transistor
projecting fT = 100 GHz is capable of processing more faithfully very high
signal frequencies than can transistors having fT = 40 GHz.
It is important for us to must appreciate that with the exception of very
specialized circuit topologies, fT is an awful (meaning overly optimistic)
measure of achievable circuit performance at high signal frequencies. It is
even more vital that we comprehend the logic that underlies this negative
viewpoint. In particular, fT is a frequency measure for only the short circuit current gain of a transistor cell whose emitter is grounded. It pertains
to a circuit topology whose base is driven by an ideal signal current
source, the response to which is a current delivered to a short circuited
load termination. As such, the fT metric effectively derives from only the
time required to transport charge carriers across the base region. Once
these carriers are delivered to the collector, where the short circuited load
is imposed, the fT metric inherently ignores the time required to charge the
substrate capacitance and any other capacitances implicit to the actual load
ultimately incident with the collector port of the BJT circuit. In other
words, fT fails to account for the frequency response of the output voltage
produced by the applied input current since in effect, the output voltage is
clamped to zero by the short circuit imposed at the output port. Moreover,
and especially for the case of a first stage in a high performance electronic
system, fT is likewise oblivious to the time required to charge input port
capacitances associated with the utilized transistor. The tacit neglect of
capacitive charging times is significant in practical circuits. For example,
in a circuit designed to deliver an output voltage response to an applied input signal, the achievable 3-dB bandwidth is rarely larger than about onefifth of the documented value of fT.
Notable exceptions to the foregoing assertions are current mode circuits,
which extract output responses as signal currents that are applied as currents to succeeding stages. Current mode signal processing is studied in
detail later in this text. But for the moment, observe that in the case of the
grounded emitter configuration, the collector is a relatively high impedance port owing to the invariably large Early resistance that prevails
therein. Accordingly, the collector can be modeled viably as a Norton signal current source. If this output current is thence applied to a subsequent
amplification stage featuring very low input impedance, a short circuit is
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effectively approximated at the collector port of the predecessor stage. To
the extent that the input port of the first stage boasts low input impedance
so that large port voltages are precluded, fT becomes a meaningful barometer of high frequency circuit performance. Of course, short circuited input
ports in either predecessor or follow on load stages are never exactly
possible, with the result that the achievable bandwidths in prudently designed current mode configurations remain rarely larger than 70% to 80%
of the published fT value.
In summary, fT is arguably a viable, and indeed convenient, metric for
comparative shopping of transistors earmarked for deployment in high
performance, broadband electronic networks. But except for current mode
configurations, which can be adopted only at circuit interstages (meaning
stages that do not include the input first stage or the output last stage), it is
a virtually useless circuit level figure of merit. Its demonstrable circuit
impropriety as a high frequency performance measure stems from the fact
that the fT measure is tacitly oblivious to the time required to charge device
and circuit capacitances at both input and output ports.
60
Unity Gain Frequency, fT (GHz)
f TM
50
40
30
20
10
0
0.01
I cM
1.00
0.10
10.00
Collector Current, I cQ (mA)
Figure (3.20). The unity gain frequency, fT, plotted as a function of the quiescent collector current,
IcQ, for the transistor studied in Example #3.4. The quiescent collector-emitter voltage
of the subject transistor is held at 2 volts.
Although transistor vendors and process foundries are anxious to quote impressive fTvalues to facilitate the comparative shopping to which the foregoing commentary alludes, they
are reticent to underscore the fact that fT varies with collector current. Indeed, fT is a notably
sensitive function of the quiescent collector current, IcQ, when IcQ is small, as is typical in circuits
constrained to function at low power levels. In the true spirit of aggressive marketing, quoted
unity gain frequency values invariably reflect maximum attainable values, which may unfortunately correspond to collector currents deemed inappropriate for specific applications. To wit,
the transistor parameterized in the preceding example generates the fT -versus- IcQ characteristic
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displayed in Figure (3.20). A careful examination of the data underpinning this curve reveals
that the maximum value, say fTM, of the unity gain frequency is 58.3 GHz, which is achieved at a
collector current of IcM = 831.8 μA. Fortunately, the curve at hand displays a rather broad maximum, thereby negating the need to set the quiescent collector current precisely to achieve a unity
gain frequency that is within a few percent of its maximum value. Note, however, that it makes
little sense to bias the transistor of interest to the right of current IcM in that similar fT-values are
achievable at the lower circuit power dissipation associated with current biasing below IcM.
An analytical determination of the optimal collector current associated with maximal
unity gain frequency is a challenge owing to the dependence of numerous relevant modeling
parameters on collector current. Nonetheless, we can arrive at an acceptable approximation. To
this end, return to (3-65) and note that the net capacitance, say Cnet, in the denominator on the
right hand side is
(3-66)
Cnet = Cπ + C je + C μ = τ fe g m + C j ,
where (3-39) and (3-44) have been used, and the sum total, Cj, of transistor depletion capacitances is
(3-67)
C j = C je + C μ .
In the last expression, Cje and Cμ are given by (3-43) and (3-45), respectively. While capacitance
Cje is a constant, Cμ is a function of the intrinsic base-collector junction reverse bias, Vc, which
depends somewhat on the collector current owing to the presence of series resistances in the
collector and emitter leads of the transistor. Because these series resistances are small, this
collector current dependence can be ignored, thereby establishing Cj as a constant, independent
of quiescent collector current. In particular, the tacit neglect of intrinsic series resistances implies that the intrinsic collector-emitter voltage is simply the externally applied collector-emitter
voltage, VceQ, whence VcQ is set to the voltage difference, (Veon − VceQ). Moreover, voltage VbQ is
presumed to be significantly smaller than the Early voltage, Vaf, so that τfe in (3-39) becomes
I cQ ⎞
⎛
⎜1+
⎟
⎛
I kf ⎟
I cQ ⎞
⎜
τ fe = τ fo
≈ τ fo ⎜ 1 +
(3-68)
⎟.
⎜
⎜
VbQ ⎟
I kf ⎟⎠
⎝
⎜⎜ 1 +
⎟⎟
V
af
⎝
⎠
At this juncture, the unity gain frequency in (3-65) approximates
gm
gm
(3-69)
fT =
.
≈
⎡ ⎛
⎤
2π Cπ + C μ
I cQ ⎞
2π ⎢ τ fo ⎜ 1 +
⎟ gm + C j ⎥
I kf ⎟⎠
⎢⎣ ⎜⎝
⎥⎦
(
)
At small collector currents, the transconductance parameter, gm in (3-54) collapses to
⎞⎛
I cQ ⎛
I cQ
V ⎞
I cQ
⎜1 −
⎟ ⎜ 1 + bQ ⎟ ≈
gm =
,
(3-70)
n f VT ⎜
Vaf ⎟⎠
n f VT
2 I ccQ I kf ⎟ ⎜⎝
⎝
⎠
where VbQ continues to be presumed much smaller than Vaf. Specifically, transconductance gm,
which increases monotonically for all values of the quiescent collector current, IcQ, is seen as
increasing linearly with small quiescent collector current IcQ. This reduced transconductance
relationship, which allows expressing (3-69) as
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BJT Models & Biasing
gm
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I cQ
≈
,
(3-71)
⎡ ⎛
⎤
⎡ τ fo ⎛
⎤
I cQ ⎞
I cQ ⎞
2π ⎢ τ fo ⎜ 1 +
2πn f VT ⎢
⎟ gm + C j ⎥
⎜1 +
⎟ I cQ + C j ⎥
I kf ⎟⎠
I kf ⎟⎠
⎢⎣ ⎜⎝
⎥⎦
⎢⎣ n f VT ⎜⎝
⎥⎦
is arguably valid through the immediate neighborhood of maximum fT in that Figure (3.20) suggests maximal fT is achieved at a collector current that is substantively smaller than the forward
knee current of a BJT.
Equation (3-71) affirms the original allegation of a current dependence ascribed to the
unity gain frequency metric. Aside from such affirmation, it also highlights two additional issues. First, it validates the nominally linear rise of fT with current IcQ that is observed in Figure
(3.20) for low collector currents. From (3-71), we note that the slope of this low current rise is
1/2πnfVTCj, which means that progressively larger depletion capacitances at either or both
transistor junctions slows the current rate of fT ascent to its maximum value. Second, since (371) delivers positive fT for all considered values of IcQ and further yields fT = 0 at both IcQ = 0
and IcQ = ∞, it foretells the existence of an optimal current, say IcM, commensurate with securing
maximal unity gain frequency. This optimal current derives from constraining to zero the
derivative, dfT/dIcQ, in (3-71). The result of this somewhat tedious exercise is
n f VT I kf C j
I cM =
.
(3-72)
τ fo
Setting IcQ = IcM in (3-71) gives a maximum unity gain frequency of
1 2π τ fo
fTM =
,
n f VT C j
1+ 2
τ fo I kf
(3-73)
which advances 1/2πτfo as the largest possible value of the maximum unity gain frequency.
When (3-72) and (3-73) are applied to the transistor studied in Example #3.4, IcM = 823.3 μA,
and fTM = 54.66 MHz. These computations differ from their simulated values by slightly more
than 1% and about 6.7%, respectively, which is good enough for government work and
stereotypically aggressive marketing practices.
3.3.2. UNITY POWER GAIN FREQUENCY
The unity gain frequency discussed in the preceding subsection codifies the high frequency response capabilities of a grounded emitter transistor in terms of the frequency response
of its short circuit, and therefore maximum, current gain. Although the small signal, frequency
domain performance of electronic networks is commonly evaluated in terms of either current
gain or voltage gain characteristics, it should be noted that the primary purpose of active circuits
is to supply signal power gain between network input and output ports. Accordingly, an assessment of high frequency device response capabilities in terms of the maximum power gain afforded by a utilized transistor makes good engineering sense.
To the foregoing end, consider the grounded emitter amplifier of Figure (3.21a) in
which the static supply voltages, Vcc and Vbb, ensure that the utilized BJT operates in its forward
active regime. The signal source, Vs, is applied to the amplifier input port through a complex series impedance, Zs(jω), which is understood to include the Thévenin impedance of the signal
source itself. In response to Vs, which is a small amplitude sinusoid, a signal component, Vos, of
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the net output port voltage, Vo, is generated, as is a signal component, Vis, to the net input port
voltage, Vi. The amplifier, whose output port is terminated to signal ground in the complex load
admittance, Yl(jω), can be represented as a voltage controlled current source, as suggested in Figure (3.21b). In this representation, Yfe(jω)Vis is the Norton, or short circuit, output signal current,
while Yoe(jω) is the amplifier shunt output admittance facing load admittance Yl(jω). At the
amplifier input port, it is convenient to separate the intrinsic base resistance, rbb, from the net input impedance or admittance. Accordingly, the admittance, Yie(jω), is the load presented to the
signal source circuit by the net admittance associated with the effective load appearing across the
intrinsic base-emitter junction.
rbb
Io
Zs(jω)
+
Yie(jω)
Vs
−
Vo
Zs(jω)
Vis
+
Yl(jω)
+Vcc
Vi
Ios
Yfe(jω)Vis
Vbb
Vos
Yl(jω)
−
+
Yoe(jω)
Vs
−
(a).
(b).
Figure (3.21). (a). A simple grounded emitter amplifier. (b). Voltage controlled current source
representation of the I/O ports of the amplifier in (a).
Assuming that the transistor in Figure (3.21a) derives from a monolithic fabrication
process, the transistor equivalent circuit shown in Figure (3.14) launches the small signal amplifier model depicted in Figure (3.22a). Since the Norton equivalent output current, Yfe(jω)Vis in
Figure (3.21a), is the current conducted by a short circuited load, the model appropriate to
determining Yfe(jω) is the structure given in Figure (3.22b). Observe that the only difference between the topologies of Figures (3.22a) and (3.22b) is that load admittance Yl(jω) in the former
diagram is supplanted by a short circuit in the latter figure. From Figure (3.22b), the signal current, Ios, conducted by the short circuited load satisfies
I os = gmV − jωC μV = gm − jωC μ V ,
(3-74)
(
)
while signal voltage V relates to the signal component, Vis, of the net input port voltage, Vi, as
rπ
rπ
1 + jωrπ Cπ + C μ
V
rπ + rbb
(3-75)
=
=
.
rπ
Vis
1
+
jω
r
r
C
+
C
(
)
π bb
π
μ
+ rbb
1 + jωrπ Cπ + C μ
(
(
)
(
)
)
Using the last two expressions, we find a Norton transadmittance, Yfe(jω), of
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jωC μ ⎞
g m rπ ⎛
⎜1 −
⎟
rπ + rbb ⎝
gm ⎠
I os
Y fe (jω) =
.
=
Vis
1 + jω ( rπ rbb ) Cπ + C μ
rbb
Cμ
Vis
Zs(jω)
(
+
Vs
V
−
+
−
(3-76)
)
rπ
Cπ
gmV
ro
Ios
Vos
Cs
Yl(jω)
Lecture Supplement #05
(a).
Zs(jω)
rbb
Vis
+
V
Cμ
+
−
Vs
rπ
Cπ
Ios
gmV
ro
Cs
−
(b).
Vis
V
+
−
rπ
Cπ
Vx
gmV
ro
Cs
Ix
(c).
Yie(jω)
Cμ
Vx
Ix
Yoe(jω)
Cμ
+
V = Vx
−
rπ
Cπ
Vos
gmV
ro
Cs
Yl(jω)
Zs(jω)
rbb
(d).
Figure (3.22). (a). Small signal, high frequency equivalent circuit of the amplifier in Figure
(3.21a). (b). Small signal model used in the evaluation of the forward
transadmittance function, Yfe(jω). (c). Small signal model for evaluating the
Norton admittance, Yoe(jω), established at the amplifier output port. (d). Small
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signal model for evaluating the Norton admittance, Yie(jω), established at the
intrinsic base-emitter junction of the utilized transistor.
The right half plane zero at gm/Cμ is invariably so large as to lie outside the frequency range over
which the transistor model in Figure (3.14) can be presumed valid and is therefore ignored
henceforth. Thus, the high frequency transadmittance in (3-76) can be approximated as
I
gm
ωT
(3-77)
Y fe (jω) = os ≈
=
,
Vis
jωrbb
jωrbb Cπ + C μ
(
)
where
ωT =
gm
Cπ + C μ
(3-78)
is the device unity gain frequency introduced in (3-65). It is interesting to note that the form of
(3-77) implies that the high frequency transadmittance characteristics of a grounded emitter BJT
amplifier reflect the response properties of an ideal integrator because of the presence of (jω),
which corresponds to Laplace operator “s,” in the denominator.
Figure (3.22c) diagrams the equivalent circuit appropriate to an evaluation of the shunt
output admittance, Yoe(jω). This structure is the original model in Figure (3.22a) with two
modifications. First, the independent signal source, Vs, is set to zero, as is mandated by an
impedance computation at any network port. Second, the load admittance, Yl(jω), is supplanted
by a mathematical ohmmeter simulated by the independent current source, Ix. This current
forges a voltage, Vx, across, and in disassociated polarity with, current Ix so that the target output
admittance, Yoe(jω), is simply Ix/Vx. Conventional circuit analysis reveals
⎡1
⎤
(3-79)
I x = ⎢ + jω Cs + C μ ⎥Vx + g m − jωC μ V ,
⎣ ro
⎦
and
⎡
⎤
1
+ jω Cπ + C μ ⎥V − jωC μVx = 0 .
(3-80)
⎢
⎢⎣ rπ ( rbb + Rs )
⎥⎦
Inserting the solution for voltage V in (3-80) into (3-79) leads to
jω ⎡⎣ rπ ( rbb + Rs ) ⎤⎦ C μ g m − jωC μ
I
1
(3-81)
Yoe (jω) = x =
+ jω Cs + C μ +
.
Vx
ro
1 + jω ⎡⎣ rπ ( rbb + Rs ) ⎤⎦ Cπ + C μ
For high frequency signal environments where transconductance gm can still be presumed to be
substantively larger than the capacitive susceptance, ωCμ, (3-81) reduces to the reasonably compact relationship,
1
Yoe (jω) ≈
+ ωT C μ + jω Cs + C μ .
(3-81)
ro
Note that the base-collector depletion capacitance, Cμ, generates a conductance component,
ωTCμ, to the net shunt output admittance. We may ultimately be able to exploit this observation
when a specific circuit application warrants a lossless reduction in the amplifier output resistance.
(
)
(
(
)
)
(
(
)
(
(
)
)
)
Figure (3.22d) is the small signal model for calculating the shunt admittance, Yie(jω) for
the subject grounded emitter amplifier. Observe that the voltage, Vx, across the imposed
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mathematical ohmmeter is identical to the signal voltage, V, appearing across the base-emitter
junction. A conventional nodal circuit analysis delivers
⎡1
⎤
I x = ⎢ + jω Cπ + C μ ⎥V − jωC μVos
⎣ rπ
⎦
,
(3-82)
⎡
⎤
1
+ jω Cs + C μ ⎥Vos + gm − jωC μ V = 0
⎢
⎣ ro Z l (jω)
⎦
(
)
(
)
(
)
where Zl(jω) is the impedance corresponding to the load admittance, Yl(jω). The elimination of
voltage Vos in these two independent relationships leads directly to
⎧
⎡
⎤ ⎫⎪
gm ( ro Z l (jω))
I
1
⎪
⎥ Cμ ⎬ ,
(3-83)
Yie (jω) = x ≈
+ jω ⎨Cπ + ⎢1 +
V
rπ
1 + jω ( ro Z l (jω)) Cs + C μ ⎥ ⎪
⎢⎣
⎪⎩
⎦ ⎭
where the indicated approximation exploits the presumption that for all signal frequencies of
interest, gm >> ωCμ. At high signal frequencies, (3-83) collapses to
⎛ Cμ ⎞
I
1
(3-84)
Yie (jω) = x ≈
+ gm ⎜
⎟ + jω Cπ + C μ .
⎜ Cs + C μ ⎟
V
rπ
⎝
⎠
(
(
Vis
Zs(jω)
)
)
rbb
+
Vs
rπ
−
C s + Cμ
gmCμ
Cπ
Cμ
Yie(jω)
Vos
ωT Vis
jωrbb
ro
1
ωT Cμ
Cμ
Yl(jω)
Ios
Cs
Yoe(jω)
Figure (3.23). Approximate high frequency, Norton equivalent I/O port model for the
grounded emitter amplifier in Figure (3.21a).
As is the case with the shunt output admittance, the base-collector depletion capacitance, Cμ,
spawns a shunt input conductance component (second term on the right hand side of the Yie(jω)
relationship) to the net input admittance. Equation (3-84), along with (3-81) and (3-77), gives
rise to the high frequency I/O port model offered in Figure (3.23), which clearly identifies the net
shunt resistances and capacitances at both the input and output ports of the amplifier. In the
interest of clarity, we observe that while Yoe(jω) is the net admittance facing the terminating load
admittance, Yie(jω) is not the net input admittance faced by the signal source. Instead, the input
impedance driven by the applied input signal is [rbb + 1/Yie(jω)].
The prerequisite for maximum power gain in an amplifier, such as the one addressed
presently, is the successful realization of conjugate impedance/admittance matches at both the
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input and the output ports. In particular, the source impedance, Zs(jω), must be the complex
conjugate of the net input impedance it faces at signal frequency ω. Concurrently, the load
admittance, Yl(jω), must be a conjugate match to the net output admittance that it effectively
shunts. Achieving these conjugate matches, particularly over a broad range of signal frequencies, is hardly a casual walk in the proverbial park. The requisite engineering tasks entail the design and implementation of appropriate I/O filters that respectively interact with the source and
load terminations to produce the desired matching. These filters must invariably be nominally
lossless structures (meaning that their intrinsic topological elements are exclusively inductances
and capacitances) so that they do not waste significant amounts of applied signal power that
might otherwise be processed for delivery to the load termination. Another issue that we may
need to address with the incorporation of I/O filters is that the impedance matching at both input
and output ports for certain types of transistors and circuit architectures may result in a potentially unstable network in the sense that one or more network poles lie in the right half complex
frequency plane.
The conjugate admittance match at the output port implies two operational requirements. First, the shunt conductance component, say Gl, of the load admittance must equate to
the real part, or conductance component, of Yoe(jω). In particular,
1 + ωT roC μ
1
1
(3-85)
.
Gl = Re [Yoe (jω)] =
+ ωT C μ =
Roe
ro
ro
Second, the susceptive component of load admittance Yl(jω) must be inductive to enable its resonance with the net shunt output capacitance, (Cμ + Cs), at the radial signal frequency, ω. The
proper selection of a load that satisfies these two design requirements resultantly condenses the
output port section shown in Figure (3.23) to the elegantly simple topology of Figure (3.24a),
which projects an output signal voltage, Vos, of
ω V ⎛R ⎞
(3-86)
Vos = − T is ⎜ oe ⎟ .
jωrbb ⎝ 2 ⎠
rbb
rbb
Vis
Vos
Ios
ωT Vis
jωrbb
+
Roe
Roe
(a).
Vs
−
(b).
Figure (3.24). (a). The high frequency output port model of the grounded emitter amplifier
in Figure (3.21a) when the load admittance, Yl(jω), is selected to be a conjugate match to the Norton output admittance, Yoe(jω), in Figure (3.23). (b).
High frequency input port model of the grounded emitter amplifier under the
condition of a source impedance [Zs(jω)] conjugate match to the net input
impedance, rbb + 1/Yie(jω) in Figure (3.23).
The corresponding maximum signal power, say Pomax, delivered to the resistive component of the
load that terminates the output port is
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Pomax =
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2
Vos
Roe
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2
⎛ω V ⎞
= ⎜ T is ⎟ Roe .
⎝ 2ωrbb ⎠
(3-87)
At the input port, the real part, say Rs, of the effective source impedance, Zs(jω), must
be set to effect a conjugate match between the source impedance and amplifier input impedance,
[rbb + 1/Yie(jω)]. With reference to Figure (3.23),
⎧
⎫
1
1
⎪ 1 − jωRie Cπ + C μ ⎪
=
= ⎨
R , (3-88)
2 ⎬ ie
Yie (jω)
⎛ Cμ ⎞
1
⎪ 1 + ⎡ωRie Cπ + C μ ⎤ ⎪
+ gm ⎜
+ jω Cπ + C μ
⎣
⎦ ⎭
⎩
⎜ Cs + C μ ⎟⎟
rπ
⎝
⎠
where
βac gm
1
Rie .
(3-89)
=
⎛ Cμ ⎞
⎛ Cμ ⎞
1
1 + βac ⎜
+ gm ⎜
⎟
⎜ Cs + C μ ⎟⎟
⎜ Cπ + C μ ⎟
rπ
⎠
⎝
⎠
⎝
Interestingly, the impedance, 1/Yie(jω), is purely imaginary at very high signal frequencies. In
particular,
(
1
≈
Yie (jω) ω large
(
)
2
− ⎡ jωRie ( Cπ + C μ )⎤
⎣
⎦
− jωRie2 Cπ + C μ
(
)
=
(
1
jω Cπ + C μ
)
(
)
,
)
(3-90)
which is to say that the magnitude of the very high frequency current conducted by resistance rπ
in Figure (3.23) pales in comparison to that of the current conducted by the net shunt capacitance, (Cπ + Cμ). This revelation hardly warrants a prize paper award in view of our understanding that capacitances in the sinusoidal steady state emulate short circuited elements when they
are compelled to conduct high frequency currents. It follows that the real part of 1/Yie(jω) approaches zero at high frequencies, whence the source resistance, Rs, commensurate with input
port impedance matching becomes
⎡
⎡ 1 ⎤
1 ⎤
(3-91)
Rs = Re ⎢ rbb +
⎥ = rbb + Re ⎢
⎥ ≈ rbb .
Yie (jω) ⎦
⎣
⎣ Yie (jω) ⎦
Figure (3.24b) shows the immediate ramification of a high frequency input port impedance
match, where it is to be understood that the reactive component of the original source impedance,
Zs(jω), has been selected to resonate with the net shunt capacitance, (Cπ + Cμ). Such a design
tack is tantamount to ensuring that the sum of the reactances associated with Zs(jω) and 1/Yie(jω)
is zero at the signal frequency, ω, of interest.
For the maximum power transfer condition implied by (3-91), the maximum signal
power, Pimax, delivered to the input port of the grounded emitter amplifier is obviously
Pimax =
Vis
2
.
rbb
A combination of this result with (3-87) leads to a maximum power gain, Ap, of
2
Pomax
⎛ω ⎞ ⎛R ⎞
= ⎜ T ⎟ ⎜ oe ⎟ ,
Pimax
⎝ 2ω ⎠ ⎝ rbb ⎠
and recalling (3-85),
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2
ωT
⎛ ωT ⎞ ⎛ Roe ⎞
Ap = ⎜
⎟ =
⎟ ⎜
2
⎝ 2ω ⎠ ⎝ rbb ⎠
4ω rbbC μ 1 + 1 ωT roC μ
(
J. Choma
)
.
(3-94)
Somewhat disconcertingly, (3-94) shows that the high frequency power gain of a grounded emitter amplifier degrades sharply with increasing signal frequency. This observation explains the
debilitating pain we experience when we are tasked with the responsibility of achieving substantive signal power gain at extremely high frequencies. Indeed, power gain Ap is inversely proportional to the square of the radial frequency, ω, which means that the power gain frequency response rolls off with increasing frequency at a rate of 40 dB/decade. Since a maximum power
gain of one effectively defines the practical utility of an amplifier in the sense of its ability to deliver greater than unity power gain, the frequency, say ωmax, at which Ap degrades to one, can be
postured as an ostensibly reasonable figure of merit for broadband performance. From (3-94),
ωT
ωmax =
,
(3-95)
⎛
1 ⎞
4rbbC μ ⎜ 1 +
⎟
⎜
ωT roC μ ⎟⎠
⎝
or in units of hertz,
ωmax
fT
fT
f max =
=
≈
,
(3-96)
2π
8πr
C
⎛
⎞
1
bb μ
8πrbbC μ ⎜ 1 +
⎟⎟
⎜
2πfT roC μ ⎠
⎝
where the indicated approximation reflects the common circumstance, 2πfTroCμ >> 1. For the
transistor examined in Example #3.4, which at the stipulated operating point has rbb = 360 Ω, Cμ
= 3.49 fF, and fT = 58.32 GHz, the preceding equation delivers fmax = 42.86 GHz, which is more
than 26% smaller than the fT rating of the device.
When rbbCμ > 1/4ωT, which is a commonly satisfied inequality, particularly for silicongermanium heterostructure bipolar transistors, the unity power gain frequency, fmax, more
conservatively brackets the high frequency performance ceiling of a transistor than does the
unity current gain frequency, fT. Despite this arguably laudable conservatism, device selection
decisions premised on fmax must nonetheless be tempered in light of the myriad of analytical
approximations we invoked to arrive at (3-96). More importantly, the engineering implications
implicit to the concept of the unity power gain frequency must be placed into proper perspective.
In particular, fmax represents the approximate input signal frequency for which the maximum
possible power gain of a grounded emitter amplifier degrades to unity. But maximum power
gain is realized if and only if conjugate impedance or admittance matches prevail between
terminating load and amplifier output impedances and between signal source and amplifier input
impedances. Except for certain classes of narrowband, tuned amplifiers, such conjugate matches
are rarely achievable in broadband configurations. Indeed, most broadband amplifiers, and
particularly lowpass amplifiers, do not operate with conjugate impedance matches at I/O ports,
which means that these amplifiers do not deliver maximum power gain. In fact, they may be designed expressly for the delivery of maximum voltage or current gains or perhaps specific values
of these gains. Thus, just like the short circuit figure of merit, fT, does not reflect realistic operating conditions, fmax may likewise be somewhat impertinent to a broad range of amplifier topologies. In these cases, the actual achievable bandwidths are generally in the range of one-fourth to
one-third of fmax.
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An even more insidious problem is that all grounded emitter amplifiers cannot be designed to deliver match terminated maximum power gain. As we briefly mentioned above and as
we discuss in a subsequent chapter, some amplifiers are potentially unstable, which is to say that
there exists a range of passive load terminations for which self-sustaining oscillations are
supported by the considered network under zero input signal conditions. Potential instability
does not surface in the foregoing discourse because the high frequency models invoked are
simplified to an extent that the realistic potential instability mechanisms of common emitter units
are implicitly masked. More complicated high frequency models, which take due consideration
of the response ramifications of time delays associated with the forward transconductance and
the dynamics observed at junction sidewalls in the complicated two dimensional monolithic
macromodel of Figure (3.12), may imply potential instability for selected quiescent operating
points. It follows that grounded emitter amplifiers represented by these high level models may
be incapable of delivering maximum power gain without a significant risk of instability. In these
cases, the pertinence of fmax in (3-96) is dubious.
3.4.0. BJT BIASING
As noted earlier, the primary purpose of biasing electronic circuits is to enable nominally linear responses to suitably small input voltage or current signals that are applied to these
circuits. In the case of bipolar junction transistors earmarked for circuit architectures developed
to satisfy I/O performance specifications, the biasing problem is a two-step task. The first of
these tasks is the selection of a quiescent collector current, IcQ, which is deemed appropriate to
the target I/O specifications of the proposed circuit. Such selection is necessarily mindful of the
fact that nominally linear BJT operation requires biasing in the linear domain. Recall that in this
operating domain, the base-emitter voltage, Vbe, of each BJT must be sufficiently large to ensure
an intrinsic junction voltage, Ve, which is at least as large as the threshold voltage, Veon, of the
base-emitter junction for all relevant values of applied signal levels. Moreover, we must embrace an assurance that the intrinsic base-collector junction voltage, Vc, is negative or at most
zero for all pertinent signal levels. The latter voltage constraint is satisfied automatically in NPN
devices if collector-emitter voltages, Vce, are at least as large as base-emitter voltages, Vbe.
Analogous constraints apply to PNP units whose emitter-collector voltages, Vec, must exceed or
at least equal emitter-base voltages, Veb, which support desired quiescent collector currents.
The selection of suitable quiescent collector currents is hardly a visceral engineering
exercise. These currents are typically premised on desired circuit gains, since gain is a function
of device forward transconductance, which has been witnessed as a current-dependent small signal metric. The quiescent collector current supported by the biasing design might also be chosen
in light of network bandwidth, noise, distortion, power dissipation, or other circuit performance
barometers deemed by the circuit designer as critical to the acceptable realization of system
performance specifications. In addition to the voltage constraints underlying linear domain
operation of a BJT, an important practical issue must be appreciated and addressed by the circuit
designer during the collector current selection process. In particular, it makes little sense to bias
a BJT at a collector current that exceeds the device knee current. One problem associated with
high current biasing is needlessly high power dissipation. Another problem implicit to biasing at
or beyond the transistor knee current is that the DC beta, hFE, decreases monotonically with high
collector current levels, thereby compromising the current gain of the network into which the
subject transistor is connected. While transconductance, which is indeed a measure of achievable small signal circuit gain, increases monotonically with collector Q-point current, the unity
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gain frequency, fT, which liberally limits circuit bandwidth, peaks at a current that is generally far
smaller than the device knee current. The immediate implication of this fact is that biasing the
collector to the right of the fT peak produces an fT value that is identical to that forged slightly to
the left of the fT peak. Thus, power dissipation budgets, thermal concerns, and even electrical
noise considerations render high current biasing foolish when suitably lower current biasing nets
similar and presumably meaningful and acceptable device and circuit performance. While design generalities in electronics are fraught with peril, the portability culture that is a signature of
modern electronics renders one assertion autonomous. In particular, the quiescent collector current of each active device within an electronic network should be chosen as the smallest current
level commensurate with nominally linear device operation and both predictable and reliable
satisfaction of all stipulated circuit operating specifications.
The second of the two-step biasing design task derives from the previously espoused
fact that the quiescent collector current conducted by a BJT determines the numerical values of
several branch elements implicit to the small signal models of Figures (3.14) and (3.15). It follows that the biasing structure must reliably establish each device collector current as a robustly
rigid and predictable constant. Suppose, for example, that device biasing currents fluctuate as a
function of noise coupled parasitically to the static voltage supply line of a circuit or of signal
levels manifested between base and emitter or collector and emitter. The resultant contamination
of such small signal parameters as rπ, Cπ, gm, and ro produce a time varying model for which the
implicit challenges associated with closed form small signal circuit analyses all but preclude the
generation of predictable and reproducible results. In effect, the biasing problem is therefore
seen as entailing the implementation of collector currents whose available current levels are ideally constant, independent of operating temperature and signal levels. Implicit to the requirement of a constant and predictable biasing current is that the current in question be rendered relatively insensitive to the impact exerted on device characterization metrics by the inherently
vagarious nature of semiconductor device processing and manufacturing. Stated quite simply,
the quiescent collector current, IcQ, of each BJT must be reliably predictable in terms of designable circuit elements. It must also be adequately desensitized to temperature phenomena, signal
voltages and currents, and the parametric uncertainties that comprise implicit baggage of active
monolithic devices.
3.4.1. PASSIVE BIASING NETWORKS
The most straightforward of biasing structures engaged for use in linear signal processing networks employ only passive elements to realize a desired quiescent collector current. In
the subsections that follow, two passive networks are examined from four distinct perspectives.
The first of these design-oriented perspectives is the penchant of the proposed network to
achieve and sustain predictable quiescent operating current. Second, the sensitivity of the quiescent current to key device parameters is illuminated. Third, the degree to which the quiescent
collector current is affected by increases in the junction operating temperature of the subject
bipolar devices is examined. Finally, the dependence of Q-point collector current on signal
swings manifested at the collector port is investigated. The last investigation is tantamount to
examining the small signal impedance established at the collector port. Since sources of constant
current are characterized by infinitely large terminal impedances, we desire an aforementioned
small signal impedance that is ideally infinitely large.
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3.4.1.1. World’s Worst BJT Biasing Circuit
The task of developing biasing strategies begins by acquiring an insightful understanding of the two major issues that accompany pragmatic bias circuit design. These issues, which
embrace quiescent collector current dependence on the static gain parameter, hFE, and the inherently positive temperature coefficient of collector current, are highlighted by the simple biasing
cell offered in Figure (3.25a). The circuit at hand uses the voltage divider formed of resistances
R1 and R2 to prescribe the quiescent base-emitter voltage, VbeQ, which is required to support the
desired quiescent collector current, IcQ. Since IcQ is largely determined by the base-emitter junction bias when the transistor operates in its linear domain, it is nominally independent of the
collector load resistance, Rl, which is selected to satisfy small signal gain or other requirements.
However, Rl sets the quiescent collector-emitter voltage, VceQ in accordance with
+Vcc
R1
+Vcc
Rl
Rl
IcQ
IcQ /hFE
VbeQ
−
+
IcQ /hFE
VceQ
+
R2
IcQ
+
VceQ
+
−
R1||R2
( hh +1 ) I
VbeQ
−
−
( hh +1 ) I
FE
FE
cQ
FE
( R R+R )V
+
cQ
FE
2
1
(a).
2
cc
−
(b).
Figure (3.25). (a). Simple biasing circuit for a bipolar junction transistor. (b). An equivalent
representation of the topological structure of (a).
(3-97)
Vcc = Rl I cQ + VceQ .
For a given power supply voltage, Vcc, and a desired quiescent collector current, IcQ, this simple
KVL relationship shows that in view of the fact that VceQ must be at least as large as VbeQ to promote BJT operation in its linear regime, large values of Rl are precluded. In concert with the linear domain requirement, observe that the base current is delineated in Figure (3.25a) as IcQ/hFE,
whence an emitter current that is (hFE +1)-times larger than the base current.
The application of Thévenin’s theorem to the circuit in Figure (3.25a) results in the
equivalent representation what we offer in (3.25b). In the latter diagram,
⎛ I cQ ⎞
⎛ R2 ⎞
(3-98)
⎟ + VbeQ ,
⎜
⎟Vcc = ( R1 R2 ) ⎜
⎝ R1 + R2 ⎠
⎝ hFE ⎠
which delivers
⎤
⎛
h ⎡
R ⎞
I cQ = FE ⎢Vcc − ⎜ 1 + 1 ⎟VbeQ ⎥ .
(3-99)
R1 ⎣
R2 ⎠
⎝
⎦
Prior to using this result to assess the quality of the subject biasing circuit, it is important for the
reader to understand the reason underlying the decision to apply KVL to the base-emitter loop of
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the circuit, as opposed to using (3-97), which is the fruit of KVL applied to the collector-emitter
loop. In particular, (3-97) delivers the irrefutably simpler collector current expression,
Vcc − VceQ
I cQ =
.
(3-100)
Rl
While this equilibrium relationship is assuredly valid, it conveys the impression that the quiescent collector-emitter voltage, VceQ, is an independent voltage variable on which the quiescent
collector current, IcQ, depends. But (3-33) and (3-36) demonstrate that the collector current of a
BJT is only weakly dependent on the internal collector-emitter voltage, Vb, and thus its extrinsic
counterpart, since the Early voltage, Vaf, is a reasonably large number. Indeed, the collector current is independent of Vb if the idealized case of infinitely large Early voltage is adopted. In contrast, (3-33) and (3-36) show a pronounced, exponential dependence of collector current on internal base-emitter voltage, Ve, which relates intimately to the base-emitter terminal quiescent voltage, VbeQ. Accordingly, (3-99) propounds a design-oriented, and thus far more relevant, expression for Q-point collector current than does (3-100).
Equation (3-99) offers two reasons for nominating the biasing circuit of Figure (3.25a)
as the worst in the world. The first of these reasons is the direct dependence of quiescent collector current on the gain metric, hFE. We recall that hFE is directly proportional to the Ebers-Moll
parameter, βf, which, because of its inverse dependence on the extremely narrow base width of a
bipolar junction transistor, can be controlled typically to within only factors ranging from 2:1 to
4:1. Thus, the precise value of hFE for a given transistor is unknown, which renders an accurate
prediction of IcQ dubious. The upshot of the matter is that conventional monolithic processing,
which promulgates a vagarious nature to hFE, renders impossible the accurate numerical delineation of IcQ in Figure (3.25a).
A second reason motivating an engineering veto of the biasing circuit at hand is
unacceptably large temperature sensitivity of the quiescent collector current. Recall from the
discussion in Section (3.2.0) and the temperature sensitivity disclosures in the preceding chapter
on PN junction diodes that in order to sustain constant collector current in the face of junction
temperature increases, the internal base-emitter voltage must decrease at a nominally constant
temperature rate. This requisite decrease in intrinsic base-emitter junction voltage can be translated to a decrease in terminal base-emitter voltage, VbeQ, as
(3-101)
ΔVbeQ ≈ − Sbe ΔT j ,
where Sbe is an empirical constant of the order of 2 mV/°C, and ΔTj is the change incurred in the
operating temperature, Tj, of the base-emitter junction. Accordingly, (3-98) provides a collector
current temperature coefficient, say σi, of
ΔI cQ
h S
(3-102)
σi ≈ FE be ,
ΔT j
R1 R2
which shows that the temperature sensitivity factor, Sbe, is effectively amplified by hFE, which
while precisely unpredictable, is nonetheless an assuredly large number. The actual temperature
coefficient of the quiescent collector current can be expected to be somewhat larger than σi in (3102) owing to the slight dependence on temperature of parameter hFE and the nonzero temperature coefficients associated with the circuit resistors.
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EXAMPLE #3.5:
The silicon transistor in the biasing circuit of Figure (3.25a) has a minimum hFE of 100.
Using a 3 volt power supply, design the circuit so that it dissipates no more than 8 mW
of power, while delivering a quiescent collector current of 2 mA at a collector-emitter
voltage of 1 volt at room temperature. Assume that the transistor delivers hFE = 100 and
that the required quiescent base-emitter voltage is 720 mV. For this design, estimate the
resultant change in quiescent collector current when the base-emitter junction temperature rises by 30 °C. To the latter end, take Sbe = 1.8 mV/°C.
SOLUTION #3.5:
(1).
The simplest calculation pertains to the collector load resistance, Rl. From either Figure
(3.25a) or (3-100), IcQ = 2 mA, Vcc = 3 volts, and VceQ = 1 volt yields
Vcc − VceQ
Rl =
= 1 KΩ .
(E5-1)
I cQ
(2).
The current, say IR1, conducted by resistance R1 in Figure (3.25a) is
VbeQ
I cQ
I R1 =
+
.
(E5-2)
R2
hFE
The subject figure also confirms that the power supply must deliver a current of IcQ + IR1 to
the biasing circuit. It follows that the power delivered to the circuit by voltage source Vcc,
which is the power, Pdis, dissipated by the biasing circuit, is
VbeQ ⎤
⎡⎛ h + 1 ⎞
Pdis = Vcc I cQ + I R1 = Vcc ⎢⎜ FE
(E5-3)
⎥ .
⎟ I cQ +
R2 ⎦
⎣⎝ hFE ⎠
Note that the bracketed quantity on the right hand side of this expression is the net current
flowing to ground, since the first term in the bracketed quantity is the transistor emitter current, while the second term is the current flowing through resistance R2. For Vcc = 3 volts,
hFE = 100, IcQ = 2 mA, and VbeQ = 720 mV, Pdis = 8 mW stipulates R2 = 1.11 KΩ.
(
)
(3).
Equation (3-99) can now be exploited to determine the value of resistance R2. For Vcc = 3
volts, hFE = 100, R1 = 1.11 kΩ, IcQ = 2 mA, and VbeQ = 720 mV, R2 = 355.1 Ω. This required
value of resistance R2 means that the 8 mW power dissipation specification cannot be met in
light of all other stipulated operating requirements.
(4).
With Sbe = 1.8 mV/°C, hFE = 100, R1 = 1.11KΩ, and R2 = 355.1 Ω, the temperature coefficient, σi, of the Q-point collector current is found, using (3-102), to be σi = 668.6 μA/°C.
Given ΔTj = 30 °C, the computed change in collector current is ΔIcQ = σiΔTj = 20.1 mA. In
truth, the collector current cannot be perturbed by this amount for at best, the transistor saturates as the collector circuit in Figure (3.25a) rises toward its maximum possible value of
Vcc/Rl = 3 mA. Even this maximum cannot be precisely achieved in that the collector-emitter
voltage can be reduced to only its small, but assuredly nonzero, saturation value.
COMMENTS: Two lessons are learned by this simple example. The first is that all
calculations executed on an active network must be carefully scrutinized
in light of the assumptions on which cognate analyses are premised. In the
case at hand, it is tacitly presumed at the outset that the transistor operates
in its linear domain. For linear operation of the circuit at hand, the collector current must remain smaller than about 3 mA, which is the collector
current that theoretically flows if the collector-emitter voltage can be reMing Hsieh Department of Electrical Engineering
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duced to zero. Accordingly, the calculated, temperature-induced change
in quiescent collector current of better than 20 mA is a meaningless
computation, except to suggest that the transistor in question indeed saturates merely because of an increase in the operating temperature of the
base-emitter junction.
The second lesson articulated by this example, is that the circuit in Figure
(3.25a) is a terrible biasing topology. Aside from the unpredictability of
collector current due to the inherent uncertainty in the gain parameter, hFE,
it is difficult to sustain linear domain operation over routinely encountered
temperature excursions. For example, routine self-heating of a junction
readily results in a 10 °C increase in junction operating temperature. But
even for this modest 10 °C increment, the calculated change in quiescent
collector current is almost 6.7 mA, which is more than sufficiently large to
incur device saturation.
3.4.1.2. Current Controlled Voltage Feedback Biasing
The shortfalls of the simple biasing circuit in Figure (3.25a) are circumvented if an
emitter degeneration resistance, Ree, is inserted into the emitter lead, as depicted in Figure
(3.26a). This resistance incorporates voltage feedback into the base-emitter loop to allow for an
automatic adjustment in the base-emitter voltage when the quiescent collector current, IcQ, departs from its design target. We note that this automatic adjustment capability of base-emitter
voltage VbeQ contrasts sharply with the previously considered biasing configuration. In particular, we note in (3-98) that to the extent that hFE is very large (which is virtually guaranteed in
monolithic BJTS), VbeQ is essentially a constant determined by resistance ratio R2/R1 and power
supply voltage Vcc. Thus as the quiescent collector current rises in response to increases in the
junction operating temperature, no provision to mitigate these current increases through suitable
decreases in VbeQ is afforded by the preceding circuit.
We can glean a qualitative appreciation of the effectiveness of resistance Ree in Figure
(3.26a) by assuming that initially, the quiescent collector current meets its design goal. Subsequent to establishing the correct collector current in the steady state, let IcQ increase because of
self-heating, the deployment of a transistor whose relevant parameters differ slightly from those
invoked in the actual design process, or any other commonly encountered engineering nuance.
The increase in IcQ is sensed directly as an increase in the voltage, Vre, dropped across resistance
Ree. Assume that the voltage, Vbx, established at the base node of the transistor approximates a
constant. From the equivalent circuit in Figure (3.26b), a current invariant Vbx materializes if the
Thévenin resistance, (R1||R2), is small and/or the minimum anticipated value of hFE is large. The
latter parametric condition forces the base current conducted by the transistor to be very small,
thereby constraining the voltage drop across the aforementioned Thévenin resistance small.
Since Vbe = Vbx − Vre, an increase in voltage Vre, which manifests negative feedback with respect
to the presumably invariant voltage, Vbx, is met by a decrease in the base-emitter voltage, Vbe. In
turn, diminished Vbe serves to reduce the collector current, thereby offsetting, albeit partially, the
parasitic increase in quiescent collector current. Of course, this self-correction mechanism also
functions for a decreasing IcQ in that diminished IcQ produces a reduced Vre, which induces an increased Vbe that presumably compensates for the original current reduction.
By inspection of the equivalent circuit in Figure (3.26b),
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⎛ I cQ ⎞
⎛ R2 ⎞
⎛ hFE + 1 ⎞
(3-103)
⎟ + VbeQ + ⎜
⎜
⎟Vcc = ( R1 R2 ) ⎜
⎟ Ree I cQ ,
⎝ R1 + R2 ⎠
⎝ hFE ⎠
⎝ hFE ⎠
whence
⎡
⎤
⎛
R1 ⎞
⎢ Vcc − ⎜ 1 +
⎟VbeQ ⎥
R2 ⎠
⎛ R2 ⎞ ⎢
⎝
⎥.
I cQ = hFE ⎜
(3-104)
⎟⎢
R
+
R
R
R
+
h
+
1
R
(
)
2 ⎠ ( 1 2)
FE
ee ⎥
⎝ 1
⎢
⎥
⎣
⎦
The dependence of IcQ on the poorly controlled gain parameter, hFE, is substantively reduced if
design care is exercised to ensure (R1||R2) << (hFE + 1)Ree. The quantification of the extent to
which the parallel combination of resistances R1 and R2 is smaller than the net resistance, (hFE +
1)Ree depends on the desired degree of accuracy ascribed to setting the actual collector current.
For example, if IcQ is to be controlled to within ±10% of its design target, (R1||R2) ≤ (hFE +
1)Ree/10 constitutes an appropriate design tack. If, on the other hand, ±1% control is required,
(R1||R2) should be of the order of 100-times smaller than (hFE + 1)Ree. Degree of accuracy
notwithstanding, (R1||R2) << (hFE + 1)Ree collapses (3-104) to the approximate result,
+Vcc
R1
+Vcc
Rl
Rl
Zx
Zx
IcQ
Vbx
+
IcQ /hFE
VceQ
+
VbeQ
R2
IcQ
−
+
Vre
Vbx
−
R1||R2
Ree
−
( hh +1 ) I
FE
cQ
(
R2
V
R1+R2 cc
)
+
−
+
IcQ /hFE
VceQ
+
VbeQ
−
−
+
Vre
Ree
−
( hh +1 ) I
FE
FE
cQ
FE
(a).
(b).
Figure (3.26). (a). BJT biasing circuit incorporating emitter degeneration as a feedback vehicle for
the stabilization of the quiescent collector current. (b). Equivalent circuit of the network of (a).
⎤
⎛ α ⎞⎛ R2 ⎞ ⎡
⎛
R1 ⎞
I cQ ≈ ⎜ FE ⎟⎜
(3-105)
⎟ ⎢Vcc − ⎜ 1 +
⎟VbeQ ⎥ ,
R2 ⎠
⎝
⎝ Ree ⎠ ⎝ R1 + R2 ⎠ ⎣
⎦
where αFE is given by (3-48). If the minimum anticipated value of hFE is substantially larger
than one, as it inevitably is, αFE approaches unity, and IcQ in (3-105) is rendered virtually
independent of hFE. Accordingly, the inclusion of emitter degeneration serves to mitigate the
undesirably pronounced sensitivity of quiescent collector current on hFE, which is a signature of
the terrible network in Figure (3.25a).
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Apart from virtually eliminating the problem of IcQ sensitivity to hFE, emitter degeneration proves laudable from the standpoint of temperature sensitivity. Using (3-101),
ΔI cQ
α S
(3-106)
σi ≈ FE be ,
ΔT j
Ree
which demonstrates that unlike the collector current temperature sensitivity in the circuit of Figure (3.25a), the base-emitter junction temperature sensitivity coefficient, Sbe, is not amplified by
the large current gain parameter, hFE. Equation (3-106) presumes that (1) the temperature coefficient of resistance Ree is small and can be ignored, (2) the dependence of Vcc on temperature is
negligibly small, and (3) the minutely small temperature sensitivity of parameter αFE is
inconsequential. Note that the temperature coefficients of resistances R1 and R2 are likely to
prove immaterial in that these resistances appear only as resistive ratios in the quiescent collector
current expression. In particular, if R1 and R2 are laid out proximately on the integrated circuit
chip as comparably sized diffused or implanted geometric forms, and if their individual values
are within an order of magnitude or so of one another, the temperature dependence of either
R1/R2 or R2/R1 is unlikely to comprise a design issue in most applications. Equation (3-106)
establishes a convenient basis for selecting an appropriate emitter degeneration resistance.
The degree to which current IcQ modulates in response to signals appearing at the
collector port of the network in Figure (3.26a) can be discerned through an analytical quantification of the indicated output impedance, Zx, established at the collector terminal. To this end, the
subject transistor can be replaced by the transistor small signal model developed in Figure (3.15).
The high frequency nature of impedance Zx is invariably dominated by the shunting substrate
capacitance, Cs, which is a relatively large capacitance in conventional monolithic processes.
Accepting this contention without proof, attention presently focuses on uncovering only the low
frequency component, say Rx, of impedance Zx. Accordingly, all capacitances in the transistor
model at hand can be set to zero. Additionally, the ohmic resistances, re, and rc, are tacitly ignored without fear of significant accuracy impairment, so that the resultant low frequency, small
signal equivalent circuit is the topology delineated in Figure (3.27). In this representation, it
should be noted that voltage Vcc is supplanted by a short circuit since the small signal value of
this ideally constant voltage is obviously zero. An additional noteworthy point is that output
resistance Rx does not include the collector load resistance, Rl. Such neglect does not comprise
engineering oversight since the analytical objective herewith is to discern the sensitivity of quiescent collector current to signal changes at the collector terminal for any load resistance that sustains transistor operation in its forward active domain.
Rx
rbb
Vx
R1||R2
rπ
βac I
I
Ix−βacI
Ree
ro
Ix
I+Ix
Figure (3.27). Approximate low frequency model used to
evaluate the small signal resistance, Rout,
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presented at the collector port of the biasing
network shown in Figure (3.26a).
The desired resistance, Rx, is the voltage to current ratio, Vx/Ix, where Ix is postured as a
current source emulation of a mathematical ohmmeter. For convenience, we have delineated the
branch current responses to the ohmmeter excitation in Figure (3.27). By KVL,
0 = ( R1 R2 + rbb + rπ + Ree ) I + Ree I x
(3-107)
.
Vx = ( ro + Ree ) I x − ( βac ro − Ree ) I
Solving the first of these two equations for current I and inserting said solution into the second
expression leads to
⎛
⎞
V
βac Ree
Rx = x = Ree ( R1 R2 + rbb + rπ ) + ⎜ 1 +
⎟ ro .
⎜
Ix
Ree + R1 R2 + rbb + rπ ⎟⎠
⎝
(3-108)
⎛
⎞
βac Ree
≈ ⎜1 +
⎟⎟ ro .
⎜
R
R
R
r
r
+
+
+
ee
1
2
bb
π
⎝
⎠
The indicated approximation is reflective of the fact that the Early resistance, ro, and the AC
beta, βac, are typically large numbers. While Rx, is assuredly finite, it can be significantly larger
than the Early resistance. Because of a potentially very large Rx, the biasing network in question
appears to supply a quiescent collector current that is relatively unaffected by signal voltage
swings at the collector node.
EXAMPLE #3.6:
The silicon NPN transistor in the biasing circuit of Figure (3.26a) has a minimum hFE of
100 and a nominal base-emitter voltage of 720 mV at room temperature. Using a 6 volt
power supply, design the circuit to provide a quiescent collector current of 2 mA at a
collector-emitter voltage of 1.5 volts at room temperature. The desired quiescent collector current is to be maintained to within ±5% for junction temperature increases as large
as 50 °C. A base-emitter junction temperature coefficient of Sbe = 2.0 mV/°C can be
presumed Using the HSPICE NPN BJT model parameters given in Table (3.1), simulate the design at 27°C, 50 °C, and 75 °C. Assuming rbb = 250 Ω, rπ = 1.4 KΩ, ro = 28
KΩ, and βac = 95 amps/amp at the quoted quiescent operating point, estimate the
change in the collector Q-point current for a 500 mV signal swing at the collector terminal.
SOLUTION #3.6:
(1).
Since the maximum allowable increase in quiescent collector current is 5% of its room
temperature, 2 mA value, ΔIcQ ≤ (0.05) (2 mA) = 100 μA. Given ΔTj = 50 °C, σi = ΔIcQ /ΔTj
≤ 2 μA/°C. Using (3-106), in which Sbe = 2 mV/°C and αFE = hFE /(hFE + 1) = 100/101 =
0.9901,
α S
(E6-1)
σi ≈ FE be ≤ 2 μA / °C ,
Ree
which results in Ree ≥ 990.1 Ω. Rounding this resistance up to Ree = 1 KΩ is prudent
engineering action in that a larger than minimally required emitter degeneration resistance
provides for a small amount of proverbial breathing room with regard to the target temperature sensitivity of the biasing network.
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(2).
BJT Models & Biasing
J. Choma
The circuit in Figure (3.26a) yields
⎛ h +1⎞
Vcc = Rl I cQ + VceQ + ⎜ FE
⎟ Re e I cQ .
⎝ hFE ⎠
(E6-2)
With Vcc = 5 volts, VceQ = 1.5 volts, hFE = 100, IcQ = 2 mA, and Ree = 1 KΩ, the collector
load resistance, Rl, computes as Rl = 1.24 KΩ.
(3).
The parallel resistance combination, (R1||R2) must be selected so that it is substantially
smaller than the effective resistance, (hFE + 1)Ree. Since the target quiescent collector current is to be sustained to within ±5% over the quoted temperature excursion, (R1||R2) must be
at most (hFE + 1)Ree/20, or 5.05 KΩ. It is therefore reasonable to stipulate (R1||R2) = 4 KΩ,
thereby ensuring, with ostensibly adequate safety margin, the validity of tacitly neglecting
the parallel resistance, (R1||R2), in (3-104).
(4).
Equation (3-105) can be recast as
⎡
⎤ ⎛ R1 R2 ⎞ ⎡
⎤
⎛ R1 ⎞
hFE
(E6-3)
I cQ ≈ ⎢
⎥⎜
⎟⎟VbeQ ⎥ ,
⎟ ⎢Vcc − ⎜⎜
⎥⎦
⎢⎣ ( R1 R2 ) + ( hFE + 1) Ree ⎥⎦ ⎝ R1 ⎠ ⎢⎣
⎝ R1 R2 ⎠
in which the only unknown quantity is the resistance ratio, (R1||R2)/R1. Solving for this ratio
results in the arguably sloppy, but nonetheless tractable, relationship,
SPICE
TEXT
SYMBOL SYMBOL
BF
βf
DESCRIPTION
OF PARAMETER
VALUE
UNITS
Forward Short Circuit Gain
120
amps/amp
BR
βr
Reverse Short Circuit Gain
1.2
amps/amp
CJC
CJE
CJS
IKF
IRB
IS
MJC
MJE
MJS
NF
NR
RB
Cjco
Cjeo
Cso
Ikf
Irb
Is
mc
mje
ms
nf
nr
rbb
Zero Bias B-C Depletion Capacitance
fF
fF
fF
mA
mA
fA
–
–
–
–
–
Zero Bias Base Resistance
1.1
3.8
10.2
11.5
4.5
3.2
0.333
0.5
0.5
1.05
1.0
270
RBM
Rbm
Minimum Base Resistance
35
Ω
RC
rc
Series Collector Resistance
20
Ω
RE
re
Series Emitter Resistance
1.5
TF
τfo
Zero Bias Minority Carrier Transit Time
4.2
Ω
pSEC
TNOM
Tj
Junction Reference Temperature
27
VAF
VJC
VJE
Vaf
Vjc
Vje
Forward Early Voltage
30
780
920
Zero Bias B-E Depletion Capacitance
Zero Bias Substrate Depletion Capacitance
Forward Knee Current
Base Resistance Corner Current
Saturation Current
B-C Junction Grading Coefficient
B-E Junction Grading Coefficient
Substrate Junction Grading Coefficient
B-E Junction Injection Coefficient
B-C Junction Injection Coefficient
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B-E Junction Built-In Potential
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volts
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mvolts
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Substrate-Collector Built-In Potential
Temperature Exponent For IS
Temperature Exponent For TF
Temperature Exponent For BF
690
3
0.025
0.02
mvolts
−
−
−
Table (3.1). HSPICE model parameters for a representative NPN bipolar junction transistor having a maximum unity gain frequency of approximately 35 GHz. Although the transistor characterized herewith is fictitious, the parameters are typical of a moderately high speed BJT.
⎡ ( R1 R2 ) + ( hFE + 1) Ree ⎤
⎢
⎥ I cQ + VbeQ
hFE
R1 R2
⎢
⎣
⎦⎥
=
= 0.470 .
R1
Vcc
Since (R1||R2) = 4 KΩ, R1 = 8.51 KΩ, whence
( R1 R2 ) R1 = 7.55 KΩ .
R2 =
R1 − ( R1 R2 )
(5).
(E6-4)
(E6-5)
For the computed biasing resistances and the quoted small signal transistor parameters, (3108) gives Rx = 428.8 KΩ. This means that for a collector terminal signal of 500 mV, the
signal-induced change, ΔIcQ, in the quiescent collector current is ΔIcQ = 500 mV/428.8 KΩ =
1.17 μA, which is only 0.058% of the target quiescent current.
+6 V
8.51 K
1.24 K
3.52 V
2.74 V
2.02 V
1K
7.55 K
Figure (3.28). Biasing circuit designed in Example #3.6.
The voltages shown in the boxes correspond
to the estimated respective node voltages for a
properly functioning circuit.
The completed design is shown in Figure (3.28). To facilitate circuit debugging with
measured or simulated results, we have explicitly indicated target nodal voltages in
the diagram.
COMMENTS: The simulated results track very favorably with design predictions. In
particular, the simulated quiescent collector current at 27 °C is 1.98 mA,
which is only 1% lower than the 2 mA design target. At 50 °C, the simulated Q-point collector current is 2.01 mA, while at 75 °C, the simulated
value of IcQ is 2.05 mA, which is larger than the 27 °C value of 1.98 mA by
only 3.54%. Moreover, at 27 °C, the simulated collector, base, and emit-
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ter voltages, measured with respect to ground, are 3.55 volts, 2.75 volts,
and 2.00 volts, respectively.
The circuit at hand is an excellent biasing circuit from the admittedly limited perspective that both manual and computer-aided analyses confirm
the predictability of the quiescent collector current. It also offers adequate
desensitization of this collector current with respect to temperature
changes, uncertainties in parameter hFE, and collector signal change, which
at 500 mV is actually reasonably large by conventional small signal standards. However, it does exude at least a few shortcomings, whose
respective significance is better appreciated in a subsequent chapter that
addresses the gain and noise characteristics of the amplifier that derives
from the considered biasing topology. In particular, it turns out that the
maximum voltage gain afforded by the circuit at hand is the ratio of the
collector load to emitter degeneration resistances. In the present case, this
ratio is barely above one, but mitigation procedures are fortunately
available. Moreover, the relatively large emitter degeneration resistance
required for suitable temperature compensation increases the equivalent
input noise voltage, which is the minimum signal strength that the amplifier can detect and process reliably. In many applications, this dilemma
can likewise be addressed satisfactorily.
3.4.2. ACTIVE BIASING NETWORKS
Although prudently designed passive biasing structures are effective in stabilizing the
quiescent operating points of bipolar junction transistors over temperature, their ultimate
effectiveness in monolithic circuit realizations is often limited. One commonly encountered
problem is that the ratios of requisite resistance values in these compensation schemes are widely
divergent. Two problems prevail with respect to resistance pairs whose values differ by large
factors. The first is that controlling the accuracy of a resistance ratio becomes progressively
more difficult with increasing ratio. The second is non-uniformity of temperature coefficients
between broadly diverse resistance values. Yet another quandary is that the resistance values
required for acceptable temperature stabilization are often not synergistic with the desired small
signal performance that the network undergoing biasing must ultimately deliver. To this end, for
example, it has been noted that the large emitter degeneration resistance in the design example of
Figure (3.28) limits the achievable voltage gain of the cell.
The foregoing dilemmas can be circumvented in integrated circuits by using companion
transistors to control the operating point stability of a given transistor. The basic approach is to
develop topological structures for which the quiescent variable of interest in a particular transistor is constrained to be directly proportional to the corresponding, and presumably easily stabilized, variable of a second, subsidiary transistor whose volt-ampere characteristics match those
of the transistor upon which attention is focused. One advantage of this active stabilization approach is that judiciously laid out transistor pairs can be matched remarkably well so that their
thermal properties accurately track one another over broad temperature ranges. As a result, design attention can largely focus on the relatively simple subsidiary subcircuit, with the assurance
that the monolithic process is fully capable of delivering transistor responses that track
exceptionally well with the variables prescribed in these units. The methods documented in the
following subsections are far less effective in discrete, off the shelf component, circuit realizations since the relevant electrical characteristics of even ostensibly equivalent transistor types
from the same device manufacturer are rarely matched well.
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3.4.2.1. Diode-Resistor Current Mirror
Among the most popular of active biasing compensation structures is the circuit offered
in Figure (3.29). A comparison of this circuit with the network in Figure (3.26a) shows that a diode-connected transistor, Q2, is inserted in series with the resistance R2 in the hope of stabilizing
the quiescent collector current, IcQ, conducted by the focus transistor, Q1. It is extremely important that, save possibly for differences in base-emitter junction area, the two BJTs be matched
devices that conduct nearly identical current densities. If Q1 and Q2 are indeed matched and
conduct identical densities of static current, their base-emitter voltages, VbeQ, are necessarily
equal. An equality of these two terminal voltages over all reasonable temperature excursions
additionally requires that the subject two transistors be laid out proximately so that both experience nearly the same junction temperature changes. Accordingly, if the emitter current of
transistor Q2 is designated as IdQ,
⎛ h + 1⎞
(3-109)
VbeQ + R2 I dQ = VbeQ + ⎜ FE
⎟ Re e I cQ .
⎝ hFE ⎠
+Vcc
R1
Rl
Rx
IdQ + IcQ /hFE
IcQ /hFE
+
VbeQ
Q2
+
VbeQ
IcQ
+
Q1 VceQ
−
−
−
R2
Ree
( hh +1 ) I
IdQ
FE
cQ
FE
Figure (3.29). Active biasing compensation through the addition of diode-connected transistor Q2 to the basic
passive structure of Figure (3.26a).
Since hFE >> 1 (if hFE is not much larger than one, it is time to contract with an alternate
processing foundry),
⎛ R ⎞
⎛ h
⎞⎛ R ⎞
(3-110)
I cQ = ⎜ FE ⎟⎜ 2 ⎟ I dQ ≈ ⎜ 2 ⎟ I dQ ,
⎝ hFE + 1 ⎠⎝ Ree ⎠
⎝ Ree ⎠
which contends that IcQ mirrors current IdQ through the proportionality constant, R2/Ree. The fact
that the subject constant of proportionality is a simple resistance ratio is music to our ears. In
particular, if R2 and Ree are of the same order of magnitude, ratio R2/Ree can be controlled precisely (to within a couple of percent or less) over broad ranges of temperature. In a word,
stabilizing IdQ automatically renders current IcQ stable over temperature, despite the potential impact of other environmental factors.
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The most straight forward design circumstance is R2 = Ree, whereupon, IcQ is literally
the mirror image of IdQ. But note that if R2 is larger than Ree by a factor of k (k >1), IdQ, is a factor of k smaller than IcQ, which is advantageous from a circuit power dissipation perspective. In
this case, the junction injection area of transistor Q1 must be made k-times larger than that of
transistor Q2 to ensure that both transistors conduct the identical densities of current that sustain
equivalence between their base-emitter terminal voltages. In actual design environments, integer
or non-integer values of k that do not exceed six to eight prove practical and effective.
KVL applied to the R1−R2−Q2 branch of the circuit in Figure (3.29) gives
I cQ ⎞
⎛
(3-111)
Vcc = R1 ⎜ I dQ +
⎟ + VbeQ + R2 I dQ .
hFE ⎠
⎝
Appealing to (3-109) for the elimination of the current variable, IdQ, in (3-111) results in a quiescent collector current of
⎤
Vcc − VbeQ
⎛ R2 ⎞ ⎡
I cQ = hFE ⎜
(3-112)
⎥.
⎟⎢
⎝ R1 + R2 ⎠ ⎢⎣ ( R1 R2 ) + ( hFE + 1) Ree ⎥⎦
As in the case of the passive compensation topology of Figure (3.26a), ensuring (R1||R2) << (hFE
+ 1)Ree all but eliminates a collector current dependence on hFE in that (3-112) reduces to
⎛ R2 ⎞ ⎛ Vcc − VbeQ ⎞
(3-113)
I cQ ≈ αFE ⎜
⎟.
⎟⎜
Ree
⎝ R1 + R2 ⎠⎝
⎠
This result advances a collector current temperature coefficient of
ΔI cQ
α S ⎛ R2 ⎞
≈ FE be ⎜
σi (3-114)
⎟.
ΔT j
Ree ⎝ R1 + R2 ⎠
Two interesting observations surface from this last relationship. The first, and most clarion of
the two observations is that the active compensation scheme delivers a collector current temperature coefficient that is smaller than the coefficient associated with the passive compensator by
the voltage divider factor, [R2/(R1 + R2]. The second point is that (3-114) combines with (3-113)
to suggest
ΔI cQ
I cQ Sbe
α S ⎛ R2 ⎞
≈ FE be ⎜
σi ;
(3-115)
⎟ =
ΔT j
Ree ⎝ R1 + R2 ⎠
Vcc − VbeQ
that is, the temperature coefficient of interest is actually independent of circuit resistances in that
it is set by the selected Q-point current, IcQ, the power supply voltage, Vcc, and, of course the
transistor properties implied by VbeQ and its voltage sensitivity factor, Sbe. Whereas the passive
compensation scheme prescribes its current temperature coefficient, σi, via the emitter degeneration resistance, Ree, the active scheme effectively preserves a design degree of freedom by relying on the supply voltage to establish the temperature coefficient of the circuit.
The resistance, Rx, presented to the collector load resistance, Rl, in Figure (3.29) can be
evaluated straightforwardly by substituting the low frequency, small signal equivalent circuit of a
BJT for both of the devices in the network at hand. In the process of such substitution, care must
be exercised to account for the fact that the potentially different junction injection areas of the
two transistors foment different values among corresponding small signal parameters. But
unless the reader is exhilarated by detailed circuit analyses, a strongly recommended alternative
analytical tack entails a direct exploitation of the resistance result in (3-108), which derives from
a small signal analysis of the biasing configuration of Figure (3.26a). Clearly, the only differ-
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ence between the two circuits at hand is that a diode-connected transistor (Q2) is inserted in series with resistance R2 in Figure (3.26a). Since the diode-connected BJT is a two terminal element that is to be replaced by the low frequency version of the small signal model in Figure
(3.15), its small signal electrical properties mimic those of a simple two terminal resistance, say
Rd. The upshot of the matter is that (3-108) adapts to the circuit in Figure (3.29) merely by
replacing resistance R2 by the resistance sum, (R2 + Rd). It follows, effectively by inspection,
that Rx in Figure (3.29) is given by
⎛
⎞
βac Ree
Rx = Ree ⎣⎡ R1 ( R2 + Rd ) + rbb + rπ ⎦⎤ + ⎜ 1 +
⎟ ro
⎜
Ree + R1 ( R2 + Rd ) + rbb + rπ ⎟⎠
⎝
(3-116)
⎛
⎞
βac Ree
≈ ⎜1 +
⎟ ro .
⎜
Ree + R1 ( R2 + Rd ) + rbb + rπ ⎟⎠
⎝
The only outstanding issue is the evaluation of resistance Rd in terms of transistor
model parameters. To this end, the equivalent circuit of the Q2 interconnection is given in Figure (3.30), where as usual, the internal collector and emitter resistances of the transistor are ignored. As depicted, the use of our trusty mathematical ohmmeter delivers
Rd
rbb2
rπ2
Q2
Rd
(βac2+1)I
βac2 I
ro2
+
Ix Vx
−
I
Figure (3.30). Low frequency, small signal equivalent circuit of the diode-connected
transistor, Q2, in the biasing network of Figure (3.29). The model is configured to determine the resistance, Rd, established between the two terminals of
the diode unit.
Ix =
Vx
ro2
+ ( βac2 + 1) I =
Vx
ro2
⎛
⎞
Vx
+ ( βac2 + 1) ⎜
⎟,
+
r
r
π2 ⎠
⎝ bb2
whereupon
⎛r
Vx
+ rπ2 ⎞
rbb2 + rπ2
.
= ro2 ⎜ bb2
(3-117)
⎟ ≈
βac2 + 1
Ix
⎝ βac2 + 1 ⎠
Owing to a large AC beta, resistance Rd is small and very likely, it is significantly smaller than
the biasing resistance, R2, in the network of Figure (3.29). It therefore materializes that from a
practical perspective, resistance Rx in Figure (3.29) is virtually indistinguishable from resistance
Rx in Figure (3.26a).
Rd =
EXAMPLE #3.7:
The silicon NPN transistors in the active biasing circuit of Figure (3.29) have a minimum hFE of 100 and a nominal base-emitter voltage of 720 mV at room temperature.
Design the circuit so that with a collector load resistance to emitter degeneration resistance ratio of 10, a quiescent collector current of 2 mA flows through transistor Q1 when
its collector-emitter voltage is 1.5 volts at room temperature. The desired quiescent
collector current is to be maintained to within ±5% for junction temperature increases as
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large as 50 °C. A base-emitter junction temperature coefficient of Sbe = 2.0 mV/°C can
be presumed Using the HSPICE BJT model parameters given in Table (3.1), simulate
the design at 27°C, 50 °C, and 75 °C.
SOLUTION #3.7:
(1).
Since the maximum allowable increase in quiescent collector current is 5% of its room
temperature, 2 mA value, ΔIcQ ≤ (0.05) (2 mA) = 100 μA. Given ΔTj = 50 °C, σi = ΔIcQ /ΔTj
≤ 2 μA/°C. Using (3-115), in which Sbe = 2 mV/°C and VbeQ = 720 mV,
I cQ Sbe
σi ≈
≤ 2 μA / °C ,
(E7-1)
Vcc − VbeQ
which offers Vcc ≥ 2.72 volts. A power supply voltage of Vcc = 3 volts is appropriate,
particularly since 1.5 volt battery cells are readily available commercially.
(2).
The circuit in Figure (3.29) shows that
⎛ h +1⎞
(E7-2)
Vcc = Rl I cQ + VceQ + ⎜ FE
⎟ Re e I cQ .
⎝ hFE ⎠
With Vcc = 3 volts, VceQ = 1.5 volts, hFE = 100, IcQ = 2 mA, and Rl = 10Ree, the requisite emitter degeneration resistance is determined to be Ree = 68.1 Ω and hence, the collector load
resistance follows as Rl = 10Ree = 681 Ω.
(3).
In Figure (3.29) and (3-109), let the emitter current conducted by transistor Q2 be equal to
the emitter current flowing in transistor Q1, which means that both are required to have the
same base-emitter junction injection areas. Accordingly, R2 = Ree = 68.1 Ω. Moreover, with
R2 = Ree, (R1||R2) < Ree. It follows that the requisite inequality, (R1||R2) << (hFE +1)Ree, is
satisfied by a factor of better than (hFE +1) = 101, which is more than sufficient in light of
the ±5% tolerance constraint imposed on the desired quiescent collector current.
(4).
Setting R2 = Ree in (3-112) now leads to R1 = 1,061 Ω. The completed design is shown in
Figure (3.31). As in the preceding design example, target nodal voltages are expressly
delineated in the diagram.
+3 V
1,061
681
1.64 V
Q1
857.6 mV
Q2
137.6 mV
68.1
137.6 mV
68.1
Figure (3.31). Biasing circuit designed in Example #3.7. All
resistances are in units of ohms. The voltages
shown in the boxes correspond to the estimated
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respective node voltages for a properly functioning circuit.
COMMENTS: Once again, the simulated results confirm the propriety of the design
methodology. In particular, the simulated quiescent collector current at 27
°C is 1.97 mA, which is only 1.5% lower than the 2 mA design target. At
50 °C, the simulated Q-point collector current is 2.00 mA, while at 75 °C,
the simulated value of IcQ is 2.03 mA, which is larger than the 27 °C value
of 1.97 mA by only 3.05%. Moreover, at 27 °C, the simulated collector,
base, and emitter voltages of transistor Q1, measured with respect to
ground, are 1.66 volts, 884 mV, and 135.3 mV, respectively.
While the active compensator postured herewith comprises a superb biasing network, it, like virtually all electronic networks, is nonetheless imperfect. In the case at hand, the desired match between transistor base-emitter
voltages over temperatures is non-exact because of the finite Early voltages of the transistors and the simple fact that the collector-emitter voltages of the two transistors cannot possibly match. In particular, observe
that the collector-emitter voltage of transistor Q2 is necessarily constrained to be its base-emitter terminal voltage, while the collector emitter
voltage of Q1 is designed to be better than twice the base-emitter voltage.
Accordingly, the collector current correction for the Early effect is not the
same for each transistor.
3.4.2.2. Diode Current Mirror
The discovery that the collector current temperature coefficient of the diode-resistor
current mirror of Figure (3.29) is independent of all circuit resistances and specifically, is
independent of the emitter degeneration resistance, Ree, hints at the possibility of designing a
suitable biasing network that is divorced of emitter degeneration. The advantages of abrogating
emitter degeneration include decreased circuit power dissipation, the potential for increased
small signal gain, and reduced thermal noise. To this end, consider the diode mirror shown in
Figure (3.32), which uses, in addition to the collector load resistance, Rl, only a single resistance,
R, to bias the circuit. KVL applied to the R−Q2 branches of the circuit gives
+Vcc
Rl
R
Rx
IdQ + IcQ /hFE
IcQ /hFE
+
+
VbeQ
Q2
VbeQ
IcQ
+
Q1 VceQ
−
−
( hh +1 ) I
− IdQ
FE
cQ
FE
Figure (3.32). Diode current mirror BJT biasing circuit. The
base-emitter junction area of transistor Q1 can be
k-times larger than that of transistor Q2.
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I cQ ⎞
⎛
(3-118)
Vcc = R ⎜ I dQ +
⎟ + VbeQ .
hFE ⎠
⎝
In the interest of analytical generality, select transistor Q1 to be identical to transistor Q2, save
for the fact that the base-emitter junction area of Q1 is larger than that of Q2 by a factor of k.
Then, since the indicated circuit interconnections force equality between the base-emitter terminal voltages of both active devices, the emitter current, IdQ, flowing through Q2 is k-times
smaller than the emitter current of Q1; that is,
⎛ h + 1 ⎞⎛ I cQ ⎞
(3-119)
I dQ = ⎜ FE
⎟.
⎟⎜
⎝ hFE ⎠⎝ k ⎠
We note that in accordance with the fundamental premise of an actively compensated biasing
network, the desired Q-point collector current is merely proportional (by a factor of roughly k
herewith) to the current, IdQ, conducted by the subsidiary network, which in this case is comprised of resistance R and diode-connected transistor Q2. The substitution of (3-119) into (3118) resultantly accrues
hFE Vcc − VbeQ
I cQ =
.
(3-120)
hFE + 1 ⎞
⎛
R ⎜1 +
⎟
k
⎝
⎠
The virtual elimination of a collector current dependence on parameter hFE mandates satisfaction
of the inequality, (hFE + 1) >> k, which is easy enough to achieve. Accordingly,
αFE k Vcc − VbeQ
I cQ ≈
,
(3-121)
R
which infers a Q1 quiescent collector current that is simply k-times the current conducted by the
R−Q2 network branch. It is a simple matter to confirm a collector current temperature coefficient of
ΔI cQ
I cQ Sbe
α kS
(3-122)
σi ≈ FE be =
,
ΔT j
R
Vcc − VbeQ
(
)
(
)
whose final form is identical to the temperature factor associated with the diode-resistor mirror.
3.4.2.3. Vbe Multiplier Biasing
In the bipolar biasing circuits considered to this point, the quiescent collector current is
consistently cast as a function of two transistor variables; namely, the DC beta, hFE, and the
quiescent base-emitter voltage, VbeQ. The dependence of quiescent collector current on hFE is reduced to insignificant proportions through a sufficiently large hFE, coupled perhaps with an
appropriate choice of relevant circuit resistances. On the other hand, the current dependence on
Vbe, which is tantamount to a collector current sensitivity to junction operating temperature, is
mitigated with a prudently selected emitter degeneration resistance and/or the use of a large
enough power supply voltage. If it were possible to eliminate, as opposed to merely reducing,
the collector current sensitivity to base-emitter voltage, practical circuits offering the engineer
enhanced degrees of design freedom and possessed of phenomenally small temperature sensitivities become reality.
To the foregoing end, the circuit appearing in Figure (3.33) is theoretically capable of
realizing the somewhat idealized goal of a quiescent collector current, IcQ, which is independent
of base-emitter voltage VbeQ. The core subcircuit underpinning this enticing performance
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characteristic is the so-called Vbe multiplier, which consists of transistor Q2 and the two resistances, Rx and Ry. An analytical inspection of the Vbe multiplier cell itself, which is redrawn in
Figure (3.34a), facilitates the task of discerning the volt-ampere properties of the biasing network
in Figure (3.33). In Figure (3.33a), KCL relates the current, Im, conducted by the voltage multiplier cell to the static collector current, Ic2, flowing in transistor Q2 as
⎛h
V
I
+ 1⎞
Vbe2
(3-123)
I m = I c2 + be2 + c2 = ⎜ FE2
.
⎟ I c2 +
Rx
hFE2
h
R
x
⎝ FE2 ⎠
In addition, the voltage, Vm, sustained across the cell in response to the flow of current, Im, is
⎛V
I ⎞
(3-124)
Vm = R y ⎜ be2 + c2 ⎟ + Vbe2 .
hFE2 ⎠
⎝ Rx
If we solve (3-123) for the transistor current, Ic2, and substitute the result into the last expression,
voltage Vm is found to relate to base-emitter voltage Vbe2 and cell current Im as
+Vcc
R1
Rl
Rx
Im + IcQ /hFE
IcQ /hFE
+
Im
−
−
FE
+
+
+
Q1 VceQ
( hh +1 ) I
Ic
Ry
Rx
VbeQ
IcQ
cQ
FE
Q2 Vm
Vbe2
−
−
R2
Ree
Figure (3.33). BJT biasing circuit using active compensation
in the form of the Vbe multiplier comprised of
transistor Q2 and resistances Rx and Ry.
αFE2 R y ⎞
⎛
⎛ Ry ⎞
(3-125)
Vm = ⎜ 1 +
⎟Vbe2 + ⎜
⎟ I m kmVbe2 + Rm I m .
R
h
1
+
x
⎝
⎠
⎝ FE2
⎠
This result fosters the multiplier equivalent circuit proposed in Figure (3.34b), where model
parameters km and Rm are given by
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αFE2 R y
Rx
Ry
.
(3-126)
hFE2 + 1
The model at hand suggests that the multiplier cell emulates a voltage source whose voltage is
Vbe2, multiplied by the larger than unity factor, km, and whose effective static series resistance is
Rm. Observe that if Ry = 0, km = 1 and Rm = 0, which renders voltage Vm identical to the baseemitter voltage, Vbe2, of transistor Q2. This result reflects our expectations since Ry = 0 short
circuits the base terminal of transistor Q2 to its collector terminal, which in turn reduces the
Q2−Rx−Ry subcircuit to a simple diode-connected transistor whose terminal voltage is Vbe2. For
large hFE2, the multiplier approximates an ideal voltage source whose voltage value is
αFE2 R y ⎞
Ry ⎞
⎛
⎛
kmVbe2 = ⎜ 1 +
⎟Vbe2 ≈ ⎜ 1 +
⎟Vbe2 .
R
R
x
x⎠
⎝
⎠
⎝
Vbe2 /Rx + Ic2 /hFE2
Im
Im
+
+
Ic2
Ry
Ic2 /hFE2
+
Rx
Vbe2
Q2
−
Rm
Vm
kmVbe2
−
Vm
+
−
−
Vbe2 /Rx
(a).
(b).
Figure (3.34). (a). The Vbe multiplier used in the biasing scheme depicted in Figure
(3.31). (b). The Thévenin equivalent static circuit of the cell in (a).
Armed with the subcircuit model of Figure (3.34b), the biasing circuit in Figure (3.33)
can be represented electrically as the structure given in Figure (3.35). The latter configuration
exploits the design-oriented presumption that transistors Q1 and Q2 are identical devices that
conduct identical collector current densities. Accordingly, the voltages developed across both
base-emitter terminals are identical, as are the values of DC beta for the two transistors. It is
instructive to observe that the structure in Figure (3.35) collapses to the diode-resistor biasing
scheme offered in Figure (3.29) for the special case of km = 1 (or Ry = 0). In Figure (3.35),
I cQ ⎞
⎛
(3-127)
Vcc = R1 ⎜ I m +
⎟ + ( R2 + Rm ) I m + kmVbeQ
h
FE ⎠
⎝
and
⎛ h + 1⎞
(3-128)
( R2 + Rm ) I m + kmVbeQ = Ree ⎜ FE ⎟ I cQ + VbeQ .
⎝ hFE ⎠
Upon inserting the solution for current Im in (3-128) into (3-127), the solution for the quiescent
collector current, IcQ, conducted by transistor Q1 is found to be
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+Vcc
R1
Rl
Im + IcQ /hFE
IcQ /hFE
+
Im
Ic
Ry
+
+
Rx
+Vcc
VbeQ
R1
IcQ
Rl
Im + IcQ /hFE
+
IcQ /hFE
Q1 VceQ
−
IcQ
+
+
−
Im
( hh +1 ) I
FE
Q1 VceQ
VbeQ
−
−
( hh +1 ) I
FE
cQ
Rm
FE
cQ
FE
Q2 Vm
Vbe2
−
−
kmVbeQ
+
−
R2
Ree
R2
Ree
Figure (3.35). Equivalent electrical representation of the biasing network in Figure (3.31), wherein the Vbe
multiplier comprised of Q2−Rx−Ry is supplanted by its equivalent circuit of Figure (3.32b).
Transistors Q1 and Q2 are presumed to be identical devices that are biased to conduct the
same collector current densities, thereby implying that Vbe2 = VbeQ and hFE2 = hFE.
⎧
⎡
( km − 1) R1 ⎤V ⎫
⎪ Vcc − ⎢1 −
⎥ beQ ⎪
R2 + Rm ⎦
⎛ R2 + Rm ⎞ ⎪
⎪
⎣
I cQ = hFE ⎜
(3-129)
⎬.
⎟⎨
⎝ R1 + R2 + Rm ⎠ ⎪ R1 ( R2 + Rm ) + ( hFE + 1) Ree ⎪
⎪
⎪
⎩
⎭
Confidence in the accuracy of this disclosure is bolstered by the observation that for km = 1
(thereby constraining Rm to zero), (3-129) reduces to (3-112), which defines the Q-point collector
current appropriate to the diode-resistor compensation scheme in Figure (3.29). Moreover, if km
and resistance Rm are artificially set to zero, the network in Figure (3.35) collapses to the passive
compensation scheme in Figure (3.26a) and reassuringly, (3-129) reduces to (3-104), which is
the applicable collector current expression.
In order to desensitize the Q-point collector current in (3-129) to uncertainties in the
DC beta, hFE, it is necessary to enforce R1||(R2 + Rm) << (hFE + 1)Ree. As such, (3-129) can be
approximated as
⎧
⎡
( km − 1) R1 ⎤V ⎫
⎪Vcc − ⎢1 −
⎥ beQ ⎪
R2 + Rm ⎦
⎛ R2 + Rm ⎞ ⎪
⎪
⎣
I cQ ≈ αFE ⎜
(3-130)
⎬.
⎟⎨
Ree
⎝ R1 + R2 + Rm ⎠ ⎪
⎪
⎪
⎪
⎩
⎭
But in addition, if the constant, km, is selected such that
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R2 + Rm
,
(3-131)
R1
the resultant quiescent collector current, which becomes,
⎛ R2 + Rm ⎞⎛ αFE Vcc ⎞
(3-132)
I cQ ≈ ⎜
⎟,
⎟⎜
⎝ R1 + R2 + Rm ⎠⎝ Ree ⎠
is rendered independent of voltage VbeQ. At a minimum, (3-131) removes the ostensibly dominant source of collector current instability with respect to operating temperature. W observe further that for large hFE, which implies αFE ≈ 1 and encourages R2 >> Rm = Ry/(hFE + 1), (3-131),
becomes, with the aid of (3-126),
Ry
R
(3-133)
= 2 .
Rx
R1
Two interesting sidebars accompany this simple design requirement. First, if Ry/Rx < R2/R1, (km
− 1) < R2/R1, and the coefficient of voltage VbeQ in the numerator on the right hand side of (3130) is resultantly a positive number. Accordingly, IcQ displays its stereotypically positive
temperature coefficient in view of the fact that VbeQ must decrease with temperature to preserve
constant collector current. But if Ry/Rx > R2/R1, (km − 1) > R2/R1, and the VbeQ coefficient in
question is a negative number, thereby implying that IcQ decreases with operating temperature;
that is, the circuit projects an atypical negative temperature coefficient.
km = 1 +
RV
RV
Ix−βac2I
Ry
Ry
+
rbb2
Q2
βac2 I
rπ2
Rx
Ix Vx
Rx
Ix−(βac2+1)I
−
I
(a).
(b).
Figure (3.36). (a). The Vbe multiplier cell embedded in the biasing network of Figure (3.33). The
resistance, Rv, is the net small signal resistance established across the collector-emitter
terminals of the circuit. (b). The small signal equivalent circuit pertinent to the
evaluation of resistance Rv. As usual, the model ignores the series resistances in the
collector and the emitter leads of transistor Q2. Also ignored is the relatively large Q2
Early resistance, which appears as a simple shunting branch element across the terminals at which resistance Rv is established.
As in the case of the diode-connected transistor, Q2, in the active biasing scheme postured in Figure (3.29), the Vbe multiplier cell in the network of Figure (3.33) functions as a two
terminal resistance under small signal circumstances. As such, its net small signal terminal resistance, say Rv, as highlighted in the diagram of Figure (3.36a), derives as the voltage to current
ratio, Vx/Ix, in the low frequency equivalent circuit depicted in Figure (3.36b). The equivalent
circuit ignores the internal collector and emitter resistances of transistor Q2 and additionally, it
ignores the routinely large Early resistance, ro, of Q2. The latter resistance appears in shunt with
the current controlled current source, βacI, which implies that the effective resistance across the
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collector and emitter terminals of the Vbe multiplier cell is actually (ro||Rv). For the indicated
branch currents in Figure (3.36b),
( rbb2 + rπ2 ) I = Rx ⎡⎣ I x − ( βac2 + 1) I ⎤⎦
(3-134)
.
Vx = R y ( I x − βac2 I ) + ( rbb2 + rπ2 ) I
Substituting current I from the first expression into the second produces
⎛
V
α R ⎞
(3-135)
Rv = x = ⎜ 1 − ac2 x ⎟ R y + Rx Rd ,
+
Ix
R
R
x
d ⎠
⎝
where
βac2
αac2 (3-136)
βac2 + 1
is known as the small signal, short circuit, common base current gain (more about this definition later in the text), and Rd is the diode-connected transistor resistance introduced in (3-117).
In particular, observe in Figure (3.36a) that Ry = 0 and infinitely large Rx reduce the Vbe multiplier cell to a conventional diode-connected transistor. Reassuringly, Rv in (3-135) collapses to
Rd for this topological circumstance. Since βac2 >> 1, αac2 in (3-136) approaches one, thereby
simplifying the expression for resistance Rv to
⎛ Rd ⎞
(3-137)
Rv ≈ ⎜
⎟ Rx + R y .
⎝ Rd + Rx ⎠
which is only slightly larger than Rd if Ry > Rx.
(
)
Like the diode-connected transistor in the active biasing scheme of Figure (3.29), the
Vbe multiplier subcircuit in Figure (3.33) appears in series with biasing resistance R2. Otherwise,
the two subject circuits are identical. It follows that the resistance, Rx, presented to the collector
load in Figure (3.33) derives directly from (3-116), subject to the caveat that Rd is replaced by Rv;
that is
⎛
⎞
βac Ree
Rx = Ree ⎡⎣ R1 ( R2 + Rv ) + rbb + rπ ⎤⎦ + ⎜ 1 +
⎟ ro
⎜
⎟
+
+
+
+
R
R
R
R
r
r
(
)
ee
1
2
v
bb
π
⎝
⎠
(3-138)
⎛
⎞
βac Ree
≈ ⎜1 +
⎟ ro .
⎜
⎟
R
+
R
R
+
R
+
r
+
r
(
)
ee
1
2
v
bb
π
⎝
⎠
EXAMPLE #3.8:
The silicon NPN transistors in the active biasing circuit of Figure (3.33) have a minimum hFE of 100 and a nominal base-emitter voltage of 720 mV at room temperature.
Design the circuit so that with a power supply voltage of Vcc = 6 volts, transistor Q1
conducts a quiescent collector current of IcQ = 2 mA when the collector-emitter voltage,
VceQ, of Q1 is 1.5 volts. The circuit is to be designed so that IcQ is nominally invariant
with temperature and is maintained at its design target to with ±3%. Use the HSPICE
BJT model parameters itemized in Table (3.1) to simulate the finalized design at 27°C,
50 °C, 75 °C, and 100 °C.
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SOLUTION #3.8:
(1).
In order to optimize thermal tracking between the identical transistors, Q1 and Q2, the
collector current densities of these two transistors must be the same. Additionally,
implementing nominally identical collector-emitter voltages between the two devices is
recommended. Thus, voltage Vm in Figure (3.33) should equate to voltage VceQ, which is
stipulated to be 1.5 volts. Ignoring current Ic2/hFE2 in comparison with current Vbe2/Rx in the
companion subcircuit diagram of Figure (3.34a) results in
Ry ⎞
⎛
Vm ≈ ⎜ 1 +
(E8-1)
⎟Vbe2 = VceQ = 1.5 volts .
Rx ⎠
⎝
Given identical collector current densities in the two transistors, Vbe2 = VbeQ ≈ 720 mV,
whence Ry/Rx = 1.083. Recalling (3-133), which is the condition underpinning the nominal
thermal independence of current IcQ, R2/R1 = Ry/Rx = 1.083.
(2).
In an attempt to conserve standby power, let Q2 conduct one-half the current of transistor
Q1, which is to say that the base-emitter junction area of Q1 must be twice that of Q2. Thus,
Ic2 in Figure (3.34a) is 1 mA. Moreover, arbitrarily allow resistance Rx to conduct 1 mA of
current, which makes current Im = IcQ ≈ 2 mA. Thus, Vbe2/Rx = VbeQ/Rx = 1 mA, or Rx = 720
Ω. Since Ry/Rx = 1.083, Ry = 780 Ω. Note that Ic2/hFE2 = 1 mA/100 = 10 μA, which is 100times smaller than the current, Vbe2/Rx, thereby supporting (E8-1) to within an error of
roughly 1%, which is within the 3% error tolerance assigned to current IcQ.
(3).
If IcQ/hFE << Im, which has been set to 2 mA, Figure (3.33) confirms
Vcc = ( R1 + R2 ) I m + Vm .
(E8-2)
With Vcc = 6 volts, Im = 2 mA, and Vm = 1.5 volts, (R1 + R2) is 2,250 Ω. Recalling that R2/R1
= 1.083, this computation produces R1 = 1,080 Ω and R2 = 1,170 Ω. It is important to check
the propriety of the invoked approximations. In the present case, IcQ/hFE << Im has been presumed. Since IcQ/hFE = 2 mA/100 = 20 μA and Im = 2 mA, Im exceeds IcQ/hFE by a factor of
100, which amounts to a computational error of around only 1%.
(4).
Equation (3-132) can now be used to determine the resistance, Ree. Although resistance Rm,
as defined by (3-122) can be ignored because of its inverse dependence on (hFE + 1), it is a
trivial matter to include Rm in the calculations. To this end Rm = 7.72 Ω in that Ry = 780 Ω
and hFE = 100. Then, with R1 = 1,080 Ω, R2 = 1,170 Ω, αFE = 100/101, and Vcc = 6 volts,
Ree = 1,549 Ω. Since (3-132) presumes (R1||R2) = 561.6 Ω << (hFE + 1)Ree = 156.5 KΩ, the
approximation is satisfied by a factor of 156.5 KΩ/561.6 Ω = 278.7, which is tantamount to
a computational error of 1/278.7 = 0.359%. This small error means that the computed value
of Ree is high by nominally (0.00359)(1,549 Ω) = 5.6 Ω. Given the other approximations invoked in the course of this design procedure, it may be prudent to reduce Ree by very slightly
more than 5.6 Ω. To this end, allow Ree = 1,540 Ω.
(5).
The only remaining resistance to be computed is the collector load resistance, Rl. From Figure (3.33),
⎛ h +1⎞
(E8-3)
Vcc = Rl I cQ + VceQ + ⎜ FE
⎟ Ree I cQ ,
⎝ hFE ⎠
which straightforwardly precipitates Rl = 694.6 Ω.
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+6 V
1080
694.6
x2
4.61 V
Q1
3.83 V
780
Q2
3.06 V
720
2.34 V
3.11 V
1540
1170
Figure (3.37). Biasing circuit designed in Example #3.8. All resistances are in units
of ohms. The voltages shown in the boxes correspond to the estimated
respective node voltages for a properly functioning circuit. Transistor
Q2 has twice the base-emitter junction area of transistor Q1.
Figure (3.37) delineates the completed design. As in the preceding design examples,
the estimated static node voltages are provided in the schematic diagram.
COMMENTS: The simulated results confirm the propriety of the design methodology. In
particular, the simulated quiescent collector current of transistor Q1 at 27
°C is 2.00 mA, at 50 °C, the simulated Q-point collector current is 2.01
mA, at 75 °C, the simulated value of IcQ is 2.01 mA, and at 100 °C, IcQ =
2.01 mA. Moreover, at 27 °C, the simulated collector, base, and emitter
voltages of transistor Q1, measured with respect to ground, are 4.61 volts,
3.84 V, and 3.11 V, respectively. For Q2, the corresponding voltages are
3.84 V, 3.05 V, and 2.32 V.
Design solutions are rarely unique. In the present example, different
disclosures accrue if a current other than 1 mA is arbitrarily chosen to flow
through resistance Rx. From a thermal sensitivity perspective, the circuit
at hand is clearly excellent. Nonetheless, it is assuredly not the panacea
for BJT biasing for at least two reasons. First, a large number of resistances are required, and it is extremely important that the resistance pairs,
R1−R2 and Rx−Ry, track one another well over temperature extremes. Second, note as in the first biasing example, that resistance Ree exceeds the
value of the collector load resistance, thereby limiting the available voltage gain in the absence of additional design heroics applied to the circuit
at hand.
3.4.2.4. N-Stage Current Mirror
The satisfactory performance of many analog networks relies on the reliable and
predictable implementation of several current sources (or sinks) that act as high impedance active loads for amplifier cells or provide static paths to ground for currents used in the biasing of
other subcircuits deployed in these networks. Rather than implement this multiplicity of current
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sinks individually, it is expedient to derive them from a single reference cell. To this end, a common embodiment is the network shown in Figure (3.38). The reference circuit is comprised of
the resistance, R, and the diode-connected device, transistor Q0, whose emitter current is Io. The
collectors of identical transistors Q1, Q2, · · · QN establish the requisite current sinking paths,
where the base-emitter junction injection area of the kth transistor is k-times that of the reference
device, Q0. Assuming that the transistors are otherwise identical, the obvious equivalence of
base-emitter terminal voltages among the (N+1) cascaded transistors in Figure (3.38) implies in
general that the emitter current flowing in the kth transistor is kIo. This current supports
corresponding collector and base currents of αFEkIo and αFEkIo/(hFE+1) = (1−αFE)kIo, where
parameter αFE is related to the DC beta, hFE, by (3-48). The last statement requires that each
transistor operate in its forward active regime, which constrains the collector-emitter voltage, Vk,
implicit to the kth transistor to be at least as large as the base-emitter terminal potential, Vbe, observed for all transistors. The tacit assumption of equal hFE among all transistors stems from the
area scaling invoked and the presumption that either the forward Early voltages are large and/or
that no significant differences prevail among the individual collector-emitter voltages.
The reference current, Ir, conducted by resistance R in the circuit of Figure (3.38) must
be large enough to accommodate the emitter current, Io, flowing in reference transistor Q0 and
each of the base currents conducted by transistors Q1 through QN. Thus,
+Vcc
V1
R
V2
Rx1
Ir
Rx2
αFEk1I o
Q1
VN
RxN
αFEk2I o
αFEkNIo
Q2
QN
Q0
x k1
Io
k1Io
x k2
x kN
k2Io
kNIo
Figure (3.38). An N-stage current mirror. All transistors are fundamentally identical,
save for the fact that the kth transistor has a base-emitter junction injection
area that is k-times larger than that of the diode-connected transistor, Q0.
I r = I o + (1 − αFE ) I o
N
∑ ki ,
(3-139)
i =1
which implies that the current, Ick, conducted by the collector of the kth device is
αFE kk (Vcc − Vbe )
αFE kk I r
=
I ck =
.
(3-140)
N
N
⎡
⎤
1 + (1 − αFE ) ki
⎢1 + (1 − αFE ) ki ⎥ R
i =1
i =1 ⎦⎥
⎣⎢
Clearly, the relative insensitivity to the DC beta, hFE, of any collector current flowing in Q1
through QN mandates
∑
N
∑ ki
i =1
<<
∑
1
= ( hFE + 1) ,
1 − αFE
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whose satisfaction is progressively more challenging if one or more of the area scaling factors is
large and/or the number of current sinking stages is large.
In addition to compromising collector current sensitivity to hFE, large area scaling factors also limit the small signal collector output resistance, Rxk, achievable in the kth current stage.
It should be clear that if the kth transistor in Figure (3.38) is replaced by its low frequency, small
signal BJT equivalent circuit, Rxk, as indicated in the subject diagram, is merely the Early resistance, rok, of the kth device. Ignoring internal collector and emitter series resistances, a reference
to (3-56) spawns, in terms of the forward Early voltage, Vaf,
Vk + Vaf
Vk + Vaf
⎡
⎤
Rxk ≈ rok ≈
≈ ⎢
(3-142)
⎥R ,
I ck
⎣ αFE kk (Vcc − Vbe ) ⎦
where the validity of (3-141) is presumed. We note in this last expression that the current sink
output resistance is inversely dependent on the area scaling factor for the base-emitter junction of
the kth transistor.
An improved version to the N-stage current mirror, offered in Figure (3.39), addresses
the potential area scaling shortfall to which the circuit in Figure (3-48) succumbs. Transistor Q0
in this revised circuit diagram no longer functions as a diode. Nonetheless, its emitter is still depicted as supporting a static current of Io, as in the original diagram of Figure (3.38). The insertion of transistor QP in the form of the topological interconnection shown in Figure (3.39) forces
its emitter to conduct the sum of the base currents flowing in transistors Q0 through QN, as well
as the current, Ip, conducted by the resistance, Rp. In principle, resistance Rp, is not required.
But without Rp, the emitter of transistor QP necessarily conducts only the small base currents of
transistors Q0 through QN, thereby risking a significant reduction in the DC beta of QP. In contrast, if Rp is selected to conduct a current that is nominally equal to the emitter current of transistor Q0, hFE for transistor QP approximates the DC beta of transistor Q0 and hence, the DC beta
values of all other transistors.
+Vcc
V1
R
V2
Rx1
αFEk1I o
Ir
QP
Q1
VN
Rx2
RxN
αFEk2I o
αFEkNIo
Q2
Q0
QN
Rp
Io
x k1
x k2
k1Io
x kN
kNIo
k2Io
Ip
Figure (3.39). An improved version of the N-stage current mirror of Figure (3.38). The
insertion of transistor QP diminishes the dependence of the kth collector
current on both the number of stages deployed and the area scaling factors
of these individual stages.
An inspection of the circuit in Figure (3.39) reveals
N
⎡
⎤
I r = αFE I o + ( 1 − αFE ) ⎢ I p + ( 1 − αFE ) I o + (1 − αFE ) I o ki ⎥ .
⎢⎣
i =1 ⎥⎦
∑
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In addition to ensuring nominally identical hFE values among all devices, it is analytically
convenient to set Ip = Io. In this case,
N
⎞
2 ⎛
(3-144)
I r = I o + ( 1 − αFE ) I o ⎜ 1 +
ki ⎟ ,
⎜
⎟
i =1 ⎠
⎝
which implies that the current flowing through resistance R in Figure (3.39) is essentially
invulnerable to the number of current sink stages and the area scaling factors invoked in the circuit architecture. This observation contrasts sharply with (3-139), which depicts current Ir in the
diagram of Figure (3.38) as potentially sensitive to relevant loading effects. It is additionally
interesting to note that the subject current is nominally equivalent to the emitter current conducted by transistor Q0. Since Ir ≈ Io, the collector current of the kth transistor is
α k (V − 2Vbe )
I ck ≈ αFE kk I o ≈ FE k cc
.
(3-145)
R
The result at hand suggests that the price paid for the incorporation of transistor QP into the cascaded current mirror is a doubling of the temperature sensitivity in that current Io is now
functionally dependent on twice the base-emitter junction potential, as opposed to the single Vbe
dependence projected by (3-140).
∑
3.4.2.5. Wilson Current Mirror
The Wilson current mirror mitigates the port impedance limitations pervasive of the Nstage mirror considered in the preceding subsection by exploiting shunt-series feedback to boost
the available impedance level above the Early resistance of the output port transistor[8]. Its basic
schematic diagram is given in Figure (3.40). In this diagram, the grounded emitter transistor,
Q2, and the diode-connected device, transistor Q3, implement feedback that is in shunt with the
base terminal of output transistor Q1 and in series with the Q1 emitter lead. The three transistors
are similar, but transistors Q1 and Q3 have a base-emitter junction injection area that is k-times
larger than the corresponding injection area of transistor Q2. Accordingly, we can presume that
the DC beta values and applied base-emitter terminal voltages of all active devices are nominally
the same, especially if each transistor exudes large forward Early voltages. All devices operate
in their forward active regimes. In the case of transistor Q1, such operation requires that the output port voltage, V1, be at least as large as 2Vbe, while for transistor Q2, the reference current, Ir,
flowing into the junction of resistance R with the base of Q1 and the collector of Q2 satisfies
V − 2Vbe
I r = cc
.
(3-146)
R
If the emitter of transistor Q2 conducts a current of I2, as shown in Figure (3.40), the
emitter of transistor Q3 necessarily conducts kI2 since the base-emitter terminal voltages of these
two devices are the same. Accordingly, the collector of Q2 conducts αFEI2, while a current of (1
−αFE)I2 flows into the base of Q2. In order to keep Kirchhoff happy, the emitter of transistor Q1
supports a current, Ie1, of
(3-147)
I e1 = kI 2 + (1 − αFE ) I 2 ,
whence an output port current, I1, flowing into the collector of transistor Q1 of
1 − αFE ⎞
⎛
I1 = αFE kI 2 ⎜ 1 +
⎟.
k
⎝
⎠
It follows that the base current, Ib1, pertinent to transistor Q1 is
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I1
1 − αFE ⎞
⎛
= ( 1 − αFE ) kI 2 ⎜ 1 +
⎟,
hFE
k
⎝
⎠
(3-149)
V1
+Vcc
Rx
R
Ir
I1
Ib1
Q1
xk
αFE I2
(1−αFE )I2
Ie1
Q2
x1
Q3
xk
I2
kI2
Figure (3.40). Basic schematic diagram of the Wilson current mirror.
which produces a resistance current, Ir, of
⎡
⎛ k ⎞⎛
1 − αFE ⎞ ⎤
I r = I b1 + αFE I 2 = αFE I 2 ⎢1 + ⎜
(3-150)
⎟⎜ 1 +
⎟⎥ .
h
k
⎝
⎠
⎝ FE ⎠
⎣
⎦
Observe that for large hFE, the output current mirrors, by a factor of k, the current conducted by
resistance R, which in turn closely approximates the collector current conducted by transistor Q2.
Specifically, (3-148), (3-150), and (3-146) combine to deliver
k (Vcc − 2Vbe )
I1 ≈ αFE kI 2 ≈ kI r =
.
(3-151)
R
Recalling that Vbe decreases with junction temperature Tj in accordance with the empiricism,
ΔVbe ≈ −SbeΔTj, the temperature-induced perturbation, ΔI1, in current I1 derives as
2k Sbe
2I1Sbe
ΔI1
≈
=
,
(3-152)
ΔT j
R
Vcc − 2Vbe
which in turn stipulates the temperature-induced per-unit change in current I1 as
2Sbe ΔT j
2ΔVbe
ΔI1
≈
= −
.
(3-153)
I1
Vcc − 2Vbe
Vcc − 2Vbe
As is generally the prerequisite implicit to a design scenario premised on a high degree of
temperature stability, an appropriately large supply voltage (Vcc in this case) is recommended.
Figure (3.41a) depicts the approximate low frequency, small signal model pertinent to
an examination of the output resistance that we highlight as Rx. In this equivalent circuit, resistance Rd3 derives from (3-117) in that it represents the small signal terminal resistance of diodeconnected transistor Q3. The circuit analysis, which is sufficiently sloppy to warrant the company of a large glass of a nice merlot, can more easily be interpreted if the given junction injection ratios are judiciously exploited. To this end, assume that all transistors are characterized by
reasonably large forward knee and Early voltages. Then, since Q1 and Q3 conduct roughly the
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same collector current, their base, base-emitter diffusion, and Early resistances are nominally the
same; that is
rbb1 ≈ rbb3 rbb
rπ1 ≈ rπ3 rπ
ro1 ≈ ro3 ro
.
(3-154)
In view of the fact that the small signal beta of each device is the product of forward
transconductance, which nominally varies directly with quiescent collector current, and baseemitter diffusion resistance, which varies as an inverse function of collector current,
βac1 ≈ βac2 ≈ βac3 βac .
(3-155)
From (3-117),
⎛ r + rπ3 ⎞
⎛ rbb + rπ ⎞
rbb + rπ
Rd 3 = ro3 ⎜ bb3
.
(3-156)
⎟ ≈ ro ⎜
⎟ ≈
βac + 1
⎝ βac3 + 1 ⎠
⎝ βac + 1 ⎠
Since the base-emitter geometry of transistor Q2 is smaller than that of either Q1 or Q3 by a factor of k and since this device conducts a current that is correspondingly k-times smaller than the
current supported by transistors Q1 and Q3,
rbb2 ≈ krbb3 = k rbb
(3-157)
rπ2 ≈ krπ3 = k rπ
.
ro2 ≈ kro3 = k ro
The immediate modeling ramifications of (3-154) through (3-157) is the equivalent circuit offered in Figure (3.41b). In this diagram, resistance Rss is given by
(3-158)
Rss ( kro ) R ,
which invariably is adequately approximated by merely the circuit resistance, R.
A conventional analysis of the circuit in Figure (3.41b) generates the following equilibrium equations:
Rd3 I x + Rd3 I a = ⎡⎣ k ( rbb + rπ ) + Rd3 ⎤⎦ I b
Rss ( I a + βac I b ) + ( rbb + rπ ) I a + k ( rbb + rπ ) I b = 0
.
(3-159)
Vx = ro ( I x − βac I a ) + k ( rbb + rπ ) I b
Unfortunately, these equations must be solved simultaneously to arrive at the desired expression
for the resistance, Rx = Vx/Ix, of interest. A second glass of the aforementioned merlot mitigates
the inclination toward profanity and results in
⎡
⎤
⎛r +r ⎞
αac βac Rss + k ⎜ bb π ⎟
⎢
⎥
βac + 1 ⎠
Vx
⎝
⎢
⎥r
Rx =
= 1+
o
⎢
Ix
⎛ rbb + rπ ⎞ ⎥
k
1
R
1
k
β
2
+
+
+
+
⎡
⎤
(
)
(
)
⎢
ss
ac
⎣
⎦⎜ β + 1 ⎟⎥
⎢⎣
⎝ ac
⎠ ⎥⎦
(3-160)
⎡
⎤
⎛ rbb + rπ ⎞
k ( Rss + rbb + rπ ) ⎜
⎢
⎥
⎟
βac + 1 ⎠
⎝
⎢
⎥,
+
⎢
⎛ rbb + rπ ⎞ ⎥
⎢ ( k + 1) Rss + ⎡⎣1 + k ( βac + 2 ) ⎤⎦ ⎜
⎟⎥
⎢⎣
⎝ βac + 1 ⎠ ⎥⎦
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Rx
rbb1
Vx
rπ1
Ia
rbb2
Ia+βac2 Ib
ro2
R
βac2 Ib
rπ2
βac1 Ia
ro1
Ix−βac1 Ia
Ix+Ia
Ix
Rd3
Ix+Ia−Ib
Ib
(a).
Rx
rbb
Vx
rπ
Ia
krbb
Ia+βac Ib
Rss
β ac Ib
krπ
βac Ia
ro
Ix−βac Ia
Ix+Ia
Ix
Rd3
Ix+Ia−Ib
Ib
(b).
Figure (3.41). (a). Low frequency, small signal equivalent circuit of the Wilson current mirror shown in Figure (3.40). The small signal output resistance,
Rx, is the voltage to current ratio, Vx/Ix. (b). The model of (a) redrawn
to account explicitly for the fact that the base-emitter junction injection
areas of transistors Q1 and Q3 in Figure (3.40) are a factor of k larger
than the junction injection area of transistor Q2.
where (3-156) is used and
βac
αac =
.
(3-161)
βac + 1
For large AC beta and the invariably large Early resistance of a bipolar junction transistor, the
formidable form of the resistance expression in (3-160) collapses to
⎡
⎤
βac Rss
Rx ≈ ⎢1 +
(3-162)
⎥ ro ,
+
+
+
k
1
R
k
r
r
(
)
(
)
ss
bb
π ⎦
⎣
which can be substantially larger than the Early resistance, ro.
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EXAMPLE #3.9:
The SPICE parameters of the silicon technology transistors utilized in the Wilson current mirror of Figure (3.40) are itemized in Table (3.1). Design the circuit so that the
current, I1, conducted by transistor Q1 is 4 mA at room temperature. Assuming a baseemitter voltage temperature sensitivity of Sbe = 2 mV/°C, this current is to be sustained
to within ±5% up to operating temperatures of 75 °C. Use the HSPICE BJT model
parameters in Table (3.1) to simulate the finalized design at 27°C, 50 °C, and 75 °C.
Additionally, simulate the room temperature frequency response of the output impedance presented at the collector of Q1.
SOLUTION #3.9:
+6 V
2V
Zx
4.2 KΩ
4 mA
Q1
1.45 V
x4
Q2
727 mV
x1
Q3
x4
Figure (3.42). Schematic portrayal of the Wilson circuit designed in
Example #3.9. The voltages shown in the boxes correspond to the estimated respective node voltages for a
properly functioning circuit. The indicated 4 mA
collector current of transistor Q1 is a design target.
(1).
Given that silicon transistors are deployed in the subject Wilson mirror, there is nothing
immoral about presuming that the base-emitter terminal potentials of all active devices are
nominally 700 mV. But a slightly more satisfying approach entails deducing these potentials
by using the values of saturation current Is, junction injection coefficient nf, and forward
knee current Ikf given in Table (3.1). To this end, Ikf = 11.5 mA yields a forward transport
current, Icc, in (E3-1) of 1.342 mA for a collector current of 1 mA. Then, with Icc = 1.342
mA, Is = AeJs = 3.2 fA and nf = 1.05. Additionally, the approximate room temperature value
of base-emitter terminal potential, Vbe, derives from (3-5) as Vbe ≈ 727.1 mV. It follows that
voltage V1 must satisfy V1 ≥ 2Vbe = 1.454 V.
(2).
In an attempt to conserve standby power, let transistor Q2 conduct one-fourth the current
flowing in both transistors Q1 and Q3, which effectively stipulates a requisite junction injection area ratio of k = 4.
(3).
In (3-153), ΔI1/I1 = 0.05, ΔTj = (75 °C − 27 °C) = 48 °C, Sbe = 2 mV/°C, and Vbe = 727.1
mV. Then, since
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2Sbe ΔT j
ΔI1
=
≤ 0.05,
(E9-1)
I1
Vcc − 2Vbe
Vcc ≥ Vbe + (2SbeΔTj /0.05) = 5.294 V. Select Vcc = 6 V to provide at least token design headroom to compensate for parametric uncertainties and analytical approximations.
(4).
For a reference current, Ir, of about 1 mA, (3-151) produces R = 4.546 KΩ. Once again, a
consideration of design-oriented uncertainties motivates the selection of resistance R as R =
4.3 KΩ.
(5).
Figure (3.42) is the schematic diagram of the completed design, where V1 has been selected
as 2 V to satisfy the requirement of V1 ≥ 1.454 V. As usual, estimated static node voltages
are provided in the diagram.
COMMENTS: As in previous examples, the simulated results confirm the propriety of the
design methodology. In particular, the simulated quiescent collector current, I1, of transistor Q1 at 27 °C is 4.008 mA, at 50 °C, the simulated Qpoint current is 4.075 mA, and at 75 °C, the simulated value of I1 is 4.149
mA. Thus, the largest temperature-induced change in current I1,
which not surprisingly is observed at 75 °C, is only 3.52% larger (well
within the target 5% deviation target) than the subject current value
at room temperature.
The simulated output impedance magnitude is displayed in Figure (3.43).
At the quiescent operating point established by Vcc = 6 volts and V1 = 2
volts, SPICE discloses the operating point parametric detail itemized below. Several noteworthy observations surface from this itemization and
the subject frequency response plot.
MODEL
IB
IC
VBE
VBC
VCE
BETADC
GM
RPI
RX
RMU
RO
CPI
CMU
CBX
CCS
BETAAC
FT
Q1
NT
3.5627E-05
4.0080E-03
0.7245
-0.5505
1.2750
112.5001
1.3667E-01
7.6227E+02
6.7224E+01
1.1718E+12
7.6179E+03
6.1650E-13
3.6996E-15
0.0000E+00
2.0741E-14
1.0418E+02
3.5071E+10
Q3
NT
3.6239E-05
3.9984E-03
0.7250
0.0000
0.7250
110.3338
1.3619E-01
7.4940E+02
6.7220E+01
6.0739E+11
7.4986E+03
6.1446E-13
4.4335E-15
0.0000E+00
2.8694E-14
1.0206E+02
3.5022E+10
Q2
NT
9.0492E-06
1.0226E-03
0.7250
-0.7245
1.4495
113.0081
3.4835E-02
3.0011E+03
2.6888E+02
1.1946E+12
3.0027E+04
1.5701E-13
8.8742E-16
0.0000E+00
5.8204E-15
1.0454E+02
3.5113E+10
(a). The low frequency value of the simulated magnitude of the output
impedance is 144.85 KΩ, which is almost 19-times larger than the
simulated value of the Early resistance (shown above as R0 = 7.6179
KΩ) for transistor Q1. Accordingly, our prediction of an output resistance that is substantially larger than the Early resistance is apparently
appropriate.
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BJT Models & Biasing
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(b). Despite the fact that SPICE predicts a unity current gain frequency
(FT) of about 35 GHz for all three transistors, the 144.85 KΩ resistance level attenuates by a factor of root two at about 29 MHz. This
observation corroborates with earlier disclosures to the effect that
there is depressingly little correlation between fT and achievable frequency domain performance in most bipolar circuits.
(c). As presumed in the course of the analysis of the Wilson mirror, the
DC beta (BETADC) and the AC beta (BETAAC) are approximately the
same for all transistors. Recall that the smallest geometry transistor,
which carries a collector current that is 4-times smaller than the other
two devices is Q3. Note that the values of rπ (RPI), ro, and rbb (RX) for
transistor Q3 are nominally 4-times larger than the corresponding
parameters for transistors Q1 and Q2. On the other hand, Cπ (CPI) for
the higher current transistors is roughly 4-times the Cπ value of Q3,
which is as expected owing to the almost direct dependence of baseemitter diffusion capacitance on quiescent collector current. In contrast, the base-collector transition capacitances, Cμ (CMU) are relatively independent of current level, as expected, but they do scale with
junction area. A similar statement prevails for the substrate capacitances (CCS), which dominantly limit the attainable frequency response
of impedance Zx. Recall that substrate capacitances do not factor into
the enumeration of the unity gain frequency, fT, of the transistors.
Magnitude Of Output Impedance, Zx, (KΩ)
160
120
80
40
0
1
10
100
1000
Signal Frequency (MHz)
Figure (3.43). Simulated frequency response of the magnitude of the output impedance, Zx,
for the Wilson current mirror in Figure (3.42).
3.4.2.6. Supply-Independent Biasing
Each of the biasing networks presented thus far is capable of mitigating the deleterious
effects of junction temperature rises. Unfortunately, however, all deliver quiescent current reMing Hsieh Department of Electrical Engineering
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sponses that are sensitive functions of the applied supply voltage. As a result, fluctuations in the
supply voltage, such as those incurred by aging batteries or the interaction of nonzero Thévenin
supply resistances with large transient fluctuations in the currents delivered by these supplies,
translate directly to a corresponding perturbation in quiescent collector currents. In applications
where these voltage-induced current fluctuations are intolerable, biasing networks that deliver
reduced sensitivity to supply line variations are required.
One of the numerous examples of networks delivering biasing currents that are nominally independent of supply line voltages is the configuration offered in Figure (3.44). NPN
transistors Q1 and Q2 are identical, save for the fact that the base-emitter junction injection area
of Q2 is kn-times larger than that of Q1. If a quiescent current, IQ, is presumed to flow in the
emitter of transistor Q2, nominally the same current is conducted by the emitter of the PNP diode-connected transistor, Q3. This statement assumes that all devices have large DC beta (which
permits the tacit neglect of all transistor base currents), large forward knee current, and large forward Early voltage. Since transistors Q3 and Q4 have identical injection areas and utilize identical emitter degeneration resistances, Ree, current IQ in Q3 is mirrored in the emitter of transistor
Q4 and hence, in the emitter of transistor Q1. With the help of the Ebers-Moll model, it follows
that
+Vcc
Ree
Ree
Ree /kp
Q3
Q4
x1
Q1
x1
Q5
x1
x kp
Q2
Vo
x kn
R
IQ
IQ
Rx
Rl
Io
Figure (3.44). Schematic diagram of a biasing network delivering
quiescent currents IQ and Io that are, to first order,
independent of the applied supply voltage, Vcc.
V
n V
V
n V
IQ = I s ⎡ e be1 f T − 1⎤ = kn I s ⎡ e be2 f T − 1⎤ .
(3-163)
⎢⎣
⎥⎦
⎢⎣
⎥⎦
Upon neglecting the unity terms within the bracketed quantities, this relationship produces
Vbe1 − Vbe2 ≈ n f VT ln ( kn ) .
(3-164)
By using the Q3-Q4-Ree mirror to force equality between the emitter currents of transistors Q1
and Q2, the difference in base-emitter junction injection areas of Q1 and Q2 fosters an offset between the corresponding base-emitter terminal voltages, Vbe1 and Vbe2. This nonzero offset is
crucial in that it establishes a nominal independence of current IQ on the supply line voltage, Vcc.
In particular,
(3-165)
Vbe1 = Vbe2 + RI Q ,
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whence, by (3-164),
n f VT ln ( kn )
V − Vbe2
≈
IQ = be1
,
R
R
which is independent of voltage Vcc.
J. Choma
(3-166)
Before celebrating the supply-independent result of (3-166), at least five important
engineering points warrant careful engineering consideration. First, (3-163) and the current
mirroring action between transistors Q3 and Q4 requires that transistors Q4 and Q2 function in
their forward active regimes. Such operation for transistor Q4 requires Vec4 ≥ Veb4, where Vec4
and Veb4 respectively denote the emitter to collector and the emitter to base voltages developed
on Q4. In turn, Vec4 ≥ Veb4 demands a supply voltage that is large enough to satisfy,
(3-167)
Vcc ≥ Ree IQ + Vbe1 + Veb4 .
Assuming both Vbe1 and Veb4 are of the order of 700 mV, we see that Vcc in excess of approximately 1.4 volts is compulsory if the desired operation of the circuit is to be sustained. For
transistor Q2, linear domain operation mandates
Vce2 = Vcc − Veb3 − ( Ree + R ) IQ ≥ Vbe2 ,
(3-168)
which in turn commands
Vcc ≥ Ree IQ + Vbe2 + Veb3 + n f VT ln ( kn )
(3-169)
You are encouraged to verify that the satisfaction of (3-169) guarantees the satisfaction of (3167).
The second important point relevant to (3-166) is that while the indicated current is
ostensibly independent of Vcc, subject to the constraint imposed by (3-169), it is variant with
temperature. In fact, IQ in (3-166) is PTAT in that Boltzmann voltage VT is directly proportional
to absolute junction temperature. But the subject temperature dependence is not entirely bad
news in that the forward transconductance of transistor Q2 (and indeed Q1, Q3, and Q4, as well)
is rendered relatively insensitive to temperature. In particular, (3-54) confirms that the forward
transconductance is inversely dependent on the effective Boltzmann voltage, nfVT. To wit, if the
effects of knee current and Early voltage can be ignored (as we have done at the outset of this
study), (3-54) suggests
IQ
ln ( kn )
(3-170)
g m2 = g m1 = g m3 = g m4 ≈
≈
.
n f VT
R
This disclosure is notable because if the circuit at hand is operated as an amplifier, the gain and
particularly the open loop gain in a feedback configuration, which is often proportional to forward transconductance, is rendered temperature stable.
The third noteworthy point is that the current conducted by transistor Q5, whose baseemitter junction injection area is kp-times that of transistors Q3 and Q4, is, like current IQ, nominally invariant with supply voltage. This contention follows from the fact that the emitter
degeneration resistance of transistor Q5 is a factor of kp smaller than that of Q3, which implies
k p n f VT ln ( kn )
I o = k p IQ =
,
(3-171)
R
since
⎛R ⎞
Ree IQ + Veb = ⎜ ee ⎟ I o + Veb .
(3-172)
⎜ kp ⎟
⎝
⎠
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If transistor Q5 operates in its linear regime where Vec5 ≥ Veb5, its transconductance is
k p IQ
k p ln ( kn )
Io
gm5 ≈
=
≈
,
n f VT
n f VT
R
(3-173)
which, like the transconductances of the other transistors in the subject network, is essentially
independent of junction operating temperature. In practice, the area ratio, kp, should be kept under two or three in that large kp sustains proportionately larger collector current in Q5. In turn,
large current levels in Q5 diminish its Early resistance, which compromises the attainable output
resistance, Rx, of the current source.
The fourth noteworthy point is that resistance Ree can be set to zero without affecting
the current solution in (3-166). In fact, it is desirable to set Ree to zero in some low voltage
applications, since zero emitter degeneration in the PNP devices in Figure (3.44) lowers the
requisite minimum supply voltage, Vcc, in (3-169). It is included herewith to increase the output
resistance, Rx, so that the Q5-Ree/kp subcircuit emulates a current source whose output current is
rendered progressively more independent of supply voltage.
The final, and arguably most important, point to be offered is that while (3-166) defines
the desired current solution for the biasing network in Figure (3.44), it is unfortunately not the
only solution. In particular, Vbe1 = Vbe2 = 0 sets IQ = 0 as a plausible current solution. In other
words, it is possible that at power supply turn on, transistors Q1 and Q2, and thus all other
transistors in the network, lock to a nonconductive state. Slight parametric differences among
the current mirroring devices are likely to preclude this obviously undesirable null state, but
given the luck of the traditional circuit design engineer, gambling that the desired solution voiced
by (3-166) is realized is imprudent. Accordingly, a startup circuit −preferably a subcircuit that
consumes no or negligible steady state power− is a worthwhile investment in design time and
chip area.
To the foregoing end, a relatively simple startup addendum to the network of Figure
(3.44) is submitted in Figure (3.45). The startup cell comprised of capacitance C and transistors
Q6 and Q7 conduct current only under circuit startup conditions. Startup in the present sense
corresponds to closure of switch SW. If switch closure occurs at time t = 0, the indicated line
voltage, Vp(t), approximates an ideal voltage step; that is Vp(t) = Vccu(t). Assuming capacitance
C is initially uncharged, the idealized instantaneous jump in the power line voltage, Vp(t), is
transmitted instantly to the base-emitter terminals of transistor Q7. With the base-emitter junction of Q7 strongly forward biased, a potentially large collector current is allowed to flow
through Q7, where we understand that this current can derive only from transistor Q3. The current conducted by Q3 is mirrored to transistor Q4. In response to this mirroring action, the current forced through transistor Q1 by Q4 is accompanied by an increase in base-emitter terminal
voltage Vbe1 from its zero value that prevails prior to switch closure. Note, however, that voltage
Vbe2 remains nominally zero as Vbe1 commences its increase. This contention derives from the
fact that the large forward bias imposed across the base-emitter junction of Q7 immediately after
switch closure forces the current conducted by Q3 to flow through Q7. In effect, Q7 bypasses
the Q2-R subcircuit in the immediate neighborhood of time t = 0. But as voltage Vbe1 increases,
transistor Q6 ultimately starts to conduct. Its collector current can be supplied only by the
capacitive branch of the startup cell. This branch continues to supply current until capacitor C is
fully charged, which occurs when the indicated capacitor voltage, Vc, is Vcc. As Vc approaches
Vcc to within a base-emitter junction threshold, or turn on, voltage, the base-emitter voltage of
transistor Q7 drops below threshold potential, whereupon transistor Q7 enters its cutoff regime.
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With C almost fully charged, Q6, like Q7, is starved of current, and the startup cell is effectively
disconnected from the rest of the circuit. As such, the biasing network achieves steady state in
that the current induced to flow in Q3 necessarily flows through Q2, as presumed in the analysis
leading to (3-166).
Vp(t)
Ree
Ree
t=
Ree /kp
SW
+
Q3
Q4
x1
Vcc
Q5
Vc
+
−
x1
C
0
−
x kp
Q7
x kc
Q1
x1
x kc
Startup Cell
Q6
Rx
Q2
Vo
x kn
R
IQ
IQ
Rl
Io
Figure (3.45). The supply-independent biasing network of Figure (3.44) with a startup cell
incorporated to preclude a null current solution at network startup.
EXAMPLE #3.10:
Design the supply-independent biasing network of Figure (3.45) so that at room
temperature operating conditions, current IQ is nominally 1 mA and current Io is nominally 2 mA for supply voltages, Vcc, in the range of 1.8 volts to 6 volts. Verify the design through SPICE simulation. Specifically, simulate the static describing functions
from Vcc to both IQ and Io at operating temperatures of 27 °C, 50 °C, and 75 °C.
Additionally, simulate the time domain responses of currents IQ and Io to a 6 volt battery
switched into the circuit at time t = 0 with a 500 nSEC rise time. The HSPICE parameters for the NPN devices appear in Table (3.1), while Table (3.2) lists the parameters for
PNP transistors that are reasonably complementary to the NPN units.
SOLUTION #3.10:
(1).
Current IQ is nonzero if and only if transistors Q1 and Q2 possess differences in their baseemitter junction injection areas. Arbitrarily choose kn = 10, meaning that the base-emitter
junction area of transistor Q2 is ten-fold that of Q1. There is little point in making kn much
larger than ten or so since IQ in (3-166) is seen as dependent, not on kn, but on the natural
logarithm of kn. From Table (3.1) the junction injection coefficient, nf, of all NPN devices is
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seen to be nf = 1.05. Thus, with a junction temperature of Tj = 27 °C = 300 °K, nf = 1.05, kn
=10, and IQ = 1 mA, resistance R in the network of Figure (3.45) derives from (3-166) as
n f VT ln ( kn )
= 62.6 Ω .
R =
(E10-1)
IQ
In view of the empirical nature of parameter nf, the unavoidable uncertainties associated with
the internal junction temperature, and the relatively small size of the requisite circuit resistance, we should allow for trimming resistance R to the precise value that yields the target IQ
= 1 mA current.
(2).
The next step in the design scenario determines the appropriate emitter degeneration resistance, Ree, commensurate with satisfactory circuit operation at Vcc =1.8 volts. Equation (3169) is the applicable relationship, but prior to its use, the emitter-base voltage, Veb3, for
SPICE
TEXT
SYMBOL SYMBOL
BF
βf
DESCRIPTION
OF PARAMETER
VALUE
UNITS
Forward Short Circuit Gain
100
amps/amp
BR
βr
Reverse Short Circuit Gain
1.3
amps/amp
CJC
CJE
CJS
IKF
IRB
IS
MJC
MJE
MJS
NF
NR
RB
Cjco
Cjeo
Cso
Ikf
Irb
Is
mc
mje
ms
nf
nr
rbb
Zero Bias B-C Depletion Capacitance
fF
fF
fF
mA
mA
fA
–
–
–
–
–
Zero Bias Base Resistance
2.4
4.7
12.2
9.4
3.3
4.3
0.333
0.5
0.5
1.02
1.0
310
RBM
Rbm
Minimum Base Resistance
43
Ω
RC
rc
Series Collector Resistance
22
Ω
RE
re
Series Emitter Resistance
1.7
TF
τfo
Zero Bias Minority Carrier Transit Time
6.2
Ω
pSEC
TNOM
Tj
Junction Reference Temperature
27
VAF
VJC
VJE
VJS
XTI
XTF
XTB
Vaf
Vjc
Vje
Vjs
Forward Early Voltage
24
780
920
690
3
0.025
0.03
Zero Bias B-E Depletion Capacitance
Zero Bias Substrate Depletion Capacitance
Forward Knee Current
Base Resistance Corner Current
Saturation Current
B-C Junction Grading Coefficient
B-E Junction Grading Coefficient
Substrate Junction Grading Coefficient
B-E Junction Injection Coefficient
B-C Junction Injection Coefficient
B-C Junction Built-In Potential
B-E Junction Built-In Potential
Substrate-Collector Built-In Potential
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Temperature Exponent For IS
Temperature Exponent For TF
Temperature Exponent For BF
- 433 -
Ω
°C
volts
mvolts
mvolts
mvolts
−
−
−
USC Viterbi School of Engineering
Lecture Supplement #05
BJT Models & Biasing
J. Choma
Table (3.2). HSPICE model parameters for a representative PNP bipolar junction transistor. Although the
transistor characterized herewith is fictitious, the parameters are typical of a moderately high
speed BJT.
transistor Q3 and the base-emitter voltage, Vbe2, for transistor Q2 must be estimated. To this
end, precise calculations are not required and therefore, knee currents and Early voltages are
ignored to enable the use of the simple Ebers-Moll relationship for the forward transport current in (3-5) for both NPN and PNP transistors. In particular,
(
Vbe n f VT
I c ≈ I cc = I s e
)
Vbe n f VT
− 1 ≈ I se
,
(E10-2)
which applies to NPN devices with minimal junction injection areas. In the case of PNP
transistors, the only required change entails the replacement of base-emitter voltage Vbe by
emitter-base voltage Veb. For transistor Q2, Table (3.1) gives Is = 3.2 fA and, of course, nf =
1.05. Since Q2 has a ten-fold increase in base-emitter junction area, Is in (E10-2) must be
multiplied by 10. Then with Ic ≈ IQ = 1 mA, Is = (10)(3.2 fA), nf = 1.05, and Tj = 300 °K,
Vbe2 = 656.5 mV. On the other hand, the PNP transistor, Q3, which has minimal junction
area, offers from Table (3.2), Is = 4.3 fA and nf = 1.02. Accordingly, Ic = IQ = 1 mA in (E102) produces Veb3 = 690.8 mV. Recalling (3-169), Vcc ≥ 1.8 volts requires resistance Ree to satisfy
1.8 − Vbe2 − Veb3 − n f VT ln ( kn )
Ree ≤
= 390.1 Ω .
(E10-3)
IQ
Design conservatism on the part of the integrated circuit designer is almost always laudable
and thus, select Ree = 300 Ω.
(3).
If current Io is to be 2 mA, which is twice the value of current IQ, transistor Q5 in Figure
(3.45) should boast twice the base-emitter junction injection area of transistor Q3. Moreover, the desired current mirroring between transistors Q3 and Q5 requires that the emitter
degeneration resistance for Q5 be one-half that of transistor Q3. Note in Figure (3.45) that
the emitter degeneration resistance of Q5 is delineated as Ree/kp, where kp, the junction area
factor of Q5, is kp = 2.
(4).
When the supply line battery switch is closed at time t = 0, capacitor C begins to charge,
such that the indicated capacitor voltage, Vc, ultimately rises to 6 volts. To crude first order,
the rate of capacitor voltage charging matches the slew rate of the supply line, which is 6
volts/500 nSEC = 12 volts/μSEC. The current conducted by capacitance C in the circuit of
Figure (3.45) closely approximates the collector current, say Ic6(t) flowing in transistor Q6.
Accordingly,
dV (t)
ΔVc
(E10-4)
≈ C
≈ C ( 12 volts/μSEC ) .
I c6 (t) ≈ C c
dt
Δt
Most transistors in the subject network conduct steady state currents in the range of 1 mA. In
order to forestall excessive junction heating in the startup cell devices, it is prudent to limit
the maximum current in transistor Q6 to approximately 1 mA, especially if the indicated area
factor, kc, is set to one. With Ic6(t) =1 mA, (E10-4) delivers C = 83.3 pF. Set C = 85 pF,
which requires an off chip realization of this element.
In addition to concerns about junction heating, care must be exercised to preclude voltage
overstress in transistors Q6 and Q7. Specifically, note that if switch SW in Figure (3.45)
were ideal, the entire 6 volts of supply line energy is developed across the base-emitter junction of transistor Q6 immediately after switch closure. Depending on the process actually
adopted for the monolithic realization of the network under consideration, high voltage options may need to be exploited for transistors Q6 and Q7.
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Lecture Supplement #05
(5).
BJT Models & Biasing
J. Choma
The variable awaiting computation is the resistance, Rl, in Figure (3.45). The current, Io,
flowing through resistance Rl is 2IQ, and this same current approximates the emitter current
of transistor Q5. Thus, the emitter-collector voltage, Vec5, supported by transistor Q5 is
Vec5 = Vcc − ( Ree + 2Rl ) IQ .
(E10-5)
In order for Q5 to sustain operation in its forward active domain, Vec5 must be at least as
large as Veb5 even when Vcc lies at its minimum, 1.8-volt level. The Q5 emitter-base voltage,
Veb5, effectively matches Veb3, which has been calculated to be 690.8 mV. It follows that
6V
300
300
5.70 V
5.70 V
Q4
x1
0V
Q6
+
Q5
x1
85
Q7
0
SW
5.70 V
Q3
5.01 V
t=
150
−
x2
6
5.01 V
x1
x1
719 mV
800 mV
x 10
Q1
Q2
Vo
x1
65.0 mV
65
IQ
IQ
400
Io
Figure (3.46). The supply-independent biasing network, complete with
startup compensation, designed in Example #3.10. All
resistances are in units of ohms, the capacitor is in picofarads, and the voltage supply is in units of volts. The indicated node voltage estimates apply in the steady state
subsequent to closure of switch SW.
Rl ≤
Vcc − Ree IQ − Veb5
2IQ
= 404.6 Ω .
(E10-6)
Choose Rl = 400 Ω.
(6).
A schematic diagram of the completed design is shown in Figure (3.46). A first simulation
of the network reveals a simulated current, IQ, which is about 4.8% larger than its target factor. Accordingly, resistance R in Figure (3.45) is increased from its originally computed
62.6 Ω to (1.048)(62.6 Ω) = 65.6 Ω. Subsequent to running a few static simulations to confirm the propriety of relevant design modifications, we converge to R = 65 Ω.
Several SPICE simulations were executed to confirm the propriety of the design submitted
as the schematic diagram in Figure (3.46)
(a). Figure (3.47) displays room temperature, simulated static sweeps of currents IQ and Io
versus the supply line voltage, Vcc. At Vcc = 6 volts, IQ = 1.01 mA, which is a scant 1%
larger than the target design value. Even if Vcc drops from its steady state 6-volt value
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by 75% to 1.5 volts, IQ is maintained at 924.9 μA, which represents a degradation of
only 8.04%. On the other hand, the output current, Io, is 1.97 mA at Vcc = 6 volts and
1.77 mA at Vcc = 1.5 volts, which computes as a 10.12% decrease with respect to the
current value at Vcc = 6 volts.
The observed nonzero slopes in the current curves can largely be attributed to finite
Early voltages. Said slope is more pronounced in the output current characteristic because the Early voltage of the PNP transistor, Q5, is smaller than that of any of the
NPN devices. Below nominally 1.5 volts, transistors that are not connected as diode
elements operate in saturation to produce current characteristics that are strongly sensitive to supply line voltage variations.
2.5
Io
Current (mA)
2.0
1.5
IQ
1.0
0.5
0
0
2
4
6
8
10
Power Supply Voltage, Vcc (volts)
Figure (3.47). Simulated static describing functions for the room temperature currents, IQ
and Io, in the circuit of Figure (3.46).
(b). Figure (3.48) offers the foregoing static sweeps at 50 °C and 75 °C, as well as at 27
°C. Temperature sensitivity is apparent, which is as expected because of the current
solutions in (3-166) and (3-171). In particular, if the junction injection coefficient, nf,
and circuit resistance, R, are temperature invariant, (3-166) and (3-7) deliver
ΔIQ
n f k ln ( kn )
=
= 3.21 μA / °C .
(E10-7)
ΔT j
qR
Equation (3-171) demonstrates that the temperature sensitivity of the output current, Io,
is larger than the foregoing sensitivity by a factor of kp. Thus,
ΔIQ
k p n f k ln ( kn )
ΔI o
= kp
=
= 6.42 μA / °C .
(E10-8)
ΔT j
ΔT j
qR
The increase in the temperature sensitivity of current Io by a factor of kp over the
sensitivity of current IQ rebukes the use of high junction injection area factors in the
PNP units deployed in the circuit at hand. An examination of the data from which Figure (3.48) derive indicates that IQ = 1.006 mA at T = 27 °C, while at 50 °C and 75 °C,
the subject current is 1.086 mA and 1.173 mA, respectively. Comparing the 75 °C
simulated result to its 27 °C counterpart,
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ΔI Q
=
ΔT j
(1.173 − 1.006 ) (10 -3 )
75 − 27
J. Choma
= 3.48 μA / °C ,
(E10-9)
which is 8.4% higher than the computed sensitivity in (E10-7). This error can be
attributed to the temperature dependence of other transistor parameters (such as the
Early voltage), which are tacitly ignored in (3-166). For output current Io, Io = 1.969
mA, 2.125 mA, and 2.295 mA at 27 °C, 50 °C, and 75 °C, respectively. It follows that
2.5
Current (mA)
2.0
Io
1.5
Tj = 75 °C
Tj = 50 °C
Tj = 27 °C
1.0
IQ
0.5
0
0
2
4
6
8
10
Power Supply Voltage, Vcc (volts)
Figure (3.48). Simulated static describing functions at 27 °C, 50 °C, and 75 °C for the
currents, IQ and Io, in the circuit of Figure (3.46).
ΔI o
=
ΔT j
(c).
( 2.295 − 1.969 ) (10 -3 )
75 − 27
= 6.79 μA / °C ,
(E10-10)
which is only 5.8% larger than the calculated temperature sensitivity in (E10-8).
Finally, Figure (3.49) offers the transient responses of currents IQ and Io to switch closure at time t = 0, subject to the condition that the switch in question induces a supply
line voltage rise time of 500 nSEC. Superimposed on this plot are the currents conducted by the startup transistors, Q6 and Q7. The latter curves confirm that the startup
devices are effectively disconnected from the biasing network, well within 1 μSEC of
switch closure, in that the collector currents of these transistors are seen to reduce to
zero. The currents, IQ and Io, are seen to settle to their respective steady state values at
584.75 nSEC. Since the supply line does not reach 6 volts until 500 nSEC, the circuit
can be said to settle within 84.75 nSEC subsequent to the time at which the supply line
is fully charged. Observe a significant amount of peaking in the current outputs, IQ
and Io, while the currents conducted by the startup devices always remain below IQ and
Io.
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Current (mA)
Line Voltage, Vp(t) (volts)
Lecture Supplement #05
BJT Models & Biasing
J. Choma
6
4
2
0
3
Io
2
IQ
1
Ic7
Ic6
0
0
0.2
0.4
0.6
0.8
1.0
1.2
Time (microseconds)
Figure (3.49). Transient current responses to switch closure in the circuit of Figure (3.46).
The current, Ic6, is the collector current conducted by transistor Q6, while Ic7
denotes the collector current of transistor Q7.
COMMENTS: As suggested earlier, the circuit addressed in this example is one of many
whose operation is premised on formulating a subcircuit that establishes
an offset between base-emitter terminal voltages of key transistors. All
are capable of delivering static current responses that, while not strictly
independent of power supply voltage, are significantly desensitized with
respect to supply line voltage variations. Most of these networks are able
to limit current variations about nominal design targets to 5%-10%, despite upwards of 50% degradation in line voltage. The prices paid for
these supply-independent topologies are potentially significant temperature sensitivities, a recurring need for resistor trimming, and the inevitable
requirement of startup cells that preclude null current states. Three additional biasing circuits are reserved for your own edification in Problems
#3.28 through #3.30.
Arguably the best of the supply-independent biasing schemes is the bandgap reference circuit[9].
In addition to offering laudable voltage
desensitization, these schemes also deliver superior performance over
wide extremes of operating temperature[10]. An analytical consideration of
the bandgap reference supply is reserved for a later chapter that addresses
high performance analog CMOS signal processing.
3.5.0. REFERENCES
[1]. J. J. Ebers and J. L. Moll, “Large-Signal Behavior of Junction Transistors,” Proceedings of the
IRE, vol. 42, pp. 1761-1772, Dec. 1954.
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[2]. H. K. Gummel and H. C. Poon, “An Integral Charge-Control Model of Bipolar Transistors,”
Bell System Technical Journal, vol. 49, pp. 115-120, May-June 1970.
[3]. C. T. Kirk, “A Theory of Transistor Cutoff Frequency (fT) at High Current Densities,” IEEE
Transactions on Electron Devices, vol. ED-9, pp. 164-174, Mar. 1962.
[4]. S. Dimitrijev, Understanding Semiconductor Devices. New York: Oxford University Press,
2000, pp. 334-341.
[5]. J. M. Early, “Effects of Space-Charge Layer Widening in Junction Transistors,” Proceedings of
the IRE, vol. 46, pp. 1141-1152, Nov. 1958.
[6]. H. N. Ghosh, “A Distributed Model of the Junction Transistor and its Application in the Prediction of the Emitter-Base Diode Characteristic, Base Impedance, and Pulse Response of the Device,” IEEE Transactions on Electron Devices, vol. ED-12, pp. 513-531, Oct. 1965.
[7]. J. R. Hauser, “The Effects of Distributed Base Potential on Emitter Current Injection Density
and Effective Base Resistance for Stripe Transistor Geometries,” IEEE Transactions on Electron Devices, vol. ED-11, pp. 238-242, May 1965.
[8]. G. R. Wilson, “A Monolithic Junction FET-NPN Operational Amplifier,” IEEE Journal of
Solid-State Circuits, vol. SC-3, pp. 341-348, Dec. 1968.
[9]. P. Brokaw, “A Simple Three-Terminal IC Bandgap Reference,” IEEE Journal of Solid-State
Circuits, vol. SC-9, pp. 388-393, Dec. 1974.
[10]. Y. Tsividis, “Accurate Analysis of Temperature Effects in Ic-Vbe Characteristics with Application to Bandgap Reference Sources,” IEEE Journal of Solid-State Circuits, vol. SC-14, pp. 655657, June 1979.
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EXERCISES
Problem #3.1
Each of three bipolar junction transistor interconnections depicted in Figure (P3.1) is functional as an effective PN junction diode. For each of these connections, derive an expression for the volt-ampere characteristic, Id -versus- Vd, and stipulate the effective saturation
current, say Io, associated with each diode emulation.
Id
−
−
−
+
Id
Vd
Vd
Vd
+
Id
(a).
+
(b).
(c).
Figure (P3.1)
Problem #3.2
In the composite transistor structure of Figure (P3.2), both transistors are identical, and the
indicated supply voltage, Vcc, is large enough to reverse bias the base-collector junctions of
both devices. Moreover, the battery voltage, Vbb, is sufficiently large to forward bias the
base-emitter junctions of both transistors. Use the Ebers-Moll model to derive expressions
for the current ratios, I2/I1, I3/I1, and I4/I1.
I2
+Vcc
I3
I1
+
Vbb
I4
−
Figure (P3.2)
Problem #3.3
Consider a bipolar junction transistor that is operated in such a manner as to ensure a
strongly reverse biased base-collector junction. Using the simple Ebers-Moll model, show
that the base-emitter voltage, Ve, commensurate with zero emitter current is negative and
given by
Ve = − n f VT ln β f + 1 .
(
)
Problem #3.4
A bipolar junction transistor is operated with forward bias applied to its base-emitter junction. Use the simple Ebers-Moll model to show that the resultant collector current to base
current transfer ratio, Ic/Ib, is necessarily smaller than the gain parameter, βf, whenever the
base-collector junction of the subject transistor is forward biased.
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Problem #3.5
Repeat Example #3.3 for the diode interconnections of Figures (3.6b) and (3.6c).
Problem #3.6
Use the Ebers-Moll model of a bipolar junction transistor to show that the ratio, Ibe/Ibc, of
forward to reverse recombination currents can be cast in terms of the BJT emitter and
collector currents, Ie and Ic, respectively, in accordance with
⎛ I e − α r I c ⎞ ⎡ 1 + 1 − α f βr ⎤
I be
⎥.
= ⎜
⎟⎢
⎜ α f I e − I c ⎟ ⎢ 1 + ( 1 − αr ) β f ⎥
I bc
⎝
⎠⎣
⎦
(
)
(a). Explain the engineering significance of a zero value to this ratio when Ie = αrIc.
(b). Explain the engineering significance of an infinite value to this ratio when Ic = αfIe.
Problem #3.7
Repeat Example #3.4 for the case in which the collector-emitter biasing voltage is only one
volt.
Problem #3.8
Repeat Example #3.4 for the stipulated biasing point, but for a transistor having three-times
the base-emitter junction area. Additionally, plot the unity gain frequency, fT, as a function
of the quiescent collector current, IcQ. Evaluate an approximate collector current
commensurate with maximum achievable fT, and compute this maximum unity gain frequency.
Problem #3.9
An occasionally invoked metric for high frequency performance capabilities of transistors is
the transverse cutoff frequency, say fb. This metric is the 3-dB frequency of the small signal, short circuit forward transadmittance, yfe(jω), evidenced in a grounded emitter topology. The “short circuit” refers to a collector-emitter port that supports zero signal. Use the
model in Figure (3.14) to derive analytical expressions for both yfe(jω) and fb. For simplicity, take rc = re = 0 in the BJT model.
Problem #3.10
The BJT in the grounded base amplifier in Figure (P3.10) operates in its forward active regime because of the constant voltage supply, Vcc, and the static current sink, IQ. The input
signal is applied as the current, Is, whose Norton resistance is Rs. The response to this input
current is extracted as the signal component, Ios, of the net current, Io, which flows through
the collector load resistance, Rl. Use the model of Figure (3.14), with resistances rc and re
tacitly ignored, to respond to the following directives.
(a). Evaluate the current transfer function, Ai = Ios/Is, at low signal frequencies. Give an
upper limit to this current gain.
(b). For a sinusoidal input signal, Is, infinitely large Rs and a short circuit load resistance,
Rl, evaluate the current transfer function, Ai = Ios/Is, as a function of frequency ω.
(c). Derive an expression for the 3-dB bandwidth of the current gain determined in Part
(b). Suitable approximations can be invoked as long as these approximations are
clearly rationalized from an engineering perspective.
(d). Compare the gain-bandwidth product of the grounded base amplifier with the short
circuit, unity gain frequency, fT, of the grounded emitter configuration.
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+Vcc
Rl
Io
Is
Rs
IQ
Figure (P3.10)
Problem #3.11
The BJT in the grounded collector amplifier in Figure (P3.11) operates in its forward active
regime because of the constant voltage supplies, Vcc and Vbb. The input signal is applied as
the voltage, Vs, whose Thévenin resistance is Rs. The response to this input signal voltage is
extracted as the signal component, Vos, of the net voltage, Vo, which is established across the
indicated load resistance, Rl. Use the model of Figure (3.14), with resistances rc and re ignored, to respond to the following directives.
+Vcc
Rs
+
Vbb
Vo
−
+
Rl
Vs
−
Figure (P3.11)
(a). Explain why the configuration in Figure (P3.11) is commonly referenced as a
grounded collector amplifier, despite the fact that the collector is not actually
grounded and instead is incident with the positive terminal of a constant voltage
source.
(b). Evaluate the voltage transfer function, Av = Vos/Vs, at low signal frequencies. Give an
upper limit to this voltage gain.
(c). For a sinusoidal input signal, Vs, zero Rs, and an infinitely large load resistance, Rl,
evaluate the voltage transfer function, Av = Vos/Vs, as a function of frequency ω.
(d). Derive an expression for the 3-dB bandwidth of the voltage gain determined in Part
(c). Suitable approximations can be invoked as long as these approximations are
clearly rationalized from an engineering perspective.
(e). Compare the gain-bandwidth product of the grounded collector amplifier with the
short circuit, unity gain frequency, fT, of the grounded emitter configuration.
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Problem #3.12
Develop a design-oriented expression for the quiescent collector current, IcQ, in the PNP
transistor cell of Figure (P3.12). Assess the shortfalls of the biasing configuration.
+Vee
R2
+
VebQ
−
+
VecQ
−
Rl
R1
IcQ
Figure (P3.12)
Problem #3.13
The silicon transistor in the biasing configuration of Figure (P3.13) operates in its linear regime where it has a static beta of hFE, a base-emitter junction temperature coefficient of
−Sbe, and a nominal base-emitter turn on voltage of Vbe.
(a). Derive a general expression for the quiescent collector current, IcQ.
(b). Stipulate the inequality that the circuit must satisfy if current IcQ is to be rendered
nominally insensitive to gain parameter hFE.
(c). Under the condition deduced in Part (b), what is the temperature sensitivity, ΔIcQ/ΔTj,
of the circuit?
(d). What small signal resistance, say Rx, is presented to load resistance Rl at the collector
node of the subject biasing network? Use reasonable approximations to simplify the
expression for this resistance and comment on the ability of the circuit to sustain
nominally constant Q-point collector current in the face of signal changes presented at
the collector node.
+Vcc
Rl
Rx
R1
IcQ
R2
Ree
Figure (P3.13)
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Problem #3.14
Using a 6 volt power supply, design the circuit in Figure (P3.13) for IcQ = 1 mA and VceQ =
1 volt at room temperature. The collector current is to be held constant to within ±2% over
a temperature range extending to 75 °C. Assume that the transistor is identical to that exploited in Example #3.6 and parameterized in Table (3.1). Use HSPICE or similar circuit
simulation software to determine the quiescent collector current at 27 °C, 50 °C, and 75 °C.
Problem #3.15
The silicon transistor in the circuit of Figure (P3.15) operates in its linear regime where it
has a static beta of hFE, a base-emitter junction temperature coefficient of −Seb, and a nominal base-emitter turn on voltage of Veb.
(a). Derive a general expression for the quiescent collector current, IcQ.
(b). Stipulate the inequality that the circuit must satisfy if current IcQ is to be rendered
nominally insensitive to gain parameter hFE.
(c). Under the condition deduced in Part (b), what is the temperature sensitivity, ΔIcQ/ΔTj,
of the circuit?
IcQ
−
Vee
Ree
R1
+
R2
Figure (P3.15)
Problem #3.16
The two identical silicon transistors in the low noise biasing circuit of Figure (P3.16) operate in their linear regimes where they display a static beta of hFE, a base-emitter junction
temperature coefficient of −Sbe, and a nominal base-emitter turn on voltage of Vbe.
(a). Derive general expressions for the quiescent collector currents, IcQ1 and IcQ2, conducted by transistors Q1 and Q2.
(b). Stipulate the inequalities that the circuit must satisfy if the two quiescent collector currents are to be rendered nominally insensitive to gain parameter hFE.
(c). Under the condition deduced in Part (b), what are the temperature sensitivity coefficients, σi1 and σi2, of the two quiescent collector currents?
(d). The circuit exploits feedback, which is implemented by resistance R3 and the inductive
coil. Explain qualitatively the operation of this feedback loop.
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R5
R2
Q2
+Vcc
Q1
R4
R1
R3
Figure (P3.16)
Problem #3.17
The power supply voltage, Vcc, in the biasing network of Figure (P3.17) is 9 volts, and the
two transistors are identical to the devices embraced by Example #3.6 and Table (3.1). Design the circuit so that each bipolar junction transistor conducts a quiescent collector current
of 2 mA ± 5% at a collector-emitter voltage of 1.5 volts over a temperature range extending
from 27 °C to 75 °C. Use HSPICE or equivalent computer-aided analysis software to confirm the propriety of the finalized design at 27 °C, 50 °C, and 75 °C.
+Vcc
R
Rl
Rl
Q1
R
Q2
Rk
Figure (P3.17)
Problem #3.18
Table (3.2) itemizes the HSPICE parameters for a representative, high-speed PNP bipolar
junction transistor. Use this device to address the following directives. Unless specified
otherwise, assume a junction operating temperature of 27 °C.
(a). Set up a computer-aided simulation that sweeps, for an emitter-collector voltage, Vec,
of 1.5 volts, the static collector current as a function of the applied emitter-base voltage, Veb, for 0 ≤ Veb ≤ 800 mV. Plot these curves.
(b). Set up a computer-aided simulation that sweeps, for an emitter-collector voltage, Vec,
of 1.5 volts, the static base current as a function of the applied emitter-base voltage,
Veb, for 0 ≤ Veb ≤ 800 mV. Plot these curves.
(c). Use the plots garnered from the execution of the preceding two parts of this problem
to generate a plot of the DC beta, hFE, as a function of collector current for Vec = 1.5
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volts.
(d). Use the foregoing simulated results to deduce the value of emitter-base junction voltage, Veb, commensurate with a collector current of 2 mA. What is the DC beta of the
transistor at this collector current?
(e). Repeat Part (a) for a junction temperature of 75 °C. Recall that the temperature induced change, ΔVeb, in static emitter-base terminal voltage can be represented as ΔVeb
≈ −SebΔTj, where ΔVeb is the voltage change required to preserve constant collector
current over the temperature excursion, ΔTj, which can be taken as the temperature
difference between 27°C and 75 °C. Deduce the value of coefficient Seb, using the
simulations already executed.
Problem #3.19
The power supply voltage, Vcc, in the biasing network of Figure (P3.19) is 3 volts, and the
two transistors are identical to the device parameterized in Table (3.2). Use the simulation
results garnered in the preceding problem to design the circuit so that transistor Q1 conducts
a quiescent collector current of 2 mA ± 5% at an emitter-collector voltage of 1.5 volts over a
temperature range extending from 27 °C to 75 °C. Use HSPICE or appropriate other computer-aided analysis software to confirm the propriety of the finalized design at 27 °C, 50
°C, and 75 °C.
Q2
Q1
IcQ
R
Rl
−Vcc
Figure (P3.19)
Problem #3.20
Redesign the circuit addressed in Example #3.8 under the constraint that the current conducted by resistance Rx is to be nominally one-fourth of the collector current conducted by
transistor Q2. Submit a finalized schematic diagram, and simulate the design at 27 °C, 50
°C, 75 °C, and 100 °C.
Problem #3.21
Redesign the circuit addressed in Example #3.8 under the constraints that the collector load
resistance imposed on transistor Q1 is at least 5-times larger than the emitter degeneration
resistance, Ree. In this approach, it is likely impossible to achieve equal collector-emitter
voltages between transistors Q1 and Q2. Submit a finalized schematic diagram, and
simulate the design at 27 °C, 50 °C, 75 °C, and 100 °C.
Problem #3.22
Derive a general expression for the static collector current, Ic, conducted by transistor Q2 in
the network of Figure (3.33). Deduce the resultant temperature coefficient of this collector
current.
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Problem #3.23
Using (3-116), develop by inspection an expression for the resistance, Rx, indicated as
presented at the collector terminal of transistor Q1. In comparison with the biasing
configuration shown in Figure (3.29), what is the effectiveness of this circuit to cope with
signal fluctuations at the collector port?
Problem #3.24
In the cascode current mirror shown in Figure (P3.24), all four transistors are identical, save
for the fact that transistors Q3 and Q4 each have base-emitter junction injection areas that
are k-times larger than those of transistors Q1 or Q2. All transistors operate in their forward
active regimes where they support identical base-emitter terminal potentials and identical
values of the DC beta, hFE.
+Vcc
V
R
Rx
Ir
IQ
Q1
Q3
x1
xk
Q2
Q4
x1
xk
Figure (P3.24)
What is the static collector-base operating voltage of transistor Q4?
What is the minimum allowable collector to ground potential, V, of transistor Q3?
Derive the equation that relates current IQ to the current, Ir, conducted by resistance R.
Derive the equation that relates current IQ to the supply voltage, Vcc, the circuit resistance, R, and the base-emitter terminal potential, Vbe, of all transistors.
(e). What condition must be satisfied to render current IQ nominally independent of hFE?
(f). Derive an expression for the temperature sensitivity, ΔIQ/ΔTj, of current IQ. Assume
ΔVbe = −SbeΔTj, where Sbe is an empirical constant and Tj represents junction operating temperature of all devices.
(g). Derive an expression for the indicated small signal resistance, Rx, established at the
collector of transistor Q3. As usual, assume low frequency conditions and ignore the
internal series resistances implicit to the collectors and emitters of all devices. Make
sure to account for the fact that while the current densities of transistors are likely to
be identical, the actual collector currents flowing in all devices are not necessarily the
same.
(a).
(b).
(c).
(d).
Problem #3.25
In the two stage Wilson current sink of Figure (P3.25), the four transistors are identical except for the fact that transistors Q1 and Q2 have twice the base-emitter junction injection
area of transistors Q3 and Q4.
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V3
+Vcc
V4
Rx3
Rx4
R
I3
I4
Q3
Ir
Q4
x1
x1
Q1
x2
Q2
x2
Figure (P3.25)
(a). What are the minimum allowable collector to ground potentials, V3 and V4, of transistors Q3 and Q4, respectively?
(b). Derive the equations that relate currents I3 and I4 to the reference current, Ir, conducted by resistance R.
(c). Derive the equations that relate currents I3 and I4 to the supply voltage, Vcc, the circuit
resistance, R, and the base-emitter terminal potential, Vbe, of all transistors.
(d). What condition must be satisfied to render currents I3 and I4 nominally independent of
hFE?
(e). Derive an expression for the temperature sensitivities, ΔI3/ΔTj and ΔI4/ΔTj, of currents
I3 and I4. Assume ΔVbe = −SbeΔTj, where Sbe is an empirical constant and Tj represents
junction operating temperature of all devices.
(f). Derive expressions for the indicated small signal resistances, Rx3 and Rx4, established
at the collectors of transistors Q3 and Q4. As usual, assume low frequency conditions
and ignore the internal series resistances evidenced in the collector and emitter leads
of all devices. Make sure to account for the fact that while the current densities of all
transistors are likely to be nearly identical, the actual collector currents flowing in all
devices are not necessarily the same.
Problem #3.26
In the Wilson current mirror of Figure (P3.26), the transistors are identical except for the
indicated differences in base-emitter junction injection ratios.
(a). Derive an expression for the low frequency, small signal resistance, Ry, presented to
the junction formed of resistance R, base terminal of transistor Q1, and collector
terminal of Q2. Ignore internal series resistances in the collectors and emitters of all
transistors and additionally, ignore all forward Early resistances. Provide an engineering justification for the tacit neglect of the Early resistance in each transistor.
(b). Reduce the expression gleaned in (a) for the case of very large βac. Discuss the size of
the resultant resistance in terms of the injection area ratio, k.
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V1
+Vcc
Rx
R
I1
Ir
Q1
xk
Ry
Q2
x1
Q3
xk
Figure (P3.26)
Problem #3.27
Using the low frequency, small signal model of a bipolar junction transistor, develop an
analytical expression for the small signal resistance, Rx, in the supply-independent biasing
configuration in Figure (3.45). Ignore the internal collector and emitter resistances of all
transistors. Furthermore, assume that the two startup transistors, Q6 and Q7, are large
geometry devices so that the substrate capacitance of transistor Q6 emulates a short circuit
for the signal frequencies of immediate interest.
Problem #3.28
+Vcc
Rk
Ree
Ree
Ree /kp
Q3
Q4
x1
Q1
x1
Q5
x1
x kp
Q2
Vo
x kn
R
IQ
IQ
Rl
Io
Figure (P3.28)
A clear advantage of the startup cell in the supply-independent biasing scheme of Figure
(3.45) is that it consumes no power in the steady state. A disadvantage is that it utilizes a
capacitor whose required value is generally sufficiently large to preclude its on chip circuit
implementation. The circuit in Figure (P3.28) supplants the subject startup cell with a simple resistance, Rk, which is chosen large enough to ensure that it exerts minimal impact on
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the overall standby power dissipation of the network. Prove that a small current flowing
through resistance Rk prevents a null startup state.
Problem #3.29
The circuit in Figure (P3.29) provides an output current, Io, which is not independent of the
supply voltage, Vcc, but instead, is a function of a natural logarithmic function of Vcc. It
therefore shows a voltage sensitivity that is smaller than the current sensitivities of biasing
networks whose currents of interest are linearly related to the supply line voltage. All three
transistors in the circuit are identical and are characterized by the parameters in Table (3.1).
+Vcc
Io
R1
Rl
Vo
Q1
x1
Q2
x1
R2
Q3
x1
Figure (P3.29)
(a). Assuming large static beta, hFE, in transistor Q1, show that the output current, Io, is
given by
⎛ V − 2Vbe ⎞
V
I o = T ln ⎜ cc
⎟,
R2 ⎝ R1 I s
⎠
where VT is the familiar Boltzmann voltage, and Is is the saturation current of the NPN
transistors. It is to be understood that while Vbe is the base-emitter terminal voltage of
each of the transistors, it can be supplanted by the junction threshold voltage for most
design purposes.
(b). Is current Io PTAT? Explain briefly.
(c). Using a nominal 5-volt supply, design the circuit so that Io = 5 mA at room temperature. Select resistance Rl so that the collector-emitter potential supported by transistor
Q1 is 2Vbe, even if the supply voltage degrades to 2.5 volts.
(d). Use SPICE to simulate the room temperature static describing function, Io versus Vcc,
for the design effected in the preceding part of this problem, over a Vcc range spanning
0 ≤ Vcc ≤ 10 volts. Does the simulated current sensitivity to supply voltage corroborate with theoretical expectations.
(e). Repeat Part (d) for junction operating temperatures of 50 °C and 75 °C. Does the
simulated current dependence on temperature track with analytical expectations? Explain briefly.
Problem #3.30
Figure (P3.30) proposes a supply-independent biasing scheme that can function as either a
current source (via the current, Io1, conducted by PNP transistor Q6) or a current sink (via
the current, Io2, flowing in the collector of NPN transistor Q3) or both, simultaneously.
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Current Io1 derives from current IQ as a result of the current mirror formed of transistors Q5
and Q4, while current Io2 is likewise directly dependent on IQ because of the effective mirror
established by transistors Q1 and Q3. To the extent that the Early voltages of all active devices are large, currents Io1 and Io2 are consequently independent, to first order, of the supply voltage, Vcc. All NPN transistors are identical, save for the indicated junction area factors, and have the parameters itemized in Table (3.1). Similarly, all PNP devices are identical, except for delineated area factors, and have the parameters listed in Table (3.2).
+Vcc
Q5
Q4
x1
Q6
x1
IQ
x kp
IQ
Io1
Vo1
Q2
Vo2
x1
Io2
Q3
Q1
x1
R
x kn
Figure (P3.30)
(a). Assuming all transistor base currents can be ignored and all transistor Early voltages
and knee currents are large, derive expressions for the output currents, Io1 and Io2.
(b). What is the minimum value, say Vmin, of supply voltage Vcc that is commensurate with
the linear active operation of transistors Q1, Q2, Q4, and Q5?
(c). Are null current states at startup an issue? If they are, mitigate the problem with a
suitably connected resistance. Show the modified circuit schematic diagram.
(d). Using a nominal 6-volt supply, design the circuit so that IQ = 1 mA, Io1 = 2 mA, and Io2
= 3 mA at room temperature. Select voltage Vo1 as the maximum voltage permissible
with linear active mode operation of transistor Q6 when Vcc = Vmin. Additionally, select voltage Vo as the minimum voltage that ensures linear active regime operation of
transistor Q3 when Vcc = Vmin.
(e). Use SPICE to simulate the room temperature static describing functions, Io1 versus Vcc
and Io2 versus Vcc, for the design executed in the preceding part of this problem, over a
Vcc range spanning 0 ≤ Vcc ≤ 10 volts. What perturbations in currents Io1 and Io2 are
observed when Vcc degrades by 50%?
(f). Repeat Part (d) for junction operating temperatures of 50 °C and 75 °C. Do the simulated current dependencies on temperature track with analytical expectations? Explain
briefly.
(g). Assuming a startup resistance is required, select its value such that the increased
power dissipation of the entire circuit is less than 2% of the dissipation observed for
the circuit with no startup provision. Simulate the transient responses of currents Io1
and Io2 when Vcc is a 6-volt pulse waveform exuding 500 nSEC rise and fall times.
What is the simulated settling time of the entire circuit?
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