110622 SMT Symp.
M.Niwa
Development of 32nm
CMOS and Recent Trend
for Beyond 32nm
Masaaki NIWA
Univ. of Tsukuba
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110622 SMT Symp.
M.Niwa
Content
●
Develop. of 32nm CMOS
- Gate Stack Process
* Cost effective process
* High-k material and related process issues (WF)
* Gate First vs Gate Last (HK first & HK last)
* Related issues (UT-SiO2 ,,, )
* Summary
●
Beyond 32nm Trend
- 2011 Symp. on VLSI Technology
* VLSI Technology trend
* Key Issues(FINFET, FD-SOI)
* Other related topics
(RTN, 3D-SI, New Ch., TFET, MRAM, BEOL FET,,, )
* Outlook on future
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110622 SMT Symp.
M.Niwa
32nm CMOS
Introduction of
High-k Gate Dielectric
and
Metal Gate Electrode
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M.Niwa
EOT Scaling by High-k material
Reduction of
Scaling limit
of SiO2
・Equivalent Oxide Thickness (EOT)
・ Inversion layer Thickness (Tinv)
0
Metal Gate
0.2~0.5nm
Poly-Si
High-κ
SiO2
C=κ
＝
κ~20
κSiO2~4
1
ln( J g ) ∝
T ph
Depletion
I dsat = µ eff C ox
W
k
(Vg − Vt ) 2 ∝ µ eff
(Vg − Vt ) 2
L
T ph
S
Tphy
Cinv=
κSiO2 ・S
Tinv
κSiO2
Tphy
EOT=
κ
Introduction of High-k/Metal Gate system
4
2011 VLSI Tech. Symp. -SC
110622 SMT Symp.
M.Niwa
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110622 SMT Symp.
M.Niwa
Gate Stack Options
HK/MG System
NiSi
PS
PS
MG
IL
MK
HK
PSG
MIPS
RPG
FUSI
Poly Si Gate
Metal Inserted
Poly Si Gate
Replacement
Gate
Fully Silicided
Gate
NECEL
Panasonic
Intel
1st introduction into Market
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M.Niwa
Potential ability of FUSI
High Potential;
・ WF controllability &
Cost effectiveness
・ No Tinv (MG)
But, tunable WF range is
rather narrow
Eg Si
A. Lauwers et.al.,
IEDM 2006
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110622 SMT Symp.
M.Niwa
Potential ability of FUSI
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110622 SMT Symp.
M.Niwa
Idsat @target Ioff [mA/um]
NiSi
NMOS
Ni31Si12
Optimum Work Function
PMOS
1.0
Optimum WF
0.8
Ioff = 100nA/um (HP)
0.6
Ioff = 1nA/um (LOP)
0.4
Ioff = 10pA/um (LSTP)
0.2
4.0
～4.05
4.2
4.4
4.6
WF [eV]
4.8
5.0
5.2
～5.15
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110622 SMT Symp.
M.Niwa
FUSI CMOS Flow
1
PS
e.g. 100
nm
PS
5
STI
Simultaneous silicidation
2
6
NiSi
(NMOS)
3
Ni3Si
(PMOS)
PN Boundary Issue
Poly etch back
NiSi
Ni
Photo Resist
4
Poly-Si
Ni3Si
Ni
Ni
HK
Si
NMOS
PMOS
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M.Niwa
High-k Gate
Dielectric Materials
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Ionic Bond vs Covalent Bond
Transition Metal ;
Low ionization energies having a positive oxidation states
Ionic Bond
Covalent Bond
HfO2
SiO2
Compared to SiO2 (strong covalent bond), HfO2 has lot of Oxygen vacancy
and this leads to essential influence on FET characteristics.
How to control of Oxygen vacancy is essential issue for HK/MG system
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110622 SMT Symp.
M.Niwa
FLP Phenomenon
K. Shiraishi et al., VLSI Tech. Symp. 2007
Oxygen in HfO2 moves into Poly Si resulting in Oxygen vacancy(V02+) in the HfO2
⇒ Electric Dipole formation at the interface ⇒ Vfb shift
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110622 SMT Symp.
M.Niwa
How to obtain the intrinsic Vfb value
V fb ( meas .) = V fb (int .) + ∆V fb (Q fix )
Slant Etch preparation
∆V fb = dQ fix / Sε + (1 / 2)d 2Q fix / Sε
MG
High-k
EOT = 0
d
d=0
+ + + + + + + + + + + +
0.1
HfO2
HfSiO
HfSiON
HfO2 + Cap
4.98±
±0.02 eV
0.0
4.90±
±0.02 eV
Si-sub
4.88
±0.01 eV
-0.2
-0.5
+
+
+
+
+
+ +
+ d
+ +
+
+
+ + + + + + + + + + + +
Si-sub
Important
regime !
-0.4
MG
+
+
4.85±
±0.02 eV
-0.3
“Linear”
+
-0.1
IL(SiO2)
High-k
IL(SiO2)
“Quadratic”
Metal Gate
0
1
2
3
4
5
6
7
8
Vfb
Vfb (V)
⇒
EOT (nm)
EOT
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M.Niwa
Effective Work Function (eWF)
Roll-Off
FLP
Qfix
-+
eWF
Φs
WF
dipole
-
CB
2e-
n-sub
P+PS
or
PMetal
HK
IL
Φs
+
O
n-sub
+
+
+
Band edge WF MG
is necessary,
however , , ,
Interfacial reaction
(FLP, Vfb roll-ff)
at MG/HK and HK/IL
causes
dipole and
fixed charge
Poly Si
Or Metal
Vo2+
P+PS
or
PMetal
VB
CB
-+
--
VB
HK
HK IL
Uniform
distribution
Si
++ +
Actual band diagram
Metal
A charge “+q” at distance of
d in the HK modulates WF
by –q(d/εε) ⇒ ”eWF”
∆V = −
1
xρ(x)dx ≈ −
ε∫
q⋅ d
ε
Retrograded Work Function
(Effective WF: eWF)
Si
+q
ρ(x)
q
Poisson’s Equation
Oxide
0 d
Ｘ
Challengeable against
EOT scaling
Ｘ
Vth lowering and
Process Integration
are Antithetical concepts!!
tox
q ⋅d
-V(x)
ε
0
d
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WF control by capping
Dipole formation
・ Various kinds of capping materials
LaO, MgO, DyO, AlO, TiO , , ,
・ Capping process
HfSiO dep
Ex.
Dielectric: ALD 2.5nm
HfSiO+DPN+PNA
Thermal budget: 1030oC
DPN+PNA
La2O3 dep
La2O3
HfSiO
HfSiON
HfSiON
Si
Si
Si
・ Allocation of capping
Above HK
Poly-Si
Poly-Si
MG
MG
La-based cap
HfSiON
HfSiON
La-based cap
Si
Si
Below HK
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M.Niwa
Deterioration of WF due to
(interfacial) reaction
(Dipole Formation; FLP, Vfb Roll-off)
Gate(HK) First Process
5.0
WF
FLP（Fermi Level Pinning）
Vfb roll-off
DMSD
2 metals
1 dielectrics
-
4.8
WF (eV)
SMDD
1 metal
2 dielectrics
4.6
eWF
＋
（ｅｆｆｅｃｔｉｖｅ Work Function）
（ｅｆｆｅｃｔｉｖｅ
）
4.4
4.2
DMDD
2 metals
2 dielectrics
MG
HK1
HK2
NMOS
PMOS
MG1
MG2
HK
NMOS
PMOS
MG1
MG2
HK1
HK2
NMOS
PMOS
Low Vth
VB
Complexity
5.2
CB
4.0
0
0.5
1.0
1.5
EOT (nm)
2.0
2.5
S:Single, M:Metal, D:Dual, D:Dielectric
Antithetical btw Integration and Vt lowering !
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Integration Issue
W effect
Concern of Oxygen penetration
BE
BE
STI
STI
O
O
W
NMOS
L
PMOS
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M.Niwa
Comprehensive understanding
of oxygen behavior
Scaling of MG/HK including IL
Possible explanation;
・ For thick IL：
： O2- HK ⇒ MG
To compensate generation of Vo2+,
O2- in IL ⇒ H K
・ When IL becomes thinner：
：
Less O2- IL ⇒ HK
・ For ultra-thin IL：
： O2- in HK ⇒ IL
S.C. Song et al., IEDM 2007
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110622 SMT Symp.
M.Niwa
Vfb modulation by capping material
Oxygen density determines direction and strength of produced dipole.
Oxygen density is different from each material.
Dipole
Dipole
+
-
HfO2 O2- V
SiO2
SiO2
I
I
La2O3
O2V
+
K. Kita et al., IEDM 2008
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M.Niwa
Start Commercial Shipment of 32nm-CMOS
with HK/MG in Sept. 2010
< First Gate First-HK/MG CMOS production >
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M.Niwa
Intel 45nm Logic FET - Gate Last (HK First)
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K. Mistry et al., IEDM 2007
110622 SMT Symp.
M.Niwa
45nm High-k + Metal Gate Strain-Enhanced FETs
(Intel)
NMOS
PMOS
tensile
Tensile Trench Contact
MG →∆Id: +16%
Compressive
Ge30%＆
＆Tensile
MG→∆µ: +50%
tensile
Since PMOS 1st , NMOS process is free from Pmetal stress
SiGe channel & Gate Last →∆µ（
（hole）
）: +50%
C. Auth et al., VLSI Tech. Symp. 2008
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Intel 32nm Logic FET
Gate Last (HK Last)
PMOS
NMOS
Metal 1
Metal 2
(Gate fill)
Metal 3 Barrier
(NMOS WF)
Metal 4 (WF Tuning)
SW
Metal 5 liner (etch stop)
HfO2
Metal 6 (NMOS WF)
Oxide
HfO2
Oxide
SiN
Epi SiGe
Epi Si
Dec. 2009 Press release: Processor 「Westmere」
」
～ March. 2010 PC with this CPU[Xeon] was on the Market
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110622 SMT Symp.
M.Niwa
Issue on HK last process (CMP Process)
Planarization, STI bump height, (Non-)Silicidation area , , ,
Conventional process
NiSi
PSG
STI SiGe
STI
P-Well
CMP1（
（PSG planarization）
）
SiGe
STI
N-Well
CMP2（
（PS denudation）
）
PSG
STI SiGe
STI
P-Well
SiGe
N-Well
STI
STI SiGe
STI
P-Well
SiGe
STI
N-Well
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Issue on HK last process (Multi-Oxide)
110622 SMT Symp.
M.Niwa
HK first: Multi-oxide is used as IL
HK last: Precise control of remaining oxide thickness after Gox removal
is key issue
HK last
HK first
Core
I/O
PS depo.
HK/MG/PS
Optimization of
remaining oxide
thickness after
Gox removal is
crucial
PS/Gox removal
Chem.Ox./HK/MG
PS removal
Core
I/O
Core
I/O
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110622 SMT Symp.
M.Niwa
Summary
Contributing factor of Vth
Gate Last
HK last
HK
1st
Gate 1st
Vfb Roll-off
None
？
Yes
FL Pinning
None
None
Yes
・WF：
：Ideal
remark
・Scaling:
・WF：
：Problematic
・Counter measures:
・Metal Etch back:
・Cost:
・Cost:
Band Edge WF but complex:
Suitable for HP
Low cost but less band edge:
Suitable for LOP/LSTP
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110622 SMT Symp.
M.Niwa
Ultra-thin Oxide thickness
SiO2 is still
a key dielectric
As
Interfacial Layer for HK/MG system,
BD mechanism of Bi-layer system (HK/IL),
Host gate dielectric of 28nm CMOS for LOP, , ,
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110622 SMT Symp.
M.Niwa
?
Physical Structure
Vg
Reliability
XTEM image
O O
O
Gate
polySi
SiO2
SiO2
Si Sub.
Si Sub.
1.39 nm
Si O Si Si
O O OO O O
Si Si Si
Strained layer
O O
O O
H
Si
Si
Si
Si
Si
Si
O
O
Si O
O
O Si
O O
Fresh
Si Sub.
Si
Si
Si
O
O
Si + O
Vg
Gate
O
H
SiO2
O Si +
O
O
Broken-down
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110622 SMT Symp.
M.Niwa
Breakdown phenomena of HK/MG stack
BD mechanism depends on Dielectric and Gate electrode
(⇒
⇒ needs new criteria)
* SILC is controlled by the trap generation in
the primarily near its interface with HK.
* MIN (w/o IL) do not exhibit an appreciable
SILC up to the BD moment.
R.Degraeve et al., in IEDM Tech. Dig.,1999, p327.
G. Bersuker et al., IEDM 2008
究極的なSiO2一層の場合は？
一層の場合は？
究極的な
●
Base oxide layer for high-k
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110622 SMT Symp.
M.Niwa
Zero Interface
J. Huang et al., VLSI Tech. Symp. 2009
⇒
EOT : ↓
Mobility : ↓ ?
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Specific PVD formation;
110622 SMT Symp.
M.Niwa
“Hf-metal sputter + RPO; Scavenging technique”
Hf
Hf
Hf
Hf
Hf
O*
O* O* O* O*
O*
HfO2
Hf-metal
Starting Surface
Si sub.
Si sub.
Si sub.
(a)
(b)
10 0
3.0
HfO 2 thickness
=1.3nm (const.)
10 -6
1.5
1.0
0.5
1.0
1.5
10 -9
2.0
Thickness (nm)
2.0
8
Hf-metal_sputter: pure Hf-metal can be deposited
6
uniformlyHfOand
layerin high density.
2
4
2
0
RPO:Interfacial
the Hf-metal
can be oxidized uniformly with
layer
oxygen radicals and referentially against Si interface
temperatures.
0at specific
1
2
3 low
4
5
H f m etal thickness (nm )
Hf m etal th ickness (n m )
Oxidation Rate (a.u.)
CET (nm)
10 -3
Jg (A/cm2)@Vfb-1V
10
2.5
0.0
K. Yamamotoet.al, APL, 83 (2003) 2229.
500℃
℃
300℃
℃
1.8
1.6
1.4
1.2
1.0
Interface
Starting Surface
HfO2
Hf
HfO2
Si
T1 T2 T3
Oxidation temperature
interfacial layer
InterfacialSi-sub.
layer (IL)
①30 s
②120 s
RPO time
③480 s
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110622 SMT Symp.
M.Niwa
Beyond 32nm CMOS
2011 Sym. On VLSI Technology @ Kyoto
+
α
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110622 SMT Symp.
M.Niwa
Keywords from
2011 Symp. on VLSI Technology
New Channel on Si
3D Approach
Nanowire
Adv. Memory
Spintronics
TFET
RTN
FINFET
SOI
,
,
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2011 VLSI Tech. Symp. -SC
110622 SMT Symp.
M.Niwa
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110622 SMT Symp.
M.Niwa
Bulk FET
FIN FET
None
with smaller size, variability increases!
FINFET;
Due to its strong carrier controllability,
1) Punch-through can be easily suppressed
⇒ SCE can be suppressed further ⇒ Better scalability
2) Lower Nsub ⇒ Smaller variablity(Vth)
Due to the same operating principle as Ultra-thin FD-SOI !
FIN-width(Wfin) should be shorter than Lg ( Wfin < Lg/2 )
110622 SMT Symp.
M.Niwa
Press release by
Intel; May, 2011
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110622 SMT Symp.
M.Niwa
Intel
Press release
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110622 SMT Symp.
M.Niwa
2011 VLSI Tech. Symp.
Tri-gate nanowire MOSFETs
M. Saito, et. al., Toshiba, Tokyo Inst. of Tech.
1. Universal line appears in Pelgrom plot of both Vth and Id variations of
nanowire transistors .
2. Avt in NW Tr. is lower than planar Tr. due to gate grain alignment.
3. Id variations can be reduced by improving side-surface roughness.
25
SCE ← Gate LWR
σWF
(Grain)
σDit
RDF
SOI
NW
BOX
σRSD ← NW LWR
(S/D crystallinity)
σµ (σv))
- roughness
- strain
HNW
22nm
15nm
8nm
19nm
<110> nFET
1 NW
I/I Before Epi
20
Gate
σ Vth (mV)
σVth
15
Avt =1.5mVµ
µm
Tox
3nm
3nm
3nm
1.2nm
W :1µ
µm
(Planar)
10
Avt =0.6mVµ
µm
5
σTox
WNW : 20~50nm
σ Id
0
0
5
10
15
20
1/(L (W +2HNW))0.5 (µ
µm-1)
g
25
NW
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2011 VLSI Tech. Symp.
110622 SMT Symp.
M.Niwa
LATE NEWS
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110622 SMT Symp.
M.Niwa
Multi Vt demonstration by FDSOI-HK/MG CMOS
with Back gate bias
VLSI 2010
Dual trench
Vt control
by
Back gate bias
+46%
⇒ For advanced SRAM, FD-SOI is very promising candidate to suppress the variability.
However, Bulk Si is still necessary for the peripheral circuits which need large current, i.e., ESD protection or
Power MOSFET. Need for the hybridization of FD-SOI & Bulk Si is becoming popular since 2009.
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110622 SMT Symp.
M.Niwa
2011 VLSI Tech. Symp.
20nm ETSOI CMOS and SRAM
K. Cheng, et. al., IBM, STMicroelectronics, GLOBALFOUNDRIES,
Renesas, Toshiba
1. First demonstration of 20nm ETSOI CMOS with 22 nm gate length, and sub-100 nm
contacted gate pitch
2. 25% improvement in speed over 28nm bulk low power technology.
3. High density 6-Transistor SRAM cells down to 0.08 µm2 cell size.
4. Competitive drive currents: (NFET/PFET) of 1150/1050 µA/µ
µm at Ioff = 100 nA/µm for
high performance (HP); and 920/880 µA/µ
µm at Ioff = 1 nA/µ
µm for low power (LP),
respectively, at VDD = 1 V.
5. Auxiliary ETSOI devices including epitaxy resistors with high precision and gated
diodes with near ideal characteristics are fabricated on ETSOI to enable early ETSOI
SoC design.
-7
Cell size
2
0.08µm
VR (V)
0.8
0.6
0.4
0.2
0.0
0.0
0.2
0.4
0.6
VL (V)
0.8
1.0
IOFFn + IOFFp (A/µm)
10
1.0
20nm ET 1V
20nm ET 0.9V
28nm Bulk 1V
10
-8
10
-9
10
-10
0.5
0.6
0.7
0.8
Delay (a.u.)
0.9
1.0
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2011 VLSI Tech. Symp.
110622 SMT Symp.
M.Niwa
50nmFDSOI 3D-integrated CMOS
P. Batude, et. al., CEA-LETI
1. 3D sequential integration enable 3D interconnections at the FET scale (CMOS
can be vertical)
2. Thanks to its high alignment performance (σ<10nm), it allows the full use of the
3rd dimension potential.
3. First demonstration of 3D sequential integration with LG=50nm
4. Molecular bonding is used to obtain perfect top active layer (cristalline quality
and thickness)
5. Low temperature FET (<650°
°C) appears viable for scaled FETs
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110622 SMT Symp.
M.Niwa
2011 VLSI Tech. Symp.
20nm High-K/Metal-Gate bulk CMOS
S.-J. Hyun, et. al., Samsung
2.
An aggressively scaled high-k last metal gate (HKMG) stack was successfully
implemented for 20nm high performance and low power applications.
Key achievements are
(a) aggressive Tinv scaling down to 1.1nm
(b) suppression of Vfb roll-off for good control of PMOS Vt
(c) replacement metal process with suitable Vt and good Vt uniformity
(d) metal gate stress engineering for transistor performance improvement
Normalized Gate Leakage
(Rel. Unit)
1.
100
Optimized
10 HK
Optimized
IL
28/32nm
1
11
12
13
14
Tinv (Å)
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2011 VLSI Tech. Symp.
110622 SMT Symp.
M.Niwa
Tunnel FETs for extremely low power application
U. Avci, et. al., Intel
1. TFET is a leading device option for low power in the beyond CMOS era
2. Steep I-V turn-on characteristic if realized enables low supply operation
3. Analysis of process variation impact on the TFET shows it is no worse than
CMOS
4. Circuit assessment of TFET logic is compared to CMOS Logic. TFET Logic
shows 8x higher performance than CMOS for extremely low-power
applications.
45
2011 VLSI Tech. Symp.
110622 SMT Symp.
M.Niwa
ETB III-V-On-Insulator MOSFET
S.-H. Kim, et. al., The University of Tokyo
1. First operation of Extremely-thin body (ETB) MOSFETs with metal S/D in
III-V MOSFETs
2. High mobility with ETB less than 10 nm by using InxGa1-xAs with high
Indium contents (0.7) and inserting In0.3Ga0.7As(large band gap) buffer
layer
46
2011 VLSI Tech. Symp. -SC
110622 SMT Symp.
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110622 SMT Symp.
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Assessment of the situation
in technology is a key issue!
Important message on recent 28nm CMOS for LOP application!
S.C. Song et al. ISAGST 2009
With appropriate Tinv scaling by SiON/PS, high speed & low power consumption can be achieved at the same time!
48
2011 VLSI Tech. Symp.
110622 SMT Symp.
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2011 VLSI Tech. Symp.
110622 SMT Symp.
M.Niwa
Spintronics: Magnetic Tunneling Junction is implemented onto CMOS
At VLSI Circ. Symp., Tohoku Univ. + NEC have developed the World’s First
Content Addressable Memory that Stores Data without using Power !
50
110622 SMT Symp. M.Niwa
VLSI Technology Trend
2006, STRJ ( Semiconductor Technology Roadmap committee of Japan )
Explorative Research
Heterogeneous
Integ.
Evolution of
Si System
By
introducing
new
Materials,
Structure
and Design
,,,
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110622 SMT Symp.
M.Niwa
Technology Evolution
ArF Enhancer
3D
3D TSV
Air gap
New evolution beyond 32nm
ArF immersion
graphene
EUV Litho. ⇔ Immersion Litho.＋
＋DP
Tr: Planar MOS ⇔ Multi Gate, SOI, 3D
nanowires
Low k
Active Area
k=2.5
Spacers
Gate
Field
TunnelFET
Ge/IIIV
Low k
CNT’
s
FinFET
k=2.7
< 20nm
22nm
metal gate
Low k
k=3.0
high -κ
κ
L=35nm
SiGe
Cu
strain
> 45nm
32-28nm
SMO
Double Pattering
EUV
USJ
Fab-less Tool
silicide
Year
52
110622 SMT Symp.
M.Niwa
Ge/Ⅲ
Ⅲ-Ⅴ
Ⅴ+Si-MOSFET;
High-performance & Multi-function by Heterogeneous integ.
High speed by Hibridgization
Ultra-low power by TFET
Multi-function by Hetrogeneous integration
S. Takagi, VLSI 2010
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110622 SMT Symp.
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54